Microelectronic assembly including partial liner in glass through-via
A partial liner in the sidewall of TGVs within glass cores addresses the CTE mismatch issue, improving the structural integrity and durability of glass cores by reducing stress, thereby preventing damage.
JP2026086345APending Publication Date: 2026-05-26INTEL CORP
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- INTEL CORP
- Filing Date
- 2025-10-09
- Publication Date
- 2026-05-26
AI Technical Summary
Technical Problem
The integration of metal-filled through-glass vias (TGVs) in glass cores for IC packaging is hindered by significant stress due to coefficient of thermal expansion (CTE) mismatch between glass and metal materials, leading to potential damage and degradation of the glass structure.
Method used
Incorporating a partial liner within the sidewall of the TGV as a buffer layer to separate the glass core from the conductive material, reducing stress induced by CTE mismatch.
Benefits of technology
The partial liner mitigates stress at the glass-conductive material interface, enhancing the structural integrity and longevity of the glass core by acting as a buffer, thus preventing crack formation and degradation.
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Smart Images
Figure 2026086345000001_ABST
Abstract
This invention provides techniques, related devices, and methods for mitigating stress induced by CTE mismatch in the vicinity of the conductive material of the TGV to the glass material of the glass core in regions subjected to large stresses. [Solution] The microelectronic assembly includes a glass core 190 having a first surface 190-1 and a second surface 190-2 opposite to it, glass through vias 110 extending between the first and second surfaces of the glass core, and a liner material between the glass core and the conductive material of the glass through vias.
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