Variable output power (VOP) integrated into current-steering digital-to-analog converters.

Abstract

The output power of the digital-to-analog converter (DAC) can be set independently of the board-level power supply. [Solution] The DAC230 adjusts the total current (I) of the switch cell 310 within the DAC by adjusting the shunt current control signals (SCCS1, SCCS2) applied to a pair of programmable shunt current sources 335b and 335c with opposite polarity to the tail current control signal (TCCS) applied to the programmable tail current source 335a. total Maintain the output voltage (V) at a controllable operating point. A controlled common-mode voltage or operating point is possible, allowing the output voltage (V) to be maintained at a controllable operating point. outp , V outn This allows for reduced device voltage stress over a wider dynamic range.

Description

Technical Field

[0001] Various embodiments generally relate to digital-to-analog converters (DACs).

Background Art

[0002] In various electronic systems, information can be converted between digital signal formats and analog signal formats. For example, a digitally encoded data stream can be transmitted as an analog signal and converted to an analog format by a digital-to-analog converter (DAC).

[0003] DACs can be employed in various applications. For example, a DAC can be used to convert a digital data stream to an analog audio signal in a music player. A DAC can also be used in a communication system. The communication system transfers data from a transmitter to a receiver via a data link. Data encoded in a digital format can be converted to an analog format by a DAC before transmission. The analog signal generated by the DAC can be amplified by a variable gain amplifier (VGA), and then the VGA can amplify the analog signal. A radio frequency (RF) power amplifier driving the transmitter's antenna can convert a low power radio frequency signal (e.g., the amplified analog signal) to a higher power signal. Different bias voltages applied to the input of the RF power amplifier can operate the RF power amplifier in different modes.

[0004] To perform both data format conversion and amplification, a DAC having an embedded variable gain amplifier (e.g., a current steering DAC) can be applied to a transmitter. The performance of a DAC having an embedded variable gain amplifier can depend on various factors such as the resolution, linearity performance, and conversion speed of the DAC.

Summary of the Invention

[0005] The apparatus and associated method relate to maintaining the total current of a switch cell in a DAC at a controllable operating point by adjusting a shunt current control signal applied to a pair of programmable shunt current sources with opposite polarity to the tail current control signal applied to a programmable tail current source. In the illustrative example, the total current may flow through the differential leg of the switch cell. The pair of programmable shunt current sources may be configured, for example, to compensate for the adjustment to the programmable tail current source. In the illustrative example, the tail current and shunt current may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current source to compensate for the adjustment to the tail current source allows, for example, a controlled common-mode voltage or operating point, thereby reducing device voltage stress over a wider dynamic range of the output voltage.

[0006] Various embodiments may achieve one or more advantages. For example, some embodiments may allow the output power of the DAC to be set independently of the board-level power supply. Thus, a power amplifier connected to the DAC (e.g., an RF power amplifier) ​​may receive different bias voltages to meet different design specifications. Also, the output power of the DAC may be dynamically programmable during operation, and as a result, the electrical (e.g., voltage) stress on the cascode transistors within the DAC can be managed. Thus, the reliability of the DAC may be advantageously improved.

[0007] Some embodiments may also include a variable resistor network coupled to the bias node voltage and the drain electrodes of the differential pair of transistors. This allows for a wider output power range of the DAC. In some embodiments, the differential resistor network may be programmable to further adjust the bias node voltage supplied to the drain electrodes of the differential pair of transistors. This allows for a further widening of the DAC's output power range while maintaining a constant board-level power supply. In some embodiments incorporating capacitance, the high-frequency performance of the DAC can be advantageously improved. In some embodiments, two programmable shunt current sources may also be used to enhance the linearity performance of the DAC.

[0008] In an exemplary embodiment, the circuit includes (a) a switch cell circuit having at least one switch cell, each of which has (a1) a differential pair of transistors having first and second control nodes, first and second shunt nodes, and a tail current node; (a2) a programmable tail current source having two terminals, one terminal of which is coupled to a tail current node and the other terminal of which is coupled to a predetermined reference voltage, and configured to draw a current proportional to a tail current control signal; (a3) ​​a first programmable shunt current source having two terminals, one terminal of which is coupled to a first shunt node and the other terminal of which is coupled to a predetermined reference voltage, and configured to draw a current proportional to a first shunt current control signal; and (a4) a second programmable shunt current source having two terminals, one terminal of which is coupled to a second shunt node and the other terminal of which is coupled to a predetermined reference voltage, and configured to draw a current proportional to a second shunt current control signal. The circuit also includes (b) a pair of differential resistors coupled between the bias node and the corresponding shunt node of the differential pair of transistors. The first and second programmable shunt current sources are configured to compensate for the adjustment to the tail current by adjusting the first and second shunt current control signals with opposite polarity to the tail current control signal, thereby maintaining the total current of the switch cell at a controllable operating point.

[0009] In some embodiments, each of at least one switch cell may also include a pair of cascode transistors coupled between the corresponding resistors of a pair of differential resistors and the corresponding shunt nodes of the differential pair of transistors. In some embodiments, the circuit may also include a control circuit configured to generate first and second shunt current control signals as a function of predetermined circuit parameters. In some embodiments, the circuit parameters may also include the resistance values ​​of the first resistor and the resistance values ​​of the second resistor.

[0010] In some embodiments, the control circuit may also include a processing engine and a data store, which is coupled to the processing engine and, when executed by the processing engine, includes a program of instructions that causes the processing engine to perform an operation to generate first and second shunt control signals in correspondence with a first lookup table that stores one or more predetermined settings for shunt current control signals as a function of tail current control signals.

[0011] In some embodiments, the circuit may also include (c) a programmable resistor coupled between a power supply node and a bias node, the programmable resistor including a variable resistor configured to adjust the voltage at the bias node to one of a predetermined set of resistance values ​​in response to a variable resistor programming signal (VRPS). In some embodiments, the control circuit may be further configured to generate the VRPS in response to a second lookup table storing one or more predetermined settings for the VRPS. In some embodiments, the circuit parameters may also include a voltage value at the bias node. In some embodiments, the circuit may also include a capacitance arranged in parallel with at least some of the programmable resistors. In some embodiments, the first and second shunt control signals may be controllable independently of each other.

[0012] In another exemplary embodiment, the method includes (a) providing a differential pair of transistors having first and second control nodes, first and second shunt nodes, and a tail current node; (b) providing a programmable tail current source having two terminals, the programmable tail current source being configured to draw a current proportional to a tail current control signal, with one terminal coupled to a tail current node and the other terminal coupled to a predetermined reference voltage; and (c) providing a first programmable shunt current source having two terminals. (d) providing a second programmable shunt current source having two terminals, configured to draw a current proportional to a first shunt current control signal, with one terminal connected to the first shunt node and the other terminal connected to a predetermined reference voltage, and (e) connecting a pair of differential resistors between the bias node and the corresponding shunt nodes of the differential pair of the transistor. The first and second programmable shunt current sources are configured to compensate for adjustments to the tail current by adjusting the first and second shunt current control signals with opposite polarity to the tail current control signal, thereby maintaining the total current of the switch cell at a controllable operating point.

[0013] In some embodiments, the method may also include (f) coupling a pair of cascode transistors between the corresponding resistors of a pair of differential resistors and the corresponding shunt nodes of the differential pair of transistors. In some embodiments, the method may also include configuring a control circuit to generate first and second shunt current control signals as a function of predetermined circuit parameters. In some embodiments, the circuit parameters may also include the resistance values ​​of the first resistor and the resistance values ​​of the second resistor. In some embodiments, the control circuit may include a processing engine and a data store which includes a program of instructions coupled to the processing engine, and which, when executed by the processing engine, causes the processing engine to perform an operation to generate first and second shunt current control signals in correspondence with a first lookup table that stores one or more predetermined settings for shunt current control signals as a function of tail current control signals.

[0014] In some embodiments, the method may also include providing a programmable resistor coupled between a power supply node and a bias node, the programmable resistor including a variable resistor configured to adjust the voltage at the bias node to one of a predetermined set of resistance values ​​in response to a variable resistor programming signal (VRPS). In some embodiments, the control circuit may be further configured to generate the VRPS in response to a second lookup table storing one or more predetermined settings for the VRPS. In some embodiments, the circuit parameters may also include the voltage value at the bias node. In some embodiments, the method may also include providing a capacitance arranged in parallel with at least a portion of the programmable resistor. In some embodiments, the first and second shunt control signals may be controllable independently of each other.

[0015] Details of various embodiments are described in the accompanying drawings and the following description. Other features and advantages will become apparent from the description and drawings, as well as from the claims. [Brief explanation of the drawing]

[0016] [Figure 1] This figure shows an exemplary programmable integrated circuit (IC) in which the circuits and processes of this disclosure may be implemented. [Figure 2] This figure shows an exemplary digital-to-analog converter (DAC) implemented within a communication system. [Figure 3] This figure shows an exemplary architecture for a current-steering DAC. [Figure 4A] This figure shows an exemplary control circuit used in the DAC described with reference to Figure 3. [Figure 4B] This is a flowchart illustrating an exemplary method for implementing the DAC described with reference to Figure 3. [Figure 5] This figure shows another exemplary architecture for a current-steering DAC. [Figure 6] This figure shows another exemplary control circuit used in the DAC described with reference to Figure 5. [Figure 7] This is a flowchart illustrating an exemplary method performed by a control circuit to adjust the DAC circuit settings, as explained with reference to Figure 5. [Figure 8] This figure shows another exemplary architecture for a current-steering DAC. [Figure 9] This figure shows another exemplary system-on-a-chip (SOC) in which the circuits and processes of this disclosure may be implemented. [Modes for carrying out the invention]

[0017] Similar reference symbols in various drawings indicate the same elements.

[0018] The apparatus and associated method relate to maintaining the total current of a switch cell in a DAC at a controllable operating point by adjusting a shunt current control signal applied to a pair of programmable shunt current sources with opposite polarity to the tail current control signal applied to a programmable tail current source. In the illustrative example, the total current may flow through the differential leg of the switch cell. The pair of programmable shunt current sources may be configured, for example, to compensate for the adjustment to the programmable tail current source. In the illustrative example, the tail current and shunt current may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current source to compensate for the adjustment to the tail current source allows, for example, a controlled common-mode voltage or operating point, thereby reducing device voltage stress over a wider dynamic range of the output voltage.

[0019] To aid understanding, this document is organized as follows: First, with reference to Figure 1, we briefly introduce an exemplary platform (e.g., FPGA) suitable for performing data communication and signal conversion. Second, with reference to Figures 2–4B, we describe an exemplary digital-to-analog converter (DAC) capable of generating different output voltages, an exemplary control circuit that may be used to provide control signals for a current source to program the DAC to generate different output voltages, and a method for implementing the DAC. With reference to Figures 5–8, we move on to describing other exemplary embodiments of the DAC, control circuits, and exemplary methods of how the control circuit may function to generate control signals for a current source to program the DAC. Finally, with reference to Figure 9, we briefly introduce another exemplary platform (e.g., SOC) suitable for performing data communication and signal conversion.

[0020] Figure 1 shows an exemplary programmable integrated circuit (IC) in which the circuits and processes of this disclosure may be implemented. Programmable IC 100 includes FPGA logic. Programmable IC 100 may be implemented using various programmable resources and may be referred to as a system-on-chip (SOC). Various examples of FPGA logic may include several different types of programmable logic blocks in an array.

[0021] For example, Figure 1 shows a programmable IC 100 that includes a number of different programmable tiles, including a multi-gigabit transceiver (MGT) 101, a configurable logic block (CLB) 102, a random access memory (BRAM) block 103, an input / output block (IOB) 104, configuration and clocking logic (CONFIG / CLOCKS) 105, a digital signal processing block (DSP) 106, a specialized input / output block (I / O) 107 (e.g., a clock port), and other programmable logic 108 (e.g., a digital clock manager, an analog-to-digital converter, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include internal and external reconfiguration ports (not shown).

[0022] In various examples, serializers / deserializers can be implemented using MGT101. MGT101 can include various data serializers and data deserializers. Data serializers can include various multiplexer implementations. Data deserializers can include various demultiplexer implementations.

[0023] In some examples of FPGA logic, each programmable tile includes a programmable interconnect element (INT) 111 having standardized interconnects 124 between it and corresponding interconnect elements within each adjacent tile. Thus, the combined programmable interconnect elements implement the programmable interconnect structure for the illustrated FPGA logic. As shown in the example included in Figure 1, the programmable interconnect element INT 111 includes internal connections 120 between it and programmable logic elements within the same tile. As shown in the example included in Figure 1, the programmable interconnect element INT 111 includes inter-INT connections 122 between it and other programmable interconnect elements INT 111 within the same tile.

[0024] For example, CLB102 may include a single programmable interconnect element INT111, as well as a configurable logic element (CLE)112 that can be programmed to implement user logic. BRAM103 may include a BRAM logic element (BRL)113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a tile may depend on the height of the tile. In the implementation described, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) may also be used. DSP tile 106 may include a DSP logic element (DSPL)114 and one or more programmable interconnect elements. IOB104 may include, for example, two instances of an input / output logic element (IOL)115 and one instance of a programmable interconnect element INT111. For example, the actual I / O bond pads connected to the I / O logic element 115 may be manufactured using layered metal on top of the various logic blocks shown, and may not be limited to the area of ​​the input / output logic element 115.

[0025] In the depicted implementation, the columnar region near the center of the die (illustrated in shaded areas in Figure 1) is used for configuration, clock, and other control logic. The horizontal region 109 extending from the column distributes the clock and configuration signals across the entire width of the programmable IC 100. Note that the references to “columnar” and “horizontal” regions refer to the vertical view of the drawing.

[0026] Some programmable ICs utilizing the architecture shown in Figure 1 may include additional logic blocks that disrupt the typical linear structure that constitutes the majority of the programmable IC. These additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC110 shown in Figure 1 spans multiple columns of CLB102 and BRAM103.

[0027] Figure 1 shows an exemplary programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of the columns, the types of logic blocks included in the columns, the relative size of the logic blocks, and the implementation of interconnections / logic are provided as examples only. For example, in a real programmable IC, wherever a CLB102 appears, two or more adjacent columns of CLB102 may be included to facilitate the efficient implementation of user logic.

[0028] In some embodiments, parts of the transceiver may be incorporated into an integrated circuit (e.g., FPGA) to perform data transmission and / or data reception during communication. A digital-to-analog converter (DAC) is used to convert digital signals to analog signals. A variable gain amplifier may be incorporated into the DAC (e.g., a current-steering DAC) to provide the power amplifier (PA) with the desired output power. The PA can amplify the modulated signal and transmit the modulated signal to an antenna for transmission over the communication medium. In some situations, the desired output power may differ to operate the PA in various modes. By programming the circuit configuration of the DAC, the board-level supply V DDDifferent output voltages can be achieved without changing the settings.

[0029] Figure 2 shows an exemplary digital-to-analog converter (DAC) implemented within a communication system. In this illustrated example, the communication system 200 includes a base station 205. The base station 205 may be used to send and receive data from several data communication devices. In this exemplary example, the base station 205 transmits a digital signal to a portable communication device (e.g., a mobile phone) 210. The base station 205 includes an integrated circuit (IC) 215 for performing data communication from the base station 205 to the mobile phone 210. The IC 215 may include an FPGA.

[0030] In this illustrated example, IC215 includes a digital-to-analog converter (DAC) 230. A digital signal 225 is received by the DAC 230 and converted to an analog signal 235. The analog signal 235 is then amplified by an amplifier (e.g., a power amplifier) ​​240 to form an amplified analog signal 245. The amplified analog signal 245 is transmitted to an antenna 250 for transmission over a communication medium (not shown). In some embodiments, IC215 may also include one or more filters for processing the analog signal 235 before amplification.

[0031] The DAC230 includes a latch 255, which can generate a set of gate control signals. In some embodiments, the DAC230 may also include a decoder (not shown) configured to receive a digital signal 225 and convert the words in the digital signal 225 into binary signals. The latch 255 may be coupled to the output of the decoder to generate gate control signals. The DAC230 also includes a switch cell circuit 260. The gate control signals may be used to control the switches in the switch cell circuit 260. The DAC230 also includes a differential resistor network 265, which acts as the termination resistor for the switch cell circuit 260. In wireless applications, the amplitude of the differential analog data signals may be changed depending on how far the data is transmitted. Therefore, the output power of the DAC230 may be adjusted to perform the transmission. The switch cell circuit 260 is designed to dynamically adjust the output power of the DAC230. An example of the DAC architecture is described in further detail with reference to Figure 3. In some embodiments, the DAC230 may also include a variable resistor network 270 for further adjustment of the output power. An example of a DAC architecture with a variable resistor network is described in more detail with reference to Figure 5. IC215 includes a control circuit 275 configured to control the settings of a switch cell circuit 260 to dynamically adjust the output power of the DAC230. An example of the control circuit 275 is described in more detail with reference to Figure 4A.

[0032] Figure 3 shows an exemplary architecture of a current-steering DAC. In this illustrated example, the current-steering DAC 230 includes a latch 255 that generates gate control signals for a switch cell circuit 260. In this illustrated example, the latch 255 includes multiple slices of the latch. The current-steering DAC 230 also includes a switch cell circuit 260. A binary signal may be applied to the switches in the switch cell circuit 260 to steer the current to the positive output of the current-steering DAC 230. In this embodiment, the switch cell circuit 260 includes multiple slices (e.g., four slices) of a switch cell 310. In some embodiments, the switch cell circuit 260 may include between one and 128 switch cells connected in parallel. For example, the switch cell circuit 260 may include 63 switch cells connected in parallel. Each slice of the latch in the latch 255 may generate a corresponding set of gate control signals for the switch cells in the switch cell circuit 260. For example, the first slice 256 of the latch generates gate control signals 305a and 305b for the first switch cell 310 in the switch cell circuit 260.

[0033] The switch cell 310 includes a first pair of switch / transistors (e.g., MOSFETs, BJTs). The first pair of switches includes a first transistor 315 and a second transistor 320. In this illustrated example, the first pair of transistors 315 and 320 are N-type metal oxide semiconductor field-effect transistors (NMOSFETs). The first transistor 315 and the second transistor 320 each have control nodes (e.g., gate electrodes) CP and CN, on which their respective gate control signals 305a and 305b (e.g., differential gate voltages) are received. The first pair of transistors also each have a first shunt node (e.g., drain electrode) SP and a second shunt node SN, as well as a source. The two source electrodes of the first NMOSFET 315 and the second NMOSFET 320 are coupled at a tail current node TC.

[0034] The switch cell 310 also includes a programmable tail current source 335a coupled between the tail current node TC and a predetermined reference voltage (e.g., GND). A current with an amplitude I DAC is supplied to the programmable tail current source 335a. To program the amplitude I DAC , a tail current control signal (TCCS) is applied to the programmable tail current source 335a. The switch cell 310 also includes a first programmable shunt current source 335b coupled between the first shunt node SP and a predetermined reference voltage (e.g., GND). To program the first current amplitude I shunt1 , a first shunt current control signal (SCCS1) is applied to the first programmable shunt current source 335b. The switch cell 310 also includes a second programmable shunt current source 335c coupled between the second shunt node SN and a predetermined reference voltage (e.g., GND). To program the second current amplitude I shunt2 , a second shunt current control signal (SCCS2) is applied to the second programmable shunt current source 335b. Thus, the total current flow through the switch cell 310 can be expressed as I total =I DAC +I shunt1 +I shunt2 . The two programmable shunt current sources may have different current values to cancel out the non - symmetry performance.

[0035] The first and second programmable shunt current sources 335b - 335c are configured to compensate for the adjustment to the tail current by maintaining the total current of the switch cell at a controllable operating point by adjusting the first and second shunt current control signals with opposite polarities with respect to the tail current control signal. By adjusting the amplitudes I shunt1 and I shunt2 of the shunt current, the current flow through the switches 315 and 320 can be dynamically adjusted, while the common - mode voltage V CM can be kept constant or at a predetermined controllable operating point, and the differential output voltages V outp and V outn can be made programmable.

[0036] In some embodiments, the first programmable shunt current source 335b and the second programmable shunt current source 335c have the same amplitude I shunt The same shunt current control signal may be used to control the total current flow through the switch cell 310, such that the total current flow through the switch cell 310 is I total =I DAC +2I shunt It can be expressed as follows. In some embodiments, two programmable shunt current sources 335b to 335c may be used to further improve the linearity performance of the DAC230. In some embodiments, the other terminal of the programmable tail current source 335a may be coupled to ground potential GND, and the first and second programmable shunt current sources 335b to 335c may be coupled to different reference voltages to reduce voltage stress between the two programmable shunt current sources 335b to 335c.

[0037] In this illustrated example, the switch cell 310 also includes a pair of cascode transistors 325 and 330. In this illustrated example, the cascode transistors 325 and 330 are NMOSFETs. The two sources of the cascode transistors 325 and 330 are coupled to the first shunt node SP and the second shunt node SN, respectively. The cascode transistors 325 and 330 reduce the Miller effect and further reduce the voltage V at the output nodes OP and ON of the DAC230. outp and V outn The voltage can be adjusted. The gates of cascode transistors 325 and 330, respectively, are configured to receive an enable signal (not shown). In some embodiments, the switch and transistors may be P-channel metal oxide semiconductor field-effect transistors (PMOSFETs).

[0038] The DAC230 also includes a differential resistor network 265. The differential resistor network 265 supplies board-level voltage V DDIt is coupled between and the switch cell circuit 260. The differential resistor network 265 includes a first termination resistor 340 and a second termination resistor 345, which are coupled to the drains of the cascode transistors 325 and 330, respectively. The current flow through the cascode transistor 325 is I CASp The amplitude may be such that the current flow through the cascode transistor 330 is I CASn It may have an amplitude of [value].

[0039] The two gate control signals 305a to 305b can steer the current in the first switch cell 310 to the left via the left termination resistor 340 or to the right via the right termination resistor 345, depending on whether the gate control signals 305a to 305b are 0 or 1. The current amplitudes of the two programmable shunt current sources 335b and 335c (e.g., I shunt1 , I shunt2 By programming the current amplitude I of the programmable tail current source 335a, DAC The common-mode voltage V CM It can be dynamically adjusted without changing it. Therefore, the differential output voltage V as a function of the gate control signals 305a and 305b outp and V outn The differential output voltage (V) can be adjusted accordingly. outdiff =V outp -V outn ) is the board level supply V DD The common-mode output voltage V of switch cell 310 can be adjusted without changing it. CM This can be kept constant or adjusted. Furthermore, the differential output voltage V outp and V outn is programmable (for example, V outp and V outn Since both are programmed to be below 2.65V, the stress on cascode transistors 325-330 is controlled, which can improve the reliability of the DAC.

[0040] Figure 4A shows an exemplary control circuit used in the DAC described with reference to Figure 3. The control circuit 275 includes a processing engine 410 configured to receive a command signal 405 (e.g., from a user) and then generate SCCS1, SCCS2, and TCCS. The control circuit 275 also includes a non-volatile memory (NVM) 415 coupled to the processing engine 410. The NVM 415, when executed by the processing engine 410, contains a program of instructions that causes the processing engine to perform operations to generate SCCS1, SCCS2, and TCCS. An exemplary operation performed by the processing engine 410 will be described in more detail with reference to Figure 7.

[0041] The NVM415 also includes a first lookup table (LUT) that stores pre-calculated circuit configurations and corresponding current source programming signals (e.g., SCCS1, SCCS2, and TCCS). For example, the first LUT programs a programmable shunt current source and a programmable tail current source to a predetermined current value I DAC Furthermore, differential output voltage V outp and V outn To obtain, DAC Value, board-level power supply V DD , terminating resistance R term , Programmable shunt current source I shunt1 and I shunt2 The current value, and the corresponding current source programming signal (e.g., SCCS1 = SCCS2, I shunt1 =I shunt2 ) may include. Therefore, the maximum and minimum differential output voltage V outp and V outn This can be set. For example, V DD =3V, and termination resistor R term If both 340 and 345 are 50 ohms, the desired differential output voltage V outdiff To obtain (for example, 0V, 0.12V, 0.15V, 0.25V, 0.4V, 0.5V, ...), the corresponding current amplitude I shunt1 and I shunt2By selecting (for example, 2mA, 7mA, ...), the corresponding current amplitude I flowing through the two switches 315 and 320 is controlled. DAC (For example, 20mA, 10mA, ...) can be obtained. The processing engine 410 then searches for the corresponding current source programming signals (for example, SCCS1, SCCS2, and TCCS) and applies the retrieved current source programming signals (for example, SCCS1, SCCS2, and TCCS) to the programmable shunt current sources 335b~335c and the tail current source 335a to obtain the corresponding current amplitude I shunt1 , I shunt2 and I DAC It is possible to obtain the output power (e.g., differential output voltage V). Therefore, the output power (e.g., differential output voltage V) can be obtained. outdiff =V outp -V outn ) is the board level supply V DD The common-mode output voltage V of switch cell 310 can be adjusted without changing it. CM It can be kept constant (e.g., 2.0V) or at a controllable operating point (e.g., 2.2V). Furthermore, the differential output voltage V outp and V outn is programmable (for example, V outp and V outn Since both are programmed to be below their maximum limits (e.g., 2.65V), the stress on cascode transistors 325-330 is controlled, which can improve the reliability of the DAC.

[0042] Figure 4B shows a flowchart of an exemplary method for implementing the DAC described with reference to Figure 3. An exemplary method 400B for implementing the DAC 230 (for example, when the switch cell circuit 260 has one switch cell 310) is described. Method 400B includes, in 425, providing a differential pair of transistors (for example, a differential pair of transistors 315 and 320) having first and second control nodes (for example, control nodes CP and CN), first and second shunt nodes (for example, shunt nodes SP and SN), and a tail current node (for example, tail current node TC). Method 400B also includes, in 430, providing a first current source (for example, a programmable tail current source 335a) having two terminals and being proportional to a tail current control signal (for example, TCCS), coupling one terminal of the programmable tail current source 335a to the tail current node TC, and coupling the other terminal of the programmable tail current source 335a to a predetermined reference voltage (for example, ground potential GND).

[0043] Method 400B also includes, in 435, providing a first programmable shunt current source (e.g., a first programmable shunt current source 335b) having two terminals and being proportional to a first shunt current control signal (e.g., SCCS1), connecting one terminal of the first programmable shunt current source 335b to a first shunt node SP, and connecting the other terminal of the first programmable shunt current source 335b to a predetermined reference voltage GND. Method 400B also includes, in 440, providing a second programmable shunt current source (e.g., a second programmable shunt current source 335c) having two terminals and being proportional to a second shunt current control signal (e.g., SCCS2), connecting one terminal of the second programmable shunt current source 335c to a second shunt node SN, and connecting the other terminal of the second programmable shunt current source 335c to a predetermined reference voltage GND.

[0044] Method 400B also involves supplying a reference voltage (e.g., V) in 445.DD The invention includes providing a pair of differential resistors (for example, a differential resistor network 265 having a first termination resistor 340 and a second termination resistor 345) coupled between a bias node that provides a voltage supply V DD The second termination resistor 345 is connected between the first shunt node SP and the voltage supply V DD It is coupled between this and the second shunt node SN.

[0045] Method 400B also includes configuring the first and second programmable shunt current sources in 450 such that the adjustment to the tail current is compensated for by adjusting the first and second shunt current control signals with opposite polarity to the tail current control signal, thereby maintaining the total current of the switch cell at a controllable operating point. By programming the current amplitudes of the two programmable shunt current sources 335b and 335c, the current amplitude I of the programmable tail current source 335a is controlled. DAC This can be dynamically adjusted without changing the total common-mode current of 335a, 335b, and 335c. Therefore, the output power of the DAC230 is the board-level supplied V DD It can be adjusted without changing anything.

[0046] Figure 5 shows another exemplary architecture of a current-steering DAC. In this illustrated example, the DAC 500 includes a latch 255, a switch cell circuit 260 having a programmable shunt current source, and a differential resistor network 265. In this illustrated example, the DAC 500 also includes a variable resistor network 270. The variable resistor network 270 is an in-phase variable resistor network connected to the differential resistor network 265 via a bias node 555. The other end of the variable resistor network 270 is connected to an external board-level power supply V DD It will be joined to

[0047] The resistors in the variable resistor network 270 are connected to the bias node 555 to provide the desired voltage V termIt can be programmed to obtain a certain value. Thus, the total current flowing through the switch cell circuit 260 can be adjusted. The variable resistor network 270 includes one or more resistors (e.g., resistors 560, 565, 570). The variable resistor network 270 also includes one or more switches (e.g., switches 575, 580, 585, 590). Each of the one or more switches is controlled by a variable resistor programming signal (VRPS). The VRPS can also be generated by the control circuit 275. The resistors and switches in the variable resistor network 270 form multiple resistance paths with different resistances. By selecting different VRPS, different resistance values ​​can be obtained. Thus, the same voltage V at the bias node 555 can be used for different values ​​of the total current flowing through the switch cell. term This acquires the selected gain mode and / or selected signal swing.

[0048] In some embodiments, the switch may be a digital switch. In some embodiments, the switch may be a metal oxide semiconductor field-effect transistor (MOSFET). In various implementation configurations, the programmable variable resistor network 270 is advantageous as the DAC500 can handle a wide range of supply voltages (e.g., V DD ) may enable operation at high frequencies. Furthermore, some embodiments may allow the signal to be adaptively tuned to match the range of load specifications. The DAC500 also includes a capacitor 595 connected in parallel with the variable resistor network 270. The capacitor 595 may favorably improve the performance of the DAC500 when it is operating at high frequencies.

[0049] By further introducing the variable resistor network 270, the differential resistor network 265 and the switch cell circuit 260 are supplied with an external board level V DD It can receive an independent, controllable common-mode voltage, and the voltage value at bias node 555 is V termThis can be programmed. The DAC500 may be capable of generating a wide range of output power. As a result, the differential gain level can be set independently, and the board level power supply V DD This can remain constant for various total current values ​​of the current sources 335a to 335c. By introducing a variable resistor network 270, reliability issues for these transistors 315, 320, 325, and 330 can be further mitigated. In some embodiments, the variable resistor network 270 may be located off-chip. In some embodiments, the variable resistor network 270 may be formed or modified (e.g., trimmed) by hardware resources on the FPGA 215, for example.

[0050] Figure 6 shows another exemplary control circuit used in the DAC described with reference to Figure 5. In this illustrated example, the control circuit 600 includes a processing engine 610 configured to receive a command signal 605 (e.g., from a user) and then generate a current source programming signal CSPS and a variable resistor programming signal VRPS. The control circuit 600 also includes a non-volatile memory (NVM) 615 coupled to the processing engine 610. The NVM 615 contains a program of instructions that, when executed by the processing engine 610, cause the processing engine 610 to perform operations to generate current control signals (e.g., SCCS1, SCCS2, and TCCS) and the variable resistor programming signal VRPS. Exemplary operations performed by the processing engine 610 are described in more detail with reference to Figure 7.

[0051] The NVM615 also includes a second lookup table (LUT) that stores pre-calculated circuit configurations and corresponding current source programming signals. For example, in this second LUT, the second lookup table stores the desired I DAC Value, board-level power supply V DD , terminating resistance R term , corresponding differential output voltage V outp and V outnThe current value of the programmable shunt current source, the corresponding current control signals (e.g., SCCS and TCCS), and the corresponding resistance R of the variable resistance network 270 var and information regarding the corresponding VRPS. By introducing the programmable shunt current source and the variable resistance network 270, the differential resistance network 265 and the switch cell circuit 260 can receive a controllable common-mode voltage independent of the external board-level supply V DD and the output voltage of the DAC can be dynamically adjusted.

[0052] FIG. 7 shows a flowchart of an exemplary method executed by a control circuit to adjust the circuit configuration of the DAC described with reference to FIG. 5. As described with reference to FIG. 6, when executed by the processing engine 610, the NVM 615 includes a program of instructions that cause the processing engine 610 to perform operations for generating current control signals (e.g., SCCS1, SCCS2, and TCCS) and VRPS. Method 700 includes, at 705, determining, by the processing engine 610, the board-level power supply voltage V DD applied to the DAC 500. Method 700 also includes, at 710, determining, by the processing engine 610, the current amplitude I DAC to be supplied to the current source 335a. Method 700 also includes, at 715, determining the circuit specifications of the DAC 500 (e.g., the resistances of the differential resistors R term 340 and 345 or the resistance of the differential resistance network 265, and the resistance path of the variable resistance network 270).

[0053] Method 700 also includes, in 720, determining by the processing engine 610 whether the DAC includes a variable resistor network. If the DAC (e.g., DAC230) does not include a variable resistor network 270, in 725, the processing engine 610 selects current amplitude values ​​for programmable shunt current sources 335b-335c from a first lookup table (e.g., the lookup table shown in Figure 4A), and in 730, searches for the corresponding SCCS1, SCCS2, and TCCS, and applies the retrieved SCCS1, SCCS2, and TCCS to the programmable shunt current sources 335b-335c and the programmable tail current source, respectively. Thus, the programmable shunt current sources 335b-335c are configured to have the corresponding current amplitudes. DAC This can be obtained, and the desired output power can be generated.

[0054] If the DAC (e.g., DAC230) includes a variable resistor network 270, then in 735, the processing engine 610 selects the current amplitude for the programmable shunt current sources 335b-335c from a second lookup table (e.g., the lookup table shown in Figure 6), and in 740, selects the corresponding resistor path (and voltage at bias node 555) in the variable resistor network 270 for DAC500. Method 700 also includes, in 745, retrieving the corresponding SCCS1, SCCS2, TCCS, and VRPS and applying the retrieved SCCS1, SCCS2, TCCS, and VRPS to DAC500. Thus, the corresponding current amplitude I DAC This can be obtained. The DAC500 may be capable of generating a wide range of output power, and the desired output power can be generated.

[0055] Figure 8 shows another exemplary architecture of a current-steering DAC. In DAC800 in Figure 8, the differential resistor network 265 shown in Figure 5 is replaced by a second differential resistor network 805. The second differential resistor network 805 controls the output voltage V OUTIt is coupled to a switch cell circuit 260 that is operable to provide the following. The second differential resistor network 805 is programmable and under the control of a variable differential resistor programming signal (VDRPS). The VDRPS can also be generated by a control circuit 275.

[0056] In this illustrated example, the second differential resistor network 805 includes a first termination resistor 340 coupled to the drain of cascode transistor 325 and a second termination resistor 345 coupled to the drain of cascode transistor 330. The second differential resistor network 805 also includes a first programmable differential resistor path connected in parallel to the first termination resistor 340. The first programmable differential resistor path includes a third termination resistor 810 connected in series with the first switch 815. The first programmable differential resistor path can be enabled or disabled by controlling the first switch 815. The second differential resistor network 805 also includes a second programmable differential resistor path connected in parallel to the second termination resistor 345. The second programmable differential resistor path includes a fourth termination resistor 820 connected in series with the second switch 825. The second programmable differential resistor path can be enabled or disabled by controlling the second switch 825. The control circuit 275 may be used to generate variable differential resistor programming signals (VDRPS) for controlling the first programmable differential resistor path and the second programmable differential resistor path. For example, the VDRPS may be applied to open and close the first switch 815 and the second switch 820 to change the differential resistors. Accordingly, the total current flowing into the switch cell circuit 260 may be changed. In some embodiments, the DAC may include, for example, the second differential resistor network 805 rather than both the variable resistor network 270 and the second differential resistor network 805.

[0057] By programming the second differential resistor network 805 and the variable resistor network 270, the common resistor value and the differential resistor value in the DAC800 can be set independently, and the board-level power supply V DDThe total current flowing through the switch cell circuit 260 can be adjusted while keeping the current constant. By adjusting the current supplied to the programmable shunt current sources 335b to 335c, the current supplied to the programmable tail current source 335a can be dynamically changed, and then the output power of the DAC can be dynamically changed.

[0058] In this illustrated example, the DAC230 is located on the same integrated circuit (e.g., IC215) as the control circuit 275 and amplifier 240. In another embodiment, the DAC230 may be implemented in a different IC (e.g., a different programmable logic) to perform signal conversion, and the control circuit 275 may be located within IC215 to control the output power of the DAC230. In some embodiments, the DAC230 may be implemented as a hard block fixed circuit. For example, application-specific integrated circuits (ASICs) may provide a DAC with customized hardware circuitry. In some embodiments, the switch cell circuit 260, differential resistor network 265, and / or variable resistor network 270 may be implemented in different integrated circuits or in different locations on a system-on-chip (SOC).

[0059] In some embodiments, some or all of the functions of the DAC230 / 500 / 800 and / or control circuit 275 may be implemented in a processor configured to execute a set of instructions stored in a data store to control signal conversion and adjust the output power of the DAC. The processor may be located on the same integrated circuit as the amplifier 240, and the integrated circuit may be a programmable IC (e.g., FPGA). For example, the DAC230 and data store may be implemented in a programmable logic block of a system-on-a-chip (SOC) or in a hard block using the fixed circuitry of the SOC, and the amplifier 240 and processor may be implemented in a separate hard block using the fixed circuitry of the SOC, for example.

[0060] Figure 9 shows another exemplary system-on-a-chip (SOC) in which the circuits and processes of this disclosure may be implemented. In the example of Figure 9, various different subsystems or regions of the illustrated SOC900 may be implemented on a single die provided within a single integrated package. In other examples, different subsystems may be implemented on multiple interconnected dies provided as a single integrated package.

[0061] In the example, the SOC900 includes multiple regions having circuits with different functionalities. In the example, the SOC900 optionally includes a data processing engine (DPE) array 902. The SOC900 includes a programmable logic (PL) region 904 (hereinafter referred to as the PL region or PL), a processing system (PS) 906, a network-on-chip (NOC) 908, and one or more hardwired circuit blocks 910. The DPE array 902 is implemented as multiple interconnected hardwired programmable processors that interface to other regions of the SOC900.

[0062] The PL904 is a circuit that can be programmed to perform specific functions. For example, the PL904 can be implemented as a field-programmable gate array type circuit. The PL904 can include an array of programmable circuit blocks. Examples of programmable circuit blocks within the PL904 include, but are not limited to, configurable logic blocks (CLBs), dedicated random-access memory blocks (BRAM, and / or UltraRAM or URAM), digital signal processing blocks (DSPs), clock managers, and / or delayed-locked loops (DLLs).

[0063] Each programmable circuit block within the PL904 typically includes both a programmable interconnect circuit and a programmable logic circuit. A programmable interconnect circuit typically includes numerous interconnect wires of varying lengths interconnected by programmable interconnection points (PIPs). Typically, the interconnect wires are configured (e.g., per wire) to provide bit-by-bit connectivity (e.g., each wire carries a single bit of information). A programmable logic circuit implements user-designed logic using programmable elements, which may include, for example, lookup tables, registers, and arithmetic logic. Programmable interconnects and programmable logic circuits can be programmed by loading configuration data into internal configuration memory cells that define how the programmable elements are configured and operate.

[0064] The PS906 is implemented as hardwired circuitry manufactured as part of the SOC900. The PS906 may be implemented as, or include, one of several different processor types, each capable of executing program code. For example, the PS906 may be implemented as individual processors, e.g., single cores capable of executing program code. In another example, the PS906 may be implemented as a multicore processor. In yet another example, the PS906 may include one or more cores, modules, coprocessors, interfaces, and / or other resources. The PS906 may be implemented using one of several different types of architecture. Examples of architectures that may be used to implement the PS906 include, but are not limited to, ARM processor architectures, x86 processor architectures, GPU architectures, mobile processor architectures, DSP architectures, or other suitable architectures capable of executing computer-readable instructions or program code.

[0065] NOC908 includes an interconnection network for sharing data between endpoint circuits within SOC900. Endpoint circuits may be located within the DPE array 902, PL area 904, PS906, and / or hardwired circuit block 910. NOC908 may include high-speed data paths with dedicated switching. In one example, NOC908 includes horizontal paths, vertical paths, or both horizontal and vertical paths. The arrangement and number of areas shown in Figure 9 are merely examples. NOC908 is an example of a common infrastructure available within SOC900 for connecting selected components and / or subsystems.

[0066] The NOC908 provides connectivity to a selected one of the following: PL904, PS906, and hardwired circuit block 910. The NOC908 is programmable. In the case of a programmable NOC used with other programmable circuits, the nets routed through the NOC908 are unknown until a user circuit design is created for implementation within the SOC900. The NOC908 can be programmed by loading configuration data into an internal configuration register that defines how elements within the NOC908, such as switches and interfaces, are configured and operate to pass data from switch to switch and between NOC interfaces.

[0067] The NOC908 is manufactured as part of the SOC900 and is not physically modifiable, but can be programmed to establish connectivity between different master and slave circuits of a user-designated circuit. For example, the NOC908 may include multiple programmable switches capable of establishing a packet-switched network connecting user-specified master and slave circuits. In this regard, the NOC908 is adaptable to different circuit designs, each of which has a different combination of master and slave circuits implemented in different locations within the SOC900 that can be coupled by the NOC908. The NOC908 can be programmed to route data, such as application data and / or configuration data, between the master and slave circuits of a user-designated circuit. For example, the NOC908 can be programmed to couple different user-specified circuits implemented within the PL904 with the PS906 and / or DPE array 902, different hardwired circuit blocks, and / or different circuits and / or systems outside the SOC900.

[0068] The hardwired circuit block 910 may include input / output (I / O) blocks and / or transceivers for sending and receiving signals to and from external circuits and / or systems, memory controllers, etc., of the SOC900. Examples of various I / O blocks may include single-ended I / O and pseudo-differential I / O, as well as high-speed differential clock transceivers. Furthermore, the hardwired circuit block 910 may be implemented to perform specific functions. Examples of hardwired circuit block 910 include, but are not limited to, cryptographic engines, digital-to-analog converters, and analog-to-digital converters. The hardwired circuit block 910 within the SOC900 may, as appropriate, be referred to as application-specific blocks in this specification.

[0069] In the example in Figure 9, PL904 is shown within two separate regions. In another example, PL904 may be implemented as an integrated region of the programmable circuit. In yet another example, PL904 may be implemented as three or more different regions of the programmable circuit. The specific organization of PL904 is not intended to be limiting. In this regard, SOC900 includes one or more PL regions 904, PS906, and NOC908. Optionally, a DPE array 902 may be included.

[0070] In other exemplary implementations, the SOC900 may include two or more DPE arrays 902 located within different regions of the IC. In yet another example, the SOC900 may be implemented as a multi-die IC. In this case, each subsystem may be implemented on a different die. Different dies may be linked in a communicative manner using any of the various available multi-die IC techniques, such as stacking dies side-by-side on an interposer using a stack die architecture in which the IC is implemented as a multi-chip module (MCM). In the multi-die IC example, it should be understood that each die may contain a single subsystem, two or more subsystems, one subsystem and another partial subsystem, or any combination thereof.

[0071] A programmable integrated circuit (IC) refers to a type of device that includes programmable logic. An example of a programmable device or IC is a field-programmable gate array (FPGA). FPGAs are characterized by containing programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random-access memory blocks (BRAMs), digital signal processing blocks (DSPs), processors, clock managers, and delayed-locked loops (DLLs). Modern programmable ICs have evolved to include programmable logic in combination with one or more other subsystems. For example, some programmable ICs have evolved into system-on-a-chip, or "SOCs," that include both programmable logic and a hardwired processor. Other types of programmable ICs include additional subsystems and / or different subsystems.

[0072] Various embodiments can be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), while other embodiments can be implemented in fixed entities (e.g., ASICs) or incorporated into a single integrated circuit (e.g., SOC) with programmable logic. Dedicated hard block circuits in ASIC implementations may not be reconfigurable once materialized in an integrated circuit, but in some implementations, for example, ASIC implementations can provide a minimized platform in terms of, for example, power consumption and / or die area.

[0073] While various embodiments have been described with reference to the figures, other embodiments are also possible. For example, the control circuit 275 may be implemented within the DAC 230. In another example, the amplifier 240 may be implemented outside the IC 215.

[0074] Various examples can be implemented using circuits that include various electronic hardware. Hardware may include, but is not limited to, transistors, resistors, capacitors, switches, integrated circuits, and / or other devices. In various examples, the circuit may include analog and / or digital logic, discrete components, traces, and / or memory circuits manufactured on a silicon substrate, including various integrated circuits (e.g., FPGAs, ASICs). In some embodiments, the circuit may include the execution of pre-programmed instructions and / or software performed by a processor. For example, various systems may include both hardware and software.

[0075] Some embodiments of the embodiment may be implemented as a computer system. For example, various implementations may include digital and / or analog circuits, computer hardware, firmware, software, or a combination thereof. Device elements may be implemented in a computer program product tangibly embodied in an information carrier, e.g., a machine-readable storage device, for execution by a fixed hardware processor, or the method may be implemented by a programmable processor that executes a program of instructions for performing the functions of various embodiments by acting on input data and producing an output. Some embodiments may be advantageously implemented in one or more computer programs executable on a programmable system including a data store, at least one processor coupled to send and receive data and instructions to and from a data store, at least one input, and / or at least one output. The data store may include one or more registers, or, for example, memory locations in memory space. A computer program is a set of instructions that can be used directly or indirectly in a computer to perform a particular activity or to produce a particular result. Computer programs can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, such as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0076] In various embodiments, a computer system may include non-transient memory. The memory may be connected to one or more processors, and the processors may be configured to store computer-readable instructions, including data and processor-executable program instructions. The data and computer-readable instructions may be accessible to one or more processors. When executed by one or more processors, the processor-executable program instructions can cause one or more processors to perform various operations.

[0077] Several implementations have been described. Nevertheless, it will be understood that various modifications are possible. For example, favorable results may be achieved if the steps of the technique of this disclosure are performed in a different order, or if the components of the system of this disclosure are combined in a different manner, or if components are complemented by other components. Therefore, other implementations are also within the scope of the appended claims.

Claims

1. (a) A switch cell circuit (260) comprising at least one switch cell (310), wherein each of the at least one switch cell (310) is (a1) A differential pair of transistors (315, 320) having first and second control nodes (CP, CN), first and second shunt nodes (SP, SN), and a tail current node (TC), (a2) A programmable tail current source (335a) having two terminals, one of which is connected to the tail current node (TC) and the other terminal of which is connected to a predetermined reference voltage (GND), and configured to draw a current proportional to the tail current control signal, (a3) A first programmable shunt current source (335b) having two terminals, one of which is connected to the first shunt node (SP) and the other terminal of which is connected to the predetermined reference voltage (GND), and configured to draw a current proportional to the first shunt current control signal (SCCS1), (a4) A second programmable shunt current source (335c) having two terminals, one of which is connected to the second shunt node (SN) and the other terminal of which is connected to the predetermined reference voltage (GND), and configured to draw a current proportional to the second shunt current control signal (SCCS2) and A circuit including a switch cell circuit (260) having, A circuit in which the first and second programmable shunt current sources (335b to 335c) are configured to compensate for the adjustment to the tail current (IDAC) by adjusting the first and second shunt current control signals with opposite polarity to the tail current control signal (TCCS) to maintain the total current of the switch cell at a controllable operating point.

2. The circuit according to claim 1, further comprising a first resistor (340) coupled between a bias node (VDD) and the first shunt node (SP), and a second resistor (345) coupled between the bias node (VDD) and a second first shunt node (SN).

3. The circuit according to claim 2, wherein each of the at least one switch cell (310) further comprises a first cascode transistor (325) coupled between the first resistor (340) and the first shunt node (SP), and a second cascode transistor (330) coupled between the second resistor (345) and the second shunt node (SN).

4. The circuit according to claim 3, further comprising a control circuit (275) configured to generate the first and second shunt current control signals as functions of predetermined circuit parameters.

5. The circuit according to claim 4, wherein the circuit parameters further include the resistance value of the first resistor and the resistance value of the second resistor.

6. The control circuit (275) A processing engine (410) operably coupled to the first and second programmable shunt current sources, A data store (415) is coupled to the processing engine (410) and, when executed by the processing engine (415), includes a program of instructions that causes the processing engine (415) to perform an operation to generate the first and second shunt control signals in correspondence with a first lookup table that stores one or more predetermined settings for the shunt current control signal as a function of the tail current control signal. The circuit according to claim 4, comprising:

7. The system further comprises a programmable resistor network coupled between the power supply node and the bias node (555), wherein a variable resistor programming signal (VRPS) is used to control the voltage (V) at the bias node. ｔｅｒｍ The circuit according to claim 4, wherein the resistance of the programmable resistor network is configured to be adjusted to one of a predetermined set of resistance values ​​in order to adjust the following:

8. The circuit according to claim 7, wherein the control circuit (275) is further configured to generate the VRPS in correspondence with a second lookup table that stores one or more predetermined settings for the VRPS.

9. The circuit according to claim 8, further comprising a capacitance (395) arranged in parallel with at least a portion of the programmable resistor network (270).

10. The circuit according to claim 1, wherein the first and second shunt control signals (SCCS1, SCCS2) are controllable independently of each other.

11. (a) To provide a differential pair of transistors (315, 320) having first and second control nodes (CP, CN), first and second shunt nodes, and tail current nodes, respectively, (b) A programmable tail current source (335a) having two terminals is provided, and the programmable tail current source is configured to draw a current proportional to a tail current control signal, with one terminal connected to the tail current node (TC) and the other terminal connected to a predetermined reference voltage (GND), (c) A first programmable shunt current source (335b) having two terminals is provided, the first programmable shunt current source is configured to draw a current proportional to a first shunt current control signal, one terminal is connected to the first shunt node (SP), and the other terminal is connected to the predetermined reference voltage (GND), (d) A second programmable shunt current source (335c) having two terminals is provided, the second programmable shunt current source is configured to draw a current proportional to a second shunt current control signal, one terminal is connected to the second shunt node (SN), and the other terminal is connected to the predetermined reference voltage (GND). A method (400B) comprising the first and second programmable shunt current sources (335b to 335c) being configured to compensate for the adjustment to the tail current by adjusting the first and second shunt current control signals with opposite polarity to the tail current control signal, thereby maintaining the total current of the switch cell at a controllable operating point.

12. A first resistor (340) is connected between the bias node (VDD) and the first shunt node (SP), and a second resistor (345) is connected between the bias node (VDD) and the second first shunt node (SN), A first cascode transistor (325, 330) is coupled between the first resistor and the first shunt node (SP), and a second cascode transistor (330) is coupled between the second resistor and the second shunt node (SN), The control circuit (275) is configured to generate the first and second shunt current control signals as functions of predetermined circuit parameters. The method according to claim 11, further comprising the circuit parameter further comprising the resistance value of the first resistor and the resistance value of the second resistor.

13. The control circuit (275) A processing engine (410) operably coupled to the first and second programmable shunt current sources, A data store (415) is coupled to the processing engine (410) and, when executed by the processing engine (415), includes a program of instructions that causes the processing engine (415) to perform an operation to generate the first and second shunt current control signals in correspondence with a first lookup table that stores one or more predetermined settings for the shunt current control signal as a function of the tail current control signal. The method according to claim 12, comprising:

14. The present invention provides a programmable resistor network (270) coupled between a power supply node and the bias node (555), wherein the variable resistor programming signal (VRPS) is a voltage (V) at the bias node. ｔｅｒｍ To adjust the following, we provide a programmable resistor network (270) configured to adjust the resistance of the programmable resistor network to one of a predetermined set of resistance values, To provide a capacitance arranged in parallel with at least a portion of the programmable resistor network. The method according to claim 12, further comprising the control circuit (275) being configured to generate the VRPS in correspondence with a second lookup table storing one or more predetermined settings for the VRPS.

15. The method according to claim 11, wherein the first and second shunt control signals are controllable independently of each other.

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