Printed circuit board

The printed circuit board design addresses bonding reliability issues by using a two-bump structure with a passivation layer and photosensitive insulating material, enhancing bonding reliability and connection strength for high-density terminals.

JP2026091230APending Publication Date: 2026-06-03SAMSUNG ELECTRO MECHANICS CO LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
SAMSUNG ELECTRO MECHANICS CO LTD
Filing Date
2025-07-03
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

The decreasing pitch of bumps on flip chip dies leads to issues such as solder ball mounting and bonding reliability, and conductive bumps have limitations in height and width resolution, affecting the bonding reliability with the die.

Method used

A printed circuit board design featuring a first conductive bump connected to a conductive pad with a passivation layer lower in height, and a second conductive bump covering the protruding upper end of the first bump, where the insulating layer contains a photosensitive material, allowing for increased height and size of the conductive bumps.

Benefits of technology

This design enhances bonding reliability and connection strength by increasing the standoff height and size of conductive bumps, facilitating high-density input/output terminals and reducing substrate thickness.

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Abstract

The present invention provides a printed circuit board in which the height and size of conductive bumps have been increased. [Solution] The printed circuit board of the present invention comprises an insulating layer, a conductive pad embedded above the insulating layer with at least a portion of its upper surface exposed above the insulating layer, a first conductive bump disposed on the upper surface of the conductive pad, a passivation layer disposed on the upper surface of the insulating layer and covering a portion of the upper surface of the conductive pad and a portion of the side surface of the first conductive bump, and a second conductive bump disposed on the upper surface of the passivation layer and covering the other portion of the side surface of the first conductive bump and the upper surface of the first conductive bump.
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