Semiconductor equipment

Abstract

To provide semiconductor devices that reduce manufacturing costs. [Solution] The semiconductor device includes a power device, a boost circuit, and an overcurrent detection circuit. The overcurrent detection circuit includes a sense circuit and a detection current generation circuit DCG that generates the detection current. The detection current generation circuit comprises a first current source I1_G that flows a first current I1 from a detection output node DC_OT, a first current circuit I1_CT that supplies a second current I2 greater than the first current I1 to the detection output node, a second current circuit I2_CT that supplies a third current I3 greater than the first current, a limiting circuit LM_CT connected between the second current circuit and the detection output node to limit the voltage at the detection output node, a first control circuit C1_CT that operates on the boost voltage from the boost circuit and controls the first current circuit according to the voltage output from the sense circuit, and a second control circuit C2_CT that operates on the power supply voltage and controls the second current circuit according to the voltage output from the sense circuit.

Description

Technical Field

[0006] , , ,

[0007] , ,

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including an overcurrent detection circuit that detects an overcurrent flowing through a power device.

Background Art

[0002] A semiconductor device including an overcurrent detection circuit that detects an overcurrent flowing through a power device (for example, a power transistor) is described in, for example, Patent Document 1.

[0003] For example, in paragraph number

[0031] and FIG. 1 of Patent Document 1, it is shown that a boosted voltage generated by a charge pump circuit is supplied to an overcurrent detection circuit (an overcurrent protection circuit in Patent Document 1). The overcurrent protection circuit performs an operation of detecting an overcurrent with this boosted voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Although it will be described in detail later using a comparative example, when an overcurrent detection circuit is operated by frequently using a boosted voltage generated by a boosting circuit such as a charge pump circuit, the present inventor has found that there is a problem that the current consumption of the boosting circuit increases, the occupied area of the boosting circuit in the semiconductor device increases, leading to an increase in manufacturing cost.

Means for Solving the Problems

[0006] The outline of typical embodiments disclosed in the present application will be briefly described as follows.

[0007] In other words, a semiconductor device according to one embodiment includes a power device, a boost circuit, and an overcurrent detection circuit. The overcurrent detection circuit includes a sense circuit that outputs a voltage corresponding to the current flowing through the power device, and a detection current generation circuit that generates a detection current according to the output from the sense circuit. Here, the detection current generation circuit includes a first current source that supplies a first current from the detection output node of the detection current generation circuit, a first current circuit that supplies a second current larger than the first current to the detection output node, and a second current circuit that supplies a third current larger than the first current. The detection current generation circuit also includes a limiting circuit connected between the second current circuit and the detection output node to limit the voltage at the detection output node. Furthermore, the detection current generation circuit includes a first control circuit that operates with the boosted voltage from the boost circuit and controls the first current circuit according to the voltage output from the sense circuit, and a second control circuit that operates with the power supply voltage and controls the second current circuit according to the voltage output from the sense circuit.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Effects of the Invention]

[0009] According to one embodiment, it is possible to provide a semiconductor device that can reduce manufacturing costs. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a block diagram showing the configuration of the detection current generation circuit according to Embodiment 1. [Figure 3] Figure 3 is a circuit diagram showing the configuration of the detection current generation circuit according to Embodiment 1. [Figure 4] Figure 4 is a cross-sectional view showing a cross-section of a semiconductor chip according to Embodiment 1. [Figure 5] Figure 5 is a diagram illustrating the operation of the detection current generation circuit according to Embodiment 1. [Figure 6] FIG. 6 is a diagram for explaining the operation of the detection current generation circuit according to Embodiment 1. [Figure 7] FIG. 7 is a diagram for explaining the operation of the detection current generation circuit according to Embodiment 1. [Figure 8] FIG. 8 is a circuit diagram showing the configuration of the detection current generation circuit according to Embodiment 2. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of the overcurrent detection circuit according to Comparative Example 1. [Figure 10] FIGS. 10(A) and (B) are diagrams for explaining the level shift circuit according to Comparative Example 1. [Figure 11] FIG. 11 is a diagram for explaining overcurrent detection according to Comparative Example 2. [Figure 12] FIGS. 12(A) and (B) are diagrams showing the configuration of the overcurrent detection circuit according to Comparative Example 3. [Figure 13] FIGS. 13(A) and (B) are waveform diagrams for explaining the operation of Comparative Example 3. [Figure 14] FIGS. 14(A) and (B) are diagrams for explaining the problems of Comparative Example 3. [Figure 15] FIGS. 15(A) and (B) are diagrams for explaining the problems of Comparative Example 3. [Figure 16] FIGS. 16(A) and (B) are diagrams for explaining the problems of Comparative Example 3. Embodiments of the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention.

[0012] In addition, in this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0013] <Comparative Example> Prior to the present invention, the inventors studied and found that when the boosted voltage generated by a charge pump circuit is used extensively to operate an overcurrent detection circuit, there are problems that the power consumption of the overcurrent detection circuit increases and the occupied area becomes large. Therefore, it has been found that it is desirable to reduce the use of the boosted voltage and operate the overcurrent detection circuit by the voltage (power supply voltage) supplied from the outside of the semiconductor device as much as possible. Thus, the inventors developed an overcurrent detection circuit that can be operated by the voltage supplied from the outside as much as possible, but it was found that new problems occur in the developed overcurrent detection circuit. Hereinafter, three types of developed overcurrent detection circuits will be described as comparative examples.

[0014] <<Comparative Example 1>> FIG. 9 is a circuit diagram showing the configuration of an overcurrent detection circuit according to Comparative Example 1. In FIG. 9, CHP indicates a semiconductor device including an overcurrent detection circuit, and DR_OT indicates an output terminal of the semiconductor device CHP. Also, in FIG. 9, OC_CT indicates a detection output terminal of the semiconductor device CHP, and OCI_OT indicates a detection current terminal of the semiconductor device CHP. A load (not shown) is connected to the output terminal DR_OT of the semiconductor device CHP, and the load is driven by an output signal from the output terminal DR_OT. For example, a high-level output signal is supplied to the output terminal DR_OT from a high-side drive circuit, and a low-level output signal is supplied from a low-side drive circuit, and the load is driven.

[0015] In FIG. 9, the low-side drive circuit is omitted, and only the high-side drive circuit is shown. The high-side drive circuit includes an N-channel type field effect transistor (hereinafter, also referred to as an N-type transistor) PWT that is a power device, a shutdown N-type transistor SHT, a drive buffer DRVB, a charge pump circuit CP_CT that is a boost circuit, a first overcurrent detection circuit OC1, and a logic circuit LG_CT. In FIG. 9, in addition to these circuits, an N-type transistor CSNT for current sensing, a current detection circuit CS, and a second overcurrent detection circuit OC2 are shown, but these will be described in Comparative Example 2, so they are omitted here.

[0016] The charge pump circuit CP_CT is connected to the first voltage wiring (first power wiring) L_V1, the second voltage wiring (second power wiring) L_V2, the third voltage wiring (third power wiring) L_V3, and the output wiring L_OT connected to the output terminal DR_OT. The first voltage wiring L_V1 is supplied with a predetermined voltage (first voltage) VCC, and the second voltage wiring L_V2 is supplied with a voltage (second voltage) VCCm that is a predetermined value (e.g., 6V) lower than voltage VCC. Here, the first voltage VCC is a power supply voltage supplied from outside the semiconductor device CHP, and the second voltage VCCm is a power supply voltage generated from the first voltage VCC inside the semiconductor device CHP.

[0017] The charge pump circuit CP_CT is controlled by the operation control signal cp-stop. As will be explained later, when an overcurrent is detected by the first overcurrent detection circuit OC1, the operation control signal cp-stop is set to a high level by the logic circuit (output circuit) LG_CT, and when no overcurrent is detected, it is set to a low level by the logic circuit LG_CT.

[0018] When the operation control signal cp-stop is at a low level, the charge pump circuit CP_CT performs a boost operation using the voltage VCC at the first voltage wiring L_V1 and the voltage VCCm at the second voltage wiring L_V2 as the power supply voltage. The predetermined voltage (e.g., 6V) generated by the boost operation is added (superimposed) to the voltage at the output wiring L_OT (i.e., the output terminal DR_OT) and supplied to the third voltage wiring L_V3. In other words, when the charge pump circuit CP_CT is operating, the voltage at the third voltage wiring L_V3 is the voltage at the output wiring L_OT + 6V. Hereafter, the voltage at the third voltage wiring L_V3 will also be referred to as outp6v. When the operation control signal cp-stop is at a high level, the charge pump circuit CP_CT stops its boost operation.

[0019] The drain-source path of the N-type transistor PWT is connected in series between the first voltage wire L_V1 and the output wire L_OT, and the gate is connected to the output of the drive buffer DRVB. The drive buffer DRVB is connected to the third voltage wire L_V3 and the output wire L_OT, and operates using the voltage outp6v of the third voltage wire L_V3 and the voltage of the output wire L_OT as the power supply voltage, supplying the supplied high-side drive signal DRV_H to the gate of the N-type transistor PWT, controlling the N-type transistor PWT to a conducted or non-conducting state. The N-type transistor PWT has a large size, and when conducted, it supplies a large drive current (drain-source current) from the first voltage wire L_V1 to the output wire L_OT and output terminal DR_OT, supplying power to a load (not shown).

[0020] The drain-source path of the shutdown N-type transistor SHT is connected in series between the gate of the N-type transistor PWT and the output wiring L_OT, and the gate is supplied with the operation control signal cp-stop. When no overcurrent is detected, the shutdown N-type transistor SHT becomes non-conductive due to the low-level operation control signal cp-stop, and when an overcurrent is detected, it becomes conductive due to the high-level operation control signal cp-stop. This prevents the N-type transistor PWT from being destroyed by becoming non-conductive when an overcurrent is detected.

[0021] <<<Configuration of the first overcurrent detection circuit>>> The first overcurrent detection circuit OC1 comprises an N-type transistor SNT as a sense device, a sense resistor Rs, a reference voltage Vrf, a first comparator circuit CMP1, and a level shift circuit LVF.

[0022] The drain of the N-type transistor SNT is connected to the first voltage wire L_V1, its source is connected to the output wire L_OT via a sense resistor Rs, and its gate is connected to the gate of the N-type transistor PWT. The positive input (+) of the first comparator circuit CMP1 is connected to the connection node that connects the source of the N-type transistor SNT to the sense resistor Rs, and its negative input (-) is connected to the output wire L_OT via a reference voltage Vrf. The first comparator circuit CMP1 is also connected to the third voltage wire L_V3 and the output wire L_OT, and performs comparison operation using the voltage outp6v of the third voltage wire L_V3 and the voltage of the output wire L_OT as the power supply voltages.

[0023] Here, the size of the N-type transistor SNT is 1 / K1 (hereinafter, K1 is also referred to as the size ratio) relative to the size of the N-type transistor PWT. As a result, when both the N-type transistor PWT and SNT are in a conductive state by the drive buffer DRVB, the value of the current (sense current) Is flowing through the drain-source path of the N-type transistor SNT is 1 / K1 times smaller than the value of the current flowing through the drain-source path of the N-type transistor PWT. The first comparator circuit CMP1 compares the sense voltage Vs generated at the sense resistor Rs by the sense current Is with the reference voltage Vrf, and outputs the comparison result to the level shift circuit LVF as a sense output signal SV_OT that changes between the voltage outp6v of the third voltage wiring L_V3 and the voltage of the output wiring L_OT.

[0024] The level shift circuit LVF comprises two amplification circuits A1 and A2. Amplifier circuit A1 is connected to the first voltage wiring L_V1 and the output wiring L_OT, and uses the voltage VCC of the first voltage wiring L_V1 and the voltage of the output wiring L_OT as the power supply voltage to amplify the sense output signal SV_OT. Amplifier circuit A2 uses the voltage VCC of the first voltage wiring L_V1 and the voltage VCCm of the second voltage wiring L_V2 as the power supply voltage to amplify the output signal from amplifier circuit A1. As a result, the sense output signal SV_OT, which changes between the voltage outp6v and the voltage of the output wiring L_OT, is level-shifted to the detection signal OCS, which changes between the voltages VCC and VCCm.

[0025] The detection signal OCS is supplied to the logic circuit LG_CT. The logic circuit LG_CT is connected to the first voltage wire L_V1 and the second voltage wire L_V2, and operates using voltages VCC and VCCm as power supply voltages. Although not particularly limited, the logic circuit LG_CT generates a high-level detection output signal when the detection signal OCS is high level (voltage VCC), and generates a low-level detection output signal when the detection signal OCS is low level (voltage VCCm). The generated detection output signal is output to the outside of the semiconductor device CHP via the detection output terminal OC_OT, and is also supplied as an operation control signal cp-stop to the gates of the charge pump circuit CP_CT and the shutdown N-type transistor SHT.

[0026] <<<Issues of Comparative Example 1>>> The voltage of output wiring L_OT fluctuates between near voltage VCC and near ground voltage (not shown) due to the conduction / non-conductivity of the N-type transistor PWT in the high-side drive circuit and the N-type transistor (not shown) power device in the low-side drive circuit. When the voltage of output wiring L_OT is near voltage VCC, the potential difference between the voltage VCC of the first voltage wiring L_V1 supplied as the power supply voltage to the level shift circuit LVF and the voltage of output wiring L_OT becomes small, causing the operation of the level shift circuit LVF to become undefined or unstable, and the sense output signal SV_OT is not accurately transmitted to the logic circuit LG_CT.

[0027] Next, an example of a level shift circuit (LVF) will be explained using the diagrams. Figure 10 is a diagram illustrating the level shift circuit according to Comparative Example 1. Here, Figure 10(A) is a circuit diagram showing the configuration of the level shift circuit (LVF), and Figure 10(B) is a waveform diagram showing the operation of the level shift circuit (LVF).

[0028] As shown in Figure 10(A), the level shift circuit LVF comprises N-type transistors NT1 and NT2, a P-channel field-effect transistor (hereinafter also referred to as a P-type transistor) PT1, a resistor R1, a Zener diode ZD1, and a current source IA1_G. The drain-source path of the N-type transistor NT1, resistor R1, and current source IA1_G are connected in series between the first voltage wiring L_V1 and the output wiring L_OT, and the sense output signal SV_OT is supplied to the gate of the N-type transistor NT1. Thus, the inverter circuit corresponding to the amplifier circuit A1 is composed of the N-type transistor NT1, resistor R1, and current source IA1_G. A signal obtained by inverting the phase of the sense output signal SV_OT is output from the connection node between the drain of the N-type transistor NT1 and resistor R1 and supplied to the amplifier circuit A2. Amplifier circuit A2 is composed of an inverter circuit consisting of an N-type transistor NT2 and a P-type transistor PT1 connected in series between the first voltage wiring L_V1 and the second voltage wiring L_V2. Amplifier circuit A2 inverts the phase of the output from amplifier circuit A1 and outputs it as a detection signal OCS. The Zener diode ZD1 clamps the input voltage of amplifier circuit A2 to a predetermined value.

[0029] In Figure 10(B), the vertical axis represents voltage V, and the horizontal axis represents time T. In Figure 10(B), L_V1(VCC) represents the voltage VCC of the first voltage wiring L_V1. Also in Figure 10(B), L_V2(VCCm) represents the voltage VCCm of the second voltage wiring L_V2. Furthermore, in Figure 10(B), L_OT(H) and L_OT(L) represent the voltages of the output wiring L_OT. Here, L_OT(H) represents the voltage of the output wiring L_OT when the power device in the high-side drive circuit becomes conductive, and L_OT(L) represents the voltage of the output wiring L_OT when the power device in the low-side drive circuit becomes conductive. The symbol nsub will be explained later in Figure 4, so its explanation is omitted here.

[0030] The level shift circuit LVF operates to convert (level shift) a signal that changes between voltage L_V1(VCC) and voltage L_OT(H) (sense output signal SV_OT) into a signal that changes between voltage L_V1(VCC) and voltage L_V2(VCCm) (detection signal OCS). However, as shown in Figure 10(B), when the voltage of output wiring L_OT becomes voltage L_OT(H), the potential difference between the voltage VCC of the first voltage wiring L_V1 supplying power to amplifier circuit A1 and the voltage L_OT(H) of output wiring L_OT is compressed and becomes small. As a result, even if the sense output signal SV_OT supplied to amplifier circuit A1 is at a high level, amplifier circuit A1 has difficulty transmitting the low level to amplifier circuit A2.

[0031] In other words, while the first overcurrent detection circuit OC1 according to Comparative Example 1 allows the supply destination of the boosted voltage generated by the charge pump circuit CP_CT to the first comparison circuit CMP1 (Figure 9), a new problem arises: difficulty in transmitting the sense signal.

[0032] <<Comparative Example 2>> As Comparative Example 1 has the aforementioned problems, the inventors have developed an overcurrent detection circuit according to Comparative Example 2, which adds a current-sensing N-type transistor CSNT, a current detection circuit CS, and a second overcurrent detection circuit OC2, as shown in Figure 9.

[0033] The current-sensing N-type transistor CSNT has its drain connected to the first voltage wiring L_V1, its source connected to the current sensing circuit CS, and its gate connected to the gate of the N-type transistor PWT. The size of the current-sensing N-type transistor CSNT is 1 / K2 (hereinafter, K2 is also referred to as the size ratio) relative to the size of the N-type transistor PWT, similar to the sense device N-type transistor SNT. As a result, when both the N-type transistor PWT and CSNT are conducted by the drive buffer DRVB, the value of the current flowing through the drain-source path of the N-type transistor CSNT (sensing current) is 1 / K2 times smaller than the value of the current flowing through the drain-source path of the N-type transistor PWT. Note that the size ratio K2 may be the same as or different from the size ratio K1.

[0034] The current sensing circuit CS comprises a second comparator circuit CMP2 and a P-type transistor PT2. The source of the P-type transistor PT2 is connected to the drain of the current-sensing N-type transistor CSNT, and its drain is connected to the sensing current terminal OCI_OT. The pair of input terminals of the second comparator circuit CMP2 are connected to the source of the N-type transistor PWT and the source of the current-sensing N-type transistor CSNT, and the output terminal is connected to the gate of the N-type transistor PT2. This second comparator circuit CMP2 operates using the voltage VCC in the first voltage wiring L_V1 and the voltage VCCm in the second voltage wiring L_V2 as power supply voltages, and controls the P-type transistor PT2 so that the current flowing through it is proportional to the current flowing through the N-type transistor PWT. As a result, it is possible to determine the value of the current flowing through the N-type transistor PWT by measuring the current at the sensing current terminal OCI_OT outside the semiconductor device CHP.

[0035] The second overcurrent detection circuit OC2 comprises a P-type transistor PT3, N-type transistors NT3 and NT4, a current source IC_G, and an inverter circuit IV1. The source of the P-type transistor PT3 is connected to the source of the P-type transistor PT2, and its gate is connected to the gate of the P-type transistor PT2. The source of the N-type transistor NT3 is connected to the fourth voltage wiring L_V4, and its drain and gate are connected to the drain of the P-type transistor PT3 and further to the gate of the N-type transistor NT4. The drain of the N-type transistor NT4 is connected to the first voltage wiring L_V1 via the current source IC_G and also to the logic circuit LG_CT via the inverter circuit IV1. The source of the N-type transistor NT4 is also connected to the fourth voltage wiring L_V4. This fourth voltage wiring L_V4 is supplied with a ground voltage VSS from outside the semiconductor device CHP.

[0036] A current mirror circuit is formed by N-type transistors NT3 and NT4, and a current proportional to the current flowing through P-type transistor PT2, i.e., the current flowing through the current-sensing N-type transistor CSNT, is supplied to the current mirror circuit via P-type transistor PT3. The inverter circuit IV1 receives a voltage input corresponding to the difference between the current generated by the current source IC_G and the current output from the current mirror circuit. For example, if the current flowing through the current-sensing N-type transistor CSNT is greater than the current generated by the current source IC_G, the input to the inverter circuit IV1 becomes low level, and a high-level signal is supplied from the inverter circuit IV1 to the logic circuit LG_CT. As a result, the logic circuit LG_CT generates a high-level detection output signal, which is output to the outside of the semiconductor device CHP via the detection output terminal OC_OT, and is also supplied as an operation control signal cp-stop to the gates of the charge pump circuit CP_CT and the shutdown N-type transistor SHT.

[0037] In the configuration of Comparative Example 2, when the voltage at output wiring L_OT is near voltage VCC, the second overcurrent detection circuit OC2 detects the overcurrent, and when the voltage is near voltage VCCm, the first overcurrent detection circuit OC1 detects the overcurrent. Figure 11 is a diagram illustrating the overcurrent detection according to Comparative Example 2. In Figure 11, the horizontal axis shows the voltage at output wiring L_OT, with the voltage increasing from left to right. Also in Figure 11, the vertical axis shows the current (drain-source current) Ids flowing through the N-type transistor PWT.

[0038] In Figure 11, the normal region indicates a region where no overcurrent is detected, the region indicated by the symbol OC1 indicates a region where overcurrent is detected by the first overcurrent detection circuit OC1, and the region indicated by the symbol OC2 indicates a region where overcurrent is detected by the second overcurrent detection circuit OC2. Note that the second overcurrent detection circuit OC2 cannot detect overcurrent if the voltage of the output wiring L_OT is lower than the voltage VCCm.

[0039] <<<Issues of Comparative Example 2>>> In Comparative Example 2, overcurrent is detected by two overcurrent detection circuits, the first overcurrent detection circuit OC1 and the second overcurrent detection circuit OC2, making the control of the two overcurrent detection circuits complex. Furthermore, a current detection circuit CS is required to configure the second overcurrent detection circuit OC2, increasing the occupied area. Moreover, when the semiconductor device CHP is equipped with multiple drive circuits (high-side drive circuits and low-side drive circuits) to create a multi-channel system, the second overcurrent detection circuit OC2 can be shared among multiple drive circuits, but the current detection circuit CS needs to be provided for each of the multiple drive circuits, resulting in a further increase in occupied area.

[0040] In other words, while Comparative Example 2 can solve the problems of Comparative Example 1, it presents new challenges such as increased control complexity and an increase in occupied area.

[0041] <<Comparative Example 3>> Since problems still existed in Comparative Example 2, the inventors conducted further studies and developed the overcurrent detection circuit according to Comparative Example 3. Figure 12 shows the configuration of the overcurrent detection circuit according to Comparative Example 3. In Comparative Example 3, the level shift circuit LVF (Figure 9) described in Comparative Example 1 has been modified. Only the modified part is shown in Figure 12.

[0042] In Comparative Example 3, amplifier circuits A3 and A4, which use the voltage outp6v generated by the charge pump circuit CP_CT (Figure 9) and supplied to the third voltage wiring L_V3 as the power supply voltage, are added to the level shift circuit LVF. That is, in Comparative Example 3, as shown in Figure 12(A), an amplifier circuit A3 is added that amplifies the sense output signal SV_OT from the first comparator circuit CMP1 (Figure 9) using the voltage outp6v at the third voltage wiring L_V3 and the voltage at the output wiring L_OT as the power supply voltage. Furthermore, as shown in Figure 12(A), an amplifier circuit A4 is added that amplifies the output signal from amplifier circuit A3 using the voltage outp6v at the third voltage wiring L_V3 and the voltage VCCm at the second voltage wiring L_V2 as the power supply voltage. The output of amplifier circuit A4 is connected to the output of the level shift circuit LVF and combined to form the detection signal OCS. The configuration of the level shift circuit LVF is the same as that described in Figure 10.

[0043] From a different perspective, in Comparative Example 3, a first signal path PS1 passes through amplifier circuits A1 and A2, which constitute the level shift circuit LVF, as a path for transmitting the sense output signal SV_OT. A second signal path PS2 (a signal path passing through amplifier circuits A3 and A4) is added in parallel to this signal path PS1, and the outputs of signal path PS1 and signal path PS2 are combined. As a result, when the power supply voltage of amplifier circuit A1 collapses and the output of amplifier circuit A1 does not become low level, it becomes possible to transmit a low level at the output of amplifier circuit A3.

[0044] A specific example of the block diagram shown in FIG. 12(A) is shown in FIG. 12(B). The amplifier circuit A3 includes a resistor R2, an N-type transistor NT3, and a current source IA2_G that are connected in series between the third voltage wiring L_V3 and the output wiring L_OT. A sense output signal SV_OT is supplied to the gate of the N-type transistor NT3, and the output signal of the amplifier circuit A3 is taken out from the connection node between the resistor R2 and the N-type transistor NT3.

[0045] The amplifier circuit A4 includes a P-type transistor PT2 and a resistor R3 that are connected in series between the third voltage wiring L_V3 and the second voltage wiring L_V2. In FIG. 12(B), the symbol BDD indicates a body diode formed between the drain and the back gate of the P-type transistor PT2. The output signal from the amplifier circuit A3 is supplied to the gate of the P-type transistor PT2, and the output signal of the amplifier circuit A4 is taken out from the connection node between the resistor R3 and the drain of the P-type transistor PT2.

[0046] The amplifier circuits A3 and A4 can also be regarded as inverter circuits because, like the amplifier circuits A1 and A2, they output an output signal with a phase inversion with respect to the signal supplied to the gate of the transistor. Since the level shift circuit LVF has been described in FIG. 10, the description thereof is omitted.

[0047] <<<Operation of Comparative Example 3>>> FIG. 13 is a waveform diagram for explaining the operation of Comparative Example 3. The operation of Comparative Example 3 shown in FIG. 12 changes depending on the voltage of the output wiring L_OT. FIG. 13(A) shows the operation when the voltage of the output wiring L_OT is less than the voltage VCC of the first voltage wiring L_V1 and exceeds the voltage VCCm of the second voltage wiring L_V2 (VCCm < L_OT(V) ≤ VCC). On the other hand, FIG. 13(B) shows the operation when the voltage in the output wiring L_OT is much smaller than the voltage VCC in the first voltage wiring L_V1 (L_OT(V) << VCC).

[0048] In Figures 13(A) and (B), the horizontal axis T represents time, and the vertical axis V represents voltage. Time progresses in the direction of the arrows on the horizontal axis, and voltage increases in the direction of the arrows on the vertical axis. Also in Figure 13, L_V3(V) represents the voltage of the third voltage wire L_V3, and L_OT(V) represents the voltage of the output wire L_OT. Similarly, in Figure 13, L_V1(VCC) represents the voltage of the first voltage wire L_V1, and L_V2(VCCm) represents the voltage of the second voltage wire L_V2.

[0049] As shown in Figure 13(A), when the voltage L_OT(V) of the output wiring L_OT is equal to or less than the voltage L_V1(VCC) of the first voltage wiring L_V1, that is, when the voltage L_OT(V) is close to the voltage VCC, the power supply voltage A1_PW of the amplifier circuit A1, which is the potential difference between the first voltage wiring L_V1 and the output wiring L_OT, becomes small (collapses). Therefore, no level shift is performed by the amplifier circuits A1 and A2.

[0050] At this time, the voltage L_OT(V) of the output wiring L_OT is higher than the voltage L_V2(VCCm) of the second voltage wiring L_V2, and the voltage L_V3(outp6v) of the third voltage wiring L_V3 is even higher than the voltage L_OT(V). Therefore, the power supply voltage A3_PW of the amplifier circuit A3, which is the potential difference between the voltage L_V3(outp6v) of the third voltage wiring L_V3 and the voltage L_OT(V) of the output wiring L_OT, becomes large, and a level shift is performed by amplifier circuits A3 and A4, so that the output IO_Out, which changes between, for example, voltage L_V1(VCC) and voltage L_V2(VCCm), is output from amplifier circuit A4.

[0051] In contrast, in Figure 13(B), the voltage L_OT(V) is much smaller than the voltage L_V1(VCC), and consequently the voltage L_V3(outp6v) is also smaller than the voltage L_V(VCCm), so no level shift occurs by amplifier circuits A3 and A4. In this case, the power supply voltage A1_PW of amplifier circuit A1 becomes larger, so a level shift occurs by amplifier circuits A1 and A2, and the output IO_Out, which changes between the voltages L_V1(VCC) and L_V2(VCCm), is output from amplifier circuit A2.

[0052] <<<Challenges of Comparative Example 3>>> According to Comparative Example 3, although it is necessary to supply the voltage output6v generated by the charge pump circuit CP_CT to the amplifier circuits A3 and A4, it is possible to suppress the amount of current supplied from the charge pump circuit CP_CT to the amplifier circuits A3 and A4 to a small extent. Furthermore, the current detection circuit CS and the second overcurrent detection circuit OC2 (Figure 9) described in Comparative Example 2 can be eliminated. Therefore, it is possible to reduce the complex control and suppress the increase in occupied area, which was a problem in Comparative Example 2.

[0053] However, it was found that Comparative Example 3 presented the following new problems (1) to (6). These new problems (1) to (6) will be explained with reference to Figures 14 to 16. Figures 14 to 16 are diagrams illustrating the problems of Comparative Example 3.

[0054] Figure 14 is a diagram illustrating problems (1) and (2). Here, Figure 14(A) is similar to Figure 12(B), and Figure 14(B) is similar to Figure 13(A). The main difference is that problems (1) and (2) are explicitly shown in Figures 14(A) and (B).

[0055] Problem (1): When the voltage L_OT(V) of the output wiring L_OT is close to the voltage VCC, as shown in Figure 14(B), the power supply voltage A1_PW of the amplifier circuit A1 (Figure 12), which is composed of resistor R1, N-type transistor NT1, and current source IA1_G, becomes small. This raises concerns that the output of amplifier circuit A1 will become undefined, and the output of amplifier circuit A2, composed of N-type transistor NT2 and P-type transistor PT1, will also become undefined. When the output of amplifier circuit A2 becomes undefined, the high-level output signal from amplifier circuit A4, composed of P-type transistor PT2 and resistor R3, may be inhibited by the undefined output from amplifier circuit A2, resulting in undefined signals that could propagate.

[0056] Problem (2): A voltage L_V3 (outp6v) higher than voltage VCC will be applied to the N-type transistor NT2 and P-type transistor PT1 via the P-type transistor PT2. It is conceivable that this high voltage L_V3 (outp6v) will destroy the N-type transistor NT2 and / or the P-type transistor PT1.

[0057] Figure 15 is a diagram illustrating problems (3) and (4). Here, Figure 15(A) is similar to Figure 12(B), and Figure 15(B) is similar to Figure 13(B). The main difference is that problems (3) and (4) are explicitly shown in Figures 15(A) and (B). Also, in Figure 15(A), the circuit connections between elements are the same as in Figure 12(B), but the arrangement of elements has been changed so that the wiring with higher voltage is higher on the page. That is, in Figure 15(A), the wirings L_V1, L_V2, L_V3 and L_OT are arranged from the top to the bottom of the page in the order of voltages L_V1(VCC), L_V2(VCCm), L_V3(outp6v), and L_OT(V) shown in Figure 15(B).

[0058] Problem (3): Because the sense output signal SV_OT is at a high level, the voltage L_V1 (VCC) should be output as the detection signal OCS via the P-type transistor PT1, but it is possible that this is not transmitted. This is because if the on-resistance of the P-type transistor PT2 is high, the body diode BDD of the P-type transistor PT2 appears as a load on the P-type transistor PT1, and the high-level detection signal OCS is transmitted to the third voltage wiring L_V3 via the body diode BDD. In this case, the body diode BDD is connected to the voltage VCC via the P-type transistor PT1, and it is possible that it may be destroyed (BRK).

[0059] Problem (4): The drains of the P-type transistor PT1 and the N-type transistor NT2 will have a voltage L_V3 (outp6v) applied to them, for example, via the body diode BDD of the P-type transistor PT2, which is lower than the voltage L_V2 (VCCm). In other words, the drains of the P-type transistor PT1 and the N-type transistor NT2 will have a voltage lower than the normally applied voltage VCCm, which could lead to the P-type transistor PT1 and / or the N-type transistor NT2 being destroyed (BRK).

[0060] Figure 16 is a diagram illustrating problems (5) and (6). Here, Figure 16(A) is similar to Figure 15(A), and Figure 16(B) is similar to Figure 15(B). The main difference is that Figure 16 shows the state when the sense output signal SV_OT is at a low level, and problems (5) and (6) are explicitly stated.

[0061] Problem (5): Since the sense output signal SV_OT is at a low level, the voltage L_V2 (VCCm) should be output as the detection signal OCS via the N-type transistor NT2, but it is possible that this is not transmitted. This is because the body diode BDD of the P-type transistor PT2 appears as a load to the N-type transistor PT2, and the low-level (Vccm) detection signal OCS is transmitted to the third voltage wiring L_V3 via the body diode BDD. Also, since the voltage L_V2 (VCCm) is applied to the body diode BDD, it is possible that the body diode BDD is destroyed (BRK).

[0062] Problem (6): The drains of the P-type transistor PT1 and the N-type transistor NT2 will have a voltage L_V3 (outp6v) applied to them, for example, via the body diode BDD, which is lower than the voltage L_V2 (VCCm). In other words, the drains of the P-type transistor PT1 and the N-type transistor NT2 will have a voltage lower than the normally applied voltage VCCm, which could lead to the P-type transistor PT1 and / or the N-type transistor NT2 being destroyed (BRK).

[0063] As problems exist in Comparative Example 3, the inventors conducted further studies and realized a semiconductor device equipped with an overcurrent detection circuit according to the embodiment described below. As will be explained in detail later, in this embodiment, the two signal paths PS1 and PS2 used in Comparative Example 3 are used in an improved form.

[0064] (Embodiment 1) <Semiconductor device> Figure 1 is a block diagram showing the configuration of a semiconductor device according to Embodiment 1. In Figure 1, the semiconductor device CHP, indicated by the dashed line, comprises a semiconductor chip, a package that encloses the semiconductor chip, and external terminals protruding from the package.

[0065] The semiconductor device CHP has numerous external terminals, but only the external terminals necessary for explanation are shown on the dashed lines in Figure 1. In Figure 1, VCC represents the power supply external terminal, and VSS represents the grounding external terminal. Also in Figure 1, OC_OT represents the detection output external terminal (hereinafter also referred to as the detection output terminal), and DR_OT represents the output external terminal (hereinafter simply referred to as the output terminal). These external terminals are electrically connected to the circuit block formed on the semiconductor chip within the package. Also in Figure 1, LOD represents the load connected between the output terminal DR_OT and the grounding external terminal VSS.

[0066] Although multiple circuit blocks are formed on the semiconductor chip, only the circuit blocks necessary for explanation are shown in Figure 1. As circuit blocks, Figure 1 shows the drive circuit DRV and the control circuit CNT. The control circuit CNT generates the high-side drive signal DRV_H and the low-side drive signal DRV_L according to the input signal IN and supplies them to the drive circuit DRV. The drive circuit DRV comprises the high-side drive circuit HDD, the low-side drive circuit LDD, and the input / output circuit IO_CT.

[0067] The high-side drive circuit HDD is connected to the external power supply terminal VCC and the output terminal DR_OT. It is also connected to the detection output terminal OC_CT via the input / output circuit IO_CT. The high-side drive circuit HDD generates a drive signal according to the high-side drive signal DRV_H and supplies it to the output terminal DR_OT. The low-side drive circuit LDD is connected to the external power supply terminal VCC, the output terminal DR_OT, and the external ground terminal VSS. The low-side drive circuit LDD generates a drive signal according to the low-side drive signal DRV_L and supplies it to the output terminal DR_OT. The drive signals generated by the high-side drive circuit HDD and the low-side drive circuit LDD are combined at the output terminal DR_OT and supplied to the load LOD. As a result, the load LOD is driven based on the input signal IN.

[0068] <<High-side drive circuit>> Next, the configuration of the high-side drive circuit HDD will be explained. The high-side drive circuit HDD includes a charge pump circuit CP_CT, which is a boost circuit, a drive buffer DRVB, an N-type transistor PWT, which is a power device, an N-type transistor SHT for shutdown, and an overcurrent detection circuit OCD.

[0069] The charge pump circuit CP_CT is connected to the first voltage wiring L_V1, the second voltage wiring L_V2, the third voltage wiring L_V3, and the output wiring L_OT. The first voltage wiring L_V1 is connected to the external power supply terminal VCC, and the power supply voltage (first voltage) VCC is supplied to the first voltage wiring L_V1 from outside the semiconductor device CHP via this external terminal. The output wiring L_OT is connected to the output terminal DR_OT.

[0070] The second voltage wiring L_V2 is supplied with a voltage (second voltage) VCCm, which is lower than the voltage VCC. This voltage VCCm is generated from the voltage VCC by a step-down circuit (not shown) within the semiconductor device CHP, although this is not particularly limited. The value of the voltage VCCm is VCC-6V, although this is not particularly limited.

[0071] The charge pump circuit CP_CT generates a voltage of a predetermined value (e.g., 6V) based on the voltage VCC supplied via the first voltage wiring L_V1 and the voltage VCCm supplied via the second voltage wiring L_V2, adds (superimposes) this voltage on the output wiring L_OT, and supplies power to the third voltage wiring L_V3. In other words, the third voltage wiring L_V3 is supplied with a voltage of output wiring L_OT + 6V (hereinafter referred to as voltage outp6v or boosted voltage, as in the <Comparative Example>) from the charge pump circuit CP_CT.

[0072] The drive buffer DRVB is connected to the third voltage wire L_V3 and the output wire L_OT, and operates using the voltage outp6v of the third voltage wire L_V3 and the voltage at the output wire L_OT as the power supply voltage. In this operation, the drive buffer DRVB buffers and outputs the high-side drive signal DRV_H from the control circuit CNT.

[0073] The drain of the N-type transistor PWT is connected to the first voltage wire L_V1, and its source is connected to the output wire L_OT. In other words, the drain-source path of the N-type transistor PWT is connected in series between the first voltage wire L_V1 and the output wire L_OT. The gate of the N-type transistor PWT is also connected to the output terminal of the drive buffer DRVB.

[0074] The drain of the shutdown N-type transistor SHT is connected to the output terminal of the drive buffer DRVB, and its source is connected to the output wiring L_OT.

[0075] The overcurrent detection circuit OCD is connected to the first voltage wiring L_V1, the second voltage wiring L_V2, the third voltage wiring L_V3, the output wiring L_OT, the output terminal of the drive buffer DRVB, and the gate of the shutdown N-type transistor SHT. Furthermore, the overcurrent detection circuit OCD is connected to the detection output terminal OC_OT via the input / output circuit IO_CT.

[0076] The overcurrent detection circuit (OCD), which will be explained in detail later, senses the current (drain-source current) flowing through the N-type transistor PWT based on the output of the drive buffer DRVB. When an overcurrent flows through the N-type transistor PWT, it supplies an overcurrent detection signal to the input / output circuit IO_CT and simultaneously turns on the shutdown N-type transistor SHT with the operation control signal cp-stop. This prevents the N-type transistor PWT from being destroyed by overcurrent.

[0077] The input / output circuit IO_CT is connected to the first voltage wiring L_V1 and the external grounding terminal VSS, and operates using the voltage VCC of the first voltage wiring L_V1 and the voltage (ground voltage) VSS at the external grounding terminal VSS as the power supply voltage. Through this operation, the input / output circuit IO_CT converts the detection signal from the overcurrent detection circuit OCD into a detection signal that changes between the voltage VCC and the ground voltage VSS. The converted detection signal is output to the outside of the semiconductor device CHP from the detection output terminal OC_OT.

[0078] <<<Overcurrent detection circuit>>> The overcurrent detection circuit OCD comprises a sense circuit SN_CT, a detection current generation circuit DCG, and a logic circuit (output circuit) LG_CT.

[0079] The sense circuit SN_CT comprises an N-type transistor SNT as a sense device, a sense resistor Rs, a first comparator circuit CMP1, and a reference voltage Vrf. Here, the drain of the N-type transistor SNT is connected to the first voltage wiring L_V1, and its source is connected to the output wiring L_OT via the sense resistor Rs. The positive input (sign +) of the first comparator circuit CMP1 is connected to the connection node connecting the source of the N-type transistor SNT and the sense resistor Rs, and the negative input (-) is connected to the output wiring L_OT via the reference voltage Vrf. The first comparator circuit CMP1 is also connected to the third voltage wiring L_V3 and the output wiring L_OT, and uses the voltage outp6v in the third voltage wiring L_V3 and the voltage in the output wiring L_OT as power supply voltages to perform a comparison operation between the sense voltage Vs at the positive input (+) and the reference voltage Vrf at the negative input (-).

[0080] Here, the size of the N-type transistor SNT is 1 / K1 of the size of the N-type transistor PWT, as explained in Figure 9. As a result, when both the N-type transistor PWT and SNT are made conductive by the drive buffer DRVB, the current (sense current) Is flowing through the drain-source path of the N-type transistor SNT is proportional to the drain-source current flowing through the drain-source path of the N-type transistor PWT, and is 1 / K1 times smaller than the value of the drain-source current of the N-type transistor PWT. The first comparator circuit CMP1 compares the sense voltage Vs generated at the sense resistor Rs by the sense current Is with the reference voltage Vrf. The first comparator circuit CMP1 outputs the comparison result to the sense current generation circuit DCG as a sense output signal SV_OT that changes between the voltage outp6v at the third voltage wiring L_V3 and the voltage at the output wiring L_OT.

[0081] The sensing current generation circuit DCG is connected to the first voltage wire L_V1, the second voltage wire L_V2, the third voltage wire L_V3, and the output wire L_OT, and operates using the voltages in these wires as the power supply voltage. Through this operation, the sensing current generation circuit DCG outputs a current from the sensing output node DC_OT according to the sense output signal SV_OT supplied from the sense circuit SN_CT. The sensing current generation circuit DCG will be explained in detail later using diagrams, so no further explanation is provided here.

[0082] The logic circuit LG_CT is connected to the first voltage wire L_V1 and the second voltage wire L_V2, and operates using the voltage VCC of the first voltage wire L_V1 and the voltage VCCm of the second voltage wire L_V2 as power supply voltages. Through this operation, the logic circuit LG_CT generates a detection signal with a voltage value according to the value of the current output from the detection output node, and an operation control signal cp-stop. The detection signal generated here is a signal that changes between voltage VCC and voltage VCCm.

[0083] <Low-side drive circuit> The low-side drive circuit LDD, like the high-side drive circuit HDD, includes a power device and an overcurrent detection circuit. However, in Figure 1, only the N-type transistor PWT_LDD, which is the power device, is shown by a dashed line. The drain of the N-type transistor PWT_LDD is connected to the output wiring L_OT, and the source is connected to the external ground terminal VSS via the voltage wiring shown by the dashed line. The gate of the N-type transistor PWT_LDD is supplied with the low-side drive signal DRV_L.

[0084] The control circuit CNT, in accordance with the input signal IN, sets the high-side drive signal DRV_H and the low-side drive signal DRV_L to complementary high levels, although this is not particularly limited. As a result, when the low-side drive signal DRV_L is set to a high level, the ground voltage VSS is supplied to the output wiring L_OT and output terminal DR_OT via the conducting N-type transistor PWT_LDD. Conversely, when the high-side drive signal DRV_H is set to a high level, the voltage VCC is supplied to the output wiring L_OT and output terminal DR_OT via the conducting N-type transistor PWT. Consequently, the voltages at the output wiring L_OT and output terminal DR_OT vary between the voltage VCC and the ground voltage VSS in accordance with the input signal IN.

[0085] <<<Sensing Current Generation Circuit>>> Next, the detection current generation circuit according to Embodiment 1 will be described with reference to the drawings. Figure 2 is a block diagram showing the configuration of the detection current generation circuit according to Embodiment 1. The detection current generation circuit DCG comprises a first control circuit C1_CT, a second control circuit C2_CT, a first current circuit I1_CT, a second current circuit I2_CT, a first current source I1_G, and a voltage limiting circuit (hereinafter also simply referred to as a limiting circuit) LM_CT.

[0086] The first control circuit C1_CT is connected to the first voltage wiring L_V1 and the output wiring L_OT, and operates using the voltage VCC of the first voltage wiring L_V1 and the voltage at the output wiring L_OT as the power supply voltage. Through this operation, the first control circuit C1_CT outputs a signal to the first current circuit I1_CT according to the sense output signal SV_OT from the sense circuit SN_CT. The signal output from the first control circuit C1_CT is a voltage signal that changes between the voltage VCC and the voltage at the output wiring L_OT. The first current circuit I1_CT is connected between the first voltage wiring L_V1 and the detection output node DC_OT of the detection current generation circuit DCG, and supplies a predetermined value of current (second current) I2 to the detection output node DC_OT according to the voltage signal from the first control circuit C1_CT.

[0087] The second control circuit C2_CT is connected to the third voltage wire L_V3 and the output wire L_OT, and operates using the voltage outp6v of the third voltage wire L_V3 and the voltage at the output wire L_OT as the power supply voltage. Through this operation, the second control circuit C2_CT outputs a signal according to the sense output signal SV_OT to the second current circuit I2_CT. The signal output from the second control circuit C2_CT is a voltage signal that changes between the voltage outp6v and the voltage at the output wire L_OT. The second current circuit I2_CT is connected between the third voltage wire L_V3 and the limiting circuit LM_CT, and supplies a predetermined value of current (third current) I3 to the limiting circuit LM_CT according to the voltage signal from the second control circuit C2_CT.

[0088] The first current source I1_G is connected between the detection output node DC_OT and the second voltage wiring L_V2. The first current source I1_G supplies a predetermined current (first current) I1, which is smaller than the second currents I2 and I3, from the detection output node DC_OT to the second voltage wiring L_V2. The values ​​of the second current I2 and the third current I3 may be equal or different, but each of the values ​​of the second current I2 and the third current I3 is greater than the value of the first current I1 (I2, I3 > I1).

[0089] The limiting circuit LM_CT is connected between the second current circuit I2_CT and the detection output node DC_OT. The limiting circuit LM_CT restricts the voltage at the detection output node DC_OT so that it does not exceed the voltage VCC of the first voltage wiring L_V1, and also restricts it so that it does not fall below the voltage VCCm of the second voltage wiring L_V2.

[0090] In Figure 2, the improved signal path PSA1 is configured by the first control circuit C1_CT and the first current circuit I1_CT, and the improved signal path PSA2 is configured by the second control circuit C2_CT, the second current circuit I2_CT, and the limiting circuit LM_CT. In signal path PSA1, the second current I2 is supplied to the detection output node DC_OT according to the voltage of the sense output signal SV_OT. In signal path PSA2, the third current I3 is supplied to the detection output node DC_OT according to the voltage of the sense output signal SV_OT. At the detection output node DC_OT, the second current I2, the third current I3, and the first current I1 are combined (I2 + I3 - I1), and the result of the combination is output from the detection output node DC_OT. Since the values ​​of the second current I2 and the third current I3 are greater than the value of the first current I1, the combined current (I2+I3) can be made greater than the first current I1, regardless of the voltage in the output wiring L_OT. Therefore, it is possible to output a current equivalent to a high level from the detection output node DC_OT.

[0091] Furthermore, the limiting circuit LM_CT limits the voltage at the detection output node DC_OT, preventing the circuits connected to the detection output node DC_OT and the second current circuit I2_CT from being damaged by high voltage.

[0092] In Figure 2, the symbol vd2 indicates the voltage at the connection node connecting the second current circuit I2_CT and the limiting circuit LM_CT.

[0093] <<<<An example of a detection current generation circuit>>>> Next, a specific example of the detection current generation circuit DCG described in Figure 2 will be explained using drawings. Figure 3 is a circuit diagram showing the configuration of the detection current generation circuit according to Embodiment 1.

[0094] The sensing current generation circuit DCG is composed of N-type transistors N1 and N2, P-type transistors P1 to P4, PH1 and PH2, and current sources (first current source to fourth current source) I1_G to I4_G.

[0095] The correspondence between the block diagram in Figure 2 and the circuit diagram in Figure 3 is as follows: The first control circuit C1_CT shown in Figure 2 is composed of a second current source I2_G, an N-type transistor N1, and a P-type transistor P3. The second control circuit C2_CT is composed of a third current source I3_G, an N-type transistor N2, and a P-type transistor P4. Furthermore, the first current circuit I1_CT is composed of a P-type transistor P1, and the second current circuit I2_CT is composed of a P-type transistor P2. In addition, the limiting circuit LM_CT is composed of a fourth current source I4_G and P-type transistors PH1 and PH2.

[0096] The drain-source path of the P-type transistor P3, the drain-source path of the N-type transistor N1, and the second current source I2_G are connected in series between the first voltage wiring L_V1 and the output wiring L_OT. The drain-source path of the P-type transistor P1 is connected between the first voltage wiring L_V1 and the sense output node DC_OT. The gate of the P-type transistor P1 is connected to the gate and drain of the P-type transistor P3 so that it forms a current mirror circuit with the P-type transistor P3. The sense output signal SV_OT is supplied to the gate of the N-type transistor N1.

[0097] The drain-source path of the P-type transistor P4, the drain-source path of the N-type transistor N2, and the third current source I3_G are connected in series between the third voltage wiring L_V3 and the output wiring L_OT. The drain-source path of the P-type transistor P2 is connected between the third voltage wiring L_V3 and the limiting circuit LM_CT. The gate of the P-type transistor P2 is connected to the gate and drain of the P-type transistor P4 so that it forms a current mirror circuit with the P-type transistor P4. The sense output signal SV_OT is supplied to the gate of the N-type transistor N2.

[0098] The drain of P-type transistor PH1 is connected to P-type transistor P2, and its source is connected to the detection output node DC_OT. The drain of P-type transistor PH2 is connected to the first voltage wiring L_V1, and its source is connected to the detection output node DC_OT via the fourth current source I4_G. The gate of P-type transistor PH2 is connected to the source of P-type transistor PH2 and the gate of P-type transistor PH1. This connection of the source and gate of P-type transistor PH2 applies a bias voltage vb to the gates of P-type transistors PH1 and PH2, which is the voltage VCC minus the threshold voltage of P-type transistor PH2 (VCC - threshold voltage). Since the threshold voltages of P-type transistor PH2 and P-type transistor PH1 are essentially the same, the value of the bias voltage vb can also be considered as the voltage VCC minus the threshold voltage of P-type transistor PH1.

[0099] The back gates of the P-type transistors PH1 and PH2 are connected to the voltage VCC of the first voltage wiring L_V1. As a result, body diodes BDD are formed between the source and back gate of the P-type transistors PH1 and PH2, and between the drain and back gate of the P-type transistors PH1 and PH2, as shown in Figure 3.

[0100] As shown in FIG. 3, since the back gates of the P-type transistors P2 and P4 are connected to the third voltage wiring L_V3, a body diode BDD is also formed between the drains and the back gates of the P-type transistors P2 and P4.

[0101] In FIG. 3, the transistors whose gate indicating lines are thick lines, that is, the P-type transistors PH1 and PH2 and the N-type transistor N1, have a structure in which the breakdown voltage between the drain and the gate and the breakdown voltage of the gate are high. For example, the breakdown voltage between the drain and the gate of the P-type transistors PH1 and PH2 and the N-type transistor N1 is higher than the breakdown voltage between the source and the gate of the P-type transistors PH1 and PH2 and the N-type transistor N1, and is also higher than the breakdown voltage between the source and the gate and between the drain and the gate of the P-type transistors P1 to P4 and the N-type transistor N2. Further, the breakdown voltage of the gates of the P-type transistors PH1 and PH2 and the N-type transistor N1 is higher than the breakdown voltage of the gates of the P-type transistors P1 to P4 and the N-type transistor N2.

[0102] <<<<Structure of P-type transistors PH1 and PH2>>>> The structure of a transistor in which the breakdown voltage between the drain and the gate is higher than the breakdown voltage between the source and the gate will be described using the drawing with the P-type transistor PH1 as an example. Here, the case of manufacturing the P-type transistor PH1 with a high breakdown voltage in a manufacturing process that enables reduction of the manufacturing cost will be described.

[0103] FIG. 4 is a cross-sectional view showing a cross-section of the semiconductor chip according to the first embodiment. In the figure, a cross-section of the P-type transistor (the fifth P-type transistor) PH1 is shown. Of course, the P-type transistor (the sixth P-type transistor) PH2 is also formed in the same manner as PH1.

[0104] In Figure 4, nsub represents an N-type semiconductor substrate, which is the substrate for the semiconductor chip. The N-type semiconductor substrate nsub is connected to the first voltage wiring L_V1, but is not particularly restricted, so that a voltage VCC is applied to it. Note that the symbol nsub shown in the comparative example drawing (for example, Figure 10(B)) represents the voltage of this N-type semiconductor substrate.

[0105] Multiple transistors, such as the P-type and N-type transistors shown in Figures 1 and 2, are formed on the N-type semiconductor substrate nsub. Of these transistors, only the region where the P-type transistor PH1 is formed is shown in Figure 4.

[0106] In the region where the P-type transistor PH1 is formed, a P-type well (pwell) and an N-type well (nwell) are formed to surround the P-type well (pwell) when viewed in plan view. The N-type well (nwell) has an N-type semiconductor region (N+) that constitutes the back gate (BG) of the P-type transistor PH1. Furthermore, the N-type well (nwell) has a P-type semiconductor region (P+) that is separated from the N-type semiconductor region (N+) by an isolation layer (ISO). This P-type semiconductor region (P+) constitutes the source (S) of the P-type transistor PH1. In addition, the N-type well (nwell) has an N-type semiconductor region (N+) that constitutes the drain (D) of the P-type transistor PH1. In Figure 4, G indicates the gate electrode (gate) formed on the N-type well (nwell) via an insulating film (not shown).

[0107] In the semiconductor device CHP according to Embodiment 1, as shown in Figure 4, the distance DLL between the gate electrode G and the P-type semiconductor region (drain region) P+ constituting the drain D is longer than the distance SLL between the gate electrode G and the P-type semiconductor region (source region) P+ constituting the source S. As a result, in the P-type transistor PH1, the breakdown voltage between the drain and gate is higher than the breakdown voltage between the source and gate.

[0108] Furthermore, as shown in Figure 4, the N-type well (nwell) to which the back gate (BG) is connected is formed without being separated from the N-type semiconductor substrate (nsub) by an isolation layer. Therefore, it is possible to reduce the manufacturing cost associated with forming the isolation layer. However, in such a structure, it is difficult to apply a voltage other than VCC, which is at the same potential as the N-type semiconductor substrate (nsub), to the back gate (BG), and as explained in Figure 3, voltage VCC is supplied.

[0109] <<<Operation of the detection current generation circuit>>> Next, the operation of the detection current generation circuit according to Embodiment 1 will be explained using drawings. Here, the detection current generation circuit will be explained using drawings corresponding to Figures 14 to 16, which were used to explain the problem in Comparative Example 3. Figures 5 to 7 are diagrams for explaining the operation of the detection current generation circuit according to Embodiment 1.

[0110] <<< <VCCm<L_OT(V)≦VCC:SV_OT=ハイレベル> >>> Figure 5, similar to Figure 14, shows the situation when the voltage L_OT(V) of the output wiring L_OT is higher than the voltage VCCm of the second voltage wiring L_V2 and less than or equal to the voltage VCC of the first voltage wiring L_V1, and the sense output signal SV_OT is at a high level (H). Figure 5 shows, for example, the situation when the N-type transistor PWT shown in Figure 1 is conducting, and the voltage of the output wiring L_OT is close to the voltage VCC due to the N-type transistor PWT, and the sense voltage Vs becomes higher than the reference voltage Vrf, indicating that an overcurrent has been detected. Also, the symbols H and L shown in Figure 5 indicate high level and low level, respectively. The meaning of the symbols H and L is the same in Figures 6 and 7 shown later. Because the voltage L_OT(V) of the output wiring L_OT is close to the voltage VCC, the voltage outp6v of the third voltage wiring L_V3 is higher than the voltage VCC of the first voltage wiring L_V1.

[0111] Since the sense output signal SV_OT is high level (H), the N-type transistor N2 becomes conductive. As a result, low levels (L) are supplied to the gates of the P-type transistors P2 and P4. Because the P-type transistors P2 and P4 form a current mirror circuit, the third current I3, which corresponds to the current of the third current source I3_G, is supplied to the P-type transistor PH1 from the third voltage wiring L_V3 via the conductive N-type transistor N2. Since the gate of the P-type transistor PH1 is biased by the bias voltage vb (= voltage VCC - threshold voltage of the P-type transistor PH2), the P-type transistor PH1 supplies the supplied third current I3 to the sense output node DC_OT. At this time, the voltage vd2 at the connection node connecting the drain of the P-type transistor PH1 and the P-type transistor P2 is limited to the voltage VCC. This is because the voltage vd2 is limited to the voltage obtained by adding the threshold voltage of the P-type transistor PH1 to the bias voltage vb, and the voltage vd2 is further limited to the voltage VCC by the body diode BDD connected between the drain and back gate of the P-type transistor PH1.

[0112] Because the voltage L_OT(V) of the output wiring L_OT is close to the voltage VCC, the potential difference applied to the series circuit consisting of the P-type transistor P3, the N-type transistor N1, and the second current source I2_G, which are connected in series between the output wiring L_OT and the first voltage wiring L_V1, approaches 0V, for example, and the power supply voltage of this series circuit collapses. Therefore, even if a high-level (H) sense output signal SV_OT is supplied to the N-type transistor N1, the current flowing through the P-type transistor P3 is very small, or the P-type transistor P3 becomes non-conducting. As a result, the current flowing through the P-type transistor P3 and the P-type transistor P1 that constitutes the mirror circuit is also very small, or almost 0A. This makes it possible to prevent the transmission of an undefined signal to the detection output node DC_OT via the P-type transistor P1.

[0113] At this time, the detection output node DC_OT is supplied with a current equivalent to the difference between the third current I3 from the P-type transistor PH1 and the first current I1 from the first current source I1_G. Since the value of the third current I3 is greater than the value of the first current I1, this difference in current corresponds to a high level (H).

[0114] Furthermore, the voltage vd2 at the connection node connecting the drains of P-type transistor P2 and P-type transistor PH1 is limited to voltage VCC and isolated from the detection output node DC_OT and the third voltage wiring L_V3. This prevents a voltage higher than VCC from being applied to the detection output node DC_OT. Moreover, even if noise is superimposed on the voltage vd2 at the connection node, causing the voltage vd2 to exceed voltage VCC, the body diode BDD of P-type transistor PH1 is connected between the connection node and voltage VCC, so the voltage vd2 is clamped to voltage VCC. This prevents the transistors (e.g., P-type transistors P1, PH1) and the first current source I1_G connected to the detection output node DC_OT from being destroyed by high voltage.

[0115] <<< <L_OT(V)<<VCC:SV_OT=ハイレベル> >>> Figure 6, similar to Figure 15, shows the case where the voltage L_OT(V) of the output wiring L_OT is significantly lower than the voltage VCC of the first voltage wiring L_V1, and the sense output signal SV_OT is at a high level (H). Figure 6 shows, for example, the case when the N-type transistor PWT_LDD in the low-side drive circuit LDD shown in Figure 1 becomes conductive, and the voltage of the output wiring L_OT drops significantly lower than the voltage VCC due to the N-type transistor PWT_LDD, and approaches the ground voltage VSS, and an overcurrent is detected.

[0116] Similar to Figure 15(A), in Figure 6 the circuit connections between elements are the same as in Figure 3, but the arrangement of the elements has been changed so that the wiring with higher voltage is higher on the page. That is, in Figure 6 the voltage decreases in the following order: VCC of the first voltage wiring L_V1, VCCm of the second voltage wiring L_V2, outp6v of the third voltage wiring L_V3, and L_OT(V) of the output wiring L_OT.

[0117] Because the sense output signal SV_OT is at a high level (H), the N-type transistor N2 becomes conductive, and current flows from the third voltage wiring L_V3 to the output wiring L_OT via the third current source I3_G, the N-type transistor N2, and the P-type transistor P4. As a result, the gate voltages of the P-type transistors P4 and P2 become low level (L), and a current smaller than the current I4 flowing through the fourth current source I4_G flows through the P-type transistor P2. The voltage vd2 at the connection node connecting the drain of the P-type transistor P2 and the P-type transistor PH1 becomes close to the voltage outp6v of the third voltage wiring L_V3. At this time, since the bias voltage vb is supplied to the gate of the P-type transistor PH1, the P-type transistor PH1 becomes non-conducting.

[0118] As a result, the connection node connecting the drains of P-type transistor P2 and P-type transistor PH1 is isolated from the detection output node DC_OT, and the voltage outp6v from the third voltage wiring L_V3 is no longer supplied to the detection output node DC_OT. This prevents high voltage from being applied between the second voltage wiring L_V2 and the detection output node DC_OT, and thus prevents, for example, the destruction of the first current source I1_G.

[0119] In the state shown in Figure 6, that is, when the voltage L_OT(V) of the output wiring L_OT drops significantly lower than the voltage VCC of the first voltage wiring L_V1, a large potential difference is supplied to the series circuit consisting of a P-type transistor P3, an N-type transistor N1, and a second current source I2_G, which are connected in series between the first voltage wiring L_V1 and the output wiring L_OT. As a result, the N-type transistor N1 becomes conductive due to the high-level (H) sense output signal SV_OT, and the P-type transistors P1 and P3 also become conductive. Consequently, a second current I2, proportional to the current of the second current source I2_G, is supplied from the P-type transistor P1 to the detection output node DC_OT, and the difference between the second current I2 and the first current I1 is output from the detection output node DC_OT. Since the value of the second current I2 is greater than the value of the first current I1, this difference in current corresponds to a high level (H).

[0120] At this time, the P-type transistor PH1 is in a non-conducting state, and the body diode BDD of the P-type transistor P2 is isolated from the detection output node DC_OT by the P-type transistor PH1. As a result, the body diode BDD does not become a load on the P-type transistor P1 and the first current source I1_G.

[0121] <<< <L_OT(V)<<VCC:SV_OT=ロウレベル> >>> Figure 7, similar to Figure 16, shows the case where the voltage L_OT (V) of the output wiring L_OT is significantly lower than the voltage VCC of the first voltage wiring L_V1, and the sense output signal SV_OT is at a low level (L). Figure 7 shows, for example, the case where the N-type transistor PWT_LDD in the low-side drive circuit LDD shown in Figure 1 is conducting, and the voltage of the output wiring L_OT is significantly lower than the voltage VCC due to the N-type transistor PWT_LDD, and is close to, for example, the ground voltage VSS, and no overcurrent is detected.

[0122] Figure 7 is similar to Figure 6. The main difference is that in Figure 7, the sense output signal SV_OT is at a low level (L). The low level (L) sense output signal SV_OT causes the N-type transistors N1 and N2 to become non-conductive.

[0123] Due to the non-conducting state of the N-type transistor N2, the gate voltages of the P-type transistors P4 and P2 become high (H). As a result, the current flowing through the P-type transistor P2 becomes almost 0A, but since a bias voltage vb is supplied to the gate of the P-type transistor PH1, the voltage vd2 at the connection node connecting the drains of the P-type transistors P2 and PH1 becomes close to the voltage outp6v of the third voltage wiring L_V3, as in the case of Figure 6. Consequently, in the case of Figure 7 as well, the P-type transistor PH1 becomes non-conducting, and the connection node between the detection output node DC_OT and the connection node connecting the drains of the P-type transistors P2 and PH1 is isolated by the P-type transistor PH1. This prevents high voltage from being applied between the second voltage wiring L_V2 and the detection output node DC_OT, and for example, prevents the first current source I1_G from being destroyed.

[0124] Even in the state shown in Figure 7, as explained in Figure 6, a large potential difference is supplied to the series circuit consisting of a P-type transistor P3, an N-type transistor N1, and a second current source I2_G, which are connected in series between the first voltage wiring L_V1 and the output wiring L_OT. As a result, the N-type transistor N1 becomes non-conductive due to the low-level (L) sense output signal SV_OT, and the P-type transistors P1 and P3 also become non-conductive. Consequently, the current supplied from the P-type transistor P1 to the detection output node DC_OT becomes almost 0A, and the difference between the first current I1 and I2 becomes only the first current I1, which corresponds to a low level (L), and the first current I1 is output from the detection output node DC_OT.

[0125] In this case, as shown in Figure 7, the P-type transistor PH1 is in a non-conducting state, and the body diode BDD of the P-type transistor P2 is isolated from the detection output node DC_OT by the P-type transistor PH1. As a result, the body diode BDD does not become a load for the first current source I1_G.

[0126] As shown in Figure 5, when the voltage L_OT(V) of the output wiring L_OT is close to the voltage VCC, the voltage outp6v of the third voltage wiring L_V3 becomes higher than the voltage VCC of the first voltage wiring L_V1. When an overcurrent is detected at this time, as explained in Figure 5, the voltage vd2 is controlled by the P-type transistors PH1 and PH2 that constitute the limiting circuit LM_CT (Figure 3), and the voltage vd2 is limited to a value close to the voltage VCC. As a result, the voltage of the detection output node DC_OT is limited so as not to exceed the voltage VCC of the first voltage wiring L_V1.

[0127] Furthermore, as shown in Figures 6 and 7, when the voltage L_OT(V) of the output wiring L_OT is significantly lower than the voltage VCC, the voltage outp6v of the third voltage wiring L_V3 becomes lower than the voltage VCCm of the second voltage wiring L_V2. In this case, as explained in Figures 6 and 7, the P-type transistor PH1 that constitutes the limiting circuit LM_CT (Figure 3) becomes non-conductive. As a result, the third voltage wiring L_V3 is isolated from the detection output node DC_OT, and the voltage of the detection output node DC_OT is limited so that it does not fall below the voltage VCCm of the second voltage wiring L_V2.

[0128] As described above, by limiting the voltage of the detection output node DC_OT, it is possible to prevent damage to the element that supplies the first current I1 to the detection output node DC_OT and to the elements connected to the detection output node DC_OT.

[0129] (Embodiment 2) Figure 8 is a circuit diagram showing the configuration of the detection current generation circuit according to Embodiment 2. Figure 8 is similar to Figure 3. The main difference is that capacitors C1 to C5 are added to the detection current generation circuit DCG in Figure 8. Specifically, capacitor C1 is connected between the gate and source of P-type transistor P1, capacitor C2 is connected in parallel with the second current source I2_G, and capacitor C3 is connected in parallel with the third current source I3_G. Capacitor C4 is connected between the gate of P-type transistor P2 and the connection node connecting P-type transistor P2 and the drain of P-type transistor PH2, and capacitor C5 is connected between the drain and source of P-type transistor P2.

[0130] When the voltage of the output wiring L_OT and / or the voltage of the sense output signal SV_OT changes, the voltage of each element and wiring changes abruptly, causing overshoot and / or undershoot, which can exceed the withstand voltage of the element and lead to failure.

[0131] In Embodiment 2, by adding capacitors C1 to C5, the occurrence of overshoot and / or undershoot can be reduced, preventing the element from being destroyed. Figure 8 shows, as an example, the change in the gate-source voltage Vgs of a P-type transistor P2. When capacitor C1 is absent, overshoot occurs, as shown by the dashed line, leading to failure (BRK). In contrast, when capacitor C1 is added, the occurrence of overshoot can be reduced, as shown by the dashed line, preventing failure (BRK).

[0132] Even at locations where capacitors C2 to C5 are connected, as with the location where capacitor C1 is connected, it is possible to reduce the occurrence of overshoot and / or undershoot, as shown by the dashed lines, and prevent the element from being damaged.

[0133] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0134] CHP Semiconductor CP_CT Charge Pump Circuit DCG detection current generation circuit HDD High-Side Drive Circuit L_OT output wiring L_V1 First Voltage Wiring L_V2 Second Voltage Wiring L_V3 Third Voltage Wiring LDD Low-Side Drive Circuit N1, N2 N-type transistors OCD Overcurrent Detection Circuit P1-P4, PH1, PH2 P-type transistors

Claims

1. A power device connected between the first voltage wiring and the output terminal, A boost circuit is connected to the first voltage wiring, a second voltage wiring different from the first voltage wiring, and the output terminal, and generates a boosted voltage which is increased relative to the voltage at the output terminal, and supplies it to a third voltage wiring different from the first voltage wiring and the second voltage wiring. The first voltage wiring, the second voltage wiring, the third voltage wiring, and the overcurrent detection circuit connected to the output terminal, Equipped with, The overcurrent detection circuit described above is: A sense circuit that outputs a voltage corresponding to the current flowing through the power device, A detection current generation circuit that generates a detection current according to the output from the sense circuit, An output circuit that generates a detection signal based on the detection current generated by the detection current generation circuit, Equipped with, The aforementioned detection current generation circuit is A first current source is connected between the detection output node of the detection current generation circuit and the second voltage wiring, and supplies a first current of a predetermined value to the second voltage wiring. A first current circuit is connected between the detection output node and the first voltage wiring, and supplies the detection output node with a second current that is greater than the predetermined value. A second current circuit connected to the third voltage wiring and supplying a third current with a value greater than the predetermined value toward the detection output node, A limiting circuit is connected between the second current circuit and the detection output node, and limits the voltage at the detection output node so as not to be greater than or equal to the first voltage in the first voltage wiring, and so as not to be less than or equal to the second voltage in the second voltage wiring. A first control circuit controls the first current circuit according to the voltage output from the sense circuit, using the first voltage in the first voltage wiring and the voltage at the output terminal as the power supply voltage, A second control circuit controls the second current circuit according to the voltage output from the sense circuit, using the voltage in the third voltage wiring and the voltage at the output terminal as the power supply voltage. Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The first current circuit includes a first P-type transistor with a drain-source path connected between the first voltage wiring and the detection output node. The second current circuit includes a second P-type transistor with a drain-source path connected between the third voltage wiring and the limiting circuit. The first control circuit comprises a third P-type transistor, a first N-type transistor, and a second current source connected in series between the first voltage wiring and the output terminal, wherein the gate of the first N-type transistor is supplied with the voltage output from the sense circuit, and the gate of the third P-type transistor is connected to the source of the third P-type transistor and the gate of the first P-type transistor. The second control circuit comprises a fourth P-type transistor, a second N-type transistor, and a third current source connected in series between the third voltage wiring and the output terminal, wherein the gate of the second N-type transistor is supplied with the voltage output from the sense circuit, and the gate of the fourth P-type transistor is connected to the source of the fourth P-type transistor and the gate of the second P-type transistor. The limiting circuit isolates the second P-type transistor from the detection output node when the voltage at the output terminal is significantly lower than the first voltage. The limiting circuit limits the voltage at the connection node connecting the limiting circuit and the second P-type transistor to the first voltage when the voltage at the output terminal is between the second voltage and the first voltage. Semiconductor equipment.

3. In the semiconductor device described in claim 2, The limiting circuit has a structure in which the drain-gate breakdown voltage is higher than the source-gate breakdown voltage, and comprises a fifth P-type transistor having a drain connected to the second P-type transistor, a source connected to the detection output node, a back gate to which the first voltage is supplied, and a gate to which a bias voltage lower than the first voltage is supplied. Semiconductor equipment.

4. In the semiconductor device described in claim 3, The limiting circuit comprises a bias circuit for generating the bias voltage, which includes a sixth P-type transistor and a fourth current source connected in series between the first voltage wiring and the second voltage wiring. The 6P-type transistor has a structure in which the drain-gate breakdown voltage is higher than the source-gate breakdown voltage, and comprises a drain connected to the first voltage wiring, a source connected to the second voltage wiring via the fourth current source, a back gate to which the first voltage is supplied, and a gate connected to the source of the 6P-type transistor and the gate of the 5P-type transistor. Semiconductor equipment.

5. In the semiconductor device according to claim 4, In the 5P-type transistor and the 6P-type transistor, when viewed in cross-section, the distance between the drain region constituting the drain and the gate electrode constituting the gate is longer than the distance between the source region constituting the source and the gate electrode constituting the gate. Semiconductor equipment.

6. In the semiconductor device described in claim 5, The aforementioned sense circuit is The system comprises a sense device through which a current proportional to the current flowing through the power device flows, a sense resistor, a comparator circuit, and a reference voltage. Between the first voltage wiring and the output terminal, the drain-source path of the sense device and the sense resistor are connected in series. The comparison circuit is connected to the third voltage wiring and the output terminal, and uses the voltage in the third voltage wiring and the voltage at the output terminal as the power supply voltage to compare the voltage at the sense resistor with the reference voltage. Semiconductor equipment.

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