Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor that can prevent cracks from reaching the internal electrode layer and suppress fatal defects such as dielectric breakdown. [Solution] A multilayer ceramic capacitor comprising a laminate 12 including a plurality of stacked dielectric layers 14, a first internal electrode layer 16a exposed on a first end face 12e and a second internal electrode layer 16b exposed on a second end face 12f, and a first external electrode 30a and a second external electrode 30b, wherein the laminate 12 has an inner layer portion where the plurality of first internal electrode layers 16a and second internal electrode layers 16b face each other, the dielectric layer 14 contains voids, the voids are segregated within the dielectric layer 14, and the dielectric layer 14 includes a plurality of void-containing dielectric layers 14a, 14b and 14c with different void area occupancy rates (porosity) in the cross-section of the dielectric layer 14.

Description

Technical Field

[0001] This invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor is composed of a capacitor body made of a ceramic sintered body composed of a dielectric such as barium titanate. Inside this capacitor body, internal electrodes made of a noble metal material such as Ag or an Ag-Pd alloy or a base metal material such as Ni are arranged so as to be alternately led out to one end face and the other end face through a ceramic layer (dielectric layer). And, the internal electrodes of one potential are electrically conductively connected to the external electrodes, and the internal electrodes of the other potential are electrically conductively connected to the external electrodes respectively (see Patent Document 1).

[0003] The multilayer ceramic capacitor described in Patent Document 1 is a multilayer ceramic capacitor in which a metal material is used as an internal electrode, and the external electrode is composed of a plurality of metal components including a metal that is the same as or can be alloyed with this and a glass component. The external electrode is adhered to a wiring board through a conductive resin adhesive, and the area occupancy rate (porosity) of the metal component with respect to the cross-sectional area of the external electrode is 60 to 95%. Thereby, this multilayer ceramic capacitor can be mounted on a wiring board at a low cost with high reliability without using solder.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in multilayer ceramic capacitors with a general structure like that described in Patent Document 1, multiple voids exist in the ceramic layer (dielectric layer), and when a voltage is applied to the multilayer ceramic capacitor, cracks occur starting from these voids. When multiple voids exist, cracks can propagate through these voids, and cracks that originate in the ceramic layer may reach the internal electrode layer. If cracks occur within the internal electrode layer, insulation degradation occurs, which presents a problem.

[0006] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can prevent cracks from reaching the internal electrode layer and suppress fatal defects such as dielectric breakdown. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate containing a plurality of stacked dielectric layers, having a first main surface and a second main surface facing each other in the height direction which is the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface. In this multilayer ceramic capacitor, the laminate has an inner layer portion where the plurality of internal electrode layers face each other, the dielectric layers contain voids, the voids are segregated within the dielectric layers, and the dielectric layers include a plurality of void-containing dielectric layers with different area occupancy rates (porosity) of voids in the cross-section of the dielectric layers.

[0008] When a voltage is applied to a multilayer ceramic capacitor, cracks are generated starting from voids. If there are multiple voids in the dielectric layer, the generated cracks will propagate through these voids, and if these propagated cracks reach the internal electrode layer, and cracks occur within the internal electrode, insulation degradation will occur. Furthermore, cracks preferentially occur at the interfaces of different dielectric layers when a voltage is applied. However, according to the multilayer ceramic capacitor of the present invention, the dielectric layer contains voids, which are segregated within the dielectric layer, and the dielectric layer includes multiple void-containing dielectric layers with different void area occupancy rates (porosity) in the cross-section of the dielectric layer. Therefore, cracks can be preferentially generated at the interfaces between dielectric layers, and the cracks remain within the dielectric layer, preventing them from reaching the internal electrode layer and suppressing fatal defects such as dielectric breakdown. [Effects of the Invention]

[0009] This invention provides a multilayer ceramic capacitor that can prevent cracks from reaching the internal electrode layer and suppress fatal defects such as dielectric breakdown.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of this invention. [Figure 2] This is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view along line III-III in Figure 1. [Figure 4] This is a cross-sectional view along line IV-IV in Figure 1. [Figure 5] This is a schematic cross-sectional view of a laminated ceramic capacitor according to an embodiment of the present invention. [Figure 6] (a) is a scanning electron microscope image showing a portion of the cross-section of the dielectric layer of a multilayer ceramic capacitor according to an embodiment of the present invention, and (b) is a schematic diagram showing the image of (a) in different colors. [Figure 7] (a) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention is divided into two parts; (b) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to the present invention is divided into three parts; and (c) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to the present invention is divided into four parts. [Modes for carrying out the invention]

[0012] 1. Multilayer ceramic capacitor A multilayer ceramic capacitor according to an embodiment of this invention will be described.

[0013] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV in Figure 1.

[0014] As shown in Figures 1 to 4, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 positioned at both ends of the laminate 12.

[0015] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. Further, the laminate 12 has a first main surface 12a and a second main surface 12b that face each other in the height direction x, a first side surface 12c and a second side surface 12d that face each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in the length direction z orthogonal to the height direction x and the width direction y. The corners and edges of this laminate 12 are rounded.

[0016] Note that the corner refers to the portion where three adjacent surfaces of the laminate 12 intersect, and the edge line portion refers to the portion where two adjacent surfaces of the laminate 12 intersect. Also, the above "rectangular parallelepiped shape" means the entire member having the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. Further, irregularities or the like may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. The dielectric layer 14 and the internal electrode layer 16 are stacked in the height direction x.

[0017] The laminate 12 has an inner layer portion 18 composed of a single or a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 disposed thereon. The internal electrode layer 16 has a first internal electrode layer 16a drawn out to the first end surface 12e and a second internal electrode layer 16b drawn out to the second end surface 12f. In the inner layer portion 18, a plurality of first internal electrode layers 16a and second internal electrode layers 16b face each other through the dielectric layer 14.

[0018] The laminate 12 has a first main surface side outer layer portion 20a formed from a plurality of dielectric layers 14 located on the first main surface 12a side and located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and on the same straight line as the outermost surface.

[0019] Similarly, the laminate 12 has a second main surface side outer layer portion 20b formed from a plurality of dielectric layers 14 that are located on the second main surface 12b side and are positioned between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and in a straight line therewith.

[0020] The laminate 12 has a first side surface side outer layer portion 22a formed from a plurality of dielectric layers 14 that are located on the first side surface 12c side and are positioned between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0021] Similarly, the laminate 12 has a second side surface side outer layer portion 22b formed from a plurality of dielectric layers 14 that are located on the second side surface 12d side and are positioned between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side.

[0022] The laminate 12 has a first end surface side outer layer portion 24a formed from a plurality of dielectric layers 14 that are located on the first end surface 12e side and are positioned between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0023] Similarly, the laminate 12 has a second end surface side outer layer portion 24b formed from a plurality of dielectric layers 14 that are located on the second end surface 12f side and are positioned between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0024] The first main surface side outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 that are located on the first main surface 12a side of the laminate 12 and are positioned between the first main surface 12a and the innermost electrode layer 16 closest to the first main surface 12a.

[0025] The second main surface side outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 that are located on the second main surface 12b side of the laminate 12 and are positioned between the second main surface 12b and the innermost electrode layer 16 closest to the second main surface 12b.

[0026] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the length z dimension is 0.2 mm or more and 6.0 mm or less, the width y dimension is 0.1 mm or more and 5.0 mm or less, and the height x dimension is 0.1 mm or more and 5.0 mm or less.

[0027] The dielectric layer 14 can be formed from, for example, a dielectric material. Such dielectric materials include, for example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the above dielectric material is used as the main component, depending on the desired properties of the laminate 12, a material with lower amounts of minor components than the main component, such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds, may be used.

[0028] The thickness of the dielectric layer 14 after firing is preferably, for example, 0.5 μm or more and 10 μm or less. The number of dielectric layers 14 to be stacked is preferably 2 or more and 1000 or less. This number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the inner layer portion 18 and the number of dielectric layers 14 in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0029] The laminate 12 has multiple dielectric layers 14, each of which contains vacancies. These vacancies are segregated within the dielectric layers 14, and each of the multiple dielectric layers 14 contains multiple vacancy-containing dielectric layers with different vacancy area occupancy rates (porosity) in its cross-section.

[0030] Furthermore, as shown in the schematic cross-sectional view of Figure 5, each of the dielectric layers 14, which is composed of a plurality of vacancy-containing dielectric layers, has a first vacancy-containing dielectric layer 14a, a second vacancy-containing dielectric layer 14b, and a third vacancy-containing dielectric layer 14c. Preferably, the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b have the same vacancy area occupancy (porosity), while the third vacancy-containing dielectric layer 14c has a different vacancy area occupancy (porosity). Also, preferably, the third vacancy-containing dielectric layer 14c is sandwiched between the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b along the height direction x.

[0031] With the above configuration, the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b have a lower vacancy area occupancy (porosity) compared to the third vacancy-containing dielectric layer 14c, thus providing higher insulating properties as dielectrics. On the other hand, since the vacancy area occupancy (porosity) of the third vacancy-containing dielectric layer 14c differs from that of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b, applying a voltage at the interface 14I between the third vacancy-containing dielectric layer and each of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b allows for preferential crack generation at the interface 14I of the vacancy-containing dielectric layers with different vacancy area occupancy (porosity).

[0032] Therefore, the presence of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b, which have relatively low vacancy area occupancy (porosity) and high insulating properties as dielectrics, ensures the high-temperature load reliability of the multilayer ceramic capacitor 10. Furthermore, the presence of the third vacancy-containing dielectric layer 14c allows cracks to preferentially occur at the interface 14I of the vacancy-containing dielectric layers, which have different vacancy area occupancy (porosity) values. As a result, cracks do not reach the internal electrode layer 16, suppressing fatal defects such as dielectric breakdown.

[0033] Preferably, the porosity of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b is less than 0.1%, and the porosity of the third vacancy-containing dielectric layer 14c is 0.1% or more and less than 5.5%.

[0034] By adopting the above configuration, it is possible to further achieve the effect of ensuring the reliability of the multilayer ceramic capacitor 10 with the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b, while simultaneously suppressing the crack occurrence rate with the presence of the third vacancy-containing dielectric layer 14c. If the porosity of the third vacancy-containing dielectric layer 14c exceeds 5.5%, the electric field in the dielectric layer 14, particularly the third vacancy-containing dielectric layer 14c, becomes concentrated due to the increased porosity, making dielectric breakdown more likely to occur in the dielectric layer 14.

[0035] Furthermore, if the porosity of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b is less than 0.1%, and the porosity of the third vacancy-containing dielectric layer 14c is also less than 0.1%, then there will be virtually no difference in porosity between the third vacancy-containing dielectric layer 14c and each of the first and second vacancy-containing dielectric layers 14a and 14b. As a result, applying a voltage at the interface 14I between the third vacancy-containing dielectric layer 14c and each of the first and second vacancy-containing dielectric layers 14a and 14b will not preferentially generate cracks at the interface 14I, making it impossible to suppress fatal defects such as cracks reaching the internal electrodes and causing dielectric breakdown.

[0036] The porosity in the dielectric layer 14 of the laminate 12 of the multilayer ceramic capacitor 10 can be measured by the following measurement method.

[0037] First, the cross-section of the multilayer ceramic capacitor 10 is exposed. Specifically, the cross-section of the WT or LT surface of the multilayer ceramic capacitor is polished until its dimensions are reduced to half. Next, the cross-section is observed with a scanning electron microscope (SEM) and color-coded to distinguish between areas where grains are present and areas where cavities are clearly visible relative to the depth. Here, the lighter colored areas are defined as grains G, and the darker colored areas are defined as pores P. The area ratio of grains G to pores P is calculated as the pore ratio, and this value is defined as the porosity.

[0038] Here, Figure 6(a) is a cross-sectional SEM image (magnification: 100,000x) of the third vacancy-containing dielectric layer 14c, and Figure 6(b) is a schematic diagram showing grains G extracted from the cross-sectional SEM image of Figure 6(a) by color coding. In Figure 6(b), grains G due to BT particles are shown in gray, and vacancies (pores) P are shown in black. The area of ​​grains G occupies the entire cross-section (particle ratio) of 85.53%, and the pore ratio (porosity) is 0.82%. The porosity of the first vacancy-containing dielectric layer 14a and the second vacancy-containing dielectric layer 14b is also measured in the same manner as described above.

[0039] The laminate 12 has a plurality of internal electrode layers 16, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded in the laminate 12 so as to be alternately arranged at equal intervals along the height direction x of the laminate 12, with the dielectric layer 14 in between. Each of the plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b is substantially parallel to the first main surface 12a and the second main surface 12b.

[0040] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b, and a first leading electrode portion 28a located on one end side of the first internal electrode layer 16a, extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. The end of the first leading electrode portion 28a is drawn out to the surface of the first end face 12e and exposed from the laminate 12. In other words, the end of the first leading electrode portion 28a is not exposed to the first main surface 12a and the second main surface 12b, the second end face 12f, and the first side surface 12c and the second side surface 12d. In detail, the end of the first internal electrode layer 16a is slightly recessed from the second end face 12f.

[0041] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0042] The shape of the first lead-out electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0043] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first leading electrode portion 28a of the first internal electrode layer 16a may be the same, or one of them may be narrower.

[0044] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a, and a second leading electrode portion 28b located on one end side of the second internal electrode layer 16b, extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second leading electrode portion 28b is drawn out to the surface of the second end face 12f and exposed from the laminate 12. In other words, the end of the first leading electrode portion 28a is not exposed to the first main surface 12a and the second main surface 12b, the first end face 12e, and the first side surface 12c and the second side surface 12d. In detail, the end of the second internal electrode layer 16b is slightly recessed from the first end face 12e.

[0045] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0046] The shape of the second lead-out electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0047] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second leading electrode portion 28b of the second internal electrode layer 16b may be the same width, or one of them may be narrower.

[0048] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0049] The thickness of the internal electrode layer 16, that is, the first internal electrode layer 16a and the second internal electrode layer 16b, is preferably 0.2 μm or more and 2.0 μm or less.

[0050] When the underlying electrode layer 32 of the external electrode 30, described later, includes a conductive resin layer, the metal constituting the internal electrode layer 16 forms a compound with the metal constituting the conductive filler contained in the conductive resin.

[0051] Furthermore, it is preferable that the total number of the first internal electrode layer 16a and the second internal electrode layer 16b is between 2 and 1000.

[0052] Furthermore, the laminated body 12 shown in Figure 1, as shown in Figure 7, is provided with a floating internal electrode layer 16c that is not extended from either the first end face 12e or the second end face 12f, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, and the floating internal electrode layer 16c divides the opposing electrode portion 26c into multiple parts. For example, there is a two-unit structure as shown in Figure 7(a), a three-unit structure as shown in Figure 7(b), and a four-unit structure as shown in Figure 7(c), and it goes without saying that structures with four or more units are also possible. By dividing the opposing electrode portion 26c into multiple parts in this way, multiple capacitor components are formed between the opposing first internal electrode layer 16a, the second internal electrode layer 16b, and the floating internal electrode layer 16c, and these capacitor components are connected in series. As a result, the voltage applied to each capacitor component becomes lower, and the voltage withstand capability of the multilayer ceramic capacitor 10 can be increased.

[0053] Furthermore, the floating internal electrode layer 16c, like the first internal electrode layer 16a and the second internal electrode layer 16b, can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0054] External electrodes 30 are arranged on the first end face 12e and the second end face 12f of the laminate 12, as shown in Figures 1 to 4.

[0055] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a lower plating layer 34 disposed on the surface of the base electrode layer 32. Preferably, the external electrode 30 also includes an upper plating layer 36 disposed on the surface of the lower plating layer 34.

[0056] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0057] The first external electrode 30a is connected to the first internal electrode layer 16a and is positioned on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 28a of the first internal electrode layer 16a.

[0058] The second external electrode 30b is connected to the second internal electrode layer 16b and is positioned on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 28b of the second internal electrode layer 16b.

[0059] Within the laminate 12, capacitance is formed when the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other via the dielectric layer 14. As a result, capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 16a is connected and the second external electrode 30b to which the second internal electrode layer 16b is connected, and the characteristics of a capacitor are exhibited.

[0060] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0061] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is positioned on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 28a of the first internal electrode layer 16a.

[0062] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is positioned on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 28b of the second internal electrode layer 16b.

[0063] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, and a thin film layer, etc.

[0064] The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, and thin film layer described above.

[0065] (In the case of a baked-on layer) The baked layer contains a metal component and glass. The metal component of the baked layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer is formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer is formed by simultaneously baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and the conductive paste applied to the laminated chip, but it may also be baked after baking the laminated chip having the internal electrode layer 16 and the dielectric layer 14. The baked layer may consist of multiple layers.

[0066] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center of the first base electrode layer 32a located at the first end face 12e in the height direction x is preferably, for example, 10 μm or more and 150 μm or less.

[0067] The thickness of the second base electrode layer 32b located at the second end face 12f in the length direction z connecting the first end face 12e and the second end face 12f at the center of the height direction x is preferably, for example, 10 μm or more and 150 μm or less.

[0068] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first underlay electrode layer 32a, which is located in a part of the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0069] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the second underlay electrode layer 32b, which is located in a part of the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0070] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first underlay electrode layer 32a, which is located in a part of the first side surface 12c and the second side surface 12d, is preferably, for example, 10 μm or more and 100 μm or less.

[0071] Furthermore, the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the second underlay electrode layer 32b located in a part of the first side surface 12c and the second side surface 12d is preferably, for example, 10 μm or more and 100 μm or less.

[0072] (In the case of a conductive resin layer) The conductive resin layer comprises a first conductive resin layer and a second conductive resin layer.

[0073] Preferably, the first conductive resin layer is arranged as a first base electrode layer 32a, further covering other layers such as a baking layer, and preferably, the second conductive resin layer is arranged as a second base electrode layer 32b, further covering other layers such as a baking layer.

[0074] Specifically, it is preferable that the first conductive resin layer and the second conductive resin layer are arranged as the first base electrode layer 32a and the second base electrode layer 32b, respectively, on top of other layers such as baking layers located on the first end face 12e and the second end face 12f, and that they extend to other layers such as baking layers located on the first main surface 12a and the second main surface 12b, as well as the first side surface 12c and the second side surface 12d. However, the first conductive resin layer and the second conductive resin layer may be arranged only on other layers such as baking layers located on the first end face 12e.

[0075] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, 10 μm to 200 μm.

[0076] The first conductive resin layer and the second conductive resin layer each contain a thermosetting resin and a metal component.

[0077] Because the first and second conductive resin layers contain thermosetting resins, they are more flexible than, for example, the base electrode layer 32 which is made of a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layers function as buffer layers, preventing cracks in the multilayer ceramic capacitor 10.

[0078] Specific examples of thermosetting resins include various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins. Among these, epoxy resins, which have excellent heat resistance, moisture resistance, and adhesion, are among the most suitable resins.

[0079] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds can be used as curing agents for the epoxy resin.

[0080] The metals contained in the first and second conductive resin layers can be Ag, Cu, or alloys thereof. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder.

[0081] Alternatively, copper treated with an anti-oxidation process can be used. The reason for using an Ag-coated metal is that it allows for the use of a less expensive base metal while maintaining the aforementioned properties of Ag.

[0082] Preferably, the metal contained in the first conductive resin layer and the second conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin.

[0083] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The conductive filler may be spherical, flattened, or the like.

[0084] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, 0.3 μm to 10 μm.

[0085] The metals contained in the first and second conductive resin layers are primarily responsible for the conductivity of the conductive resin layers. Specifically, conductive paths are formed within the conductive resin layers through contact between the conductive fillers.

[0086] The metals contained in the first conductive resin layer and the second conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0087] The conductive resin layer may be formed directly on the laminate without forming a baking layer.

[0088] (In the case of a thin film layer) When the underlying electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0089] The plating layer includes a lower plating layer 34 placed on the surface of the underlay electrode layer 32 and an upper plating layer 36 placed on the surface of the lower plating layer 34.

[0090] The lower plating layer 34 has a first lower plating layer 34a and a second lower plating layer 34b.

[0091] The first lower plating layer 34a is positioned to cover the surface of the first under electrode layer 32a. The second lower plating layer 34b is positioned to cover the surface of the second under electrode layer 32b.

[0092] The upper plating layer 36 has a first upper plating layer 36a and a second upper plating layer 36b.

[0093] The first upper plating layer 36a is positioned to cover the surface of the first lower plating layer 34a. The second upper plating layer 36b is positioned to cover the surface of the second lower plating layer 34b.

[0094] The plating layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0095] When the plating layer is formed by multiple layers, such as a lower plating layer 34 and an upper plating layer 36, it is preferable that it be a two-layer structure consisting of a Ni plating layer and a Sn plating layer. The Ni plating layer prevents the underlying electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 10, allowing the multilayer ceramic capacitor 10 to be easily mounted on the mounting substrate. In this way, by forming the plating layer by multiple layers, such as a lower plating layer 34 and an upper plating layer 36, the reliability and mountability of the multilayer ceramic capacitor 10 can be efficiently improved.

[0096] The thickness of each layer of the plating layer, specifically the Ni plating layer and the Sn plating layer, is preferably between 1 μm and 15 μm.

[0097] The length z dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension L. The height x dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension T. The width y dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0098] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the length z is L, and L is between 0.20 mm and 5.70 mm.

[0099] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the height x is the T dimension, and the T dimension is between 0.05 mm and 2.50 mm.

[0100] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the width y is the W dimension, and the W dimension is between 0.10 mm and 5.00 mm.

[0101] If vacancies exist in the dielectric layer 14, cracks will occur starting from the vacancies when a voltage is applied to the multilayer ceramic capacitor 10. If multiple vacancies exist in the dielectric layer 14, the resulting cracks will propagate through the multiple vacancies, and these propagated cracks will reach the internal electrode layer 16. If cracks occur in the internal electrode layer 16, insulation degradation will occur. Furthermore, at the interface of dielectric layers 14 with different vacancy area occupancy rates (porosity), cracks will preferentially occur when a voltage is applied.

[0102] In the multilayer ceramic capacitor 10 shown in Figure 1, the dielectric layer 14 is provided with multiple void-containing dielectric layers having different void area occupancy rates (porosity). This allows for the preferential generation of cracks at the interfaces between the multiple void-containing dielectric layers with different void area occupancy rates (porosity). The cracks remain within the dielectric layer 14 and do not reach the internal electrode layer 16, thus suppressing fatal defects such as dielectric breakdown.

[0103] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, the dielectric layer 14, which is composed of multiple void-containing dielectric layers, preferably has a first void-containing dielectric layer 14a, a second void-containing dielectric layer 14b, and a third void-containing dielectric layer 14c, as shown in Figure 5. In this case, the first void-containing dielectric layer 14a and the second void-containing dielectric layer 14b have the same void area occupancy rate (porosity), while the third void-containing dielectric layer 14c has a different void area occupancy rate (porosity). The third void-containing dielectric layer 14c is sandwiched between the first void-containing dielectric layer 14a and the second void-containing dielectric layer 14b along the height direction x.

[0104] In this configuration, the presence of a first vacancy-containing dielectric layer 14a and a second vacancy-containing dielectric layer 14b, which have relatively low vacancy area occupancy (porosity) and high insulating properties as dielectrics, ensures the high-temperature load reliability of the multilayer ceramic capacitor 10. Furthermore, the presence of a third vacancy-containing dielectric layer 14c allows cracks to preferentially occur at the interface 14I between the vacancy-containing dielectric layers, where the vacancy area occupancy (porosity) of the dielectric layer 14 differs from that of the dielectric layer 14. As a result, cracks do not reach the internal electrode layer 16, suppressing fatal defects such as dielectric breakdown.

[0105] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of multilayer ceramic capacitors.

[0106] First, a ceramic green sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The ceramic green sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known.

[0107] (Process for forming a void-containing dielectric layer) When preparing ceramic green sheets for dielectric layers, a slurry containing multiple dielectric materials, binders, and polymers with different compositions is applied to a carrier film to prepare multiple ceramic green sheets. These prepared ceramic green sheets are then bonded together separately to prepare a ceramic green sheet for dielectric layers. After firing, each of the multiple ceramic green sheets becomes a first void-containing dielectric layer, a second void-containing dielectric layer, and a third void-containing dielectric layer, respectively. The ceramic green sheet for dielectric layers, formed by bonding these multiple ceramic green sheets together, becomes a void-containing dielectric layer after firing. The porosity of each dielectric layer can be changed during the slurry preparation process for the ceramic green sheets for dielectric layers by using multiple dielectric materials with different compositions and varying the ratio of each dielectric material to the binder.

[0108] Then, a conductive paste for the internal electrode layer is printed on the ceramic green sheet for the dielectric layer in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a ceramic green sheet with the pattern for the first internal electrode layer formed on it, and a ceramic green sheet with the pattern for the second internal electrode layer formed on it.

[0109] (Process for obtaining laminated sheets) Next, a predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are laminated to form the second outer layer portion on the second main surface side. Then, a ceramic green sheet with the pattern of the first internal electrode layer printed on it, and a ceramic green sheet with the pattern of the second internal electrode layer printed on it, are sequentially laminated on the second outer layer portion on the second main surface side to form the inner layer portion. Then, a predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on it, are laminated on the inner layer portion to form the first outer layer portion on the first main surface side. This completes the production of the laminated sheet.

[0110] (Process for obtaining laminated blocks) Next, a laminated block is produced by pressing the laminated sheets in the lamination direction using means such as a hydrostatic press.

[0111] (Process for obtaining stacked chips) Then, the laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0112] (Process for obtaining a laminate) Next, the laminated chips are fired to create a laminate. The firing temperature depends on the temperature of the dielectric layer and the internal electrode layer, but it is preferably between 900°C and 1400°C.

[0113] Next, a conductive paste for the base electrode layer, containing metal and glass components, is prepared.

[0114] (Process for forming external electrodes) A conductive paste, which will serve as the base electrode layer, is applied to both ends of the laminate to form the base electrode layer. Methods such as dipping or screen printing can be used to apply the conductive paste to both ends of the laminate. The temperature during this baking process is preferably between 700°C and 900°C.

[0115] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a barrel plating method.

[0116] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0117] According to the manufacturing method of a multilayer ceramic capacitor of the present invention, even if the multilayer ceramic capacitor is subjected to voltage, temperature load, or physical shock, the cracks will remain only on the periphery of the dielectric interface with different pore content and will not reach the internal electrode layer. Therefore, fatal defects such as dielectric breakdown can be suppressed, and a multilayer ceramic capacitor with a suppressed crack occurrence rate can be obtained.

[0118] 3. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, a multilayer ceramic capacitor sample was prepared according to the manufacturing method described above, and an experiment was conducted to measure the crack occurrence rate.

[0119] (1) Specification of the sample in the experimental example First, according to the manufacturing method of the multilayer ceramic capacitor described above, samples of multilayer ceramic capacitors according to Examples 1 to 9 and the Comparative Example were prepared with the following specifications. In each example and comparative example, in order to bring out the features of the present invention, multiple ceramic green sheets constituting the laminate were prepared such that the sum of the sheet thicknesses was the desired thickness, and multiple sheets were obtained by stacking them using, for example, the manufacturing method described above.

[0120] (Specifications of multilayer ceramic capacitors) • Dimensions of the multilayer ceramic capacitor (design value): L × W × T = 3.2 mm × 1.6 mm × 1.6 mm • Main component of the dielectric layer: Ceramic material: BaTiO3 ·Capacity: 10μF • Rated voltage: 25V • Material of the internal electrode layer: Ni • Structure of the external electrode: Cu • Film thickness at the center of the height direction of the first and second end faces of the external electrode: approximately 90 μm • Plating layer Formation of a two-layer structure consisting of a Ni plating layer and a Sn plating layer. Ni plating layer thickness: approximately 4 μm Sn plating layer thickness: approximately 4 μm

[0121] (2) Method for measuring the crack occurrence rate First, in the measurement (screening) process of multilayer ceramic capacitors, chips with an insulation resistance of 1 kΩ or less at room temperature were considered defective chips. Defective chips were observed with a stereomicroscope, and chips with cracks, or chips with internal cracks in the dielectric layer after cross-sectional polishing from the LT surface, were defined as cracked chips. The crack occurrence rate was defined as the percentage of the total number of measured chips (50,000) and the number of cracked chips. The criteria for judging the crack occurrence rate were as follows: 0.1% or more was marked "×", 0.02% or more and less than 0.1% was marked "△", 0.005% or more and less than 0.02% was marked "〇", and less than 0.005% was marked "◎".

[0122] (3) Results Table 1 shows the crack occurrence rates of the dielectric layers of the laminates for Examples 1 to 9 and the comparative examples.

[0123] [Table 1]

[0124] As shown in Table 1, each sample from Example 1 to Example 9 contained multiple vacancy-containing dielectric layers with different porosities within the dielectric layer, resulting in a good crack occurrence rate of less than 0.1%.

[0125] Furthermore, in each of the samples from Examples 4 to 9, the porosity of the first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer was less than 0.1%, and the porosity of the third vacancy-containing dielectric layer was 0.1% or more and less than 5.5%, resulting in a crack occurrence rate of 0%, which is an even better result.

[0126] On the other hand, in the comparative example, since the porosity of the first vacancy-containing dielectric layer, the second vacancy-containing dielectric layer, and the third vacancy-containing dielectric layer were all the same at 10%, the crack occurrence rate was 0.4%.

[0127] From the above results, it is suggested that in the present invention, the dielectric layer constituting the laminate contains vacancies, the vacancies are segregated within the dielectric layer, and the dielectric layer includes multiple vacancy-containing dielectric layers with different area occupancy rates (porosity) of the vacancies in the cross-section of the dielectric layer, thereby preventing cracks from reaching the internal electrode layer and suppressing fatal defects such as dielectric breakdown.

[0128] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0129] In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention.

[0130] <1> A laminate comprising a plurality of stacked dielectric layers, having a first main surface and a second main surface opposite to each other in the height direction which is the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in the width direction which is perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in the length direction which is perpendicular to the height direction and the width direction, A first internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the first end face, A second internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the second end face, A first external electrode disposed on the first end face, A second external electrode disposed on the second end face, In a multilayer ceramic capacitor having, The laminate has an inner layer portion in which the plurality of internal electrode layers face each other, The dielectric layer contains voids, The aforementioned vacancies are segregated within the dielectric layer. In the dielectric layer, A multilayer ceramic capacitor comprising a plurality of void-containing dielectric layers having different area occupancy rates (porosity) of the voids in the cross-section of the dielectric layer.

[0131] <2> The aforementioned vacancy-containing dielectric layer is It comprises a first vacancy-containing dielectric layer, a second vacancy-containing dielectric layer, and a third vacancy-containing dielectric layer. The first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer have the same area occupancy rate (porosity) of the vacancies, and the third vacancy-containing dielectric layer has a different area occupancy rate (porosity) of the vacancies. The third vacancy-containing dielectric layer is sandwiched between the first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer in the height direction. <1> The multilayer ceramic capacitor described above.

[0132] <3> The porosity of the first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer is less than 0.1%. The porosity of the third vacancy-containing dielectric layer is 0.1% or more and less than 5.5%. <2> The multilayer ceramic capacitor described above.

[0133] <4> <1> or <3> A method for manufacturing a multilayer ceramic capacitor as described in any of the following: The process involves preparing multiple ceramic green sheets by coating a carrier film with a slurry containing dielectric materials, binders, and polymers of different compositions, and separately bonding the multiple ceramic green sheets to form the multiple void-containing dielectric layers. The process involves applying a conductive paste for forming internal electrodes to the plurality of ceramic green sheets, A step of stacking multiple ceramic green sheets coated with the aforementioned ceramic green sheet and the conductive paste for forming the internal electrode to obtain a laminated sheet, The process of pressing the laminated sheet in the stacking direction of the ceramic green sheet to obtain a laminated block, The process of cutting the aforementioned laminated block to obtain laminated chips, A step of firing the laminated chips to obtain the laminated body, The process includes the steps of applying a conductive paste for forming external electrodes to the laminate and baking it to form the first external electrode and the second external electrode. A method for manufacturing multilayer ceramic capacitors. [Explanation of symbols]

[0134] 10 Multilayer ceramic capacitors 12-layer structure 12a First main surface 12b Second main surface 12c First side 12d Second aspect 12e First end face 12f Second end face 14 Dielectric layer 14a First vacancy-containing dielectric layer 14b Second vacancy-containing dielectric layer 14c Third vacancy-containing dielectric layer 14I Interface 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 16c floating internal electrode layer 18 Inner layer 20a First main surface side outer layer 20b Second main surface side outer layer 22a First side outer layer 22b Second side outer layer 24a First end face side outer layer 24b Second end face side outer layer 26a First counter electrode portion 26b Second counter electrode portion 26c Counter electrode section 28a First extraction electrode section 28b Second extraction electrode section 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 34 Lower plating layer 34a First lower plating layer 34b Second lower plating layer 36 Upper plating layer 36a First upper plating layer 36b Second upper plating layer

Claims

1. A laminate comprising a plurality of stacked dielectric layers, having a first main surface and a second main surface facing each other in the height direction which is the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, A first internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the first end face, A second internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the second end face, A first external electrode disposed on the first end face, A second external electrode disposed on the second end face, In a multilayer ceramic capacitor having, The laminate has an inner layer portion in which the plurality of internal electrode layers face each other, The dielectric layer contains voids, The aforementioned vacancies are segregated within the dielectric layer. In the dielectric layer, A multilayer ceramic capacitor comprising a plurality of vacancy-containing dielectric layers having different area occupancy rates (porosity) of the vacancies in the cross-section of the dielectric layer.

2. The aforementioned vacancy-containing dielectric layer is It comprises a first vacancy-containing dielectric layer, a second vacancy-containing dielectric layer, and a third vacancy-containing dielectric layer. The first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer have the same area occupancy ratio (porosity) of the vacancies, and the third vacancy-containing dielectric layer has a different area occupancy ratio (porosity) of the vacancies. The multilayer ceramic capacitor according to claim 1, wherein the third vacancy-containing dielectric layer is sandwiched between the first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer in the height direction.

3. The porosity of the first vacancy-containing dielectric layer and the second vacancy-containing dielectric layer is less than 0.1%. The multilayer ceramic capacitor according to claim 2, wherein the porosity of the third vacancy-containing dielectric layer is 0.1% or more and less than 5.5%.

4. A method for manufacturing a multilayer ceramic capacitor according to claim 1, The process involves preparing multiple ceramic green sheets by coating a carrier film with a slurry containing dielectric materials, binders, and polymers of different compositions, and separately bonding the multiple ceramic green sheets to form the multiple void-containing dielectric layers. The process involves applying a conductive paste for forming internal electrodes to the plurality of ceramic green sheets, A step of stacking multiple ceramic green sheets coated with the aforementioned ceramic green sheet and the conductive paste for forming the internal electrode to obtain a laminated sheet, The process of pressing the laminated sheet in the stacking direction of the ceramic green sheet to obtain a laminated block, The process of cutting the aforementioned laminated block to obtain laminated chips, A step of firing the laminated chips to obtain the laminated body, The process includes the steps of applying a conductive paste for forming external electrodes to the laminate and baking it to form the first external electrode and the second external electrode. A method for manufacturing multilayer ceramic capacitors.

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