Semiconductor equipment

Abstract

The goal is to reduce the size of the equipment and make it more compact. [Solution] The high-side switching element 1c1 and the low-side switching element 1c2 are connected to a load 9 and drive the load 9 by switching operation. The high-side operation detection circuit 1a1 detects the operating state of the high-side switching element 1c1 and generates first operation information DH. The transmission circuit 1a2 transmits the first operation information DH to the low-side circuit 1b. The low-side operation detection circuit 1b1 detects the operating state of the low-side switching element 1c2 and generates second operation information DL. The operation information notification circuit 1b2 receives the first operation information DH and the second operation information DL transmitted from the high-side circuit 1a and makes an external notification of at least one of the first operation information DH or the second operation information DL.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device having switching elements, which are power semiconductors, incorporated on the high side and the low side has a configuration for outputting operation information such as the temperature state during the operation of the switching elements to the outside.

[0003] As related art, for example, a technique has been proposed in which an abnormal signal held in a circuit for the upper arm is transmitted to a circuit section with a ground potential reference during the on-period of the main switching element of the lower arm (Patent Document 1). Further, a technique has been proposed in which information transmission is performed by using the current flowing through a diode by switching the signal switching element of a signal transmission circuit (Patent Document 2). Furthermore, a technique has been proposed in which information necessary for the protection operation of semiconductor elements constituting a power conversion device is detected, and an alarm signal with a pulse width corresponding to a protection factor is generated and output to the outside (Patent Document 3).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a semiconductor device that reduces the device scale and miniaturizes the device by aggregating and outputting the operation information of switching elements.

Means for Solving the Problems

[0006] To solve the above problems, a semiconductor device is provided. The semiconductor device includes an output section including a high-side switching element and a low-side switching element that are connected to a load and drive the load; a high-side circuit including a high-side operation detection circuit that detects the operating state of the high-side switching element and generates first operation information, and a transmission circuit that transmits the first operation information to the low-side side; a low-side operation detection circuit that detects the operating state of the low-side switching element and generates second operation information; and an operation information notification circuit including an operation information notification circuit that receives the first operation information and the second operation information transmitted from the high-side circuit and provides external notification of at least one of the first operation information or the second operation information. [Effects of the Invention]

[0007] One aspect of this approach is that it becomes possible to reduce the size of the device and miniaturize it. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram illustrating an example of a semiconductor device. [Figure 2] This is a diagram showing the configuration of a semiconductor device as an example. [Figure 3] This is a diagram showing an example of the configuration of a semiconductor device. [Figure 4] This figure shows an example of a high-side circuit configuration. [Figure 5] This figure shows an example of the internal configuration of a high-side circuit and a low-side circuit. [Figure 6] This figure shows an example of bit allocation for notification data. [Figure 7] This figure shows examples of the waveforms of clock signals indicating the start and end of communication for motion detection pulses. (a) shows the case where multiple motion information is transmitted in the interval between the start and end of communication, and (b) shows the case where one motion information is transmitted in the interval between the start and end of communication. [Figure 8] This diagram shows the configuration of a modified HVIC. [Figure 9] This figure shows an example of a timing chart for operating waveform pulse transmission. [Figure 10] This diagram shows a modified configuration of the HVIC, including the gate drive function. [Figure 11] This figure shows an example of a timing chart for data transmission functions. [Modes for carrying out the invention]

[0009] This embodiment will now be described with reference to the drawings. Note that elements having substantially the same configuration in this specification and the drawings may be denoted by the same reference numerals, thus omitting redundant explanations.

[0010] Figure 1 is a diagram illustrating an example of a semiconductor device. The semiconductor device 1 comprises a high-side circuit 1a, a low-side circuit 1b, and an output section 1c. The high-side circuit 1a includes a high-side operation detection circuit 1a1 and a transmission circuit 1a2. The low-side circuit 1b includes a low-side operation detection circuit 1b1 and an operation information notification circuit 1b2. The output section 1c includes a high-side switching element 1c1 and a low-side switching element 1c2.

[0011] The high-side circuit 1a drives the high-side switching element 1c1 based on the high-side drive control signal DgH transmitted from an external source. The low-side circuit 1b drives the low-side switching element 1c2 based on the low-side drive control signal DgL transmitted from an external source. The high-side switching element 1c1 and the low-side switching element 1c2 are connected to the load 9 and drive the load 9 through their switching operation.

[0012] The high-side operation detection circuit 1a1 detects the operating state of the high-side switching element 1c1 and generates first operation information DH. The transmission circuit 1a2 transmits the first operation information DH to the low-side circuit 1b.

[0013] The low-side operation detection circuit 1b1 detects the operation state of the low-side switching element 1c2 and generates second operation information DL. The operation information notification circuit 1b2 receives the first operation information DH transmitted from the high-side circuit 1a and the second operation information DL on the low-side circuit 1b side, and performs at least one external notification of the first operation information DH or the second operation information DL.

[0014] As described above, in the semiconductor device 1, the first operation information regarding the operation state of the high-side switching element 1c1 detected by the high-side circuit 1a is transmitted to the low-side circuit 1b. Then, in the low-side circuit 1b, at least one of the transmitted first operation information or the second operation information regarding the operation state of the low-side switching element 1c2 detected by the low-side circuit 1b is notified to the outside.

[0015] With such a configuration, the first operation information on the high-side and the second operation information on the low-side can be aggregated and notified to the outside. Therefore, for example, the number of output pins for operation information can be reduced, the device scale can be reduced, and the device can be miniaturized.

[0016] Next, the semiconductor device of the reference example will be described with reference to FIG. 2. FIG. 2 is a diagram showing the configuration of the semiconductor device of the reference example. The semiconductor device 200 of the reference example includes a high-side circuit 7, high-side switching circuits 4a1, 4a2, 4a3, a low-side circuit 8, and low-side switching circuits 4b1, 4b2, 4b3.

[0017] The high-side circuit 7 includes drive circuits 7U, 7V, 7W, and the low-side circuit 8 includes drive circuits 8X, 8Y, 8Z, and an alarm output circuit 80. The U-phase high-side switching circuit 4a1 includes a switching element 4U, a FWD (Free Wheel Diode) 5U, and a temperature detection diode 6U. The V-phase high-side switching circuit 4a2 includes a switching element 4V, a FWD 5V, and a temperature detection diode 6V. The W-phase high-side switching circuit 4a3 includes a switching element 4W, a FWD 5W, and a temperature detection diode 6W.

[0018] Furthermore, the X-phase low-side switching circuit 4b1 includes a switching element 4X, FWD 5X, and a temperature sensing diode 6X. The Y-phase low-side switching circuit 4b2 includes a switching element 4Y, FWD 5Y, and a temperature sensing diode 6Y. The Z-phase low-side switching circuit 4b3 includes a switching element 4Z, FWD 5Z, and a temperature sensing diode 6Z.

[0019] The high-side switching elements 4U, 4V, and 4W are located between the positive terminal P and the output terminals U, V, and W of each phase, while the low-side switching elements 4X, 4Y, and 4Z are located between the output terminals U, V, and W of each phase and the negative terminal N. A load 9 is connected to the output terminals U, V, and W.

[0020] FWD5U, 5V, and 5W are connected in antiparallel to switching elements 4U, 4V, and 4W respectively to commutate the load current. Similarly, FWD5X, 5Y, and 5Z are connected in antiparallel to switching elements 4X, 4Y, and 4Z respectively to commutate the load current.

[0021] The anode of the temperature sensing diode 6U, which detects the temperature of the switching element 4U, is connected to the U-phase drive circuit 7U, and the cathode of the temperature sensing diode 6U is connected to the output terminal U. The anode of the temperature sensing diode 6V, which detects the temperature of the switching element 4V, is connected to the V-phase drive circuit 7V, and the cathode of the temperature sensing diode 6V is connected to the output terminal V. The anode of the temperature sensing diode 6W, which detects the temperature of the switching element 4W, is connected to the W-phase drive circuit 7W, and the cathode of the temperature sensing diode 6W is connected to the output terminal W.

[0022] On the other hand, the anode of the temperature sensing diode 6X, which detects the temperature of the switching element 4X, is connected to the alarm output circuit 80, and the cathode of the temperature sensing diode 6X is connected to GND. The anode of the temperature sensing diode 6Y, which detects the temperature of the switching element 4Y, is connected to the alarm output circuit 80, and the cathode of the temperature sensing diode 6Y is connected to GND. The anode of the temperature sensing diode 6Z, which detects the temperature of the switching element 4Z, is connected to the alarm output circuit 80, and the cathode of the temperature sensing diode 6Z is connected to GND.

[0023] The drive circuit 7U controls the drive of the switching element 4U based on the drive control signal InU transmitted from the control unit 3. The drive circuit 7U also generates an alarm signal HALM(U phase) regarding the temperature state of the switching element 4U based on the temperature signal from the temperature sensing diode 6U and transmits it to the control unit 3.

[0024] The drive circuit 7V controls the drive of the switching element 4V based on the drive control signal InV transmitted from the control unit 3. The drive circuit 7V also generates an alarm signal HALM(V phase) regarding the temperature state of the switching element 4V based on the temperature signal from the temperature sensing diode 6V and transmits it to the control unit 3.

[0025] The drive circuit 7W controls the drive of the switching element 4W based on the drive control signal InW transmitted from the control unit 3. The drive circuit 7W also generates an alarm signal HALM (W phase) regarding the temperature state of the switching element 4W based on the temperature signal from the temperature sensing diode 6W and transmits it to the control unit 3.

[0026] Meanwhile, the drive circuit 8X controls the drive of the switching element 4X based on the drive control signal InX transmitted from the control unit 3, and the drive circuit 8Y controls the drive of the switching element 4Y based on the drive control signal InY transmitted from the control unit 3. The drive circuit 8Z controls the drive of the switching element 4Z based on the drive control signal InZ transmitted from the control unit 3.

[0027] The alarm output circuit 80 generates an alarm signal LALM (X phase) regarding the temperature state of the switching element 4X based on the temperature signal from the temperature detection diode 6X and transmits it to the control unit 3. The alarm output circuit 80 also generates an alarm signal LALM (Y phase) regarding the temperature state of the switching element 4Y based on the temperature signal from the temperature detection diode 6Y and transmits it to the control unit 3. Furthermore, the alarm output circuit 80 generates an alarm signal LALM (Z phase) regarding the temperature state of the switching element 4Z based on the temperature signal from the temperature detection diode 6Z and transmits it to the control unit 3.

[0028] As described above, in the configuration of the reference example semiconductor device 200, there are three output lines for the alarm signal on the high side and one output line for the alarm signal on the low side. This increases the number of pins required to output the alarm signal, which leads to an increase in the size of the device. This embodiment was made in view of this issue, and aims to reduce the size of the device and miniaturize it by aggregating the operation information of the switching elements (corresponding to the alarm signal) and notifying it externally.

[0029] Next, the semiconductor device of this embodiment will be described in detail. Figure 3 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 1-1 includes an HVIC (High Voltage IC) 100, a high-side switching circuit UD1, a high-side drive power supply VB, a low-side switching circuit LD1, a low-side drive power supply VCCL, a load 9, and a power supply V3.

[0030] The HVIC100 includes a high-side circuit 10 and a low-side circuit 20. The high-side switching circuit UD1 includes a switching element SW1 and a temperature sensing diode D1, and the low-side switching circuit LD1 includes a switching element SW2 and a temperature sensing diode D2. A control unit 3, such as a microcontroller, is connected to the HVIC100, and the high-side circuit 10 and the low-side circuit 20, respectively, control the driving of the half-bridge connected switching elements SW1 and SW2, using the drive control signals DgH and DgL transmitted from the control unit 3 as input.

[0031] The switching elements SW1 and SW2 are, for example, IGBTs (Insulated Gate Bipolar Transistors). Alternatively, power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) may be used (the following explanation will assume the use of IGBTs).

[0032] The collector of switching element SW1 is connected to the positive terminal of power supply V3. The emitter of switching element SW1 is connected to one end of load 9, the cathode of temperature sensing diode D1, the negative terminal of high-side drive power supply VB, and the collector of switching element SW2. The emitter of switching element SW2 is connected to the negative terminal of power supply V3, the negative terminal of low-side drive power supply VCCL, the other end of load 9, the cathode of temperature sensing diode D2, and GND.

[0033] The high-side circuit 10 is operated by a high-side drive power supply VB, whose reference potential VS is the potential at the connection node n0 between the emitter of switching element SW1 and the collector of switching element SW2.

[0034] The high-side circuit 10 receives the drive control signal DgH for the switching element SW1 transmitted from the control unit 3, generates a drive signal HO, and outputs the drive signal HO to the gate of the switching element SW1 to drive the switching element SW1.

[0035] Furthermore, the high-side circuit 10 provides overcurrent protection for the switching element SW1 using a current signal HOC based on the sense current output from the sense emitter of the switching element SW1 when the switching element SW1 is turned on.

[0036] Furthermore, the high-side circuit 10 provides overheat protection for the switching element SW1 using a temperature signal HOH based on the potential generated in the temperature sensing diode D1 due to the operating temperature of the switching element SW1.

[0037] On the other hand, the low-side circuit 20 operates using a low-side drive power supply VCCL with GND as the reference potential. The low-side circuit 20 receives a drive control signal DgL for the switching element SW2 transmitted from the control unit 3, generates a drive signal LO, and outputs the drive signal LO to the gate of the switching element SW2 to drive the switching element SW2.

[0038] Furthermore, the low-side circuit 20 provides overcurrent protection for the switching element SW2 using a current signal LOC based on the sense current output from the sense emitter of the switching element SW2 when the switching element SW2 is turned on.

[0039] Furthermore, the low-side circuit 20 provides overheat protection for the switching element SW2 using a temperature signal LOH based on the potential generated in the temperature sensing diode D2 due to the operating temperature of the switching element SW2.

[0040] The low-side circuit 20 transmits a clock signal CLK to the high-side circuit 10, and the high-side circuit 10 transmits an operation detection pulse P0, generated from first operation information DH (temperature information, current information, etc. of the switching element SW1), to the low-side circuit 20 in synchronization with the clock signal CLK.

[0041] The low-side circuit 20 then aggregates the operation detection pulse generated from the second operation information of the low-side switching element SW2 and the operation detection pulse P0 generated from the first operation information of the high-side switching element SW1, and transmits notification data Dout, which includes the aggregated operation information of the switching elements SW1 and SW2, to the control unit 3.

[0042] Figure 4 shows an example of the configuration of a high-side circuit. The high-side circuit 10 includes a temperature detection circuit 11, a current detection circuit 12, a driver circuit 13, and a data control circuit 14. The temperature detection circuit 11, the current detection circuit 12, and the data control circuit 14 correspond to the high-side operation detection circuit 1a1 in Figure 1. The temperature detection circuit 11 detects the operating temperature of the high-side switching element SW1 based on the temperature signal HOH and outputs a temperature detection signal OHIN. The current detection circuit 12 detects the current flowing through the high-side switching element SW1 based on the current signal HOC and outputs a current detection signal OCIN.

[0043] The driver circuit 13 outputs a drive signal HO to the gate of the switching element SW1 based on the drive control signal from the control unit 3. Furthermore, if the temperature detection signal OHIN transmitted from the temperature detection circuit 11 indicates an overheating condition, the driver circuit 13 stops outputting the drive signal HO and turns off the switching element SW1. In addition, if the current detection signal OCIN transmitted from the current detection circuit 12 indicates an overcurrent condition, the driver circuit 13 stops outputting the drive signal HO and turns off the switching element SW1.

[0044] The data control circuit 14 includes a digital output circuit 14-1 and a pulse generation circuit 14-2. The digital output circuit 14-1 includes an A / D converter and a latch circuit, which performs A / D conversion of the temperature detection signal OHIN and the current detection signal OCIN to convert them into digital signals and holds the values ​​of the digital signals.

[0045] The pulse generation circuit 14-2 generates an operation detection pulse for transmitting digital signal data to the low-side circuit 20 based on the clock signal CLK transmitted from the low-side circuit 20.

[0046] The transmission circuit 15 has a level conversion function for clock transmission from the low side to the high side and data transmission from the high side to the low side. The transmission circuit 15 transmits the clock signal CLK transmitted from the low side circuit 20 to the pulse generation circuit 14-2, and transmits the operation detection pulse P0 (a pulse containing the first operation information of the high-side switching element SW1) generated by the pulse generation circuit 14-2 to the low side circuit 20. The low side circuit 20 transmits notification data Dout to the control unit 3, which aggregates the temperature / current information of the high-side switching element SW1 and the low-side switching element SW2 that have been transmitted.

[0047] In the above example, temperature and current information were detected to detect the operation information of the switching element, but voltage information can also be included. Voltage information could include, for example, the voltage applied to the collector of the switching element or the voltage applied to the gate of the switching element.

[0048] In this case, the high-side circuit 10 transmits an operation detection pulse P0 containing the detected voltage information to the low-side circuit 20 in synchronization with the clock signal CLK. The low-side circuit 20 then transmits notification data Dout to the control unit 3, which aggregates the voltage information of the high-side switching element SW1 and the voltage information of the low-side switching element SW2.

[0049] Figure 5 shows an example of the internal configuration of the high-side and low-side circuits. The HVIC100a includes a U-phase high-side circuit 10a, a V-phase high-side circuit 10b, a W-phase high-side circuit 10c, and a low-side circuit 20. Note that the driver circuits 13 are not shown for the high-side circuits 10a, 10b, and 10c. The low-side circuit 20 shows an example of an internal configuration for collecting X-phase temperature information.

[0050] High-side circuit 10a includes a temperature detection circuit 11a, a current detection circuit 12a, a data control circuit 14a, and a transmission circuit 15a. High-side circuit 10b includes a temperature detection circuit 11b, a current detection circuit 12b, a data control circuit 14b, and a transmission circuit 15b. High-side circuit 10c includes a temperature detection circuit 11c, a current detection circuit 12c, a data control circuit 14c, and a transmission circuit 15c.

[0051] The low-side circuit 20 includes a temperature detection circuit 21, a digital output circuit 22, an aggregation unit 23, an oscillator 24 (clock circuit), and a communication circuit 25. The temperature detection circuit 21 and the digital output circuit 22 correspond to the low-side operation detection circuit 1b1 in Figure 1. The aggregation unit 23, oscillator 24, and communication circuit 25 correspond to the operation information notification circuit 1b2 in Figure 1.

[0052] The transmission circuit 15a within the high-side circuit 10a includes a high-voltage transistor element PMOS transistor PU, a high-voltage transistor element NMOS transistor NU, a resistor R1 (first resistor), and a resistor R2 (second resistor).

[0053] The source of the PMOS transistor PU is connected to one end of resistor R1, and the voltage of the high-side drive power supply VB1 is applied to it. The drain of the PMOS transistor PU is connected to one end of resistor R2 and to the first input terminal of the aggregation unit 23. The gate of the PMOS transistor PU is connected to the output terminal of the data control circuit 14a.

[0054] Furthermore, the other end of resistor R1 is connected to the drain of NMOS transistor NU and the clock input terminal of data control circuit 14a. The source of NMOS transistor NU is connected to the other end of resistor R2 and GND. The gate of NMOS transistor NU is connected to the first output terminal of oscillator 24.

[0055] The transmission circuit 15b within the high-side circuit 10b includes a high-voltage transistor element PMOS transistor PV, a high-voltage transistor element NMOS transistor NV, a resistor R3 (first resistor), and a resistor R4 (second resistor).

[0056] The source of the PMOS transistor PV is connected to one end of resistor R3, and the voltage of the high-side drive power supply VB2 is applied to it. The drain of the PMOS transistor PV is connected to one end of resistor R4 and to the second input terminal of the aggregation unit 23. The gate of the PMOS transistor PV is connected to the output terminal of the data control circuit 14b.

[0057] Furthermore, the other end of resistor R3 is connected to the drain of NMOS transistor NV and the clock input terminal of data control circuit 14b. The source of NMOS transistor NV is connected to the other end of resistor R4 and GND. The gate of NMOS transistor NV is connected to the second output terminal of oscillator 24.

[0058] The transmission circuit 15c within the high-side circuit 10c includes a high-voltage transistor element PMOS transistor PW, a high-voltage transistor element NMOS transistor NW, a resistor R5 (first resistor), and a resistor R6 (second resistor).

[0059] The source of the PMOS transistor PW is connected to one end of resistor R5, and the voltage of the high-side drive power supply VB3 is applied to it. The drain of the PMOS transistor PW is connected to one end of resistor R6 and the third input terminal of the aggregation unit 23. The gate of the PMOS transistor PW is connected to the output terminal of the data control circuit 14c.

[0060] Also, the other end of resistor R5 is connected to the drain of NMOS transistor NW and the clock input terminal of data control circuit 14c. The source of NMOS transistor NW is connected to the other end of resistor R6 and GND. The gate of NMOS transistor NW is connected to the third output terminal of oscillator 24.

[0061] Note that the low-side circuit 20 operates with the voltage of the low-side drive power supply VCCL (e.g., 15V) having GND as the reference potential, while the high-side circuit 10 operates with the high-side drive power supply VB having the floating potential VS as the reference potential, and may vary up to about 800V, for example. Therefore, high-voltage-resistant transistor elements are used for the PMOS transistor and NMOS transistor provided in the transmission circuit 15 within the high-side circuit 10.

[0062] <Transmission of Operation Information from U-Phase High-Side Circuit 10a to Low-Side Circuit 20> Oscillator 24 within low-side circuit 20 outputs clock signal CLK1 when collecting operation information from the U-phase high-side. NMOS transistor NU turns on every H-level period of clock signal CLK1 according to the clock signal CLK1 input to its gate. Then, clock signal CLK1 is transmitted to the clock input terminal of data control circuit 14a through the drain of NMOS transistor NU.

[0063] On the other hand, data control circuit 14a converts the temperature detection signal OHIN output from temperature detection circuit 11a or the current detection signal OCIN output from current detection circuit 12a into a digital signal to generate a serial operation detection pulse, and outputs it to the gate of PMOS transistor PU in synchronization with clock signal CLK1.

[0064] PMOS transistor PU turns on every L-level period of the operation detection pulse input to its gate. Then, the operation detection pulse P1 of the temperature data or current data in the switching element of the high-side U-phase is transmitted to the first input terminal of aggregator 23 through the drain of PMOS transistor PU.

[0065] <Transmission of operation information from the V-phase high-side circuit 10b to the low-side circuit 20> When the oscillator 24 in the low-side circuit 20 collects operation information from the V-phase high-side, it outputs a clock signal CLK2. The NMOS transistor NV is turned on every H-level period of the clock signal CLK2 by the clock signal CLK2 input to its gate. Then, the clock signal CLK2 is transmitted to the clock input terminal of the data control circuit 14b through the drain of the NMOS transistor NV.

[0066] On the other hand, the data control circuit 14b converts the temperature detection signal OHIN output from the temperature detection circuit 11b or the current detection signal OCIN output from the current detection circuit 12b into a digital signal to generate a serial operation detection pulse, and outputs it to the gate of the PMOS transistor PV in synchronization with the clock signal CLK2.

[0067] The PMOS transistor PV is turned on every L-level period of the operation detection pulse input to its gate. Then, the operation detection pulse P2 of the temperature data or current data in the switching element of the high-side V-phase is transmitted to the second input terminal of the aggregation unit 23 through the drain of the PMOS transistor PV.

[0068] <Transmission of operation information from the W-phase high-side circuit 10c to the low-side circuit 20> When the oscillator 24 in the low-side circuit 20 collects operation information from the W-phase high-side, it outputs a clock signal CLK3. The NMOS transistor NW is turned on every H-level period of the clock signal CLK3 by the clock signal CLK3 input to its gate. Then, the clock signal CLK3 is transmitted to the clock input terminal of the data control circuit 14c through the drain of the NMOS transistor NW.

[0069] Meanwhile, the data control circuit 14c converts the temperature detection signal OHIN output from the temperature detection circuit 11c or the current detection signal OCIN output from the current detection circuit 12c into a digital signal to generate a serial operation detection pulse, which is output to the gate of the PMOS transistor PW in synchronization with the clock signal CLK3.

[0070] The PMOS transistor PW turns on with each L-level period of the operation detection pulse input to its gate. Then, the operation detection pulse P3 for temperature data or current data in the high-side W-phase switching element is transmitted to the third input terminal of the aggregation unit 23 through the drain of the PMOS transistor PW.

[0071] <Output of operational information aggregated by the low-side circuit 20 to the outside> The low-side circuit 20 notifies the control unit 3 of temperature information as operational information. The temperature detection circuit 21 detects the operating temperature of the switching element on the low-side based on the temperature signal HOH in the X phase and outputs a temperature detection signal OHIN. The digital output circuit 22 performs A / D conversion of the temperature detection signal OHIN to convert it into a digital signal and holds the value of the digital signal. The digital output circuit 22 also receives the clock signal CLK4 output from the fourth output terminal of the oscillator 24 and transmits temperature-related operation detection pulses to the aggregation unit 23 in synchronization with the clock signal CLK4.

[0072] The aggregation unit 23 receives the clock signal CLK4 and aggregates the operation detection pulses P1, P2, and P3 transmitted from the high-side circuits 10a, 10b, and 10c, respectively, and the low-side X-phase operation detection pulse output from the digital output circuit 22. The communication circuit 25 then controls the communication interface with the communication partner and outputs the aggregated data to the outside as notification data Dout. For example, the communication circuit 25 outputs the notification data Dout to the control unit 3. The notification data Dout also includes the clock signal (for example, the clock signal CLK4).

[0073] Figure 6 shows an example of bit allocation for notification data. The notification data Dout has an identification code part f1 and a data part f2. In the example in Figure 6, the data is 10 bits, with the upper 4 bits being the identification code part f1 and the remaining 6 bits being the data part f2.

[0074] The identification code section f1 contains a first identification code related to the phase of the switching element and a second identification code related to the operation information. The first identification code indicates the phase in which the high-side switching element or low-side switching element is located (for example, a U-phase switching element). The second identification code indicates that the operating state of the high-side switching element or low-side switching element is one of the following: temperature state, current information, or voltage information. The data section f2 corresponds to the payload area and contains digital data information that is the detected value of the operating state of the high-side switching element or low-side switching element.

[0075] Figure 7 shows an example of the waveform of a clock signal indicating the start and end of communication for an action detection pulse. (a) shows the case where multiple action information is transmitted in the interval between the start and end of communication, and (b) shows the case where one action information is transmitted in the interval between the start and end of communication.

[0076] When the low-side circuit 20 collects operational information from the high-side circuit 10, the low-side circuit 20 transmits a clock signal CLK to a designated high-side circuit 10. When the high-side circuit 10 detects the clock signal CLK, it determines that communication has started and transmits an operation detection pulse to the low-side circuit 20. The high-side circuit 10 also determines that data communication has ended after data transmission.

[0077] On the other hand, as shown in Figure 7(a), data transmission from the high-side circuit 10 to the low-side circuit 20 can be performed by inserting multiple operational information, such as temperature data and current data, into the section between the start and end of communication.

[0078] Alternatively, as shown in Figure 7(b), it is possible to transmit one piece of operational information at a time between the start and end of communication, such as inserting temperature data in one interval between the start and end of communication and current data in another interval between the start and end of communication.

[0079] Figure 8 shows the configuration of a modified HVIC. On the high-side, only the internal configuration of the U-phase high-side circuit 10a1 is shown, and the V-phase and W-phase high-side circuits are omitted. The modified HVIC 100b includes a high-side circuit 10a1 and a low-side circuit 20a. Note that the driver circuit 13 is not shown for the high-side circuit 10a1. The low-side circuit 20a shows an example of an internal configuration for collecting X-phase temperature information.

[0080] The high-side circuit 10a1 includes a temperature detection circuit 11a, a current detection circuit 12a, a data control circuit 14a1, and a transmission circuit 15a1. The low-side circuit 20a includes a temperature detection circuit 21, a digital output circuit 22, an aggregation unit 23, an oscillator 24a (clock circuit), a communication circuit 25, and an RS flip-flop 26 (low-side RS flip-flop). The RS flip-flop 26 is included in the function of the operation information notification circuit 1b2.

[0081] The transmission circuit 15a1 within the high-side circuit 10a1 includes an RS flip-flop 150 (high-side RS flip-flop), a PMOS transistor P1 (first PMOS transistor), a PMOS transistor P2 (second PMOS transistor), an NMOS transistor N1 (first NMOS transistor), an NMOS transistor N2 (second NMOS transistor), and resistors R11 (first resistor), R12 (second resistor), R13 (third resistor), and R14 (fourth resistor).

[0082] In the modified configuration, the data control circuit 14a1 outputs parallel operation detection pulses from the first and second output terminals. The transmission circuit 15a1 is equipped with two NMOS transistors N1 and N2 for inputting the reset / set clock signal to the RS flip-flop 150, and two PMOS transistors P1 and P2 for transmitting the parallel operation detection pulses to the low-side circuit 20.

[0083] The source of PMOS transistor P1 is connected to the source of PMOS transistor P2, one end of resistor R11, and one end of resistor R12, and the voltage of the high-side drive power supply VB1 is applied. The drain of PMOS transistor P1 is connected to one end of resistor R13 and the reset input terminal R of RS flip-flop 26. The gate of PMOS transistor P1 is connected to the first output terminal of data control circuit 14a1. The output terminal Q of RS flip-flop 26 is connected to the input terminal of aggregation unit 23.

[0084] The drain of PMOS transistor P2 is connected to one end of resistor R14 and the set input terminal S of RS flip-flop 26. The gate of PMOS transistor P2 is connected to the second output terminal of data control circuit 14a1.

[0085] The other end of resistor R11 is connected to the set input terminal S of RS flip-flop 150 and the drain of NMOS transistor N1. The other end of resistor R12 is connected to the reset input terminal R of RS flip-flop 150 and the drain of NMOS transistor N2. The output terminal Q of RS flip-flop 150 is connected to the clock input terminal of data control circuit 14a1.

[0086] The gate of NMOS transistor N1 is input to the set clock signal SET(CLK) output from oscillator 24a, and the gate of NMOS transistor N2 is input to the reset clock signal RESET(CLK) output from oscillator 24a. Oscillator 24a also outputs clock signals to the aggregation unit 23 and the digital output circuit 22, as in Figure 5. The other end of resistor R13 is connected to the other end of resistor R14, the source of NMOS transistor N1, the source of NMOS transistor N2, and GND.

[0087] Figure 9 shows an example of a timing chart for operating waveform pulse transmission. CLK0 is a clock signal output from RS flip-flop 150 and input to data control circuit 14a1.

[0088] SET(DATA) is the data that is turned on / off by the output from the second output terminal of the data control circuit 14a1 (second operation detection pulse) and input to the set input terminal S of the RS flip-flop 26.

[0089] RESET(DATA) is the data that is input to the reset input terminal R of the RS flip-flop 26 when the PMOS transistor P1 is turned on / off by the output from the first output terminal of the data control circuit 14a1 (first operation detection pulse). Q(DATA) is the data output from the output terminal Q of the RS flip-flop 26.

[0090] Furthermore, if we represent SET(DATA) as S, RESET(DATA) as R, and Q(DATA) as Q, and show the relationship of truth values, then (S, R, Q) = (1, 0, 0), (S, R, Q) = (0, 0, hold), and (S, R, Q) = (0, 1, 1).

[0091] [Period cy1] SET(DATA) is at a high level on the rising edge of CLK0 and at a low level on the falling edge of CLK0. RESET(DATA) is at a low level. Therefore, Q(DATA) transitions to a low level from the rising edge of CLK0.

[0092] [Period cy2] SET(DATA) is at the L level. RESET(DATA) becomes H level on the rising edge of CLK0 and L level on the falling edge of CLK0. Therefore, Q(DATA) transitions to the H level from the rising edge of CLK0.

[0093] [Periodic cy3] SET(DATA) is at the L level. RESET(DATA) is at the L level. Therefore, Q(DATA) remains at the H level. [Period cy4] ​​SET(DATA) is at a high level on the rising edge of CLK0 and at a low level on the falling edge of CLK0. RESET(DATA) is at a low level. Therefore, Q(DATA) transitions to a low level from the rising edge of CLK0.

[0094] As described above, when transmitting an operation detection pulse from the high-side to the low-side, it is transmitted in synchronization with the clock signal generated by the low-side circuit 20a. For example, when the high-side circuit 10a1 sets the output of Q(DATA) to "0", it turns on SET(DATA), and when it changes Q(DATA) from "0" to "1", it turns on RESET(DATA).

[0095] Figure 10 shows a modified configuration of the HVIC including a gate drive function. The HVIC100c includes a high-side circuit 110 and a low-side circuit 120. The HVIC100c includes IGBTs 131 and 132 in its output section, and a load 9 and power supplies V1, V2, and V3 are connected to the output section. Furthermore, the HVIC100c in Figure 10 shows a configuration of a data transmission function for transmitting operation detection pulses and a gate drive function for driving the IGBTs.

[0096] The data transmission function of the high-side circuit 110 includes an RS flip-flop 111, inverter elements 112 and 113, a data (high-side data) circuit 114, diodes D21, D22, D23 and D24, resistors R21 and R22, and PMOS transistors P21 and P22.

[0097] The gate drive function of the high-side circuit 110 includes a latch / driver 115, diodes D25, D26, D27, D28, and resistors R23, R24. Parasitic capacitance exists between the source and drain of PMOS transistors P21 and P22. Diodes D21 to D28 are elements intended to stabilize the potential fluctuation between the voltage VB and the reference potential VS, and Zener diodes are used as an example.

[0098] On the other hand, the data transmission function of the low-side circuit 120 includes a control circuit 121, an RS flip-flop 122, diodes D29 and D30, resistors R25 and R26, and NMOS transistors N21 and N22.

[0099] The gate drive function of the low-side circuit 120 includes a pulse circuit 123, a latch / driver 124, and NMOS transistors N23 and N24. Note that parasitic capacitance exists between the drain and source of NMOS transistors N21 to N24. Furthermore, diodes D29 and D30 are elements intended to stabilize potential fluctuations between the voltage VCCL and GND; Zener diodes are used as an example.

[0100] In the connection relationships of each component, the positive terminal of power supply V1 is connected to the cathodes of diodes D21, D22, D25, and D26, one end of resistors R21, R22, R23, and R24, the sources of PMOS transistors P21 and P22, the power supply terminal of data circuit 114, and the power supply terminal of latch / driver 115.

[0101] The negative terminal of power supply V1 is connected to the anodes of diodes D23, D24, D27, and D28, the ground terminal of RS flip-flop 111, the ground terminal of data circuit 114, and the ground terminal of latch / driver 115. Furthermore, the negative terminal of power supply V1 is connected to the emitter of IGBT 131, one end of load 9, and the collector of IGBT 132.

[0102] The anode of diode D21 is connected to the other end of resistor R21, the reset input terminal R of RS flip-flop 111, the cathode of diode D23, and the drain of NMOS transistor N21.

[0103] The anode of diode D22 is connected to the other end of resistor R22, the set input terminal S of RS flip-flop 111, the cathode of diode D24, and the drain of NMOS transistor N22.

[0104] The output terminal Q of RS flip-flop 111 is connected to the clock input terminal of data circuit 114. The drain of PMOS transistor P21 is connected to the reset input terminal R of RS flip-flop 122, the cathode of diode D29, and one end of resistor R25. The drain of PMOS transistor P22 is connected to the set input terminal S of RS flip-flop 122, the cathode of diode D30, and one end of resistor R26.

[0105] The input terminal of inverter element 112 is connected to the first output terminal of data circuit 114, and the input terminal of inverter element 113 is connected to the second output terminal of data circuit 114. The output terminal of inverter element 112 is connected to the gate of PMOS transistor P21, and the output terminal of inverter element 113 is connected to the gate of PMOS transistor P22.

[0106] The anode of diode D25 is connected to the other end of resistor R23, the first input terminal of latch / driver 115, the cathode of diode D27, and the drain of NMOS transistor N23.

[0107] The anode of diode D26 is connected to the other end of resistor R24, the second input terminal of latch / driver 115, the cathode of diode D28, and the drain of NMOS transistor N24. The output terminal of latch / driver 115 is connected to the gate of IGBT 131 and the input terminal of data circuit 114.

[0108] The positive terminal of power supply V2 is connected to the power terminal of RS flip-flop 122 and the power terminal of latch / driver 124. The negative terminal of power supply V2 is connected to the ground terminal of control circuit 121, the ground terminal of RS flip-flop 122, the sources of NMOS transistors N21 and N22, the anodes of diodes D29 and D30, the other ends of resistors R25 and R26, the ground terminal of pulse circuit 123, the sources of NMOS transistors N23 and N24, and the ground terminal of latch / driver 124. Furthermore, the negative terminal of power supply V2 is connected to the emitter of IGBT 132, the other end of load 9, the negative terminal of power supply V3, and GND. The positive terminal of power supply V3 is connected to the collector of IGBT 131.

[0109] The first clock output terminal (CLK) of the control circuit 121 is connected to the clock input terminal of the control unit 3. The data output terminal (DATA) of the control circuit 121 is connected to the data input terminal of the control unit 3. The pulse generation instruction (IN) output from the control unit 3 is input to the input terminal of the pulse circuit 123.

[0110] The clock input terminal of control circuit 121 is connected to the output terminal Q of RS flip-flop 122. The second clock output terminal (RESET (CLK)) of control circuit 121 is connected to the gate of NMOS transistor N21, and the third clock output terminal (SET (CLK)) of control circuit 121 is connected to the gate of NMOS transistor N22.

[0111] The first output terminal of pulse circuit 123 is connected to the gate of NMOS transistor N23, and the second output terminal of pulse circuit 123 is connected to the gate of NMOS transistor N24. The output terminal of latch / driver 124 is connected to the gate of IGBT 132.

[0112] Figure 11 shows an example of a timing chart for a data transmission function. RESET(CLK) is input to the gate of NMOS transistor N21, and SET(CLK) is input to the gate of NMOS transistor N22. The phase relationship between SET(CLK) and RESET(CLK) is shifted by a period T from each other.

[0113] SET (CLK) is input to the set input terminal S of the RS flip-flop 111 through the NMOS transistor N22, and RESET (CLK) is input to the reset input terminal R of the RS flip-flop 111 through the NMOS transistor N21.

[0114] Therefore, the output terminal Q of the RS flip-flop 111 outputs a clock signal CLK that is high level from the rising edge of SET(CLK) to the rising edge of RESET(CLK), and low level from the rising edge of RESET(CLK) to the rising edge of SET(CLK).

[0115] Here, it is assumed that the following data is output from inverter elements 112 and 113 for each bit of the clock signal CLK. [Clock signal CLK: 10th, 9th, and 8th bits] An L-level SET (DATA) signal is output from inverter element 113, and an L-level RESET (DATA) signal is output from inverter element 112.

[0116] [Clock signal CLK: 7th bit] When the clock signal CLK is at a high level, inverter element 113 outputs a high-level SET(DATA), and when the clock signal CLK is at a low level, inverter element 112 outputs a high-level RESET(DATA).

[0117] [Clock signal CLK: 6th bit] When the clock signal CLK is at a high level, inverter element 113 outputs a high-level SET(DATA), and when the clock signal CLK is at a low level, inverter element 112 outputs a high-level RESET(DATA).

[0118] [Clock signal CLK: 5th bit] A low-level SET (DATA) signal is output from inverter element 113, and a low-level RESET (DATA) signal is output from inverter element 112.

[0119] [Clock signal CLK: 4th bit] When the clock signal CLK is at a high level, inverter element 113 outputs a high-level SET(DATA), and when the clock signal CLK is at a low level, inverter element 112 outputs a high-level RESET(DATA).

[0120] [Clock signal CLK: 3rd bit] A low-level SET (DATA) signal is output from inverter element 113, and a low-level RESET (DATA) signal is output from inverter element 112.

[0121] [Clock signal CLK: 2nd bit] When the clock signal CLK is at a high level, inverter element 113 outputs a high-level SET(DATA), and when the clock signal CLK is at a low level, inverter element 112 outputs a high-level RESET(DATA).

[0122] [Clock signal CLK: 1st bit] An L-level SET (DATA) is output from inverter element 113, and an L-level RESET (DATA) is output from inverter element 112.

[0123] Since the RESET(DATA) and SET(DATA) values ​​described above are input to the reset input terminal R and the set input terminal S of the RS flip-flop 122, respectively, the following data is output from the output terminal Q of the RS flip-flop 122.

[0124] [Clock signal CLK: 10th, 9th, and 8th bits] The data "0" is output from the output terminal Q of RS flip-flop 122. [Clock signal CLK: 7th bit] From the output terminal Q of RS flip-flop 122, the data "1" is output from the rising edge of SET(DATA) to the rising edge of RESET(DATA).

[0125] [Clock signal CLK: 6th bit] From the output terminal Q of RS flip-flop 122, the data "1" is output from the rising edge of SET(DATA) to the rising edge of RESET(DATA).

[0126] [Clock signal CLK: 5th bit] The data "0" is output from the output terminal Q of RS flip-flop 122. [Clock signal CLK: 4th bit] From the output terminal Q of RS flip-flop 122, the data "1" is output from the rising edge of SET(DATA) to the rising edge of RESET(DATA).

[0127] [Clock signal CLK: 3rd bit] The data "0" is output from the output terminal Q of RS flip-flop 122. [Clock signal CLK: 2nd bit] From the output terminal Q of RS flip-flop 122, the data "1" is output from the rising edge of SET(DATA) to the rising edge of RESET(DATA).

[0128] [Clock signal CLK: 1st bit] The data "0" is output from the output terminal Q of RS flip-flop 122. As described above, for each of the 10th bit through the 1st bit of the clock signal CLK, the data “0001101010” is output from the RS flip-flop 122 to the control circuit 121. The control circuit 121 transmits the data “0001101010” and the clock signal CLK to the control unit 3 to notify the control unit 3 of the operation information on the high side. The data from the 10th bit through the 7th bit is the identification code part f1, and the data from the 6th bit through the 1st bit is the data part f2.

[0129] As described above, this embodiment provides a configuration that aggregates operation information from the high-side and low-side and notifies the outside. This allows the number of pins used to output operation information such as alarm signals to the outside to be reduced to one, making it possible to reduce the size of the device and miniaturize it.

[0130] Although embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Furthermore, various modifications or improvements can be made to the above embodiments. Moreover, the technical scope of the present invention may also include modified or improved forms and their equivalents without departing from the spirit of the invention. [Explanation of symbols]

[0131] 1 Semiconductor device 1a High-side circuit 1a1 High-side operation detection circuit 1a2 Transmission Circuit 1b Low-side circuit 1b1 Low-side motion detection circuit 1b2 Operation information notification circuit 1c output section 1c1 High-side switching element 1c2 Low-side switching element 9 Load DgH High-side drive control signal DgL Low-Side Drive Control Signal DH 1st Operation Information DL 2nd operation information

Claims

1. An output section including a high-side switching element and a low-side switching element that are connected to a load and drive the load, A high-side circuit including a high-side operation detection circuit that detects the operating state of the high-side switching element and generates first operation information, and a transmission circuit that transmits the first operation information to the low-side side, A low-side circuit includes a low-side operation detection circuit that detects the operating state of the low-side switching element and generates second operation information, and an operation information notification circuit that receives the first operation information and the second operation information transmitted from the high-side circuit and provides external notification of at least one of the first operation information or the second operation information. Semiconductor device.

2. The high-side operation detection circuit detects at least one of the temperature state, current state, and voltage state of the high-side switching element and generates the first operation information. The low-side operation detection circuit detects at least one of the temperature state, current state, and voltage state of the low-side switching element and generates the second operation information. The semiconductor device according to claim 1.

3. The operation information notification circuit includes a clock circuit that generates a clock signal, and the high-side operation detection circuit includes a data control circuit that converts the first operation information into a digital signal and generates an operation detection pulse from the digital signal. The transmission circuit transmits the clock signal to the data control circuit. The data control circuit generates the operation detection pulse from the first operation information based on the clock signal, The transmission circuit transmits the operation detection pulse to the operation information notification circuit. The semiconductor device according to claim 2.

4. The transmission circuit comprises a PMOS transistor, a high-voltage transistor element, an NMOS transistor, a first resistor, and a second resistor. One end of the first resistor is connected to the power supply terminal of the high-side circuit and the source of the PMOS transistor. The other end of the first resistor is connected to the drain of the NMOS transistor and to the clock input terminal of the data control circuit to which the clock signal is input. The gate of the NMOS transistor is connected to the output terminal of the clock circuit that outputs the clock signal. The gate of the PMOS transistor is connected to the output terminal of the data control circuit that outputs the operation detection pulse. The drain of the PMOS transistor is connected to one end of the second resistor. The other end of the second resistor is connected to the source of the NMOS transistor and grounded. The semiconductor device according to claim 3.

5. The operation information notification circuit includes a clock circuit that generates a clock signal, and the high-side operation detection circuit includes a data control circuit that converts the first operation information into a digital signal and generates an operation detection pulse from the digital signal. The transmission circuit transmits the clock signal to the data control circuit. The data control circuit generates a first operation detection pulse and a second operation detection pulse from the first operation information based on the clock signal. The transmission circuit transmits the first operation detection pulse and the second operation detection pulse to the operation information notification circuit. The semiconductor device according to claim 2.

6. The transmission circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a high-side RS flip-flop, and the operation information notification circuit further comprises a low-side RS flip-flop. One end of the first resistor is connected to the power supply terminal of the high-side circuit, the source of the first PMOS transistor, the source of the second PMOS transistor, and one end of the second resistor. The other end of the first resistor is connected to the set input terminal of the high-side RS flip-flop and the drain of the first NMOS transistor. The other end of the second resistor is connected to the reset input terminal of the high-side RS flip-flop and the drain of the second NMOS transistor. The gate of the first NMOS transistor is connected to the first output terminal of the clock circuit to which the set clock signal is output. The gate of the second NMOS transistor is connected to the second output terminal of the clock circuit to which the reset clock signal is output. The gate of the first PMOS transistor is connected to the first output terminal of the data control circuit to which the first operation detection pulse is output. The gate of the second PMOS transistor is connected to the second output terminal of the data control circuit, which outputs the second operation detection pulse. The drain of the first PMOS transistor is connected to the reset input terminal of the low-side RS flip-flop and to one end of the third resistor. The drain of the second PMOS transistor is connected to the set input terminal of the low-side RS flip-flop and one end of the fourth resistor. The other end of the third resistor is connected to the other end of the fourth resistor, the source of the first NMOS transistor, and the source of the second NMOS transistor, and is grounded. The semiconductor device according to claim 5.

7. The operation information notification circuit notifies an external party of data including an identification code section that includes a first identification code indicating the phase on which the high-side switching element or the low-side switching element is located, a second identification code indicating that the operation information of the high-side switching element or the low-side switching element is one of temperature information, current information, or voltage information, and a data section that is a detected data value of the operating state of the high-side switching element or the low-side switching element. The semiconductor device according to claim 1.

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