Design methods, programs, and semiconductor memory devices

Abstract

To suppress variations in the layer thickness of the resist pattern on multiple contact holes with different reach depths. [Solution] The design method of the embodiment is a design method for determining the arrangement of a plurality of holes with different reach depths, and when there is one or more design constraints, when a resin layer is formed covering a plurality of holes having a first arrangement that satisfies one or more constraints, the first layer thickness difference caused by a part of the resin layer flowing into the plurality of holes is calculated in the resin layer on the plurality of holes, and it is determined whether the first layer thickness difference is less than or equal to a predetermined upper limit value, and if the first layer thickness difference exceeds the upper limit value, the arrangement of the plurality of holes is changed to a second arrangement that satisfies one or more constraints, and the second layer thickness difference caused in the resin layer on the plurality of holes is calculated, and it is determined whether the second layer thickness difference is less than or equal to an upper limit value, and if the second layer thickness difference is less than or equal to an upper limit value, the second arrangement is adopted.

Description

Technical Field

[0001] Embodiments of the present invention relate to a design method, a program, and a semiconductor memory device.

Background Art

[0002] In a semiconductor memory device such as a three-dimensional non-volatile memory, a plurality of conductive layers are stacked, and a plurality of contacts connected to each of these conductive layers at different depth positions are formed. Such contacts are obtained by repeatedly forming a resist pattern and contacts holes having different reach depths a plurality of times. When repeatedly forming a resist pattern on a plurality of contact holes having different reach depths, controlling the layer thickness of the resist pattern has been an issue.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a design method, a program, and a semiconductor memory device capable of suppressing variations in the layer thickness of a resist pattern on a plurality of contact holes having different reach depths.

Means for Solving the Problems

[0005] The design method of the embodiment is a design method for determining the arrangement of a plurality of holes with different reach depths, and when one or more design constraints exist, when a resin layer is formed covering the plurality of holes having a first arrangement that satisfies the one or more constraints, a first layer thickness difference caused by a part of the resin layer flowing into the plurality of holes is calculated in the resin layer on the plurality of holes, and it is determined whether the first layer thickness difference is less than or equal to a predetermined upper limit value, and if the first layer thickness difference exceeds the upper limit value, when the arrangement of the plurality of holes is changed to a second arrangement that satisfies the one or more constraints, a second layer thickness difference caused in the resin layer on the plurality of holes is calculated, and it is determined whether the second layer thickness difference is less than or equal to the upper limit value, and if the second layer thickness difference is less than or equal to the upper limit value, the second arrangement is adopted. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic diagram showing an example of the general configuration of a semiconductor memory device according to Embodiment 1. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to Embodiment 1. [Figure 3] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 4] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 5] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 6] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 7] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 8] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 9] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 10]A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 11] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 12] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 13] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 14] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 15] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 16] A cross-sectional view showing an example of the arrangement of contact holes in a comparative example. [Figure 17] A diagram illustrating a part of the procedure for manufacturing a semiconductor memory device according to a modified example 1 of Embodiment 1. [Figure 18] A diagram illustrating a part of the procedure for manufacturing a semiconductor memory device according to a modified example 2 of Embodiment 1. [Figure 19] A schematic diagram showing the layout during the manufacturing process of a semiconductor memory device according to a modified example 3 of Embodiment 1. [Figure 20] A diagram illustrating a part of the procedure for manufacturing a semiconductor memory device according to the comparative example. [Figure 21] A diagram illustrating a part of the procedure for manufacturing a semiconductor memory device according to the comparative example. [Figure 22] A block diagram showing an example of the physical configuration of the design device according to Embodiment 2. [Figure 23] A block diagram showing an example of the functional configuration of the design device according to Embodiment 2. [Figure 24] A schematic diagram illustrating an example of the design operation for contact hole arrangement using the design apparatus according to Embodiment 2. [Figure 25] A schematic diagram showing examples of variations in the arrangement of contact holes by the design apparatus according to Embodiment 2. [Figure 26]Flowchart showing an example of the procedure for designing the contact hole layout by the design apparatus according to Embodiment 2. [Figure 27] Schematic diagram for explaining an example of the design operation of the contact hole layout by the design apparatus according to the modified example of Embodiment 2. [Figure 28] Flowchart showing an example of the procedure for designing the contact hole layout by the design apparatus according to the modified example of Embodiment 2.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0008] [Embodiment 1] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0009] (Configuration Example of Semiconductor Memory Device) FIG. 1 is a schematic configuration diagram showing a schematic configuration example of the semiconductor memory device 1 according to Embodiment 1. More specifically, FIG. 1(a) is a cross-sectional view along the X direction of the semiconductor memory device 1, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0010] However, in FIG. 1(a), hatching is omitted for the sake of clarity of the drawing. Also, in FIG. 1(a), some upper-layer wirings and the like are omitted.

[0011] Furthermore, in this specification, both the X and Y directions are directions along the orientation of the surface of the word line WL, and the X and Y directions are orthogonal to each other. The electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is along the X direction. The direction intersecting the first direction may be referred to as the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing tolerances, the first direction and the second direction are not necessarily orthogonal.

[0012] As shown in Figure 1(a), the semiconductor memory device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, and a plurality of word lines WL. Above the plurality of word lines WL, the semiconductor memory device 1 also comprises a peripheral circuit CBA provided on the semiconductor substrate SB.

[0013] A source line SL is arranged on the electrode film EL via an insulating layer 60. Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source line SL and the electrode film EL via the plugs PG. This allows a source potential to be applied to the source line SL from outside the semiconductor memory device 1 via the electrode film EL and plugs PG. Multiple word lines WL are stacked on the source line SL.

[0014] As shown in Figures 1(a) and 1(b), a contact area ER is located in the center of multiple word lines WL, and memory areas MR are located at both ends of multiple word lines WL. These contact areas ER and memory areas MR are divided into multiple regions by multiple plate-like portions LI that penetrate the multiple word lines WL and extend in a direction along the X direction.

[0015] Furthermore, the area located between adjacent plate-shaped parts LI in the Y direction, and including the contact area ER and the memory area MR, is called the block area BLK. As will be described later, the memory area MR contains multiple memory cells that hold data non-volatilely, and the above-mentioned block area BLK serves as the unit for erasing this data.

[0016] Furthermore, among the multiple block regions BLK aligned in the Y direction, the block regions BLK at both ends in the Y direction are dummy block BLKd containing dummy contact regions ERd and dummy memory regions MRd. Although these contact regions ERd and memory regions MRd do not contribute to the operation of the semiconductor memory device 1, they may be configured in the same way as the regular contact regions ER and memory regions MR, which will be described later. By providing dummy block regions BLK in this way, even if there is a quality degradation at the ends in the Y direction, the impact on the overall quality of the semiconductor memory device 1 is suppressed.

[0017] Multiple pillars PL are arranged in the memory region MR, penetrating the word line WL in the stacking direction. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. As a result, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] Multiple contacts CC are arranged in the contact region ER, each connected to a multiple word line WL. In this specification, in the extending direction of the contact CC, the end of the contact CC that connects to the word line WL is considered to be on the lower side of the semiconductor memory device 1.

[0019] From the contact CC, write voltage and read voltage are applied to memory cells included in the memory area MR in the center of multiple word lines WL, via the word lines WL located at the same height as the memory cells. In this way, these contact CCs individually draw out the multi-layered word lines WL.

[0020] As shown in Figure 1(b), in the contact area ER located in the center of multiple word lines WL, the placement positions of multiple contacts CC are shifted relative to each other in the X direction for every two block areas BLK. That is, in Figure 1(b), if two block areas BLK adjacent in the Y direction have the contact CC placement area closer to the memory area MR on the right side of the page, then the next two block areas BLK adjacent to these block areas BLK in the Y direction will have the contact CC placement area closer to the memory area MR on the left side of the page.

[0021] This alternating arrangement ensures that wiring paths are secured to each of the multiple contact CCs, allowing the voltage applied to the memory cell to be supplied to the multiple contact CCs.

[0022] As shown in Figure 1(a), the multiple word lines WL, pillar PL, and contact CC are covered with an insulating layer 50. The insulating layer 50 also extends around the multiple word lines WL.

[0023] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0024] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with the insulating layer 50 covering the laminate LM, a semiconductor memory device 1 is formed that includes multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0025] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to Embodiment 1.

[0026] More specifically, Figure 2(a) is a cross-sectional view along the Y direction showing an example of the configuration of the memory area MR. Figure 2(b) is a cross-sectional view along the X direction showing an example of the configuration of the contact area ER. However, in Figures 2(a) and (b), the structures below the insulating layer 60 and above the insulating layer 40 are omitted.

[0027] As shown in Figure 2(a), in the memory region MR, the source line SL has a multilayer structure in which, for example, the lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are stacked on the insulating layer 60 in this order.

[0028] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be a conductive polysilicon layer with diffused impurities.

[0029] As shown in Figure 2(b), in the contact region ER, the source wire SL has an intermediate insulating layer SCO between the lower source wire DSLa and the upper source wire DSLb, instead of an intermediate source wire BSL. This is because the pillar PL to which the source wire SL is connected is not located in the contact region ER. The intermediate insulating layer SCO is, for example, a silicon oxide layer. However, the source wire SL may also have an intermediate source wire BSL in the contact region ER.

[0030] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time. Laminate LMa is placed above the source line SL, and laminate LMb is placed on top of laminate LMa.

[0031] In the laminate LMa, one or more selectable gate lines SGS are arranged in the layer below the bottom word line WL, via an insulating layer OL. In the example in Figure 2, the laminate LMa has two selectable gate lines SGS0 and SGS1, in that order from the top. In the laminate LMb, one or more selectable gate lines SGD are arranged in the layer above the top word line WL, via an insulating layer OL. In the example in Figure 2, the laminate LMb has two selectable gate lines SGD0 and SGD1, in that order from the top.

[0032] However, the number of stacks of these word lines WL and selected gate lines SGD, SGS in the laminate LM is arbitrary.

[0033] The multiple conductive layers, name lines WL and selection gate lines SGD, SGS, are, for example, tungsten layers or molybdenum layers. The multiple insulating layers OL are, for example, silicon oxide layers.

[0034] The uppermost insulating layer OL of each laminate LMa and LMb is, for example, thicker than other insulating layers OL in the LMa and LMb. The uppermost insulating layer OL of laminate LMa is in contact with the bottommost word line WL of laminate LMb, and insulating layers 52 and 53 are arranged in this order on the uppermost insulating layer OL of laminate LMb. Insulating layers 52 and 53 constitute a part of the insulating layer 50 described above, and the upper surface of insulating layer 53 is in contact with the lower surface of insulating layer 40 on the peripheral circuit CBA side, for example.

[0035] As shown in Figure 2(a), the laminate LM is divided in the Y direction by a plurality of plate-like contacts LI.

[0036] In other words, each of the plate-shaped contacts LI is aligned with the others in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM. Thus, the plate-shaped contacts LI extend continuously within the laminate LM, including the memory area MR and the contact area ER, from one end in the X direction of the laminate LM to the other.

[0037] In the memory region MR, the plate-shaped contact LI penetrates the laminate LM and the upper source wire DSLb, reaching the intermediate source wire BSL. In the contact region ER, the plate-shaped contact LI penetrates the laminate LM and the upper source wire DSLb, reaching the intermediate insulating layer SCO.

[0038] Furthermore, each plate-shaped contact LI includes an insulating layer 55 and a conductive layer 25. The insulating layer 55 is, for example, a silicon oxide layer. The conductive layer 25 is, for example, a tungsten layer or a conductive polysilicon layer.

[0039] The insulating layer 55 covers the side walls of the plate-shaped contact LI that face each other in the Y direction. The conductive layer 25 is filled inside the insulating layer 55. However, instead of the plate-shaped contact LI, a plate-shaped member filled with the insulating layer may penetrate the laminate LM and extend in a direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0040] Multiple isolation layers SHE are arranged between adjacent plate-shaped contacts LI in the Y direction. These isolation layers SHE penetrate the selective gate lines SGD0 and SGD1 of the laminate LMb, reach the insulating layer OL directly beneath the selective gate line SGD1, and are insulating layers 57 such as silicon oxide layers that extend along the X direction within the memory area MR of the laminate LM. With this configuration, the isolation layers SHE selectively separate the selective gate lines SGD0 and SGD1 between the plate-shaped contacts LI in the Y direction.

[0041] In the memory region MR of the stacked LM, multiple pillars PL are distributed and arranged, penetrating the stacked LM, the upper source line DSLb, and the intermediate source line BSL, and reaching the lower source line DSLa.

[0042] Multiple pillars PL are arranged in a periodic, for example, staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape such as a circle, ellipse, or oval shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane.

[0043] The pillar PL comprises a pillar PLa that penetrates the laminate LMa from the uppermost insulating layer OL of the laminate LMa to reach the source wire SL, and a pillar PLb that penetrates the laminate LB from the uppermost insulating layer OL of the laminate Lb to reach the uppermost insulating layer OL of the laminate LMa and is connected to the upper end of the corresponding pillar PLa.

[0044] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN penetrating the laminate LM and connecting to the intermediate source line BSL, and a core layer CR that serves as the core material of the pillar PL.

[0045] The memory layer ME is located on the side of the pillar PL, except at the depth of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, reaching the depth of the lower source line DSLa. The memory layer ME has a multilayer structure in which a block insulating layer, a charge storage layer, and a tunnel insulating layer (none of which are shown) are stacked in this order from the outer periphery of the pillar PL.

[0046] The channel layer CN extends inside the memory layer ME, through the stack LM, the upper source line DSLb, and the intermediate source line BSL, to the depth of the lower source line DSLa. That is, the channel layer CN is located on the sides and bottom of the pillar PL via the memory layer ME. Further inside the channel layer CN is the core layer CR.

[0047] However, a portion of the channel layer CN is in contact with the intermediate source line BSL on its side, thereby electrically connecting to the source line SL, which includes the intermediate source line BSL. Additionally, a cap layer CP is positioned at the upper end of the channel layer CN and is connected to the bit line BL, which extends along the Y direction through the insulating layer 53, via a plug CH located in the insulating layer 52.

[0048] In the cross-section shown in Figure 2(a), of the five pillars PL between adjacent plate-shaped contacts LI in the Y direction, only one pillar PL is connected to the bit line BL via a plug CH. The other pillars PL positioned between the plate-shaped contacts LI are connected at different locations than in the cross-section shown in Figure 2(a), via different plugs CH than those in Figure 2(a), and to different bit lines BL than those in Figure 2(a).

[0049] The block insulating layer and tunnel insulating layer of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN is a semiconductor layer, for example, a polysilicon layer or an amorphous silicon layer.

[0050] With the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0051] Data from the memory cell MC is read out to the bit line BL, which is connected to the pillar PL. The bit line BL is connected to the electrode pad PDb located on the surface of the insulating layer 53. The electrode pad PDb is connected to the electrode pad PDc located on the surface of the insulating layer 40 and electrically connected to the peripheral circuit CBA. As a result, the data from the memory cell MC read out to the bit line BL is processed by the peripheral circuit CBA.

[0052] Furthermore, with the above configuration, a selection gate STD is formed in the portion of the pillar PL side facing each individual selection gate line SGD. Also, a selection gate STS is formed in the portion of the pillar PL side facing each individual selection gate line SGS. When a predetermined voltage is applied from the selection gate lines SGD and SGS, the selection gates STD and STS are turned on or off, and the memory cell MC formed in the pillar PL to which these selection gates STD and STS belong becomes selected or deselected.

[0053] As shown in Figure 2(b), the contact region ER is arranged with multiple contact CCs and multiple columnar parts HRs.

[0054] Some of the multiple contact CCs extend within the laminate LMb in the stacking direction of the laminate LM and are connected to one or more selected gate lines SGD or multiple word lines WL of the laminate LMb, respectively.

[0055] Some of the multiple contact CCs extend through the stacking direction of the laminate LM in the LMa and LMB layers and are connected to one or more selected gate lines SGS belonging to the LMa layer. Although not shown in the diagram, some of the other contact CCs extending through the LMa and LMB layers are also connected to several word lines WL of the LMa layer.

[0056] More specifically, in the semiconductor memory device 1 of Embodiment 1, in the array of multiple contact CCs aligned in the X direction, approximately half of the contact CCs are connected to odd-numbered word lines WL and selection gate lines SGD and SGS, counting from the upper layer side of the laminate LM. On the other hand, the remaining contact CCs are connected to even-numbered word lines WL and selection gate lines SGD and SGS, counting from the upper layer side of the laminate LM.

[0057] Furthermore, the depth of contact CCs connected to odd-numbered word lines WL, etc., and the depth of contact CCs connected to even-numbered word lines WL, etc., increases from the side furthest from each other to the side closest to each other. In other words, they are arranged in the X direction so that they connect to lower-level word lines WL, etc.

[0058] In Figure 2(b), the contact CCs connected to the topmost selection gate line SGD0, the topmost word line WL, and the uppermost selection gate line SGS0 are shown from the left side of the page as examples of contact CCs connected to odd-numbered word lines WL, etc. Furthermore, following the contact CCs connected to the selection gate line SGS0, further to the left of the page, the contact CCs connected to the bottommost selection gate line SGS1, the second word line WL from the top, and the second selection gate line SGD0 from the top are shown as examples of contact CCs connected to even-numbered word lines WL, etc.

[0059] In actual semiconductor memory devices 1, the number of stacked word lines WL, etc., can range from tens to hundreds of layers. Therefore, the contact CCs arranged in the X direction as described above may be arranged in multiple rows, spaced apart from each other in the Y direction. In this case as well, each of these multiple rows of contact CCs will be connected to word lines WL, etc., of a different layer.

[0060] Each of these contact CCs has an insulating layer 56 covering the outer circumference of the contact CC and a conductive layer 26, such as a tungsten layer or a copper layer, which is filled inside the insulating layer 56.

[0061] The conductive layer 26 of contact CC is connected to the upper wiring MX located in the insulating layer 53 via a plug V0 located in the insulating layer 52. This upper wiring MX is electrically connected to the peripheral circuit CBA (see Figure 1) via electrode pads PDb on the surface of the insulating layer 53 and electrode pads PDc on the surface of the insulating layer 40, etc.

[0062] Furthermore, within the region sandwiched between the plate-shaped contacts LI, the aforementioned multiple isolation layers SHE extend in the direction along the X-direction within the memory region MR between the plate-shaped contacts LI, and also extend in the direction along the X-direction within the contact region ER where the multiple contacts CC connected to the selected gate line SGD are located.

[0063] As a result, the selective gate line SGD is selectively separated into multiple regions, with its Y-direction end sandwiched between plate-shaped contacts LI and separation layer SHE, or two separation layers SHE, and its X-direction end separated by separation layer SHE. Contact CC is connected to each of the multiple regions of the selective gate line SGD separated by the plate-shaped contacts LI and separation layer SHE.

[0064] This configuration allows for the electrical extraction of the word lines WL and the selected gate lines SGD and SGS for each layer.

[0065] In other words, with the above configuration, a predetermined voltage can be applied to the memory cell MC from the peripheral circuit CBA via the upper layer wiring MX, contact CC, and word line WL, thereby enabling the memory cell MC to operate as a memory element.

[0066] Furthermore, by applying a predetermined voltage from the peripheral circuit CBA to the selection gates STD and STS via the upper layer wiring MX, contact CC, and selection gate lines SGD and SGS, the memory cell MC can be set to a selected or deselected state. At this time, the memory cell MC will be in a selected or deselected state for each region separated by the plate-shaped contact LI and the isolation layer SHE.

[0067] In the contact region ER where multiple contacts CC are located, multiple columnar sections HR are distributed and penetrate the laminate LM, the upper source wire DSLb, and the intermediate insulating layer SCO to reach the lower source wire DSLa.

[0068] The multiple columnar sections HR are arranged in a roughly periodic pattern, such as a grid or staggered pattern, when viewed from the stacking direction of the laminate LM. The reason the arrangement of the multiple columnar sections HR is roughly periodic is that, in order to avoid interference with the multiple contacts CC and plate-shaped contacts LI, the periodicity of the arrangement of the columnar sections HR is slightly disrupted around the multiple contacts CC and plate-shaped contacts LI.

[0069] Each columnar section HR has a cross-sectional shape in the direction along the XY plane, such as a circular, elliptical, or oval shape.

[0070] Each columnar section HR has a columnar section HRa that penetrates the laminate LMa from the uppermost insulating layer OLc of the laminate LMa to reach the source wire SL, and a columnar section HRb that penetrates the laminate LB from the uppermost insulating layer OLc of the laminate Lb to reach the uppermost insulating layer OLc of the laminate LMa and is connected to the upper end of the corresponding columnar section HRa.

[0071] These columnar sections HR, as will be described later, serve to support the structure when forming the laminate LM from a laminate consisting of a sacrificial layer and an insulating layer, and are dummy pillars that do not contribute to the function of the semiconductor memory device 1. For this reason, each of the columnar sections HRa and HRb is composed of a single insulating layer 54 such as a silicon oxide layer, and is configured so that the columnar sections HR do not have an electrical influence on the other components.

[0072] Furthermore, at the same height position of the laminate LM, the cross-sectional area of ​​the columnar portion HR in the direction along the XY plane may be larger than, for example, the cross-sectional area of ​​the pillar PL in the direction along the XY plane. Also, the pitch between multiple columnar portions HR may be larger than, for example, the pitch between multiple pillar PLs. In the XY plane, the arrangement density of columnar portions HR per unit area of ​​the word line WL in the laminate LM may be lower than the arrangement density of pillar PL per unit area of ​​the word line WL.

[0073] Thus, by configuring the pillar PL to have a smaller cross-sectional area and a narrower pitch compared to, for example, the columnar portion HR, a large number of memory cells MC can be formed at high density within a stacked LM of a predetermined size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portion HR is used solely to support the stacked LM, it does not need to have a small cross-sectional area and a precise narrow-pitch configuration like, for example, the pillar PL, which can reduce the manufacturing load of the semiconductor memory device 1.

[0074] (Method of manufacturing semiconductor memory devices) Next, the method for manufacturing the semiconductor memory device 1 according to Embodiment 1 will be described using Figures 3 to 16. Figures 3 to 16 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to Embodiment 1.

[0075] First, Figures 3 to 6 show how pillars PL are formed in the configuration that will later become the stacked structure LM. Figures 3 to 6 show a cross-section along the Y direction of the semiconductor memory device 1 during manufacturing, including the region that will later become the memory area MR.

[0076] As shown in Figure 3(a), the lower source line DSLa, the intermediate sacrificial layer SCN, and the upper source line DSLb are formed on the support substrate SS in this order.

[0077] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 described above (see Figure 2(a), etc.) may be formed on the upper surface of the support substrate SS.

[0078] The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced by a polysilicon layer or the like to become the intermediate source line BSL. Although not shown in the diagram, in the region that later becomes the contact region ER, an intermediate insulating layer SCO is formed between the lower source line DSLa and the upper source line DSLb.

[0079] On the upper source line DSLb, a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, one layer at a time. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0080] As shown in Figure 3(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa are the parts that will later become pillars PLa.

[0081] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 27, such as an amorphous silicon layer or a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 27.

[0082] Furthermore, in the region that will later become the contact region ER, a sacrificial layer is filled into the through-holes of the laminate LMsa in parallel with the processing shown in Figures 3(b) and 3(c), forming a structure that will later become the columnar portion HRa.

[0083] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0084] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts that will later become pillars PLb.

[0085] As shown in Figure 5(a), the sacrificial layer 27 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0086] Furthermore, if the sacrificial layer 27 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 27 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0087] Furthermore, in the region that will later become the contact region ER, through holes are formed in the laminate LMsb in parallel with the processes shown in Figures 4(b) to 5(a), and the sacrificial layer is removed by connecting to the structure that will later become the columnar portion HRa. Also, for example, prior to the process shown in Figure 5(b) below, an insulating layer 54 (see Figure 2(b)) is filled into the through holes penetrating the laminates LMsb and LMsa, thereby forming the columnar portion HR described above.

[0088] As shown in Figure 5(b), a memory layer ME is formed on the side wall of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, starting from the side wall side of the memory hole MH. This layer ME includes a block insulating layer, a charge storage layer, and a tunnel insulating layer (none of which are shown) in that order. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0089] Furthermore, the channel layer CNb and core layer CR are formed in this order within the memory hole MH via the memory layer ME. As a result, the memory layer ME and channel layer CN covering the sides and bottom of the memory hole MH are formed in this order, and the core layer CR fills the center of the memory hole MH. The channel layer CN and core layer CR are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0090] Subsequently, the core layer CR, channel layer CN, and memory layer ME on the upper surface of the laminate LMsb are removed in that order. At this time, the core layer CR within the memory hole MH is retracted to form a depression at the upper end of the memory hole MH.

[0091] As shown in Figure 6(a), a cap layer CP is formed in the recess at the upper end of the memory hole MH. The cap layer CP is also formed on the upper surface of the laminate LMsb. The cap layer CP on the upper surface of the laminate LMsb is removed along with a portion of the insulating layer OL of the uppermost layer of the laminate LMsb.

[0092] As shown in Figure 6(b), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked. This forms a pillar PL in which the cap layer CP is embedded in the insulating layer OL on the top layer. However, at this point, the memory layer ME covers the entire side wall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME.

[0093] Next, Figures 7 to 11 show how contact holes CL, which will later become contact CCs, are formed in the laminates LMsa and LMsb. Figures 7 to 11 show cross-sections of the semiconductor memory device 1 in the manufacturing process, along the X direction, including the region that will later become the contact region ER.

[0094] However, Figures 7 to 11 show, as an example, an example in which contact holes CL(1) to CL(16) are formed at the respective depth positions of the 16 insulating layers NL of the laminated LMs. Also, in Figures 7 to 11, the illustration of multiple columnar parts HR is omitted, and in Figures 7 to 10, the lower layer portion of the laminated LMs is omitted.

[0095] As described below, multiple contact holes CL with different depths are formed by creating a resist pattern multiple times, exposing different contact holes CL each time, and processing them to different depths.

[0096] As shown in Figure 7(a), a hard mask pattern 81 having multiple openings is formed on the upper surface of the laminated LMs. The hard mask pattern 81 is an inorganic layer that is not removed by, for example, ashing using oxygen plasma. Each of the multiple openings in the hard mask pattern 81 has, for example, a hole shape.

[0097] As shown in Figure 7(b), the upper surface of the laminated LMs exposed through the opening in the hard mask pattern 81 is etched to remove the uppermost insulating layer OL. This creates multiple contact holes CL that penetrate the uppermost insulating layer OL and reach the insulating layer NL directly beneath it.

[0098] As shown in the diagram, from this point forward, the top layer, the second layer from the top, the third layer, ..., and the bottom layer of insulating layers NL will be denoted as insulating layer NL(1), NL(2), NL(3), ..., NL(16), respectively. Also, the first, second, third, ..., and sixteenth contact holes CL from the left side of the page will be denoted as contact hole CL(1), CL(2), CL(3), ..., CL(16), respectively.

[0099] In other words, in Figure 7(b), contact holes CL(1) to (16) reaching the insulating layer NL(1) are formed.

[0100] Next, the contact holes CL are divided into those that reach the odd-numbered insulating layer NL and those that reach the even-numbered insulating layer NL, and the processing proceeds accordingly.

[0101] First, the following shows the processing procedure for the contact holes CL on the left half of the page, which will reach the odd-numbered insulating layer NL among the multiple contact holes CL.

[0102] As shown in Figure 7(c), a hard mask pattern 81 covers a portion of the upper surface of the laminated LMs, forming a resist pattern 101 having multiple openings. The resist pattern 101 is an organic layer, such as a photoresist layer, that can be removed by ashing using an oxygen plasma, and is formed by a spin coating method or the like. Contact holes CL(4) and CL(8), for example, are exposed through the openings in the resist pattern 101.

[0103] As shown in Figure 7(d), the contact holes CL(4) and CL(8) exposed from the opening of the resist pattern 101 are further etched to penetrate two layers of insulating layer NL and reach the insulating layer NL below them. As a result, both contact holes CL(4) and CL(8) reach the insulating layer NL(3).

[0104] As described above, by pre-forming the hard mask pattern 81, even if a slight misalignment occurs during the formation of the resist pattern 101, the additional processing of these contact holes CL(4) and CL(8) prevents the additionally processed portion from shifting significantly from the original formation position of the contact holes CL(4) and CL(8).

[0105] After this, the resist pattern 101 is removed by ashing using oxygen plasma or the like.

[0106] As shown in Figure 8(a), a hard mask pattern 81 covers a portion of the upper surface of the laminated LMs, forming a resist pattern 102 having multiple openings. Contact holes CL(3), CL(4), CL(7), and CL(8), for example, are exposed through the openings in the resist pattern 102.

[0107] Furthermore, as the depth reached by individual contact holes CL increases, the amount of resist material flowing into these contact holes CL increases when forming the resist layer by methods such as spin coating, resulting in uneven thickness of the resist pattern on the upper surface of the laminated LMs. In other words, the resist pattern above deeper contact holes CL becomes thinner than other parts.

[0108] Furthermore, as the depth reached by individual contact holes CL increases, if the opening portion of the resist pattern is formed above the deep contact hole CL, exposure and development alone may not be sufficient to completely remove the resist material inside the contact hole CL. In such cases, after exposure and development, the resist pattern is further etched back to remove the resist material inside the contact hole CL.

[0109] As shown in Figure 8(b), the contact holes CL(3), CL(4), CL(7), and CL(8) exposed from the openings of the resist pattern 102 are further etched to penetrate two layers of insulating layer NL and reach the insulating layer NL below them.

[0110] As a result, contact holes CL(4) and CL(8) reach the insulating layer NL(5), and contact holes CL(3) and CL(7) reach the insulating layer NL(3). In this case as well, the hard mask pattern 81 suppresses the misalignment of each contact hole CL(3), CL(4), CL(7), and CL(8).

[0111] After this, the resist pattern 102 is removed by ashing using oxygen plasma or the like.

[0112] As shown in Figure 8(c), a hard mask pattern 81 covers a portion of the upper surface of the laminated LMs, forming a resist pattern 103 with multiple openings. Contact holes CL(2), CL(3), CL(4), CL(6), CL(7), and CL(8), for example, are exposed through the openings in the resist pattern 103. At this time, if necessary, after exposure and development, the resist material in the deep contact holes CL is removed by, for example, etching back the entire resist pattern 103.

[0113] As shown in Figure 9(a), the contact holes CL(2), CL(3), CL(4), CL(6), CL(7), and CL(8) exposed from the opening of the resist pattern 103 are further etched to penetrate two layers of insulating layer NL and reach the insulating layer NL below them. As a result, contact holes CL(4) and CL(8) reach the insulating layer NL(7), contact holes CL(3) and CL(7) reach the insulating layer NL(5), and contact holes CL(2) and CL(6) reach the insulating layer NL(3).

[0114] After this, the resist pattern 103 is removed by ashing using oxygen plasma or the like.

[0115] Next, the processing procedure for the contact holes CL on the right half of the page, which reach the even-numbered insulating layer NL among the multiple contact holes CL, is shown below. The contact holes CL that reach the even-numbered insulating layer NL are processed using the same procedure as the contact holes CL that reach the odd-numbered insulating layer NL described above.

[0116] As shown in Figure 9(b), a resist pattern 104 is formed by covering a portion of the upper surface of the laminated LMs via a hard mask pattern 81, with contact holes CL(9) and CL(13) exposed through multiple openings. Furthermore, the contact holes CL(9) and CL(13) exposed through the openings of the resist pattern 104 are both made to reach the insulating layer NL(3).

[0117] As shown in Figure 9(c), after ashing the resist pattern 104, a resist pattern 105 is formed that covers a portion of the upper surface of the laminated LMs via the hard mask pattern 81, exposing contact holes CL(9), CL(10), CL(13), and CL(14) through multiple openings. Furthermore, the contact holes CL(9) and CL(13) exposed through the openings of the resist pattern 105 are allowed to reach the insulating layer NL(5), and the contact holes CL(10) and CL(14) are allowed to reach the insulating layer NL(3).

[0118] As shown in Figure 10(a), after ashing the resist pattern 105, a resist pattern 106 is formed that covers a portion of the upper surface of the laminated LMs via the hard mask pattern 81, exposing contact holes CL(9), CL(10), CL(11), CL(13), CL(14), and CL(15) through multiple openings. Furthermore, the contact holes CL(9) and CL(13) exposed through the openings of the resist pattern 105 are allowed to reach the insulating layer NL(7), the contact holes CL(10) and CL(14) are allowed to reach the insulating layer NL(5), and the contact holes CL(11) and CL(15) are allowed to reach the insulating layer NL(3).

[0119] Up to this point, the same processing is applied to contact holes CL that reach even-numbered insulating layers NL as is applied to contact holes CL that reach odd-numbered insulating layers NL. However, for contact holes CL that reach even-numbered insulating layers NL, one more step is performed, as described below.

[0120] As shown in Figure 10(b), after the resist pattern 106 is ashingly removed, a resist pattern 107 is formed that covers a portion of the upper surface of the laminated LMs via the hard mask pattern 81, exposing all the contact holes CL, i.e., contact holes CL(9) to CL(16), which reach the even-numbered insulating layer NL through multiple openings.

[0121] Furthermore, the contact holes CL(9) to CL(16) exposed from the opening of the resist pattern 107 are allowed to penetrate through one layer of the insulating layer NL, so that contact holes CL(9) and CL(13) reach the insulating layer NL(8), contact holes CL(10) and CL(14) reach the insulating layer NL(6), contact holes CL(11) and CL(15) reach the insulating layer NL(4), and contact holes CL(12) and CL(16) reach the insulating layer NL(2).

[0122] As a result, on the left side of the paper, two sets of contact holes CL(1) to CL(4) and contact holes CL(5) to CL(8) are formed, reaching the odd-numbered insulating layers NL, i.e., insulating layers NL(1), NL(3), NL(5), and NL(7), respectively. On the other hand, on the right side of the paper, two sets of contact holes CL(9) to CL(12) and contact holes CL(13) to CL(16) are formed, reaching the even-numbered insulating layers NL, i.e., insulating layers NL(2), NL(4), NL(6), and NL(8), respectively.

[0123] In other words, the contact holes CL(1) to (8) on the left half of the page and the contact holes CL on the right half of the page differ by one layer in the insulating layer NL they reach.

[0124] Subsequently, as shown below, additional processing is performed on the left half of the paper, specifically on contact holes CL(5) to CL(8) that are closer to the center of the paper, out of two sets of contact holes CL(1) to CL(4) and CL(5) to CL(8) that reach the same insulating layer NL, and on the right half of the paper, specifically on contact holes CL(9) to CL(12) that are closer to the center of the paper, out of two sets of contact holes CL(9) to CL(12) and CL(13) to CL(16) that reach the same insulating layer NL.

[0125] As shown in Figure 10(c), a resist pattern 108 is formed to further process the contact holes CL(5) to CL(12) in the center of the paper. Figure 10(c) shows the resist pattern 108 immediately after exposure and development.

[0126] The resist pattern 108 has openings that overlap with the contact holes CL(5) to CL(12) after exposure and development. In addition, the contact holes CL(5) to CL(12) are filled with resist material that was not removed during exposure and development.

[0127] Thus, because the resist material flowed into the relatively deep contact holes CL(5) to CL(12), the layer thickness of the resist pattern 108 is thinner in the areas overlapping with the contact holes CL(5) to CL(12) than in other areas.

[0128] As shown in Figure 11(a), the resist material in the contact holes CL(5) to CL(12) is removed by etching back the entire resist pattern 108. This further reduces the overall thickness of the resist pattern 108.

[0129] As shown in Figure 11(b), the contact holes CL(5) to CL(12) exposed from the resist pattern 108 are etched to penetrate the eight insulating layers NL and reach the insulating layer NL below them.

[0130] As a result, contact holes CL(5) to CL(8) reach the insulating layer NL below the odd-numbered insulating layer NL that contact holes CL(1) to CL(4) reach. Specifically, contact hole CL(5) reaches insulating layer NL(9), contact hole CL(6) reaches insulating layer NL(11), contact hole CL(7) reaches insulating layer NL(13), and contact hole CL(8) reaches insulating layer NL(15).

[0131] Furthermore, contact holes CL(9) to CL(12) reach the insulating layer NL below the even-numbered insulating layer NL of contact holes CL(13) to CL(16). That is, contact hole CL(9) reaches insulating layer NL(16), contact hole CL(10) reaches insulating layer NL(14), contact hole CL(11) reaches insulating layer NL(12), and contact hole CL(12) reaches insulating layer NL(10).

[0132] As a result, on the left side of the paper, contact holes CL(1) to CL(8) are formed that reach the odd-numbered insulating layers NL, i.e., insulating layers NL(1), NL(3), NL(5), NL(7), NL(9), NL(11), NL(13), and NL(15), respectively. On the other hand, on the right side of the paper, contact holes CL(9) to CL(16) are formed that reach the even-numbered insulating layers NL, i.e., insulating layers NL(2), NL(4), NL(6), NL(8), NL(10), NL(12), NL(14), and NL(16), respectively.

[0133] In other words, the contact holes CL(1) to (8) on the left half of the page and the contact holes CL on the right half of the page are reached by one layer of the insulating layer NL, respectively. As a result, each of the 16 insulating layers NL(1) to (16) is reached by one of the 16 contact holes CL(1) to (16).

[0134] After this, the resist pattern 108 is removed by ashing using oxygen plasma or the like. In addition, a sacrificial layer such as an amorphous silicon layer or a CVD-carbon layer is filled into the contact holes CL(1) to CL(16), and in a later process, an insulating layer 56 and a conductive layer 26 (see Figure 2(b), etc.) are formed to form multiple contact CCs.

[0135] Next, Figures 12 to 15 show how the intermediate source line BSL is formed from the intermediate sacrificial layer SCN of the source line SL, and how the word line WL and other lines are formed from the insulating layers NL of the laminates LMsa and LMsb. Figures 12 to 15, like Figures 3 to 6 described above, show a cross-section along the Y direction of the semiconductor memory device 1 during manufacturing, including the region that will later become the memory region MR.

[0136] As shown in Figure 12(a), a slit ST is formed that penetrates the laminates LMsb, LMsa and the upper source wire DSLb, reaching the intermediate sacrificial layer SCN. An insulating layer 55s is also formed on the side walls of the slit ST facing in the Y direction. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0137] As shown in Figure 12(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through the slit ST, whose sidewalls are protected by the insulating layer 55s, to remove the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb.

[0138] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs. At this time, since the sidewall of the slit ST is protected by the insulating layer 55s, the removal of the insulating layer NL within the laminates LMsa and LMsb is suppressed.

[0139] As shown in Figure 13(a), chemical solutions are introduced into the gap layer GPs through the slit ST as needed, sequentially removing the block insulating layer, charge storage layer, and tunnel insulating layer (none of which are shown) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0140] As shown in Figure 13(b), a raw material gas, such as amorphous silicon, is injected through a slit ST whose sidewall is protected by an insulating layer 55s, and the gap layer GPs is filled with amorphous silicon or the like. In addition, the support substrate SS is heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0141] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0142] Although not shown in the diagram, the slit ST extends into the area that later becomes the contact area ER, and the lower end of the slit ST reaches the intermediate insulating layer SCO sandwiched between the lower source wire DSLa and the upper source wire DSLb. Therefore, the intermediate insulating layer SCO is not affected by the processing shown in Figures 12 to 13 and remains even after the processing shown in Figures 12 to 13.

[0143] As shown in Figure 14(a), the insulating layer 55s on the side wall of the slit ST is removed.

[0144] As shown in Figure 14(b), a solution for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb from the slit ST from which the insulating layer 55s has been removed, thereby removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0145] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. Although not shown in the figures, in the contact region ER, the aforementioned columnar parts HR (see Figure 2(b), etc.) also support the fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminates LMga and LMgb from bending, and prevents the laminates LMga and LMgb from deforming or collapsing.

[0146] As shown in Figure 15(a), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0147] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0148] As shown in Figure 15(b), a plate-shaped contact LI is formed by filling the slit ST with a conductive layer 25 via an insulating layer 55. Additionally, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 57 is filled into the groove to form a separation layer SHE that divides these conductive layers into a pattern of selected gate lines SGD.

[0149] Subsequently, although not shown in the diagram, after removing the sacrificial layer from the multiple contact holes CL (see Figure 11(b), etc.) already formed in the contact region ER, the conductive layer 26 is filled into these contact holes CL via the insulating layer 56 to form multiple contacts CC that are connected to multiple word lines WL and selection gate lines SGD and SGS, respectively.

[0150] Furthermore, after forming an insulating layer 52 that covers the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL and insulating layer 52 of the laminate LM and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed that covers the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0151] In parallel with this, a plug V0 is formed that penetrates the insulating layer 52 and is connected to the upper end of contact CC. Also, an upper wiring MX is formed in the insulating layer 53 to which the individual plugs V0 are connected.

[0152] Furthermore, the plug CH and bit line BL, and the plug V0 and upper layer wiring MX may be formed together by using, for example, the dual damascene method.

[0153] Furthermore, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40, and these are connected to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0154] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0155] The semiconductor memory device 1 of Embodiment 1 is manufactured as described above.

[0156] (Comparative example) In semiconductor memory devices such as 3D non-volatile memory, multiple word lines and the like may penetrate a stacked structure, and multiple contacts may be formed that connect to each individual word line or the like. Multiple contacts are obtained by forming a resist pattern multiple times to create multiple contact holes with different depths.

[0157] However, when a resist pattern is formed on multiple contact holes during their formation, the resist material is also filled into these contact holes. At this time, the amount of resist material filling differs depending on the depth reached by the contact holes, which can cause variations in the layer thickness of the resist pattern. This can lead to variations in the exposure state of the resist pattern for each layer thickness, resulting in variations in the opening area of ​​multiple openings, or even the inability to expose the contact holes being processed due to the presence of unopened areas.

[0158] Furthermore, when removing the resist material filled into the contact holes, the overall thickness of the resist pattern decreases, which may result in insufficient protection of areas not targeted for etching during subsequent additional etching of the contact holes.

[0159] As a result of diligent research, the inventors have found that variations in the layer thickness of such resist patterns can be suppressed by optimizing the arrangement of contact holes with different penetration depths. According to the inventors, if there are areas where the penetration depth of the contact holes changes abruptly, the variations in the layer thickness of the resist pattern become large. More specifically, if the volume of contact holes per unit area changes abruptly between adjacent regions, the variations in the layer thickness of the resist pattern become large. Several examples are shown in Figure 16.

[0160] Figure 16 is a cross-sectional view showing an example of the arrangement of contact holes CLx and CLy in a comparative example.

[0161] In the example shown in Figure 16(a), the arrangement of the multiple contact holes CLx extending within the laminate LMx is reversed compared to the contact holes CL in Embodiment 1 described above, with respect to the central portion of the paper.

[0162] In other words, the depth reached by multiple contact holes CLx that reach the odd-numbered insulating layer NL in the left half of the page decreases as you approach the multiple contact holes CLx that reach the even-numbered insulating layer NL in the right half of the page, starting from the left side of the page. Similarly, the depth reached by multiple contact holes CLx that reach the even-numbered insulating layer NL in the right half of the page decreases as you approach the multiple contact holes CLx that reach the odd-numbered insulating layer NL in the left half of the page, starting from the right side of the page.

[0163] In this configuration, the volume of contact holes CLx per unit area changes abruptly on both sides of the X direction of multiple contact holes CLx, from the area where deep contact holes CLx are formed to the area outside the contact hole CLx arrangement region where no contact holes CLx are formed. As described above, in this configuration, the variation in the layer thickness of the resist pattern becomes large.

[0164] In the example shown in Figure 16(b), the depth reached by multiple contact holes CLy extending through the laminate LMy increases sequentially from the right to the left side of the paper. Even in this arrangement, on the left side in the X direction of the multiple contact holes CLy, the volume of contact holes CLy per unit area changes abruptly from the area where deep contact holes CLy are formed to the area outside the contact hole CLy arrangement region where no contact holes CLy are formed. As described above, even in this arrangement, the variation in the layer thickness of the resist pattern becomes large.

[0165] As described above, in order to minimize variations in the thickness of the resist pattern, it is desirable to avoid abrupt changes in the depth reached by the contact holes as much as possible and to arrange the contact holes in an order that suppresses abrupt changes in the volume of contact holes per unit area.

[0166] According to the semiconductor memory device 1 of Embodiment 1, the multiple contacts CL are arranged in a line in the X direction, and the depth reached increases from both ends in the X direction towards the center. By arranging them in this way, abrupt changes in the depth reached by the contact holes can be avoided. Therefore, variations in the layer thickness of the resist pattern 108, etc., on multiple contact holes CL with different depths can be suppressed.

[0167] (Variation 1) Next, using Figure 17, the method for forming contact holes CL, CLa, and CLb in the semiconductor memory device of Modification 1 of Embodiment 1 will be described. The semiconductor memory device of Modification 1 differs from Embodiment 1 described above in that the pitch of the multiple contact holes CLa and CLb is varied.

[0168] Figure 17 illustrates a part of the procedure for manufacturing a semiconductor memory device according to Modification 1 of Embodiment 1. Figure 17 shows the stage just before all contact holes CL, CLa, and CLb reach the target insulating layer NL, and corresponds to Figure 11(a) of Embodiment 1 described above. This is because, among the multiple repeated contact hole CL, CLa, and CLb formation processes, the contact holes CLa and CLb that are processed in the final step are the deepest holes, and the difference in layer thickness in the resist pattern at this time tends to be the most pronounced.

[0169] In Figure 17, the same reference numerals are used for components similar to those in Embodiment 1 described above, and their descriptions may be omitted.

[0170] In the example shown in Figure 17(a), among the multiple contact holes CL(1)~CL(4), CLa(5)~CLa(12), and CL(13)~CL(16) arranged from left to right, the pitch of the contact holes CLa(5)~CLa(12), which are to be machined in the final step, is wider than that of the other contact holes CL(1)~CL(4), CL(13)~CL(16).

[0171] In this case, the pitches of the contact holes CLa(5) to CLa(12) may be equal or different.

[0172] Thus, in this final stage, by pre-widening the pitch of the contact holes CLa(5) to CLa(12), which are the deepest holes to be processed, the density of these contact holes CLa(5) to CLa(12) can be reduced, thereby decreasing the amount of resist material flowing into the contact holes CLa(5) to CLa(12) per unit area. As a result, the difference in layer thickness of the resist pattern 108a is reduced.

[0173] In the example shown in Figure 17(b), among the multiple contact holes CL(1)~CL(4), CLb(5)~CLb(12), and CL(13)~CL(16) arranged from left to right, a blank area is provided between contact holes CLb(5)~CLb(12), which are the target of processing in the final step, where no contact holes CL or CLb are placed. More specifically, contact holes CLb(5)~CLb(12) are divided into multiple groups such as contact holes CLb(5)~CLb(7), CLb(8)~CLb(9), CLb(10)~CLb(12), and a blank area is placed between each group.

[0174] In this case, the pitches between contact holes CLb(5) to CLb(7), between contact holes CLb(8) to CLb(9), and between contact holes CLb(10) to CLb(12) may be equal or different. Also, the pitches between each group may be equal or different.

[0175] This configuration also reduces the arrangement density of these contact holes CLb(5) to CLb(12), thereby reducing the amount of resist material flowing into the contact holes CLb(5) to CLb(12) per unit area. As a result, the difference in layer thickness of the resist pattern 108b is reduced.

[0176] According to the semiconductor memory device of Modified Example 1, it is equipped with a contact CC formed from a plurality of contact holes CL, CLa, and CLb. That is, among the plurality of contact holes CL, CLa, and CLb, the average pitch of multiple contact holes CLa and CLb whose reach depth is greater than or equal to the depth of the insulating layer NL(9) is greater than the average pitch of multiple contact holes CL whose reach depth is less than the depth of the insulating layer NL(9).

[0177] This makes it possible to suppress variations in the layer thickness of the resist patterns 108a and 108b on multiple contact holes CL, CLa, and CLb with different reach depths.

[0178] According to the semiconductor memory device of Modified Example 1, it comprises a contact CC formed from a plurality of contact holes CL and CLa. That is, the pitch of the plurality of contact holes CLa whose reach depth is greater than or equal to the depth of the insulating layer NL(9) is equal.

[0179] This configuration also makes it possible to suppress variations in the layer thickness of the resist pattern 108a on multiple contact holes CL and CLa with different reach depths.

[0180] According to the semiconductor memory device of Modified Example 1, it is equipped with a contact CC formed from a plurality of contact holes CL and CLb. That is, in the region where a plurality of contact holes CLb whose reach depth is greater than or equal to the depth of the insulating layer NL(9) are arranged, there is a blank region where none of the plurality of contact holes CL and CLb are arranged.

[0181] This configuration also makes it possible to suppress variations in the layer thickness of the resist pattern 108b on multiple contact holes CL and CLb with different reach depths.

[0182] The semiconductor memory device of Modified Example 1 also provides the same effects as the semiconductor memory device 1 of Embodiment 1 described above.

[0183] (Modification 2) Next, using Figure 18, the method for forming contact holes CL and CLc in the semiconductor memory device of Modification 2 of Embodiment 1 will be described. The semiconductor memory device of Modification 2 differs from Embodiment 1 described above in that a dummy contact hole CLc is added.

[0184] Figure 18 illustrates a part of the procedure for manufacturing a semiconductor memory device according to a modified example 2 of Embodiment 1. Figure 18 shows the stage just before all contact holes CL reach the target insulating layer NL, and corresponds to Figure 11(a) of Embodiment 1 described above.

[0185] In Figure 18, the same reference numerals are used for components similar to those in Embodiment 1 described above, and their descriptions may be omitted.

[0186] As shown in Figure 18, in Modification 2, a dummy contact hole CLc with a predetermined reach depth is added further outward in the X direction from the multiple contact holes CL(1) to CL(16) arranged from left to right. The number of additional contact holes CLc and their reach depths are arbitrary.

[0187] However, to avoid increasing the number of steps, it is preferable that the contact holes CLc are formed in parallel with any of the other contact holes CL(1) to CL(16), and that the depth reached is determined to match the relatively deep contact hole CL among these contact holes CL(1) to CL(16). Furthermore, the number of additional contact holes CLc can be adjusted so as to minimize the difference in layer thickness of the resist pattern 108c used in the final step.

[0188] This further suppresses the abrupt change in the volume of contact holes CL per unit area at both ends of the X-direction of multiple contact holes CL, from the portion where multiple contact holes CL are formed to the portion outside the contact hole CL arrangement area where no contact holes CL are formed.

[0189] According to the semiconductor memory device of Modified Example 2, it comprises a contact CC formed from a plurality of contact holes CL and CLc. Specifically, dummy contact holes CLc having a reachable depth of a predetermined depth or greater are arranged outside both ends in the X direction of the arrangement region of the plurality of contact holes CL.

[0190] This configuration also makes it possible to suppress variations in the layer thickness of the resist pattern 108c on multiple contact holes CL with different reach depths.

[0191] The semiconductor memory device of Modified Example 2 also provides the same effects as the semiconductor memory device 1 of Embodiment 1 described above.

[0192] (Variation 3) In Modification 2, dummy contact holes CLc are added to both ends of the contact hole CL in the X direction, but dummy contact holes may also be added to both ends in the Y direction when viewed as the entire semiconductor memory device.

[0193] Figure 19 is a schematic diagram showing the manufacturing process layout of a semiconductor memory device according to Modification 3 of Embodiment 1. More specifically, Figure 19(a) is a plan view of the semiconductor memory device of Modification 3, Figure 19(b) is a cross-sectional view of the semiconductor memory device of Modification 3 along the X direction, and Figure 19(c) is a cross-sectional view of the semiconductor memory device of Modification 3 along the Y direction.

[0194] In Figure 19, the same reference numerals are used for components similar to those in Embodiment 1 and Modification 2 described above, and their descriptions may be omitted.

[0195] As shown in Figures 19(a) and 19(c), in the semiconductor memory device of Modification 3, dummy contact holes CLd having a predetermined reach depth are formed in the dummy contact region ERd included in the dummy block region BLK at both ends in the Y direction.

[0196] This further suppresses abrupt changes in the volume of contact holes CL per unit area across multiple contact regions ER and ERd aligned in the Y direction.

[0197] As shown in Figures 19(a) and 19(b), in addition to the above configuration, dummy contact holes CLc may also be added to both ends in the X direction of each contact region ER, similar to the modified example 2.

[0198] According to the semiconductor memory device of Modified Example 3, it comprises a contact CC formed from a plurality of contact holes CL and CLd. Specifically, dummy contact holes CLd having a reachable depth of a predetermined depth or greater are arranged on the outer sides of both ends in the Y direction of the arrangement region of the plurality of contact holes CL.

[0199] This configuration also makes it possible to suppress variations in the layer thickness of the resist pattern on multiple contact holes CL with different reach depths.

[0200] The semiconductor memory device of Modified Example 3 also provides the same effects as the semiconductor memory device 1 of Embodiment 1 described above.

[0201] (Other variations) In Embodiment 1 and Modifications 1-3 described above, the contact area ER, etc., is positioned in the center of the laminate LM in the X direction. However, the position of the contact area in the laminate LM is not limited to this. The contact area may be positioned at both ends of the laminate LM in the X direction, for example, in which case the memory area can be positioned in the center of the laminate LM.

[0202] Furthermore, in Embodiment 1 and Modifications 1-3 described above, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this configuration. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0203] Furthermore, in Embodiment 1 and Modifications 1-3 described above, the insulating layers NL and OL are laminated in two stages, resulting in a laminate LM with a 2-tier structure including laminates LMa and LMb. However, the laminate may have a 1-tier structure, or a structure with 3 or more tiers. By increasing the number of tiers, the number of laminates of word lines WL can be further increased.

[0204] [Embodiment 2] Embodiment 2 will be described in detail below with reference to the drawings.

[0205] In the above-described embodiment 1, as an arrangement to reduce the difference in layer thickness of the resist pattern 108, etc., a configuration was described in which the reach depth of the contact holes CL aligned in the X direction increases toward the center in the X direction.

[0206] In this method, approximately half of the contact holes CL arranged in the X direction and the other half are pre-set to have different penetration depths, and the penetration depth is increased through repeated processing. In this method, the arrangement of the contact holes CL can be said to be appropriate.

[0207] However, various methods exist for forming contact holes with different reach depths, and the optimal arrangement order of the contact holes may vary depending on the method. As an example, Figures 20 and 21 show a method in which approximately half and the other half of a group of contact holes arranged in the X direction are formed to have the same reach depth, and then their reach depths are made to differ in the final stage.

[0208] Figures 20 and 21 illustrate a part of the procedure for manufacturing a semiconductor memory device according to a comparative example. Of Figures 20 and 21, Figure 20 shows the step immediately before all contact holes CL,CLz reach the target insulating layer NL.

[0209] As shown in Figure 20(a), the contact holes CLz(9) to CLz(16) in the right half of the page, which will eventually reach the even-numbered insulating layer NL, have a symmetrical configuration with respect to the central part of the page, with respect to the contact holes CL(1) to CL(8) in the left half of the page, which have already reached the final target, the odd-numbered insulating layer NL. That is, the contact holes CLz(9) to CLz(16) have reached the same insulating layers NL(15), NL(13), NL(11), NL(9), NL(7), NL(5), NL(3), and NL(1) as their corresponding contact holes CL(8) to CL(1).

[0210] Thus, in the comparative example semiconductor memory device, for example, the contact holes CL(1) to CL(8) and contact holes CLz(9) to CLz(16) are processed in parallel so that they have the same configuration until just before the final stage of contact hole CL and CLz formation. Furthermore, additional processing is performed on contact holes CLz(9) to CLz(16) to reach the insulating layer NL one layer below.

[0211] As shown in Figure 20(b), a resist pattern 108z is formed to create additional contact holes CLz(9) to CLz(16). Figure 20(b) shows the resist pattern 108z immediately after exposure and development.

[0212] The resist pattern 108z has openings that overlap with the contact holes CLz(9) to CLz(16) after exposure and development. In addition, the contact holes CLz(9) to CLz(16) are filled with resist material that was not removed during exposure and development.

[0213] Furthermore, in the comparative example configuration, openings must be provided across the entire range from the shallowest to the deepest contact holes CLz(9) to CLz(16). This range includes the thinnest to the thickest parts of the resist pattern 108z. As a result, adjusting the focus position during exposure becomes difficult. For example, if exposure is performed with the resist pattern 108z aligned to the position above the thinnest contact hole CLz(9), the resist pattern 108z may not have openings above the thickest contact hole CLz(19), for instance.

[0214] As shown in Figure 21(a), in the above state, in order to remove the resist material from the contact holes CLz(9) to CLz(16), it is necessary to perform a longer full-surface etch-back of the resist pattern 108z. Therefore, after removing the resist material from the contact holes CLz(9) to CLz(16), the layer thickness of the resist pattern 108z is significantly reduced.

[0215] As shown in Figure 21(b), additional contact holes CLz(9) to CLz(16) are machined to reach the even-numbered insulating layers NL(16), NL(14), NL(12), NL(10), NL(8), NL(6), NL(4), and NL(2) of the layer below, respectively.

[0216] However, as mentioned above, if the reduction in the thickness of the resist pattern 108z is large, the resist pattern 108z in areas that were originally thin may disappear, and the mask function may be partially impaired. In the example in Figure 21(b), the hard mask pattern 81 such as the contact holes CLz(9) to CLz(11), and the uppermost insulating layer OL of the laminated LMs, are etched, and the openings of the contact holes CLz(9) to CLz(11), etc., are enlarged.

[0217] Thus, the arrangement of the contact holes in Embodiment 1 described above may not necessarily be appropriate if the method for forming these contact holes is different.

[0218] Therefore, in order to properly arrange contact holes with different depths, it is necessary to consider not only the method of forming these contact holes, but also the number of layers of word lines etc. that the semiconductor memory device will have, that is, the required number of contact holes, and other design constraints.

[0219] Embodiment 2 describes a design apparatus 30 for optimizing the arrangement of contact holes with different reach depths, using Figures 22 to 26.

[0220] (Example of a design device configuration) Figure 22 is a block diagram showing an example of the physical configuration of the design apparatus 30 according to Embodiment 2.

[0221] As shown in Figure 22, the design apparatus 30 of Embodiment 2 is configured as a computer equipped with a CPU (Central Processing Unit) 21, ROM (Read Only Memory) 22, RAM (Random Access Memory) 23, and storage device 34.

[0222] The CPU 31 controls the entire design device 30. The ROM 32 functions as a storage area in the design device 30. Information stored in the ROM 32 is retained even when the power to the design device 30 is turned off. The RAM 33 functions as a primary storage device and serves as the CPU 31's workspace. The storage device 34 is an HDD, SSD, etc., and functions as an auxiliary storage device for the CPU 31.

[0223] The design device 30 may also be equipped with input / output devices 35 such as a keyboard, mouse, and display. The input / output devices 35 are configured as a Human Machine Interface (HMI) between the design device 30 and the user, allowing the user to input information and commands to the design device 30 and to receive information from the design device 30.

[0224] Furthermore, the ROM 32 of the design device 30 may store a control program 36 executed by the CPU 31. The control program 36 can be provided by recording it on various computer-readable recording media such as flexible disks, CD-R (Compact Disc-Recordable), DVD (Digital Versatile Disk), Blu-ray Disc (registered trademark), and semiconductor memory.

[0225] Alternatively, the control program 36 may be configured to be stored on a computer connected to a network such as the Internet and provided by allowing users to download it via the network. Alternatively, the control program 36 may be provided or distributed via a network such as the Internet.

[0226] Figure 23 is a block diagram showing an example of the functional configuration of the design device 30 according to Embodiment 2. As shown in Figure 23, the CPU 31 described above loads the control program 36 stored in the ROM 32 or the like into the RAM 33 and executes it, thereby realizing the functional units: acquisition unit 301, generation unit 302, simulation unit 303, determination unit 304, and storage unit 305.

[0227] However, some or all of the above functional configurations of the design device 30 may be implemented by a dedicated ASIC (Application Specific Integrated Circuit).

[0228] The acquisition unit 301 acquires design information relating to the contact holes to be optimized. The design information includes the number of stacked word lines, etc., in the semiconductor memory device having the contact holes, the layout of the semiconductor memory device including the contact area and memory area, design constraints for arranging the contact holes, and the resist pattern when the contact holes are formed, or more precisely, the upper limit of the thickness difference of the resist layer before exposure and development.

[0229] This design information may be input by the user through the input / output device 35 described above, or it may be obtained from a higher-level design device for designing the entire semiconductor memory device.

[0230] The generation unit 302 generates a predetermined arrangement of contact holes based on various design information acquired by the acquisition unit 301.

[0231] The simulation unit 303 simulates the difference in thickness of the resist layer that would occur if a resist layer were formed on the contact holes generated by the generation unit 302.

[0232] The determination unit 304 determines whether the arrangement of contact holes generated by the generation unit 302 satisfies various design constraints. The determination unit 304 also determines, based on the simulation results from the simulation unit 303, whether the difference in the thickness of the resist layer is within the upper limit in a predetermined arrangement.

[0233] The memory unit 305 stores various control parameters and control programs necessary for the operation of the design device 30. The memory unit 305 may also store various design information acquired by the acquisition unit 301, various arrangements generated by the generation unit 302, and various simulation results performed by the simulation unit 303.

[0234] (Example of operation of the designed device) Next, an example of the operation of the design apparatus 30 of Embodiment 2 will be described using Figures 24 and 25.

[0235] Figure 24 is a schematic diagram illustrating an example of the design operation of the contact hole CLe arrangement by the design apparatus 30 according to Embodiment 2.

[0236] The acquisition unit 301 of the design device 30 acquires design information for a target semiconductor memory device when designing the arrangement of contact holes for a predetermined semiconductor memory device.

[0237] The generation unit 302 generates the initial arrangement of contact holes based on the design information acquired by the acquisition unit 301. For example, if the design information indicates that the semiconductor memory device has 10 layers of word lines and selection gate lines, it is determined that 10 contact holes with different reach depths are required.

[0238] As shown in Figure 24(a), the generation unit 302 arranges these 10 contact holes CLe in any order. The arbitrary order of the contact holes CLe can be any order, such as the one shown in Figure 24(a), where the reachable depth increases sequentially from one side to the other in the X direction, or an order in which contact holes CLe of different reachable depths are randomly arranged. Several template arrangements may be prepared in advance, and an arrangement with a predetermined order may be selected from among them.

[0239] The determination unit 304 refers to the design information acquired by the acquisition unit 301 and determines whether the initial arrangement of contact holes CLe generated by the generation unit 302 satisfies various design constraints.

[0240] Design constraints include, for example, placement constraints on at least some contacts due to the word lines being connected. One example is the constraint that contacts connected to upper or lower selection gate lines must be adjacent to each other. In addition, some word lines may have specific functions assigned to them, and contacts connected to these word lines may also be required to be adjacent to each other.

[0241] Alternatively, contacts may be divided into several groups depending on the hierarchical level of the word lines being connected, such as high-rise, mid-rise, and low-rise. In this case, it may be required that a group of contacts belonging to the same group be adjacent to each other. Furthermore, constraints may be imposed, such as the requirement to place blank areas between these groups where no contacts are located.

[0242] Furthermore, there may be constraints that require contacts to be distributed within a predetermined number of contacts within the contact area. In this case, it becomes necessary to divide these contacts into multiple groups and place blank areas between each group.

[0243] Furthermore, when dividing contacts into multiple groups, the order in which contacts are placed within each group may be constrained depending on whether they are odd-numbered or even-numbered, or other factors related to the word lines they are connected to.

[0244] Furthermore, since each contact is ultimately connected to wiring that leads to the surrounding circuitry, the need to secure these wiring paths can also be a constraint.

[0245] If the initial arrangement of the contact holes CLe generated by the generation unit 302 satisfies various constraints, the simulation unit 303 simulates the difference in layer thickness when a resist layer 111 is formed on the contact holes CLe with the initial arrangement. As described above, the resist layer 111 is the state of the resist pattern used when additionally processing the contact holes CLe before exposure and development.

[0246] The determination unit 304 refers to the design information acquired by the acquisition unit 301 and determines whether the thickness difference of the resist layer 111 simulated by the simulation unit 303 is within the upper limit.

[0247] If the initial arrangement of the contact holes CLe does not satisfy any of the constraints, or if the difference in thickness of the resist layer 111 obtained from the simulation exceeds the upper limit, the generation unit 302 rearranges the contact holes CLe to satisfy these conditions. Various methods can be considered for rearranging the contact holes CLe. The generation unit 302 can select a predetermined method from among these various rearrangement methods.

[0248] The following describes an example of changing the arrangement of contact holes CLe based on the difference in the thickness of the resist layer 111 for each region A to E.

[0249] In the example shown in Figure 24(a), the initial placement of the contact holes CLe satisfies the design constraints, but the difference in the thickness of the resist layer 111 obtained from the simulation exceeds the upper limit. In this case, the generation unit 302 divides the region where the contact holes CLe are placed into several regions A to E, and compares the thickness of the resist layer 111 in each region A to E with the design value thickness THd. This allows the difference from the design value of the resist layer 111 in each region A to E to be determined.

[0250] As shown in FIG. 24(b), the generation unit 204 generates a new layout of the contact holes CLe by swapping the arrangement order of the contact holes CLe so that the bias of the difference from the design values of the resist layers 111 in the individual regions A to E is reduced.

[0251] In the example of FIG. 24(b), assume that the differences from the design values of the resist layers 111 in the individual regions A to E are A > B > C > D > E. That is, in the above initial layout of the contact holes CLe, as the depth of reach of the contact holes CLe increases, the bias of the layer thickness difference of the resist layer 111 becomes larger. Therefore, the generation unit 302 generates a new layout of the contact holes CLe so that, for example, by swapping the arrangement order of the contact holes CLe, the resist layer 112 has a smaller bias of the layer thickness difference, such as B > C > E > A > D.

[0252] Note that the method for generating a new layout of the contact holes CLe so that the bias of the difference from the design values of the resist layers 111 in the individual regions A to E is reduced is not limited to the above. As an example, after quantifying the layer thickness change of the resist layer 111 using a moving average or the like, a method such as swapping the arrangement order of the contact holes CLe can be used.

[0253] The determination unit 304 determines whether the newly generated layout of the contact holes CLe satisfies various design constraints. Also, the simulation unit 303 simulates the layer thickness difference when the resist layer 112 is formed for the new layout.

[0254] The design device 30 repeats the above operations until a layout that satisfies various design constraints for these contact holes CLe and has a layer thickness difference of the resist layer within the upper limit value is obtained.

[0255] Furthermore, as described above, the contact holes of the semiconductor memory device undergo multiple additional processing steps until the reachable depth reaches the target insulating layer NL. During this process, the reachable depth of each contact hole changes constantly, and therefore the difference in the thickness of the resist layer formed above them may also differ from step to step. Thus, the design apparatus 30 examines whether the difference in the thickness of the resist layer in other steps remains below the upper limit for the appropriate arrangement of contact holes obtained in one step.

[0256] The operation of the design apparatus 30 ends when an arrangement is obtained in which the difference in thickness of the resist layers is less than or equal to the upper limit value in all processes.

[0257] The design device 30 may also adjust the number of contact holes in the arrangement and make other adjustments during the initial arrangement of contact holes or the rearrangement of contact holes after modification. When multiple contact holes are arranged in an arrangement, various variations become available. Figure 25 shows some examples.

[0258] Figure 25 is a schematic diagram showing examples of variations in the arrangement of contact holes CLf and CLg by the design apparatus 30 according to Embodiment 2.

[0259] Figure 25(a) shows an example where the reach depth of the contact hole CLf is aligned across multiple arrays.

[0260] Figure 25(b) shows an example of a case where the depth of the contact hole CLg is increased from one direction to the other, and the increase or decrease in the depth is reversed among multiple arrays.

[0261] (Example of processing for the design device) Next, an example of processing in the design apparatus 30 of Embodiment 2 will be described using Figure 26. Figure 26 is a flowchart showing an example of the procedure for designing contact hole arrangement using the design apparatus 30 according to Embodiment 2.

[0262] As shown in Figure 26, the acquisition unit 301 of the design apparatus 30 acquires design information of the semiconductor memory device to be processed (step S101). The generation unit 302 generates the initial arrangement of contact holes based on the design information (step S102). The determination unit 304 determines whether the arrangement satisfies the design constraints (step S103).

[0263] If the arrangement of the generated contact holes does not satisfy any of the design constraints (step S103: No), the arrangement is changed to satisfy the constraint (step S107), and the process from step S103 onwards is repeated.

[0264] If the arrangement of contact holes generated by the generation unit 302 satisfies the design constraints (step S103: Yes), the simulation unit 303 simulates the difference in layer thickness of the resist layer formed on those contact holes (step S104). The determination unit 304 determines whether the simulated difference in layer thickness of the resist layer is less than or equal to the upper limit (step S105).

[0265] If the difference in the thickness of the resist layer exceeds the upper limit in the arrangement of the generated contact holes (step S105: No), the thickness of each region is extracted (step S108), the arrangement is changed so that the difference in the thickness of each region of the resist layer is reduced (step S109), and the process from step S103 onwards is repeated.

[0266] If the difference in the thickness of the resist layer is below the upper limit (step S105: Yes), the determination unit 304 determines whether the resist layer before exposure and development of the resist pattern is below a predetermined upper limit in all processes necessary for forming the target contact hole (step S106).

[0267] If there is a step in which the resist layer exceeds a predetermined upper limit (step S106: No), the process from step S102 is repeated.

[0268] If, throughout the entire process, the resist layer is below a predetermined upper limit value (step S106: Yes), the process ends.

[0269] As described above, the design process for contact hole placement in the design apparatus 30 of Embodiment 2 ends.

[0270] (Summary) Optimizing the placement of contact holes with different reach depths so that the layer thickness difference of the resist pattern is below the upper limit value is difficult because various factors are involved. Factors affecting the layer thickness difference of the resist pattern include differences in the formation methods of contact holes with different reach depths and the large variety of variations in the placement of contact holes. In addition, there are many design constraints, such as restrictions on the arrangement order of contact holes and the need to secure wiring paths connected to contacts.

[0271] According to the design method in the design apparatus 30 of Embodiment 2, it is determined whether the layer thickness difference in the resist layer covering a plurality of holes having a predetermined arrangement that satisfies design constraints is below a predetermined upper limit value. Thereby, when optimizing the placement of contact holes, it is possible to evaluate both the design constraints and the layer thickness difference of the resist layer.

[0272] According to the design method in the design apparatus 30 of Embodiment 2, when the layer thickness difference of the resist layer described above exceeds the upper limit value, the placement of the plurality of holes is changed to another placement that satisfies the design constraints, and when the layer thickness difference in the resist layer covering these holes is below a predetermined upper limit value, this placement is adopted. Thereby, it is possible to balance both the design constraints and the layer thickness difference of the resist layer. Therefore, it is possible to obtain a placement of contact holes that can suppress the variation in the layer thickness of the resist pattern on a plurality of contact holes with different reach depths.

[0273] According to the design method in the design apparatus 30 of Embodiment 2, the calculation and determination of the layer thickness difference for multiple different arrangements of holes is repeated until the layer thickness difference of the resist layer is less than or equal to an upper limit. This makes it possible to more reliably reconcile design constraints with the layer thickness difference of the resist layer.

[0274] According to the design method in the design apparatus 30 of Embodiment 2, for each different arrangement of multiple holes, the difference in the thickness of the resist layer is calculated and determined for each of the multiple processes at each stage of these holes. This makes it possible to balance design constraints with the difference in the thickness of the resist layer throughout the entire process.

[0275] According to the design method in the design apparatus 30 of Embodiment 2, the newly generated arrangement from the initial arrangement is generated by calculating the difference in layer thickness of the resist layer in the initial arrangement for each predetermined region, and changing the arrangement of multiple holes so that the difference in layer thickness of the resist layer for each predetermined region is minimized. This makes it possible to suppress variations in the layer thickness of the resist pattern on multiple contact holes with different reach depths.

[0276] (modified version) Next, a modified design apparatus of Embodiment 2 will be described using Figures 27 and 28. The modified design apparatus differs from Embodiment 2 described above in that it has a function to add a dummy contact hole CLj under predetermined conditions.

[0277] Figure 27 is a schematic diagram illustrating an example of the design operation of the contact hole arrangement CLe and CLj by a design apparatus according to a modified example of Embodiment 2.

[0278] Figure 27(a) is a reproduction of Figure 24(b) of Embodiment 2 described above. The modified design apparatus determines whether or not to add dummy contact holes CLj to the arrangement of predetermined contact holes CLe generated by the generation unit.

[0279] More specifically, the modification determination unit determines whether the thickness difference of the resist layer 112 formed on a contact hole CLe having a predetermined arrangement has decreased by a predetermined value or more compared to the thickness difference of the resist layer in the contact hole CLe with the arrangement generated immediately before it. Referring to the example in Figure 24 above, the layer immediately before the resist layer 112 is the resist layer 111. Therefore, it is determined whether the thickness difference of the resist layer 112 has decreased by a predetermined value or more compared to the thickness difference of the resist layer 111.

[0280] If the thickness difference of the resist layer 112 is not significantly reduced compared to the thickness difference of the resist layer 111, that is, if the reduction is less than a predetermined value, it means that the arrangement of contact holes CLe in the modified Figure 27(a) is not significantly improved compared to the arrangement of contact holes CLe in the previous Figure 24(a). The fact that there is not sufficient improvement in the thickness difference of the resist layer 112 in the modified arrangement of contact holes CLe suggests that it is difficult to improve the thickness difference of the resist layer by simply changing the order of the contact holes CLe.

[0281] As shown in Figure 27(b), in such cases, the modified model generation unit does not further change the order of the contact holes CLe to generate a new arrangement, but rather adds dummy contact holes CLj to the arrangement in Figure 27(a). The position and number of added dummy contact holes CLj are determined based on the difference in the thickness of the resist layer in the arrangement in Figure 27(a).

[0282] This increases the likelihood of seeing improvements in the thickness difference of the resist layer 113 that cannot be achieved simply by changing the arrangement of the contact holes CLe.

[0283] Figure 28 is a flowchart showing an example of the procedure for designing contact hole placement using a design apparatus according to a modified example of Embodiment 2.

[0284] As shown in Figure 28, in the modified design apparatus, in addition to the processes of steps S101 to S109 shown in Figure 26 of Embodiment 2 described above, the processes of steps S107a, S107b, and S108a are performed. The processes of steps S107a and S107b are processes to decide whether or not to add dummy contact holes, and the process of step S108a is a process to add dummy contact holes.

[0285] In other words, if the difference in the thickness of the resist layer in a predetermined arrangement of contact holes exceeds the upper limit (step S105: No), the modified form determination unit determines whether or not that arrangement is the initial arrangement generated at the beginning of the process (step S107a).

[0286] If the predetermined arrangement of the contact holes is not the initial arrangement but an arrangement generated by modification from the previously generated arrangement (step S107a: No), the modified arrangement determination unit further determines whether the difference in the thickness of the resist layer in the arrangement generated by modification is reduced by a predetermined value or more compared to the difference in the thickness of the layer in the previous arrangement (step S107b).

[0287] If the difference in the thickness of the resist layer in the arrangement generated by the change is less than a predetermined value compared to the difference in thickness in the previous arrangement (step S107b: No), it is considered difficult to improve the difference in the thickness of the resist layer to below the upper limit even if the order of the contact holes in that arrangement is further changed.

[0288] Therefore, the modified form generation unit does not change the order of contact holes in the arrangement generated by the modification, but rather adds dummy contact holes to the arrangement generated by the modification (step S108a).

[0289] For configurations where dummy contact holes have been added, the process from step S103 is repeated.

[0290] On the one hand, when a predetermined arrangement of contact holes is the initial arrangement (step S107a: Yes), there is no previous arrangement to be compared. Therefore, the process of step S107b is skipped.

[0291] Also, even when a predetermined arrangement of contact holes is a newly generated arrangement due to a change (step S107a: No), if the layer thickness difference of the resist layer in that arrangement has decreased by a predetermined value or more compared to the layer thickness difference in the previous arrangement (step S107b: Yes), it is considered that there is room to improve the layer thickness difference of the resist layer to be within the upper limit value by further changing the arrangement order of the contact holes in that arrangement.

[0292] Therefore, the generation unit of the modified example extracts the layer thickness difference of the resist layer for each region in that arrangement (step S108), and based on this, further changes the arrangement order of the contact holes (step S109).

[0293] For the arrangement obtained by further changing the arrangement order of the contact holes, the process from step S103 is repeated.

[0294] As described above, the design process of the contact hole arrangement in the modified example design apparatus ends.

[0295] According to the design method in the modified example design apparatus, a predetermined arrangement of contact holes is generated including adding dummy contact holes in the vicinity of the arrangement regions of a plurality of holes. Thereby, the variation in the layer thickness of the resist pattern on a plurality of contact holes with different reach depths can be further suppressed.

[0296] According to the design method in the modified design apparatus, dummy contact holes are added when the decrease in the thickness difference of the resist layer in a given arrangement of contact holes from the thickness difference in the previous arrangement is less than a predetermined value. This makes it possible to obtain a contact hole arrangement that can suppress variations in the thickness of the resist pattern on multiple contact holes with different reach depths, even in situations where further changes to the order of the contact holes would not be sufficient for improvement.

[0297] According to the design method in the modified design apparatus, a predetermined arrangement of contact holes is generated by calculating the thickness difference of the resist layer in each predetermined region in arrangements where the thickness difference of the resist layer exceeds an upper limit, when the decrease in the thickness difference of the resist layer in the predetermined arrangement of contact holes from the thickness difference in the previous arrangement is greater than or equal to a predetermined value, and by changing the arrangement of multiple holes so that the thickness difference in each predetermined region is minimized.

[0298] The design method in the modified design apparatus also provides the same effects as the design method in the design apparatus of Embodiment 2 described above.

[0299] (Other variations) In the above-described embodiment 2 and its modifications, the difference in the thickness of the resist layer formed on contact holes having a predetermined arrangement is calculated by simulation. However, the evaluation method for contact holes having a predetermined arrangement is not limited to this. For example, the difference in the thickness of the resist layer may be determined based on the distribution of the volume density of these contact holes.

[0300] Furthermore, in the above-described embodiment 2 and its modifications, the arrangement of contact holes generated by the generation unit is appropriately determined to satisfy various design constraints. However, the method for obtaining an arrangement that satisfies design constraints is not limited to this. For example, based on various constraints, prohibited items may be set in advance in the generation of the arrangement by the generation unit. Alternatively, the generation unit may be provided with a grouping function for individual contact holes, and configured to treat each group of contact holes as a single unit.

[0301] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0302] 1...Semiconductor memory device, 30...Design device, 36...Control program, 81...Hard mask pattern, 101~108,108a~108c...Resist pattern, 111~113...Resist layer, 301...Acquisition unit, 302...Generation unit, 303...Simulation unit, 304...Determination unit, 305...Storage unit, CBA...Peripheral circuit, CC...Contact, CL,CLa~CLe,CLj...Contact hole, ER...Contact area, LM,LMa,LMb,LMga,LMgb,LMsa,LMsb...Laminate, MC...Memory cell, MR...Memory area, NL,OL...Insulating layer, PL,PLa,PLb...Pillar, SB...Semiconductor substrate, SGD,SGS...Selection gate line, STD,STS...Selection gate, WL...Word line.

Claims

1. A design method for determining the arrangement of multiple holes with different reach depths, When one or more design constraints exist, and a resin layer is formed covering the plurality of holes having a first arrangement that satisfies the one or more constraints, the first layer thickness difference caused by a portion of the resin layer flowing into the plurality of holes is calculated in the resin layer on the plurality of holes. Determine whether the first layer thickness difference is less than or equal to a predetermined upper limit. If the first layer thickness difference exceeds the upper limit, the second layer thickness difference that occurs in the resin layer on the plurality of holes when the arrangement of the plurality of holes is changed to a second arrangement that satisfies one or more of the constraints is calculated. Determine whether the second layer thickness difference is less than or equal to the upper limit value. If the second layer thickness difference is less than or equal to the upper limit, the second arrangement is adopted. Design method.

2. The calculation and determination of the layer thickness difference are repeated for different arrangements of the plurality of holes until the layer thickness difference of the resin layer becomes less than or equal to the upper limit. The design method according to claim 1.

3. The second arrangement described above is, The first layer thickness difference in the first arrangement is calculated for each predetermined region, The generated includes changing the arrangement of the plurality of holes so that the difference in the first layer thickness for each predetermined region is minimized, The design method according to claim 1.

4. If the second layer thickness difference exceeds the upper limit, the third layer thickness difference that occurs in the resin layer on the plurality of holes when the arrangement of the plurality of holes is changed to a third arrangement that satisfies one or more of the constraints is calculated. To determine whether the third layer thickness difference is less than or equal to the upper limit, The design method according to claim 1.

5. The third arrangement described above is, The process involves adding dummy holes adjacent to the arrangement area of ​​the aforementioned multiple holes, which is then generated. The design method according to claim 4.

6. The one or more of the above constraints are, This includes inserting a blank area into the area where none of the aforementioned holes are located, The design method according to claim 1.

7. From the aforementioned multiple halls, Multiple conductive layers are stacked spaced apart from each other, and a plurality of contacts are formed extending in the stacking direction of the stack and connected to any of the plurality of conductive layers. At least a portion of the plurality of conductive layers are divided into one or more groups as a group of conductive layers, The one or more of the above constraints are, This includes arranging the group of conductive layers belonging to the same group adjacent to each other. The design method according to claim 1.

8. Multiple conductive layers are stacked spaced apart from each other, and a plurality of contacts are formed extending in the stacking direction of the stack and connected to any of the plurality of conductive layers. Each of the aforementioned multiple contacts is connected to a wire, The one or more of the above constraints are, This includes securing wiring paths to the aforementioned plurality of contacts, The design method according to claim 1.

9. A program for determining the arrangement of multiple holes with different reach depths, On the computer, When one or more design constraints exist, and a resin layer is formed covering the plurality of holes having a first arrangement that satisfies the one or more constraints, the first layer thickness difference caused by a portion of the resin layer flowing into the plurality of holes is calculated in the resin layer on the plurality of holes. Determine whether the first layer thickness difference is less than or equal to a predetermined upper limit. If the first layer thickness difference exceeds the upper limit, the second layer thickness difference that occurs in the resin layer on the plurality of holes when the arrangement of the plurality of holes is changed to a second arrangement that satisfies one or more of the constraints is calculated. Determine whether the second layer thickness difference is less than or equal to the upper limit value. If the second layer thickness difference is less than or equal to the upper limit, the second arrangement is to be adopted. program.

10. A laminate in which multiple conductive layers are stacked apart from each other, A pillar extending within the laminate in the stacking direction of the laminate, with memory cells formed at each intersection with at least a portion of the plurality of conductive layers, The laminate comprises a plurality of contacts extending in the lamination direction and having different penetration depths within the laminate, The aforementioned multiple contacts They are arranged in a line in a predetermined direction, The arrangement is such that the reach depth increases from both ends in the predetermined direction toward the center. Semiconductor memory device.

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