Semiconductor wafer manufacturing method
By stopping the susceptor rise during wafer placement and adjusting raising speeds, the method addresses wafer misalignment issues in single-wafer furnaces, enhancing the flatness of semiconductor wafers through reduced temperature differences and stable support.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SUMCO CORP
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-30
Smart Images
Figure 2026106505000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor wafer. More specifically, the present invention relates to a method for manufacturing a semiconductor wafer, including heat treatment of the semiconductor wafer (for example, formation of an epitaxial layer).
Background Art
[0002] As an example of the processes performed during the manufacture of a semiconductor wafer such as a silicon wafer, various heat treatments such as formation of an epitaxial layer, annealing, and formation of a thermal oxide film can be mentioned. During such heat treatment, usually, the susceptor in the heat treatment furnace is raised and lowered to place the semiconductor wafer on the susceptor (see, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] For heat treatment of a semiconductor wafer (also simply referred to as a "wafer"), a single-wafer heat treatment furnace is widely used. The heat treatment of a semiconductor wafer in a single-wafer heat treatment furnace (also simply referred to as a "heat treatment furnace") is performed, for example, as follows. When a semiconductor wafer is carried into the process chamber of the heat treatment furnace by a transfer means, the lift pins rise upward in a state of protruding from the through holes of the susceptor to receive and support the semiconductor wafer. Further, as the susceptor rises, the semiconductor wafer is placed on the susceptor and heat treatment is performed. When the heat treatment is completed, the lift pins protrude upward again from the through holes of the susceptor to support the semiconductor wafer. The semiconductor wafer supported by the lift pins is transferred onto the transfer means and discharged out of the process chamber.
[0005] When heat-treating multiple semiconductor wafers using a single-wafer heat treatment furnace, wafer placement on the susceptor and heat treatment are performed sequentially for each wafer within the furnace. If the wafer placement position on the susceptor is misaligned from the target position (also referred to as "wafer placement misalignment"), the outer edge thickness shape of the heat-treated wafer may not be the desired shape. When such a phenomenon occurs, for example, the heat-treated wafer may not meet the desired outer edge flatness quality. Therefore, it is desirable to suppress the occurrence of wafer placement misalignment on the susceptor during wafer heat treatment in a single-wafer heat treatment furnace.
[0006] One aspect of the present invention aims to suppress the occurrence of wafer placement misalignment on a susceptor in a single-wafer heat treatment furnace. [Means for solving the problem]
[0007] Through diligent research, the inventors have concluded that the cause of wafer misalignment lies in wafer warping resulting from the temperature difference between the front and back surfaces of the wafer. Based on this conclusion, further diligent research has led the inventors to discover that wafer misalignment can be suppressed by temporarily stopping the rise of the susceptor during the period when only the susceptor is raised to place a semiconductor wafer on it. The inventors surmise that this is because the temperature difference between the front and back surfaces of the wafer caused by radiant heat from the susceptor can be reduced by providing the above-mentioned stopping period, thereby mitigating the wafer warping caused by this temperature difference. However, the present invention is not limited to the conclusions described herein.
[0008] One aspect of the present invention is as follows: [1] A method for manufacturing a semiconductor wafer, comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace, The above single-wafer heat treatment furnace comprises a plurality of lift pins and a susceptor having a plurality of through holes through which each of the lift pins can be inserted into the semiconductor wafer mounting area. Insert each of the multiple lift pins into each of the multiple through holes, causing each of the multiple lift pins to protrude upward from the multiple through holes, raise the susceptor and the multiple lift pins so that the multiple lift pins come into contact with the back surface of the semiconductor wafer and the semiconductor wafer is supported by the multiple lift pins. Raising only the susceptor to place the semiconductor wafer supported by the multiple lift pins onto the semiconductor wafer mounting area of the susceptor, and The semiconductor wafer placed on the semiconductor wafer mounting area of the susceptor is subjected to heat treatment. Includes, A method for manufacturing a semiconductor wafer, comprising: a period during which the raising of the susceptor is stopped while only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting region of the susceptor. [2] During the period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor, the susceptor is raised at a first susceptor raising rate, followed by a second susceptor raising rate which is slower than the first susceptor raising rate. The method for manufacturing a semiconductor wafer as described in [1], wherein the period during which the rise of the susceptor described above is stopped is included in the second susceptor rise period. [3] A method for manufacturing a semiconductor wafer according to [1], comprising a period during which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, and a period during which the raising of the susceptor and the plurality of lift pins is stopped. [4] During the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, the period includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed that is slower than the first raising speed. The method for manufacturing a semiconductor wafer according to [3], wherein the period during which the rise of the susceptor and the plurality of lift pins is stopped is included in the second rise period. [5] The method for manufacturing a semiconductor wafer according to [2], comprising a period during which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, and a period during which the raising of the susceptor and the plurality of lift pins is stopped. [6] During the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, the period includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed that is slower than the first raising speed. The method for manufacturing a semiconductor wafer according to [5], wherein the period during which the rise of the susceptor and the plurality of lift pins is stopped is included in the second rise period. [7] The method for manufacturing a semiconductor wafer according to any one of [1] to [6], wherein the single-wafer heat treatment furnace is an epitaxial growth furnace and the heat treatment is the formation of an epitaxial layer. [Effects of the Invention]
[0009] According to one aspect of the present invention, a method for manufacturing a semiconductor wafer can be provided, which includes suppressing the occurrence of wafer placement misalignment on a susceptor and heat-treating a semiconductor wafer in a single-wafer heat treatment furnace. [Brief explanation of the drawing]
[0010] [Figure 1] This is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. [Figure 2]It is a flowchart for explaining the operations of lift pins and susceptors in the single-wafer epitaxial growth furnace shown in FIG. 1. [Figure 3] For each of Levels 1 to 7 described later, the placement position (two-dimensional coordinate system) of the center of the wafer on the susceptor in the state of S6 in FIG. 2 is shown. [Figure 4] The result of graphing the data of the placement positions of the wafer centers at each level shown in FIG. 3 in a one-way graph is shown.
Embodiments for Carrying Out the Invention
[0011] Hereinafter, the above manufacturing method will be described in more detail.
[0012] <Semiconductor Wafer> Examples of semiconductor wafers heat-treated in a single-wafer heat treatment furnace include various semiconductor wafers such as silicon wafers. For example, a wafer cut from an ingot of a semiconductor material grown by a known method (e.g., a silicon single crystal wafer cut from a silicon single crystal ingot) can be subjected to one or more processes such as planarization, polishing processes such as mirror polishing, chamfering processes, and cleaning processes, and then introduced into a heat treatment furnace for heat treatment. The conductivity type of the semiconductor wafer may be p-type or n-type.
[0013] <Single-Wafer Heat Treatment Furnace> Examples of single-wafer heat treatment furnaces include an epitaxial growth furnace for forming an epitaxial layer on a semiconductor wafer, an annealing furnace for annealing a semiconductor wafer, a thermal oxidation furnace for forming a thermal oxide film on a semiconductor wafer, and the like. The configurations of these heat treatment furnaces are known.
[0014] In a single-wafer heat treatment furnace, a semiconductor wafer is placed on a susceptor provided in the heat treatment furnace, and heat treatment is performed in the furnace.
[0015] FIG. 1 is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. The epitaxial growth furnace 1 shown in FIG. 1 includes a process chamber 10 where an epitaxial layer is formed inside. A reaction gas is introduced into the quartz glass process chamber 10, and the susceptor 12 and the preheating ring 17 are heated by the lamp 19 from the outside of the process chamber 10 to form an epitaxial layer on the surface of the semiconductor wafer W. The semiconductor wafer W is carried into the process chamber 10 by the transfer blade 18 which is a conveying means, and after the formation of the epitaxial layer is completed, it is carried out of the process chamber 10 by the transfer blade 18. The susceptor 12 has a plurality of through-holes through which the lift pins 11 can be inserted in the semiconductor wafer placement area, and a plurality of lift pins 11 are respectively inserted into such through-holes. The lift pin 11 is connected to the lift assembly 16 via a lift shaft 14 and a lift arm 15. The susceptor 12 is connected to the lift assembly 16 via a susceptor support shaft 13. In FIG. 1, two lift pins 11 are shown as an example. However, in the single-wafer heat treatment furnace used in the above manufacturing method, the number of lift pins may be plural (that is, two or more), and is not limited to the number illustrated in the drawing.
[0016] FIG. 2 is a flowchart for explaining the operations of the lift pins and the susceptor in the single-wafer epitaxial growth furnace shown in FIG. 1. In FIG. 2, some of the various components of the single-wafer epitaxial growth furnace shown in FIG. 1 are omitted. Hereinafter, the operations shown in FIG. 2 will be described. The semiconductor wafer W is carried into the process chamber (see FIG. 1) by the transfer blade 18 (S1). The susceptor 12 and lift pin 11 are raised by the drive of the lift assembly (see Figure 1) with the lift pin 11 protruding upward from the through-hole of the susceptor 12 (S2-S4). As the susceptor 12 and lift pin 11 rise while maintaining the state in which the lift pin 11 protrudes upward from the through-hole of the susceptor 12, the lift pin 11 comes into contact with the back surface of the semiconductor wafer W on the transfer blade 18 (S3). Furthermore, as the susceptor and lift pin 11 rise while maintaining the state in which the lift pin 11 protrudes upward from the through-hole of the susceptor 12, contact between the semiconductor wafer W and the transfer blade 18 is released (S4). Subsequently, the transfer blade 18 exits the process chamber. During the period until the transfer blade 18 exits the process chamber, the rise of the susceptor 12 and the lift pin 11 is stopped. After the transfer blade 18 exits the process chamber, the susceptor support shaft (see Figure 1) drives the susceptor 12 to rise only (S5, S6), and the semiconductor wafer W supported by the lift pins 11 is placed on the semiconductor wafer mounting area of the susceptor 12 (S6). Specifically, the semiconductor wafer W is housed in the recess of the semiconductor wafer mounting area of the susceptor 12 (S6). In the present invention and herein, during the period when "only the susceptor is rising", the drive of the lift assembly for raising and lowering the lift pins inserted through the through-holes of the susceptor is stopped. Subsequently, the susceptor 12 on which the semiconductor wafer W is placed is further raised to the film deposition position while holding the lift pins 11 (S7). After forming an epitaxial layer at the film deposition location, steps S1 to S6 are performed in reverse order, that is, in the order of S6, S5, S4, S3, S2, and S1, and then the semiconductor wafer W is transported out of the process chamber by the transfer blade 18.
[0017] <Specific examples and comparative examples of lift pin and susceptor operation> Table 1 shows specific examples and comparative examples of the operation of the lift pin and susceptor.
[0018] [Table 1]
[0019] In Table 1, "a seconds" in the "S1→S2" column indicates that the time required to transition from state S1 to state S2 in the flow diagram shown in Figure 2 is a seconds. The same applies to the "S2→S3", "S3→S4", "S4→S5", "S5→S6", and "S6→S7" columns. Unless otherwise specified, the lift pin's upward speed is constant and does not stop rising after it begins, and the susceptor's upward speed is also constant and does not stop rising after it begins. In this invention and specification, "constant speed" includes cases where the speed is completely the same and cases where the speed fluctuates unintentionally due to device-related causes, etc. In Table 1, the period "S1→S2→S3" is the period during which the susceptor and lift pin are raised until the lift pin and the back surface of the semiconductor wafer come into contact. Subsequently, during the period "S3→S4", the susceptor and lift pin are raised further, releasing the support of the semiconductor wafer by the transfer blade, and the semiconductor wafer is supported only by the lift pin (S4). Although not shown in Figure 2, in state S4, the semiconductor wafer is supported only by the lift pins, after which the transfer blade exits the process chamber. As previously described, the rise of the susceptor and lift pins is stopped during the period until the transfer blade exits the process chamber. The period from when the susceptor alone begins to rise after the transfer blade has exited the process chamber until S6 is defined as "the period during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor." This period corresponds to "S4→S5→S6" in Table 1. For details, as described in "Note 1" in the margin of Table 2, "S4→S5" is the period from when the susceptor alone begins to rise after the transfer blade has exited the process chamber until S5. In Table 1, the "Specific Example" includes a period during which the susceptor rise is stopped while only the "S4→S5→S6" susceptor is raised. The "Comparative Example" does not include a period during which the susceptor rise is stopped while only the "S4→S5→S6" susceptor is raised. The details of each level shown in Table 1 are described below. During the period when the susceptor and lift pin are rising, the rising speed of the susceptor and the rising speed of the lift pin are the same. This ensures that the lift pin remains above the through-hole of the susceptor throughout the period when the susceptor and lift pin are rising. In this invention and specification, "same speed" includes cases where the speeds are exactly the same and cases where there is an unintentional difference in speed due to device-related reasons, etc. Hereafter, the rising speed of the susceptor and lift pin will also be referred to as "rising speed (susceptor + lift pin)". The rising speed of the susceptor alone will also be referred to as "susceptor rising speed".
[0020] (Level 1: Comparative Examples) During the entire "S1→S2→S3" period (i.e., the period during which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer), the upward speed (susceptor + lift pin) is constant. During the entire "S4→S5→S6" period (i.e., the period in which only the susceptor is raised), the susceptor's raising speed is constant.
[0021] (Level 2: Comparative Examples) During the "S1→S2→S3" phase, the ascent rate (susceptor + lift pin) during the "S2→S3" phase is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" phase. For the period "S4→S5→S6", the susceptor ascent rate is constant throughout the entire period, just like at level 1.
[0022] (Level 3: Comparative Examples) For the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) is constant throughout the entire period, just like in Level 1. During the "S4→S5→S6" period, the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period.
[0023] (Level 4: Comparative Examples) During the "S1→S2→S3" phase, the ascent rate (susceptor + lift pin) during the "S2→S3" phase is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" phase. During the "S4→S5→S6" period, the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period.
[0024] (Level 5: Specific Examples) During the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. Furthermore, the "S2→S3" period includes a period during which the ascent of the susceptor and lift pin is stopped. In Table 1, "Stop p seconds" in the "S2→S3" column indicates that the ascent of the susceptor and lift pin is stopped for p seconds during the "S2→S3" period (total ascent time (susceptor + lift pin) before and after the stop: n seconds). During the "S4→S5→S6" period, the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period. Furthermore, the "S5→S6" period includes a period during which the susceptor ascent is stopped. In Table 1, the "Stop r seconds" listed in the "S5→S6" column indicates that the susceptor ascent is stopped for r seconds during the "S5→S6" period (total time the susceptor is rising before and after the stop: q seconds).
[0025] (Level 6: Comparative Examples) During the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. Furthermore, the "S2→S3" period includes a period during which the ascent of the susceptor and lift pin is stopped. In Table 1, "Stop p seconds" in the "S2→S3" column indicates that the ascent of the susceptor and lift pin is stopped for p seconds during the "S2→S3" period (total ascent time (susceptor + lift pin) before and after the stop: n seconds). For the period "S4→S5→S6", the susceptor ascent rate is constant throughout the entire period, just like at level 1.
[0026] (Level 7: Specific Examples) For the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) is constant throughout the entire period, just like in Level 1. During the "S4→S5→S6" period, the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period. Furthermore, the "S5→S6" period includes a period during which the susceptor ascent is stopped. In Table 1, the "Stop r seconds" listed in the "S5→S6" column indicates that the susceptor ascent is stopped for r seconds during the "S5→S6" period (total time the susceptor is rising before and after the stop: q seconds).
[0027] Levels 5 and 7 include a period during which the susceptor is stopped rising while only the susceptor is raised. As mentioned earlier, including such a period can help suppress wafer misalignment by reducing the temperature difference between the front and back surfaces of the wafer caused by the radiant heat of the susceptor. Furthermore, "Level 5" includes a period during the "S1→S2→S3" phase, that is, the period during which the susceptor and lift pins are raised until the lift pins contact the back surface of the semiconductor wafer, during which the raising of the susceptor and lift pins is stopped. The inventors surmise that including such a period contributes to reducing the temperature difference between the front and back surfaces of the wafer caused by the radiant heat of the lift pins and susceptor. The inventors believe that reducing the temperature difference between the front and back surfaces of the wafer in this way helps to suppress timing discrepancies in contact with the back surface of the wafer among multiple lift pins, which in turn leads to stable support of the semiconductor wafer by the lift pins. The inventors surmise that by stably supporting the semiconductor wafer with the lift pins, the occurrence of wafer placement misalignment can be further suppressed.
[0028] Furthermore, the inventors surmise that, from the viewpoint of further suppressing wafer placement misalignment, it is even more preferable to adopt one or both of the following embodiments (1) and (2).
[0029] (1) During the period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor, there is a first susceptor raising period in which the susceptor is raised at the first susceptor raising rate, followed by a second susceptor raising period in which the susceptor is raised at a second susceptor raising rate that is slower than the first susceptor raising rate. In "Level 5" and "Level 7" shown in Table 1, during the period "S4→S5→S6", the period "S5→S6" is the "second susceptor raising period", and the period "S4→S5" is the "first susceptor raising period". Setting a slow rate for raising the susceptor is preferable from the viewpoint of suppressing the rapid occurrence of a temperature difference between the front and back surfaces of the wafer due to radiant heat from the susceptor. On the other hand, from the viewpoint of increasing productivity by shortening the processing time in the heat treatment furnace, it is preferable to set a high rate for raising the susceptor. Embodiment (1) is preferable from the viewpoint of improving productivity and reducing the effects of radiant heat from the susceptor, because the susceptor is raised at a high speed until it comes into close proximity to the wafer, and the period during which the susceptor is raised at a low speed when the wafer is in close proximity to the wafer and is more susceptible to the effects of radiant heat from the susceptor. From both of these viewpoints, it is more preferable to include a period during which the raising of the susceptor is stopped in the second susceptor raising period.
[0030] (2) During the period in which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer, the process includes a first raising period in which the susceptor and lift pin are raised at a first raising rate, followed by a second raising period in which the susceptor and lift pin are raised at a second raising rate that is slower than the first raising rate. In "Level 5" shown in Table 1, during the period "S1→S2→S3", the period "S2→S3" is the "second raising period", and the period "S1→S2" is the "first raising period". Setting a low speed for raising the susceptor and lift pin is preferable from the viewpoint of suppressing the rapid occurrence of a temperature difference between the front and back surfaces of the wafer due to radiant heat from the lift pin and susceptor. On the other hand, from the viewpoint of increasing productivity by shortening the processing time in the heat treatment furnace, it is preferable to set a high speed for raising the susceptor and lift pin. Embodiment (2) is preferable from the viewpoint of improving productivity and reducing the influence of radiant heat from the lift pin and susceptor, because the susceptor and lift pin are raised at high speed until the lift pin approaches the wafer, and the period during which the susceptor and lift pin are raised at a low speed when the wafer is in close proximity to the wafer and is more susceptible to the effects of radiant heat from the lift pin and susceptor. From both of these viewpoints, it is more preferable to include a period during which the raising of the susceptor and lift pin is stopped in the second raising period.
[0031] The susceptor rising speed during the period when the susceptor is raised after the semiconductor wafer is placed on the wafer mounting area of the susceptor (the period from "S6" to "S7" in Table 1), and the rising speed (susceptor + lift pin) during the period when the susceptor and lift pin are raised after the lift pin contacts the back surface of the semiconductor wafer (the period from "S3" to "S4" in Table 1), are not particularly limited.
[0032] During the period when only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor, a longer period during which the susceptor's rise is stopped is preferable from the viewpoint of reducing the effect of radiant heat from the susceptor, while a shorter period during which the susceptor's rise is stopped is preferable from the viewpoint of improving productivity. From both of these viewpoints, if the total time during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor is taken as 100%, then the period during which the susceptor's rise is stopped is preferably 40% to 60%. Note that when the susceptor's rise is stopped, the above total period (100%) also includes the period during which the susceptor's rise is stopped.
[0033] During the period in which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer, a longer period during which the susceptor and lift pin are stopped rising is preferable from the viewpoint of reducing the effect of radiant heat from the lift pin and susceptor, while a shorter period during which the susceptor and lift pin are stopped rising is preferable from the viewpoint of improving productivity. From both of these viewpoints, if the total time during which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer is taken as 100%, then the period during which the susceptor and lift pin are stopped rising is preferably 40% to 60%. Note that when the susceptor and lift pin are stopped rising, the above total time (100%) also includes the period during which the susceptor and lift pin are stopped rising.
[0034] As described above, according to one aspect of the present invention, a semiconductor wafer manufacturing method can suppress the occurrence of wafer placement misalignment on the susceptor and allow semiconductor wafers to be heat-treated in a single-wafer heat treatment furnace. [Examples]
[0035] The present invention will be further described below based on examples. However, the present invention is not limited to the embodiments shown in the examples.
[0036] Heat treatments were performed using each of the levels 1 to 7 shown in Table 1. In each heat treatment using a level, epitaxial layers were formed on a total of more than 200 semiconductor wafers (silicon single crystal wafers) in a single-wafer epitaxial growth furnace as shown in Figure 1. In levels 5 and 7, the total time spent raising only the susceptor until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor was defined as 100%, and the period during which the susceptor stopped rising was set to a range of 40% to 60%. At levels 5 and 6, the total time spent raising the susceptor and lift pin until the lift pin contacts the back surface of the semiconductor wafer was defined as 100%, and the period during which the susceptor and lift pin stopped rising was set to a range of 40% to 60%.
[0037] Figure 3 shows the placement position (two-dimensional coordinate system) of the wafer center on the susceptor in state S6 of Figure 2 for each of levels 1 to 7. The "center of gravity" is the center of the wafer placement area of the susceptor. The positional relationship between the wafer center and the center of gravity was confirmed by the bias of the flatness measurement data in the outer circumferential direction. In the figure, when the X axis is 0 mm and the Y axis is 0 mm, the wafer center is located on the center of gravity.
[0038] Figure 4 shows the results of graphing the wafer center placement data for each level shown in Figure 3 into a single-location graph.
[0039] Table 2 shows the average (arithmetic mean) of the discrepancy between the wafer center and the center of gravity (placement position deviation) at each level shown in Figure 3.
[0040] [Table 2]
[0041] The results shown in Table 2 confirm that by adopting "Level 5" and "Level 7," the misalignment between the wafer center and the center of gravity (mounting position misalignment) is less compared to when other levels are adopted. From these results, it can be confirmed that including a period during which the susceptor stops rising in the period during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor contributes to suppressing the occurrence of wafer mounting position misalignment on the susceptor. Furthermore, comparing "Level 5" and "Level 7" in the results shown in Table 2, the misalignment (positional misalignment) between the wafer center and the center of gravity is smaller at Level 5. From these results, it can be confirmed that by including a period during which the rise of the susceptor and lift pins is stopped in the period during which the lift pins and lift pins are raised until they contact the back surface of the semiconductor wafer, the occurrence of wafer positional misalignment on the susceptor can be further suppressed. [Industrial applicability]
[0042] One aspect of the present invention is useful in the manufacturing field of various semiconductor wafers. For example, according to one aspect of the present invention, it becomes possible to manufacture semiconductor wafers with excellent flatness quality. High-performance semiconductors containing semiconductor wafers with excellent flatness quality as substrates can play an important role in the development and industrialization of advanced industrial products. For example, semiconductors are used in control systems for various products such as automobiles, home appliances, and medical devices, and improving the performance of semiconductors is important for improving the quality and reliability of these products. Furthermore, high-performance semiconductors enable high-speed processing of large amounts of data in data centers, which are essential for providing digital services such as the internet and cloud services. This enables high-speed communication with network terminal devices. Thus, one aspect of the present invention can promote the development of many industrial fields such as medical, healthcare, energy, transportation infrastructure, and information and communication industries through semiconductor devices, and can contribute to solving the SDGs (Sustainable Development Goals) by solving various social and environmental issues.
Claims
1. A method for manufacturing a semiconductor wafer, comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace, The single-wafer heat treatment furnace comprises a plurality of lift pins and a susceptor having a plurality of through holes through which each of the lift pins can be inserted into the semiconductor wafer mounting area. Inserting each of the multiple lift pins into each of the multiple through holes so that each of the multiple lift pins protrudes above the multiple through holes, raise the susceptor and the multiple lift pins so that the multiple lift pins come into contact with the back surface of the semiconductor wafer and the semiconductor wafer is supported by the multiple lift pins. Raising only the susceptor to place the semiconductor wafer supported by the plurality of lift pins onto the semiconductor wafer mounting area of the susceptor, and The semiconductor wafer placed on the semiconductor wafer mounting region of the susceptor is subjected to heat treatment. Includes, A method for manufacturing a semiconductor wafer, comprising a period during which the raising of the susceptor is stopped while only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting region of the susceptor.
2. During the period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of the susceptor, the process includes a first susceptor raising period in which the susceptor is raised at a first susceptor raising rate, followed by a second susceptor raising period in which the susceptor is raised at a second susceptor raising rate that is slower than the first susceptor raising rate. The method for manufacturing a semiconductor wafer according to claim 1, wherein the period during which the rise of the susceptor is stopped is included in the second susceptor rise period.
3. A method for manufacturing a semiconductor wafer according to claim 1, comprising a period during which the raising of the susceptor and the plurality of lift pins is stopped while the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer.
4. During the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins contact the back surface of the semiconductor wafer, the period includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed. The method for manufacturing a semiconductor wafer according to claim 3, wherein the period during which the rise of the susceptor and the plurality of lift pins is stopped is included in the second rise period.
5. A method for manufacturing a semiconductor wafer according to claim 2, comprising a period during which the raising of the susceptor and the plurality of lift pins is stopped while the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer.
6. During the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins contact the back surface of the semiconductor wafer, the period includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed. The method for manufacturing a semiconductor wafer according to claim 5, wherein the period during which the rise of the susceptor and the plurality of lift pins is stopped is included in the second rise period.
7. The method for manufacturing a semiconductor wafer according to any one of claims 1 to 6, wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the heat treatment is the formation of an epitaxial layer.