Bottom-up plating of glass through-vias

Abstract

This paper discloses various techniques, as well as related apparatus and methods, for metallizing glass through-vias (TGVs) in glass substrates using a bottom-up plating method. [Solution] The first technique is based on the use of subtractive etching. The second technique is based on the use of a modified semi-additive process. The third technique is based on filling the cavity of the glass substrate with a fluid material in parallel with a bottom-up plating method. All of these techniques can be further improved by providing a liner on the sidewall of the TGV that functions as a buffer layer between the glass substrate and the conductive material inside the TGV.

Description

Technical Field

[0001] This application relates to bottom-up plating of glass through vias.

Background Art

[0002] Over the past few decades, the scaling of features in integrated circuits (ICs) has been the driving force behind the growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communication, and autonomous driving. In parallel with optimization at the IC level, the advanced semiconductor packaging environment has been evolving rapidly to meet the performance expectations and requirements associated with the miniaturization of IC features. Currently, it is common for multiple IC dies to be combined together in a multi-die semiconductor package to integrate features or functions and facilitate connection with other components such as a package substrate. For example, an IC package may include an embedded multi-die interconnect bridge (EMIB) for combining two or more IC dies.

[0003] Integrating multiple dies into a single IC package has significant advantages, but it increases complexity due to the placement of materials with different material properties in close proximity to each other. When an IC package undergoes multiple processing steps involving various temperature and pressure loads, the individual materials within the package may exhibit different behaviors, resulting in out-of-plane deformation of various layers, which is known as "package warpage." One way to address package warpage is to use a more rigid core to which different IC dies are attached. Recently, glass substrates have been considered as an alternative to organic resin-based cores (e.g., cores using Ajinomoto build-up film (ABF)). Glass is considered to be more rigid than organic resin-based materials and has several advantages, such as excellent thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, light transmissibility, and compatibility with advanced semiconductor properties.

[0004] Due to its superior properties, glass is useful not only as a core material for semiconductor / IC packages but also for a variety of other applications. For example, glass substrates exhibit high mechanical stability, precise flatness, and a smooth surface, making them ideal for high-density interconnect and redistribution layers (RDLs) used in advanced IC packages. Another example is the stability and low coefficient of thermal expansion (CTE) of glass, which is particularly advantageous for directly embedding passive components such as capacitors and inductors within the substrate, resulting in increased circuit density, simplified layout, and reduced need for additional external components. Yet another example is the low dielectric constant and dielectric loss of glass, which makes it very suitable for applications where signal attenuation and interference must be minimized, such as radio frequency (RF) and 5G communications. In these applications, glass substrates can function as the base layer for RF modules and antennas, enabling high-frequency performance while reducing signal loss. Furthermore, because glass is optically transparent, it allows for efficient light transmission, which is a significant advantage over silicon and organic substrates in optical and photon applications. In these applications, glass substrates are suitable for housing optoelectronic components such as photon integrated circuits (PICs), image sensors, and light-emitting diodes (LEDs).

[0005] In many applications of glass substrates in IC packaging, metal-filled through-glass vias (TGVs) are essential. TGVs are conductive vertical channels that penetrate the glass substrate, enabling electrical connections from one side of the substrate to the other, or from one side of the substrate to components embedded within it. Achieving cost-effective and high-performance TGV metallization (i.e., filling TGVs with conductive materials such as metal) remains a significant technical challenge, and further advancements are essential for the wider adoption of glass substrates in IC packaging. [Brief explanation of the drawing]

[0006] The embodiments will be readily understood by reading the following detailed description in conjunction with the accompanying drawings. For the sake of clarity, similar reference numerals indicate similar structural elements. The embodiments shown in the accompanying drawings are illustrative and not limiting. [Figure 1] This is a schematic side cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure, capable of mounting a glass substrate having a TGV manufactured using the bottom-up plating technique described herein. [Figure 2] This is a schematic side cross-sectional view of an alternative example of a microelectronic assembly according to some embodiments of the present disclosure, capable of mounting a glass substrate having a TGV manufactured using the bottom-up plating technique described herein. [Figure 3] This figure shows the surface of a glass core that can be a source of TGV stress. [Figure 4A] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 4B] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 4C] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 4D] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 4E] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 4F]These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching, according to some embodiments of the present disclosure. [Figure 5A] These are schematic side cross-sectional views of a portion of an exemplary glass substrate, illustrating features of the manufacturing method used in some embodiments of the present disclosure, as shown in Figures 4A to 4F. [Figure 5B] These are schematic side cross-sectional views of a portion of an exemplary glass substrate, illustrating features of the manufacturing method used in some embodiments of the present disclosure, as shown in Figures 4A to 4F. [Figure 5C] These are schematic side cross-sectional views of a portion of an exemplary glass substrate, illustrating features of the manufacturing method used in some embodiments of the present disclosure, as shown in Figures 4A to 4F. [Figure 6A] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6B] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6C] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6D] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6E]These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6F] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6G] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6H] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6I] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6J] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 6K] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process, according to some embodiments of the present disclosure. [Figure 7A]These are schematic side cross-sectional views of exemplary glass substrates illustrating features of the manufacturing methods used in some embodiments of the present disclosure, as shown in Figures 6A to 6K. [Figure 7B] These are schematic side cross-sectional views of exemplary glass substrates illustrating features of the manufacturing methods used in some embodiments of the present disclosure, as shown in Figures 6A to 6K. [Figure 7C] These are schematic side cross-sectional views of exemplary glass substrates illustrating features of the manufacturing methods used in some embodiments of the present disclosure, as shown in Figures 6A to 6K. [Figure 7D] These are schematic side cross-sectional views of exemplary glass substrates illustrating features of the manufacturing methods used in some embodiments of the present disclosure, as shown in Figures 6A to 6K. [Figure 8A] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity-filling material, according to some embodiments of the present disclosure. [Figure 8B] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity-filling material, according to some embodiments of the present disclosure. [Figure 8C] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity-filling material, according to some embodiments of the present disclosure. [Figure 8D] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity-filling material, according to some embodiments of the present disclosure. [Figure 8E] These are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity-filling material, according to some embodiments of the present disclosure. [Figure 8F] Schematic side cross-sectional view of a microelectronic assembly including an exemplary glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a flowable cavity filling material, according to some embodiments of the present disclosure. [Figure 8G] Schematic side cross-sectional view of a microelectronic assembly including an exemplary glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a flowable cavity filling material, according to some embodiments of the present disclosure. [Figure 8H] Schematic side cross-sectional view of a microelectronic assembly including an exemplary glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a flowable cavity filling material, according to some embodiments of the present disclosure. [Figure 9A] Schematic side cross-sectional view of an exemplary glass substrate showing features representative of the use of the manufacturing method of FIGS. 8A-8H, according to some embodiments of the present disclosure. [Figure 9B] Schematic side cross-sectional view of an exemplary glass substrate showing features representative of the use of the manufacturing method of FIGS. 8A-8H, according to some embodiments of the present disclosure. [Figure 10A] Schematic side cross-sectional view of a microelectronic assembly including an exemplary glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10B] Schematic side cross-sectional view of a microelectronic assembly including an exemplary glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10C]These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10D] These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10E] These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10F] These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10G] These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 10H] These are schematic side cross-sectional views of exemplary microelectronic assemblies, including a glass substrate, at various stages in the manufacture of a TGV formed by bottom-up plating using subtractive etching in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11A]This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11B] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11C] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11D] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11E] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11F] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11G]This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11H] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11I] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11J] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11K] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11L] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 11M]This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a modified semi-additive process in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12A] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12B] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12C] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12D] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12E] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12F] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12G] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12H] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12I] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 12J] This is a schematic side cross-sectional view of an exemplary microelectronic assembly including a glass substrate at various stages in the manufacture of a TGV formed by bottom-up plating using a fluid cavity filling material in combination with the use of a liner, according to some embodiments of the present disclosure. [Figure 13] This is a top view of a wafer and die that may be included in a microelectronic assembly including a glass core according to some embodiments of the present disclosure, or any of the embodiments disclosed herein. [Figure 14] This is a side cross-sectional view of an IC device that may be included in a microelectronic assembly including a glass core according to some embodiments of the present disclosure, or any of the embodiments disclosed herein. [Figure 15] This is a side cross-sectional view of an IC device assembly that may include a glass core according to some embodiments of the present disclosure, or any of the embodiments disclosed herein. [Figure 16] This is a side cross-sectional view of an IC device that may be included in a microelectronic assembly including a glass core according to some embodiments of the present disclosure, or any of the embodiments disclosed herein. [Modes for carrying out the invention]

[0007] As mentioned above, glass possesses properties that make it promising for integration into advanced IC packages. When a glass substrate is included in a microelectronic assembly, it may be desirable to route electrical signals within and / or through the glass substrate. For this purpose, conductive vias may be provided in the glass substrate, and such conductive vias are commonly referred to as "TGVs". TGVs can also support efficient thermal management by providing a heat dissipation path from active components to the external environment of the package. In some embodiments, TGVs extend between the top and bottom surfaces of the glass substrate, providing electrical connections between electronic components such as dies and / or package substrates coupled to the top and bottom surfaces of the glass substrate, for example. In other embodiments, TGVs are blind vias that extend from the top / bottom surface of the glass substrate toward the opposite surface but do not reach the opposite surface, providing electrical connections from the surface of the glass substrate to conductive traces or passive components embedded in the glass substrate, for example.

[0008] One challenge associated with the integration of TGV into glass substrates arises from the difference in CTE between the materials that can be used for the glass substrate and the conductive materials / metals (e.g., conductive fillers and / or seed materials) deposited on the TGV. CTE is a measure of the degree to which a material expands or contracts with temperature changes, typically defined as the increase in length per unit temperature rise, and measured, for example, in parts per million (ppm) / K or ppm / K. The CTEs of metals and glass materials differ significantly. Metals have relatively high CTEs and can expand or contract significantly with temperature changes. Glass materials, on the other hand, have much lower CTEs and are less responsive to temperature changes. For example, the CTE of glass is on the order of approximately 3.5 ppm / K, while the CTE of metals such as copper is on the order of approximately 15 ppm / K. When metals are in close contact with glass (e.g., seed materials or conductive fillers in the TGV of a glass substrate) and the assembly is exposed to temperature changes such as heating or cooling, the metals heat or cool much faster and significantly more than the glass. This generates significant thermal stress at the interface between the two materials. This high thermal stress exceeds the strength of the glass, leading to crack formation, which can propagate and compromise the structural integrity of the glass. Even if cracking does not occur immediately, repeated thermal cycling gradually weakens the glass surface, potentially leading to surface defects or microcracks. Prolonged exposure to stress caused by CTE mismatch causes the glass to gradually degrade and become more brittle over time. The stress caused by CTE mismatch resulting from the proximity of the TGV conductive material to the glass material of the glass substrate is called "TGV stress."

[0009] Embodiments of this disclosure relate to various techniques, as well as related apparatus and methods, for metallizing TGVs in a glass substrate using bottom-up plating in a cost-effective manner that meets performance standards. The first technique is based on subtractive etching (SE) and can therefore be called "bottom-up plating with SE". The second technique is based on a modified semi-additive process (mSAP) and can therefore be called "bottom-up plating with mSAP". The third technique is based on filling the cavity of the glass substrate with a fluid material while performing bottom-up plating and can therefore be called "bottom-up plating with fluid cavity filling material". All three of these techniques rely on performing bottom-up plating without using a seed material layer on the sidewalls of the TGV openings before filling the TGV openings with conductive material, which is in stark contrast to many conventional TGV metallization techniques. As a result, an air gap may inevitably be formed between the sidewalls of the TGV openings and the conductive material inside the TGV openings. Such an air gap can help reduce (e.g., alleviate or reduce) stress caused by CTE mismatch resulting from the proximity of the conductive material in the TGV to the glass material in the glass substrate, thus separating the glass substrate from the conductive material in the TGV (i.e., helping to reduce stress in the TGV). Furthermore, the air gap can advantageously provide space for thermal expansion of the conductive material in the TGV without affecting the sidewalls of the TGV opening with thermal expansion. In addition, the bottom-up plating technique described herein may be more cost-effective than conventional TGV metallization methods because it can omit one or more processing steps, such as planarization or the use of seed material on the sidewalls of the TGV opening.

[0010] Any bottom-up plating technique disclosed herein can be further modified by including a liner in the sidewall of the TGV that functions as a buffer layer between the glass substrate and the conductive material in the TGV, which can further help reduce TGV stress because the liner further separates the glass and metal deposited in the TGV (in addition to the air gap formed by bottom-up plating without seed material in the sidewall). In some embodiments, using a liner with a relatively low modulus of elasticity, e.g., Young's modulus of less than about 30 gigapascals (GPa), may be particularly advantageous for reducing TGV stress. This is because it can help reduce compressive stress caused, for example, by the expansion of the metal subsequently filled into the TGV. In some embodiments, using a liner with a lower CTE than the metal in the TGV can reduce the CTE mismatch at the interface with the glass, which can help reduce stress in the TGV. In some embodiments, the liner can function as a stress-absorbing layer. In some embodiments, the liner may contain an organic material such as parylene, the name "parylene" refers to a group of polymers known as polyparaxylylene. In some embodiments, any of the bottom-up plating techniques disclosed herein can be modified by including multiple liners in the sidewalls of the TGV before metallization, with different liners serving different purposes aimed at reducing stress on the TGV.

[0011] Integrating layers of different materials (e.g., multiple dies, redistribution layers, package substrates) into a single IC package or microelectronic assembly is challenging, particularly due to package warping. Providing a glass substrate with TGV manufactured using the bottom-up plating technique described herein to an IC package or microelectronic assembly can be helpful. Various embodiments disclosed herein can help reliably integrate multilayer structures of different materials within a single microelectronic assembly at a lower cost and / or with greater design flexibility compared to conventional approaches. Various microelectronic assemblies disclosed herein may exhibit reduced warping compared to microelectronic assemblies without glass substrates. Microelectronic assemblies disclosed herein may be particularly advantageous for small and thin applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).

[0012] The following detailed description refers to the accompanying drawings, which constitute part of this specification. Throughout the drawings, similar reference numerals indicate similar parts, and the drawings illustrate possible embodiments. It should be understood that other embodiments may be used, and structural or logical modifications may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive.

[0013] Any feature discussed with reference to the accompanying drawings herein can be combined with other features as needed to form a microelectronic assembly 100, a glass substrate 110, an IC device 1600, an IC device assembly 1700, or a communication device 1800. For convenience, the term “die 114” may be used to refer to a set of dies such as 114-1, 114-2, etc. Some elements of a drawing that have the same reference numerals may be shared between different drawings. For the sake of ease of discussion, descriptions of these elements provided in one drawing will not be repeated in other drawings, and these elements may take any form of the embodiments disclosed herein. To avoid cluttering the drawings, if multiple instances of a particular element are shown, only some of the elements may be given reference numerals (for example, Figure 1 shows multiple conductive contacts 122, but only one of them is given a reference numeral). Also to avoid cluttering the drawings, not all reference numerals shown in one drawing are shown in other similar drawings. Furthermore, multiple drawings that are denoted with different letters may be referred to without letters. For example, Figures 4A to 4F may be called "Figure 4," and Figures 5A to 5C may be called "Figure 5."

[0014] The drawings are not necessarily to scale. Many drawings depict linear structures with flat walls and right-angle corners, but this is merely for illustrative purposes and may not reflect actual process constraints. Therefore, when inspecting any of the structures described herein using, for example, scanning electron microscope (SEM) or transmission electron microscope (TEM) images, various features may not appear "ideal." Such images of actual structures may also reveal process defects, such as material edges not being perfectly straight, tapered vias or other openings, unintentionally rounded corners, and variations in the thickness of different material layers. Other defects common in the field of semiconductor device manufacturing and packaging may exist, although these are not described herein. By inspecting the layout and mask data, and by reconstructing the circuit by reverse engineering of device components using optical microscopes, TEM, or SEM, and / or inspecting the device cross-section using physical failure analysis (PFA), it is possible to determine the presence of a glass substrate with TGV manufactured using the bottom-up plating technique described herein.

[0015] In this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). In this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When describing a range of dimensions, the phrase "between X and Y" refers to a range that includes X and Y. When describing the position of an element, the phrase "between X and Y" refers to a spatial area between element X and element Y. The terms "substantially," "near," "approximately," "close," and "about" generally mean within ±20%, for example, within ±5% or ±2%, of a target value based on the context of a particular value described herein or known in the art. Similarly, terms describing the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or other angles between elements, generally mean within ±10% of the exact orientation, for example, within ±5% or ±2%.

[0016] In this specification, the phrases “in one embodiment” or “in one embodiment” may refer to one or more identical or different embodiments, respectively. Furthermore, terms such as “comprising,” “having,” and “having” as used in reference to embodiments of this disclosure are synonymous. As used herein, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Furthermore, the terms “chip,” “chiplet,” “die,” and “IC die” may also be used interchangeably herein.

[0017] In this specification, certain elements may be referred to in the singular, but such elements may include multiple sub-elements. For example, “dielectric material” may include one or more dielectric materials, or “insulating material” may include one or more insulating materials. Terms such as “oxide,” “carbide,” and “nitride” refer to compounds containing oxygen, carbon, nitrogen, etc., respectively. The term “high dielectric constant dielectric” refers to a material having a dielectric constant higher than silicon oxide, and the term “low dielectric constant dielectric” refers to a material having a dielectric constant lower than silicon oxide. The term “insulating” and its variations (e.g., “insulating” or “insulator”) mean “electrically insulating” unless otherwise specified, and the term “conductive” and its variations (e.g., “conductive” or “conductor”) mean “electrically conductive.” With respect to optical signals and / or devices, components, and elements that operate with or use optical signals, the term “conductivity” may also mean “photoconductivity.” The term “insulating material” refers to a substantially nonconductive solid material (and / or a liquid material that solidifies after the processing described herein). These may include, but are not limited to, organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, alumina, or combinations thereof. These may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. These may be transparent or opaque without departing from the scope of this disclosure. Further examples of insulating materials include underfill, molded, or shaped materials used in packaging applications, such as materials used in organic interposers, package supports, and other components.

[0018] Figure 1 is a schematic side cross-sectional view of an example microelectronic assembly 100 on which a glass substrate having a TGV manufactured using the bottom-up plating technique described herein can be mounted, according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a substrate 107 containing a double-sided bridge die 114-1 in a cavity 119 of the substrate 107, the die 114-1 may be electrically coupled to a conductive path, e.g., a conductive trace 108A or a conductive via 108B, in a metal layer N-1 of the substrate 107 located below the bottom of the cavity 119. The substrate 107 includes a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, as shown, collectively referred to as "one or more layers of dielectric material 112") and a conductive material 108 disposed on one or more layers of dielectric material 112, providing conductive paths through the substrate 107 (e.g., conductive trace 108A and conductive via 108B), as well as conductive pads and contacts. The substrate 107 may include a first surface 120-1 and a second surface 120-2 opposite to it. The die 114-1 may be surrounded by the dielectric material 112 of the substrate 107. The die 114-1 may include a lower surface (e.g., the surface facing the first surface 120-1) having a first conductive contact 122, an opposite upper surface (e.g., the surface facing the second surface 120-2) having a second conductive contact 124, and through-silicon vias (TSVs) 125 connecting the first and second conductive contacts 122 and 124, respectively. In some embodiments, the pitch of the first conductive contacts 122 on the first die 114-1 may be between 25 microns (μm) and 250 microns. In this specification, the pitch is measured center-to-center (e.g., from the center of one conductive contact to the center of an adjacent conductive contact). In some embodiments, the pitch of the second conductive contact 124 on the first die 114-1 may be between 25 microns and 100 microns. Dies 114-2 and 114-3 may include a set of conductive contacts 122 on the underside of the die (e.g., the side facing the first surface 120-1). Die 114 may include other conductive paths (e.g., wiring and vias) and / or other circuits (not shown) coupled to each conductive contact (e.g., conductive contacts 122 and 124) on the surface of die 114.In this specification, “die,” “microelectronic component,” and similar terms may be used interchangeably. In this specification, “interconnection component,” “bridge die,” and similar terms may be used interchangeably. The bridge die 114-1 may be electrically coupled to dies 114-2 and 114-3 by a die-to-die (DTD) interconnect 130 on the second surface 120-2. In particular, the conductive contact 124 on the upper surface of die 114-1 may be coupled to the conductive contact 122 on the lower surface of dies 114-2 and 114-3 by a conductive via 108B that penetrates the second dielectric material layer 112B.

[0019] In this specification, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an electrical interface between different components (e.g., a portion of a conductive interconnect). A conductive contact may be embedded in the surface of a component, flush with it, or extending away from the surface of a component (e.g., columnar), or may take any suitable shape (e.g., a conductive pad or socket, or a portion of a conductive line or via). In a general sense, “interconnection” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides an electrical connection between two electrical components, facilitating the communication of electrical signals between them. An optical interconnection provides an optical connection between two optical components, facilitating the communication of optical signals between them. In this specification, the term “interconnection” includes both electrical and optical interconnections. The properties of interconnections described herein should be understood in reference to the signaling medium associated with them. Thus, in relation to electronic devices such as ICs that operate using electrical signals, the term “interconnection” refers to any element formed of a conductive material to provide an electrical connection to, or between, one or more elements related to the IC. In such cases, the term “interconnection” can refer to both conductive traces (also called “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also called “vias” or “metal vias”). In some cases, conductive traces and vias may be called “metal traces” and “metal vias,” respectively, to emphasize that these elements contain a conductive material such as metal. Similarly, when used in relation to devices that also operate using optical signals (e.g., photonic ICs (PICs)), the term “interconnection” can refer to any element formed of a photoconductive material to provide an optical connection to one or more elements related to the PIC. In such cases, the term “interconnection” can refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0020] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include dielectric materials such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimaging dielectrics, and / or benzocyclobutene polymers). In some embodiments, the insulating material of the die 114 may include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths within the die 114 may include conductive traces and / or conductive vias, and any conductive contacts within the die 114 may be connected in any suitable manner (e.g., by connecting multiple conductive contacts on the same or different surfaces of the die 114). Exemplary structures that may be included in the die 114 disclosed herein are described below with reference to IC device 1600. The conductive paths within the die 114 may be bounded by liners such as adhesive liners and / or barrier liners, as necessary. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., a wafer stack, die stack, or multilayer die stack).

[0021] In some embodiments, die 114 may include conductive paths for routing power, ground, and / or signals to and from other dies 114 included in the microelectronic assembly 100. For example, die 114-1 may include a TSV 125 containing conductive vias such as metal vias separated from the surrounding silicon or other semiconductor material by a barrier oxide, or other conductive paths that can transmit power, ground, and / or signals to and from the package substrate 102 and one or more dies 114 (e.g., dies 114-2 and / or 114-3 in the embodiment of Figure 1). In some embodiments, die 114-1 may not route power and / or ground to dies 114-2 and 114-3. Alternatively, dies 114-2 and 114-3 can be directly coupled to power lines and / or ground lines in the package substrate 102 by a substrate-to-package substrate (STPS) interconnect 150, conductive paths provided by conductive material 108 in the substrate 107, and a die-to-substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than dies 114-2 and 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes) such as PCI Express (Peripheral Component Interconnect). In some embodiments, die 114-1 may be a processing die, an RF chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryption device. In some embodiments, dies 114-2 and / or dies 114-3 may be processing dies, an RF chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryption device. In some embodiments, die 114 may be as described below with reference to die 1502 in Figure 13.

[0022] The dielectric material 112 of the substrate 107 may be formed in layers (for example, at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material such as an organic build-up film. In some embodiments, the dielectric material 112 may include, for example, a ceramic, an epoxy film containing filler particles, glass, an inorganic material, or a combination of organic and inorganic materials. In some embodiments, the conductive material 108 may include a metal (for example, copper). In some embodiments, the substrate 107 may include layers of dielectric material 112 / conductive material 108, where a line / trace / pad / contact (e.g., conductive trace 108A) of the conductive material 108 in one layer is electrically coupled to a line / trace / pad / contact (e.g., conductive trace 108A) of the conductive material 108 in an adjacent layer by a via (e.g., 108B) of the conductive material 108 that penetrates the dielectric material 112. The conductive trace 108A may be referred to herein as a “conductive line,” “conductive element,” “conductive pad,” or “conductive contact.” A substrate 107 containing such a layer may be formed, for example, using printed circuit board (PCB) manufacturing techniques.

[0023] Each individual layer of dielectric material 112 (e.g., a first dielectric material layer 112A) may contain a cavity 119, and the bridge die 114-1 may be at least partially nested within the cavity 119. The bridge die 114-1 may be surrounded (e.g., embedded) by the next individual layer of dielectric material 112 (e.g., a second dielectric material layer 112B). In some embodiments, the cavity 119 has a tapered shape that narrows toward the bottom surface of the cavity 119 (e.g., the surface facing the first surface 120-1 of the substrate 107). The cavity 119 may be indicated by a seam between dielectric material 112A and dielectric material 112B. When the bridge die 114-1 is partially nested within the cavity 119, as shown in Figure 1, the top surface of the bridge die 114-1 may extend above the top surface of dielectric material 112A. When the bridge die 114-1 is completely nested within the cavity 119 (not shown), the upper surface of the bridge die 114-1 may be planar with the upper surface of the dielectric material 112A, or it may be located below the upper surface of the dielectric material 112A.

[0024] The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to 1. In Figure 1, each layer is numbered in descending order from the second surface 120-2 (e.g., top surface) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). In particular, as shown in Figure 1, the substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layers include conductive contacts 121 on the second surface 120-2 of the substrate 107, and these contacts 121 are coupled by DTS interconnects 140 to conductive contacts 122 on the underside of dies 114-2, 114-3. The N-2 metal layer may include a conductive trace 108A having an upper surface (e.g., the surface facing the second surface 120-2 of the substrate 107), an opposite lower surface (e.g., the surface facing the first surface 120-1 of the substrate 107), and a side surface extending between the upper and lower surfaces of the conductive trace 108A. The substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the N metal layers, and a portion of the N-1 metal layer may include a metal ring 118 exposed around the lower part of the cavity 119. The metal ring 118 may be coplanar with the conductive trace 108A of the N-1 metal layer, or it may be close to the edge of the cavity 119, as shown in the figure.

[0025] The attached drawings show a specific number and arrangement of layers of dielectric material 112 / conductive material 108, but these specific numbers and arrangements are merely examples, and any desired number and arrangement of dielectric material 112 / conductive material 108 may be used. Furthermore, a specific number of layers (e.g., four layers) are shown on the substrate 107, but these layers may represent only a portion of the substrate 107, and further layers may be present (e.g., layers N-4, N-5, N-6, etc.).

[0026] As shown in Figure 1, the substrate 107 further comprises a glass substrate 110 having TGV 115, and a further layer 111 may be located beneath the glass substrate 110 and bonded to the package substrate 102 by interconnects 150. Any of the TGV 115 may be conductive vias manufactured using the bottom-up plating techniques described herein. In this specification, the term “glass substrate” refers to a layer (e.g., a glass layer) or structure (e.g., a part of a glass layer) of any glass material such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, boroflote glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the glass substrate 110 may be bulk glass or a solid mass / layer of glass, unlike materials that may contain glass particles, such as glass fiber reinforced polymer (e.g., a substrate / board composed of glass fibers and an epoxy binder). Such glass materials are typically amorphous and often transparent amorphous solids. In some embodiments, the glass substrate 110 may be an amorphous solid glass layer. In some embodiments, the glass substrate 110 may contain a material comprising silicon and oxygen, as well as one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass substrate 110 may contain, for example, any of the above materials, with a weight percentage of silicon of at least about 0.5%, for example, between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass substrate 110 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass substrate 110 may contain a material comprising at least 23% by weight of silicon and / or at least 26% by weight of oxygen, and in some further embodiments, the glass substrate 110 may further contain at least 5% by weight of aluminum.In some embodiments, the glass substrate 110 may contain any of the materials described above and may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass substrate 110 may be a glass layer that does not contain organic adhesives or organic materials. The glass substrate 110 may be distinguished from a PCB substrate “prepreg” or “RF4” core, for example, which typically contains glass fibers embedded in a resinous organic material such as epoxy. In such conventional cores / substrates containing glass fibers and epoxy, the diameter of the glass fibers is generally in the range of 5 to 200 microns. In contrast, the glass substrate 110 may be a glass layer with sides ranging from about 10 millimeters to about 250 millimeters (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some embodiments, the cross-section of the glass substrate 110 in the xz, yz, and / or xy planes of the exemplary coordinate system 105 shown in Figure 1 may be substantially rectangular (the axes shown in subsequent figures refer to the axes of the coordinate system 105). However, in some further embodiments, the glass substrate 110 may have rounded or beveled edges / sides / sidewalls. In some embodiments, in a top view of the glass substrate 110 (e.g., in the xy plane of the coordinate system 105), the glass substrate 110 may have a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, where the first length is perpendicular to the second length. The thickness of the glass substrate 110 (e.g., a dimension measured along the z axis of the coordinate system 105) may be in the range of about 50 microns to 1.4 mm. In some embodiments, the glass substrate 110 may be a glass core, and the thickness of the glass core is in the range of about 50 microns to 1.4 mm. In some embodiments, the glass substrate 110 may be a glass layer comprising a rectangular prism volume having possibly rounded or beveled edges / sides / sidewalls.In some such embodiments, the volume of the right-angle prism has a first side and a second side perpendicular to the first side, where the length of the first side is in the range of 10 mm to 250 mm and the length of the second side is in the range of 10 mm to 250 mm. In some embodiments, the glass substrate 110 may be the volume of the right-angle prism from which sections (e.g., vias) have been removed and which has been filled with another material (e.g., metal) (e.g., TGV115). In some embodiments, the glass substrate 110 may be a layer of glass having a thickness in the range of 50 microns to 1.4 mm, a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, where the first length is perpendicular to the second length.

[0027] In some embodiments, the substrate 107 including the glass substrate 110 and the die 114 together may be referred to as a “multilayer die subassembly 104”. The glass substrate 110 can provide mechanical stability to the multilayer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass substrate 110 can reduce warping and provide a more robust surface for mounting the multilayer die subassembly 104 to the package substrate 102 or other substrates (e.g., interposers or circuit boards). In some embodiments of the microelectronic assembly 100 shown in Figure 1, the glass substrate 110 may be referred to as the core or glass core of the microelectronic assembly 100.

[0028] In some embodiments, the dielectric material 112 of the substrate 107 and the glass substrate 110 together may be referred to as a “multilayer glass substrate”. In some such embodiments, the multilayer glass substrate may be a coreless substrate. In some such embodiments, the glass substrate 110 may be a glass layer having a thickness in the range of about 25 to 50 microns. In some embodiments, a further layer 111 may also be part of the multilayer glass substrate.

[0029] The TGV115 may be a via extending between the first and second surfaces of the glass substrate 110 (for example, between the bottom and top surfaces of the glass substrate 110), and the via may contain any suitable conductive material such as a metal such as copper, silver, nickel, gold, or aluminum, or any other metal or alloy. The opening of the TGV115 may be formed using any suitable process, including, for example, direct laser drilling or a laser-induced etching process (which may also be called "laser patterning" or "selective laser activation"). For any TGV115, the metallization of the via may be carried out using any of the bottom-up plating techniques described herein, for example, any of the methods shown in Figures 4 to 12. Thus, although not specifically shown in Figure 1 or Figure 2, any of the TGV115s shown in these figures may be mounted as described by the manufacturing methods shown in Figures 4 to 12. In some embodiments, the pitch of the TGV115 disclosed herein can be 50 to 500 microns, for example, measured from the center of one TGV115 to the center of an adjacent TGV115. The TGV115 may have any suitable size and shape. In some embodiments, the TGV115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, at least a portion of the TGV115 may have an hourglass shape, as shown, for example, in Figure 2. In some embodiments, at least a portion of the TGV115 may be tapered from one side of the glass substrate 110 to the other, for example, from the top surface of the glass substrate 110 to the bottom surface of the glass substrate 110.

[0030] A substrate 107 (e.g., an additional layer 111) may be coupled to a package substrate 102 by an STPS interconnect 150. In particular, the upper surface of the package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the lower surface of the substrate 107 may be electrically and mechanically coupled to the conductive contacts 146 on the upper surface of the package substrate 102 by the STPS interconnect 150. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) for routing power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be an organic dielectric material, a flame-retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric containing an inorganic filler, or a dielectric material such as a low-k dielectric and an ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). When the package substrate 102 is formed using a standard printed circuit board process, the package substrate 102 may contain FR-4, and the conductive paths within the package substrate 102 may be formed by patterned copper sheets separated by a build-up layer of FR-4. The conductive paths within the package substrate 102 may be separated by liners such as adhesive liners and / or barrier liners, as needed. In some embodiments, the package substrate 102 may be formed using lithography defined by the packaging process. In some embodiments, the package substrate 102 may be manufactured using a standard organic package manufacturing process, thereby allowing the package substrate 102 to take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spin-coating dielectric materials and forming conductive vias and lines by laser drilling and plating.In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique, such as redistribution layer technique. Any method known in the art for manufacturing the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0031] In some embodiments, the package substrate 102 may be a low-density medium, and the die 114 may be a high-density medium or have regions having a high-density medium. As used herein, the terms “low-density” and “high-density” are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) of the low-density medium are larger and / or have a larger pitch than the conductive paths of the high-density medium. In some embodiments, the high-density medium may be manufactured using an improved semi-additive process or semi-additive build-up process with advanced lithography (including small vertical interconnect features formed by an advanced laser process or lithography process), while the low-density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process including the removal of unwanted copper regions using etching chemistry and rough vertical interconnect features formed by a standard laser process). In other embodiments, the high-density medium may be manufactured using a semiconductor manufacturing process such as a single damascene process or a dual damascene process. In some embodiments, additional dies may be located on the top surface of dies 114-2, 114-3. In some embodiments, additional components may be located on the upper surfaces of dies 114-2, 114-3. Additional passive components such as surface-mount resistors, capacitors, and / or inductors may be located on the upper or lower surface of the package substrate 102, or embedded in the package substrate 102.

[0032] The microelectronic assembly 100 in Figure 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102, around the associated STPS interconnect 150. In some embodiments, the underfill material 127 may extend between the different dies of the top-level dies 114-2, 114-3 and the upper surface of the substrate 107 around the associated DTS interconnect 140, and between the bridge die 114-1 and the top-level dies 114-2, 114-3, around the DTD interconnect 130. The underfill material 127 may be an insulating material such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering the multilayer die subassembly 104 to the package substrate 102 when forming the STPS interconnect 150, and then polymerizes and seals the STPS interconnect 150. The underfill material 127 can be selected to have a CTE that can reduce or minimize the stress between the substrate 107 and the package substrate 102 resulting from non-uniform thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 can be an intermediate value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the die 114 and / or dielectric material 112 of the substrate 107.

[0033] The STPS interconnect 150 disclosed herein can take any suitable form. In some embodiments, the set of STPS interconnect 150 may include solder (e.g., solder bumps or balls that form the STPS interconnect 150 by thermal reflow), for example, as shown in Figure 1, the STPS interconnect 150 may include solder between conductive contacts 144 on the lower surface of the substrate 107 and conductive contacts 146 on the upper surface of the package substrate 102. In some embodiments, the set of STPS interconnect 150 may include an anisotropic conductive material such as an anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material.

[0034] The DTD interconnect 130 disclosed herein can take any suitable form. The DTD interconnect 130 may have a narrower pitch than the STPS interconnect 150 in a microelectronic assembly. In some embodiments, the dies 114 on both sides of the set of DTD interconnects 130 may be unpackaged dies, and / or the DTD interconnect 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnect 130 may have a pitch that is too narrow to be directly coupled to the package substrate 102 (e.g., too narrow to function as a DTS interconnect 140 or STPS interconnect 150). In some embodiments, the set of DTD interconnects 130 may include solder. In some embodiments, the set of DTD interconnects 130 may include an anisotropic conductive material such as any of the materials discussed above. In some embodiments, the DTD interconnect 130 may be used as a data transfer lane, while the STPS interconnect 150 may be used, among other things, for power lines and ground lines. In some embodiments, some or all of the DTD interconnects 130 within the microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the DTD interconnects 130 may be joined together (e.g., under high pressure and / or high temperature) without the use of intervening solder or anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) may include, for example, bond pads, solder bumps, conductive posts, or other suitable conductive contacts. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 within the microelectronic assembly 100 may be solder interconnects containing solder with a higher melting point than the solder included in some or all of the STPS interconnects 150.For example, if the DTD interconnect 130 and DTS interconnect 140 in the microelectronic assembly 100 are formed before the STPS interconnect 150 is formed, the solder-based DTD interconnect 130 and DTS interconnect 140 may use a higher temperature solder (e.g., with a melting point above 200°C), while the STPS interconnect 150 may use a lower temperature solder (e.g., with a melting point below 200°C). In some embodiments, the higher temperature solder may include tin, tin and gold, or tin, silver, and copper (e.g., 96.5% tin, 3% silver, 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth), or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium.

[0035] In the microelectronic assembly 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. The DTD interconnects 130 may have a smaller pitch than the STPS interconnects 150 because the materials of the different dies 114 on both sides of the DTD interconnects 130 are more similar than the materials between the substrates 107 on both sides of the DTS interconnects 140 and the top dies 114-2, 114-3, and between the substrates 107 on both sides of the STPS interconnects 150 and the package substrate 102. In particular, differences in the material composition of the substrates 107 and the dies 114 or package substrate 102 may result in different expansions and contractions due to the heat generated during operation (and the heat applied during various manufacturing processes). To mitigate damage (e.g., cracking, solder bridging, etc.) caused by expansion and contraction due to this difference, the DTS interconnect 140 and STPS interconnect 150 may be formed larger and further apart than the DTD interconnect 130. The DTD interconnect 130 may experience less thermal stress due to the greater similarity of the materials of the pair of dies 114 on either side of the DTD interconnect. In some embodiments, the pitch of the DTS interconnect 140 disclosed herein may be 25 to 250 microns. In some embodiments, the pitch of the STPS interconnect 150 disclosed herein may be 55 to 1000 microns, while the pitch of the DTD interconnect 130 disclosed herein may be 25 to 100 microns.

[0036] The microelectronic assembly 100 in Figure 1 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board by a second-level interconnect on the underside of the package substrate 102. The second-level interconnect may be any suitable second-level interconnect, including solder balls for ball grid array arrangement, pins for pin grid array arrangement, or lands for land grid array arrangement. The circuit board may be, for example, a motherboard, to which other components may be mounted. The circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board, as is known in the art. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, but instead couple the package substrate 102 to another IC package, interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, but instead to a circuit board such as a PCB.

[0037] Figure 1 shows a microelectronic assembly 100 having a substrate including a specific number of dies 114 and conductive paths provided by conductive material 108 bonded to other dies 114, but this number and arrangement is merely illustrative, and the microelectronic assembly 100 may include any desired number and arrangement of dies 114. In Figure 1, die 114-1 is shown as a double-sided die, and dies 114-2 and 114-3 are shown as single-sided dies, but dies 114-2 and 114-3 may also be double-sided dies, and die 114 may be a single-pitch die or a mixed-pitch die. In some embodiments, additional components may be placed on the top surface of die 114-2 and / or 114-3. In this context, a double-sided die refers to a die having connections on both sides. In some embodiments, a double-sided die may include through-TSVs for forming connections on both sides. The active surface of a double-sided die (the surface containing one or more active devices and most interconnections) may face either direction depending on design and electrical requirements.

[0038] Many of the elements of the microelectronic assembly 100 in Figure 1 are also included in other drawings of the accompanying drawings, and the discussion of these elements will not be repeated when discussing those drawings, as any of these elements can take any form disclosed herein. Furthermore, although Figure 1 shows various elements included in the microelectronic assembly 100, some of these elements may not be included in various embodiments. For example, in various embodiments, the additional layer 111, underfill material 127, and package substrate 102 may not be present in the microelectronic assembly 100. In some embodiments, individual microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP) containing multiple dies 114 having different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0039] Figure 2 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 on which a glass substrate having a TGV manufactured using a bottom-up plating technique as described herein may be mounted, according to some embodiments of the present disclosure. The configuration of the embodiments shown in the figure is the same as that of Figure 1, except for differences described later. Instead of including the glass substrate 110 as part of the substrate 107 as shown in Figure 1, the microelectronic assembly 100 of Figure 2 includes the glass substrate 110 alone, and one or more dies 114 may be coupled to the glass substrate 110. In Figure 2, the multilayer die subassembly 104 includes the glass substrate 110 and the plurality of dies 114, as described above. The multilayer die subassembly 104 may have a first surface 160-1 (e.g., bottom surface) and a second surface 160-2 (e.g., top surface) opposite to it. The glass substrate 110 can provide mechanical stability to the multilayer die subassembly 104 and / or the microelectronic assembly 100 in Figure 2, reduce warping, and provide a more robust surface for mounting the multilayer die subassembly 104 to the package substrate 102 or other substrates (e.g., interposer or circuit board).

[0040] The glass substrate 110 may include a cavity 129 having an opening facing the second surface 160-2. In some embodiments, further components, or a number of further components, may be fully or at least partially nested within the cavity 129. Figure 2 shows an embodiment in which the further component is a die 114-1, but in other embodiments, another further component may be fully or at least partially nested within the cavity 129 instead of, or in addition to, the die 114-1. In some embodiments, such components may be passive components such as capacitors or inductors. In some embodiments, such components may be active components such as logic circuits. In embodiments, when a further component, for example, a die 114-1, is fully nested within the cavity 129, the upper surface of the further component may be plane with or below the upper surface of the glass substrate 110. When a further component, for example, a die 114-1, is partially nested within the cavity 129, the upper surface of the further component may extend above the upper surface of the glass substrate 110. The cavity 129 may be at least partially filled with a dielectric material, such as the dielectric material 112A or 112B described above. Further components, such as the die 114-1, may be attached to the underside of the cavity 129 by a die attach film (DAF) 132. The DAF 132 may be any suitable material, including a non-conductive adhesive, a die attach film, a B-stage underfill, or an adhesive polymer film. The DAF 132 may have any suitable dimensions; for example, in some embodiments, the thickness (e.g., height or z-height) of the DAF 132 may be 5 to 10 microns.

[0041] Die 114-1 may be coupled to dies 114-2 and 114-3 located above die 114-1 via a DTD interconnect 130. The DTD interconnect 130 may be positioned between some of the conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some of the conductive contacts 124 at the top of die 114-1. Other conductive contacts 122 at the bottom of dies 114-2 and / or 114-3 may further couple one or more of dies 114-2 and 114-3 to the glass substrate 110 via a glass substrate-to-die (GCTD) interconnect 142. The GCTD interconnect 142 may be positioned between some of the conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some of the conductive contacts 128 at the top of the glass substrate 110. The GCTD interconnect 142 may be similar to the DTS interconnect 140 described above. In some embodiments, the underfill material 127 may extend between a plurality of dies 114 around the associated DTD interconnect 130 and / or GCTD interconnect 142. In some embodiments, dies 114-2 and / or dies 114-3 may be embedded in the insulating material 133. In some embodiments, the overall thickness (e.g., z-direction height) of the insulating material 133 may be between 200 microns and 800 microns (e.g., substantially equal to the thickness of dies 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 may form a plurality of layers (e.g., dielectric material formed in a plurality of layers, as known in the art), and one or more dies 114 may be embedded in the layers. In some embodiments, the insulating material 133 may be an organic dielectric material, a flame retardant grade 4 material (FR-4), BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or a dielectric material such as a low-k dielectric or an ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the insulating material 133 may be a molding material such as an organic polymer containing inorganic silica particles.

[0042] As shown in Figure 2, the glass substrate 110 may further include conductive contacts 126 at the bottom of the glass substrate 110, and the TGV 115 extends between the conductive contacts 126 at the bottom of the glass substrate 110 and the conductive contacts 128 at the top of the glass substrate 110, and can electrically couple them. The conductive contacts 126, 128 may be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146), and may include, for example, bond pads, solder bumps, conductive posts, or any other suitable conductive contacts. As shown in Figure 2, in some embodiments, at least a portion of the TGV 115 may have an hourglass shape. For example, at least a portion of the TGV115 has a first width on the first surface of the glass substrate 110 (e.g., the bottom surface of the glass substrate 110), a second width on the second surface of the glass substrate 110 (e.g., the top surface of the glass substrate 110), and a third width between the first and second surfaces of the glass substrate 110, the third width being smaller than the first and second widths.

[0043] Dies 114-2 and 114-3 may be electrically coupled to the package substrate 102 via TGV 115 and glass substrate-to-package substrate (GCTPS) interconnects 152, the GCTPS interconnects 152 may be power supply interconnects or high-speed signal interconnects. The GCTPS interconnects 152 may be similar to the STPS interconnects 150 described above. A set of conductive contacts 146 is provided on the upper surface of the package substrate 102, and a set of conductive contacts 126 is provided on the first surface 160-1 of the multilayer die subassembly 104, the GCTPS interconnects 152 are provided between the conductive contacts 146 and their corresponding conductive contacts 126, and the conductive contacts 146 may be coupled to their corresponding conductive contacts 126. In some embodiments, underfill material 127 may extend between the glass substrate 110 and the package substrate 102 around the relevant GCTPS interconnects 152.

[0044] A glass substrate 110 included in a microelectronic assembly 100, as described with reference to Figure 1 or Figure 2, or a glass substrate 110 included in another microelectronic assembly or device, may be subject to TGV stress. For example, Figure 3 shows a surface of a glass substrate 110 in which TGV stress may occur, according to some embodiments of the present disclosure. As shown in Figure 3, the glass substrate 110 may have a first surface 190-1 and a second surface 190-2 opposite to it, the second surface 190-2 may be the bottom and top surfaces, for example, when the glass substrate 110 is included in a microelectronic assembly 100 (in this case, the first surface 190-1 and the second surface 190-2 may together be called "surface 190"). The glass substrate 110 may also have a side surface 191, which is a surface of the glass substrate 110 and may also be called the edge or sidewall of the glass substrate 110, i.e., a surface extending between the first surface 190-1 and the second surface 190-2. As further shown in Figure 3, a TGV opening 192 extending between the first surface 190-1 and the second surface 190-2 may be formed in the glass substrate 110. The sidewall 194 may refer to one or more sidewalls of the TGV opening 192. When conductive material is deposited in the TGV opening 192, a mismatch in CTE between the glass material of the glass substrate 110 and the conductive material in the TGV opening 192 may cause TGV stress to be generated from the sidewall 194.

[0045] One or more techniques for TGV stress relief described herein can be applied to reduce TGV stress in the sidewall 194 before the glass substrate 110 is incorporated into the microelectronic assembly 100. Various techniques for TGV stress relief are based on creating conductive vias (e.g., TGV 115) in the glass substrate using bottom-up plating without using seed material in the sidewall 194. In particular, three manufacturing methods according to three such techniques are shown. The first manufacturing method is a bottom-up plating method using SE technique, shown in Figures 4A-4F and 5A-5C. The second manufacturing method is a bottom-up plating method using mSAP technique, shown in Figures 6A-6K and 7A-7D. The third manufacturing method is a bottom-up plating method using a fluid cavity filling material, shown in Figures 8A-8H and 9. For each of these techniques, a first set of drawings (e.g., Figures 4A–4F, 6A–6K, and 8A–8H) shows schematic side cross-sectional views of exemplary glass substrates at various stages in the manufacture of the TGV, while a second set of drawings (e.g., Figures 5A–5C, 7A–7D, and 9A–9B) shows schematic side cross-sectional views of exemplary glass substrates representing features that demonstrate the use of the corresponding techniques in the first set of drawings. Furthermore, any of these three techniques can be further modified by providing a liner on the sidewall of the TGV that functions as a buffer layer between the glass substrate and the conductive material within the TGV, and the modified first, second, and third manufacturing methods are shown in Figures 10A–10H, 11A–11H, and 12A–12J, respectively.

[0046] Moving on to the first manufacturing method, Figures 4A to 4F are schematic side cross-sectional views of an exemplary microelectronic assembly including a glass substrate 110 at various stages in the manufacturing of a TGV formed by bottom-up plating using SE, according to several embodiments of the present disclosure.

[0047] As shown in the microelectronic assembly 400A of Figure 4A, the first manufacturing method may begin by providing the glass substrate 110 with one or more TGV openings 420 extending between the first surface 190-1 and the second surface 190-2 of the glass substrate 110. In some embodiments, a cavity 421 may be provided in the glass substrate 110. The above description with respect to the cavity 129 also applies to the cavity 421. Although four TGV openings 420 and one cavity 421 are shown in this figure, in other embodiments, the microelectronic assemblies 400A to 400F may include any number of one or more TGV openings 420 and any number of zero or more cavities 421. The TGV openings 420 and cavities 421 can be formed in the glass substrate 110 using any suitable process such as direct laser drilling or laser-induced etching. The illustrations in Figure 4A and subsequent figures of the bottom-up plating method described herein show the microelectronic assembly in a side section view, for example, a yz plan view similar to that in Figures 1 to 3. In the upper right corner of Figure 4A, a reduced inset 402 of a top-down view (i.e., xy plan view) of the microelectronic assembly 400A is further shown, illustrating an example of how the cavity 421 is positioned within the glass substrate 110, and a vertical dotted line indicates a plane showing the cross-sections in Figure 4A and subsequent figures of the bottom-up plating method described herein.

[0048] As further shown in Figure 4A, the microelectronic assembly 400A may further include a metal coil 410 mounted on a first surface 190-1 of the glass substrate 110, and optionally an adhesive 412 between the metal coil 410 and the first surface 190-1. The metal coil 410 can assist in electroplating in subsequent processes; for example, the metal coil 410 can generate a uniform electric field and distribute the current uniformly within the plating solution. The material of the metal coil 410 can be selected based on factors such as electrical requirements (e.g., highly conductive materials such as copper are preferred when efficiency is the primary consideration), the type of electroplating solution (e.g., acidic solutions such as copper sulfate baths may require more corrosion-resistant materials such as titanium or platinum-coated titanium), cost considerations, and process stability. In various embodiments, the metal coil 410 may include conductive materials such as metals or metal alloys such as copper, titanium, platinum, nickel, gold, palladium, or silver. In some embodiments, the metal coil 410 may be attached to the first surface 190-1 using adhesive 412. In some embodiments, the adhesive 412 is a conductive adhesive (e.g., silver epoxy resin or epoxy resin containing other conductive particles) that can provide both mechanical adhesion and conductivity. In such embodiments, the adhesive 412 may remain at the bottom of the TGV opening 420 when electroplating is initiated, provided that the material of the adhesive 412 is suitable for the electroplating conditions (e.g., suitable for the electroplating bath and resistant to chemical erosion). In other embodiments, the adhesive 412 may be a non-conductive adhesive (e.g., non-conductive epoxy) or an adhesive that is not suitable for the electroplating conditions, in which case the adhesive 412 may be removed from the bottom of the TGV opening 420 when electroplating is initiated.

[0049] As shown in the microelectronic assembly 400B of Figure 4B, in embodiments where the adhesive 412 is a non-conductive adhesive or an adhesive unsuitable for electroplating conditions, the first manufacturing method can proceed to a process of removing the adhesive 412 from the bottom of the TGV opening 420 to expose the metal coil 410 located at the bottom of the TGV opening 420. In some embodiments, the adhesive 412 can be removed from the bottom of the TGV opening 420 using an etching process such as dry etching, for example, reactive ion etching (RIE). Figure 4B shows the adhesive 412 being removed from the bottom of the cavity 421 as well, although in other embodiments, the adhesive 412 may remain at the bottom of the cavity 421 (for example, as shown in Figure 6B).

[0050] The following figures continue the description of the embodiment shown in Figure 4B. However, in embodiments in which the adhesive 412 includes a conductive adhesive suitable for electroplating conditions, the process in Figure 4B may be omitted, and the adhesive 412 may remain at the bottom of the TGV opening 420. Furthermore, the following figures continue the description of embodiments in which the adhesive 412 is used, but in other embodiments, the metal coil 410 may be attached to the first surface 190-1 without using adhesive (i.e., the adhesive 412 may be omitted in all the techniques described herein).

[0051] As shown in the microelectronic assembly 400C of Figure 4C, the first manufacturing method can then proceed to the implementation of bottom-up plating. In this plating, the conductive filler material 426 is deposited in the TGV opening 420, starting from the bottom of the TGV opening 420 and gradually filling the TGV opening 420 to the top, and possibly beyond. Figure 4C shows how the TGV opening 420 and cavity 421 can be filled with the conductive filler material 426 as a result of the implementation of bottom-up plating. The conductive filler material 426 may include any suitable conductive material, such as a metal, a metal alloy, or a combination of metals (e.g., a low-resistance metal such as copper). In some embodiments, the conductive filler material 426 may include one or more metals such as copper, ruthenium, nickel, gold, palladium, platinum, or silver.

[0052] As shown in the microelectronic assembly 400D in Figure 4D, the first manufacturing method may further include performing SE of the conductive material of the microelectronic assembly 400C as defined by the features of the mask material 414. The mask material 414 may include any suitable material that allows etching of the conductive filler 426 from the top and bottom of the glass substrate 110 and etching of the metal coil 410 from the bottom of the glass substrate 110, except for the portions of the conductive filler 426 and metal coil 410 covered by the features of the mask material 414. For example, as shown in Figure 4D, a positive or negative photoresist may be used to form the features of the mask material 414. The features of the mask material 414 of the microelectronic assembly 400D can be formed using any suitable patterning technique such as photolithography or electron beam patterning.

[0053] As shown in Figure 4D, after performing SE, the TGV opening 420 may remain substantially filled with conductive filler material 426, although some of the conductive filler material 426 may remain in the cavity 421. In this case, the first manufacturing method may further include a subsequent SE process, as shown in the microelectronic assembly 400E of Figure 4E, in which the conductive material in the TGV opening 420 is still protected by the features of the mask material 414 (which may differ from the features used in the process of Figure 4E), but the conductive filler material 426 is removed from the cavity 421. Performing SE in two stages, as shown in Figures 4D and 4E, can be advantageous in that it allows for careful control of the critical dimensions of etching.

[0054] The first manufacturing method can be completed by removing the mask material 414, as shown in the microelectronic assembly 400F of Figure 4F. Any suitable process, such as ashing or photoresist stripping, may be used to remove the mask material 414. In the microelectronic assembly 400F, the TGV opening 420, which is at least partially filled with conductive filler material 426, forms conductive vias in the shape of TGV 415. TGV 415 is one example of any of the TGV 115 described herein. In the microelectronic assembly 400F, the portion of the metal coil 410 located below the TGV opening 420 and below the first surface 190-1 forms conductive contacts 436 on the lower surface of the glass substrate 110, while the portion of the conductive filler material 426 located above the TGV opening 420 and above the second surface 190-2 forms conductive contacts 438 on the upper surface of the glass substrate 110. Thus, TGV415 extends between the conductive contact 436 at the bottom of the glass substrate 110 and the conductive contact 438 at the top of the glass substrate 110, and these can be electrically connected. This is similar to how TGV115 extends between the conductive contact 126 at the bottom of the glass substrate 110 and the conductive contact 128 at the top of the glass substrate 110, and these can be electrically connected.

[0055] Figures 4A to 4F show an ideal structure produced by the first manufacturing method, for example, a linear shape with flat walls and right-angled corners for ease of illustration. Figures 5A to 5C show examples of detectable features in an actual structure produced using the first manufacturing method of Figures 4A to 4F, showing that the features of Figures 4A to 4F may not necessarily appear "ideal" when the structure is examined using, for example, an SEM or TEM image. Figures 5A to 5C are schematic side cross-sectional views of a portion of an exemplary glass substrate, illustrating features of the use of the manufacturing method of Figures 4A to 4F according to some embodiments of the present disclosure. In particular, Figure 5A shows portion 452 indicated by a dashed contour in Figure 4F, Figure 5B shows portion 454 indicated by a dashed contour in Figure 4F, and Figure 5C shows portion 456 indicated by a dashed contour in Figure 4F.

[0056] Figure 5A shows that in some embodiments, one or more voids 502 may exist between the conductive filler material 426 and one or more sidewalls 194 of TGV415. Figure 5A shows a plurality of such voids along the sidewall 194. In some embodiments, the voids 502 may be air gaps. In some embodiments, the width of the voids 502 (e.g., dimensions measured horizontally in the plane of the drawing) may be about 20 nanometers (nm) to about 200 nanometers, for example, about 40 nanometers to about 140 nanometers.

[0057] Figure 5B shows that in some embodiments, the conductive contact 438 may have a tapered shape, with its width (measured horizontally in the plane of the drawing) tapering / decreasing away from the glass substrate 110. Thus, as shown in Figure 5B, the conductive contact 438 may be narrower at the top (i.e., the side furthest from the glass substrate 110) and wider at the bottom (i.e., the side closest to the glass substrate 110). In some embodiments, the angle between the sidewall of the conductive contact 438 and the first surface 190-1 of the glass substrate 110 may be less than about 90°, for example less than 85°, for example between about 60° and about 90°, or between about 60° and about 85°. The angle may depend on factors such as the chemicals used for etching, the thickness of the conductive contact 438, and the tools used for manufacturing.

[0058] Similar to Figure 5B, Figure 5C shows that in some embodiments, the conductive contact 436 may have a tapered shape, and its width (measured horizontally in the plane of the drawing) may also taper / decrease away from the glass substrate 110. Thus, as shown in Figure 5C, the conductive contact 436 may be wider at the top (i.e., the side closest to the glass substrate 110) and narrower at the bottom (i.e., the side furthest from the glass substrate 110). In some embodiments, the angle between the sidewall of the conductive contact 436 and the second surface 190-2 of the glass substrate 110 may be similar to the angle between the sidewall of the conductive contact 438 and the first surface 190-1 of the glass substrate 110, and these two angles may be the same, but do not necessarily have to be the same.

[0059] In some embodiments, the sidewall profiles of the conductive contacts 436, 438 formed by the SE process shown in Figures 4A to 4F may be defined by the etching chemistry used to form the conductive contacts 436, 438 in this manufacturing method. For example, as a result of the SE process, in some embodiments, recesses may be formed on one or more sidewalls of the conductive contact 438, as shown in Figure 5B, and / or recesses may be formed on the sidewall of the conductive contact 436, as shown in Figure 5C. Furthermore, the absence of seed material (e.g., seed material 424 used in the second manufacturing method shown in Figures 6A to 6K, etc., as described herein) on the sidewall 194 of TGV 415, the first surface 190-1, or the second surface 190-2 of the glass substrate 110 is also a feature indicating that the first manufacturing method of Figures 4A to 4F is being used.

[0060] Moving on to the second manufacturing method, Figures 6A to 6K are schematic side cross-sectional views of an exemplary microelectronic assembly including a glass substrate 110 at various stages in the manufacturing of a TGV formed by bottom-up plating using mSAP, according to several embodiments of the present disclosure.

[0061] As shown in the microelectronic assembly 600A of Figure 6A, a second manufacturing method may begin with a glass substrate 110 having one or more TGV openings 420 extending between a first surface 190-1 and a second surface 190-2 of the glass substrate 110, a metal coil 410 attached to the first surface 190-1 of the glass substrate 110, and optionally a cavity 421 and adhesive 412 between the metal coil 410 and the first surface 190-1. The description of the microelectronic assembly 400A of Figure 4A is also applicable to the microelectronic assembly 600A of Figure 6A and will not be repeated for brevity.

[0062] In embodiments where the adhesive 412 is a non-conductive adhesive or an adhesive unsuitable for electroplating conditions, as shown in the microelectronic assembly 600B of Figure 6B, the second manufacturing method can proceed by removing the adhesive 412 from the bottom of the TGV opening 420, exposing the metal coil 410 at the bottom of the TGV opening 420. The description of the microelectronic assembly 400B in Figure 4B is also applicable to the microelectronic assembly 600B in Figure 6B and will not be repeated for brevity. Figure 6B shows that the adhesive 412 remains at the bottom of the cavity 421, but in other embodiments, the adhesive 412 may also be removed from the bottom of the cavity 421 (for example, as shown in Figure 4A).

[0063] As shown in the microelectronic assembly 600C in Figure 6C, the second manufacturing method may further include providing the features of the mask material 414 on the second surface 190-2 of the glass substrate 110. The mask material 414 may include any suitable material that allows bottom-up plating to be applied to openings in the glass substrate 110 that are not covered by the features of the mask material 414 (for example, the TGV opening 420 may remain uncovered, as shown in Figure 6C). For example, a positive or negative photoresist may be used to form the features of the mask material 414, as shown in Figure 6C. The features of the mask material 414 of the microelectronic assembly 600C may be formed using any suitable patterning technique such as photolithography or electron beam patterning.

[0064] As shown in the microelectronic assembly 600D of Figure 6D, the second manufacturing method can then proceed to a bottom-up plating process. In this process, conductive filler material 426 is deposited within the opening of the mask material 414. This process begins from the bottom of the TGV opening 420 and gradually fills the TGV opening 420 upwards, and possibly beyond. Figure 6D shows that as a result of bottom-up plating, the TGV opening 420 (however, the cavity 421 is not filled because it is covered by the mask material 414) can be filled with conductive filler material 426.

[0065] The second manufacturing method may further include removing the mask material 414 from the second surface 190-2, as shown in the microelectronic assembly 600E in Figure 6E. Any suitable process, such as ashing or photoresist stripping, may be used to remove the mask material 414.

[0066] Next, as shown in the microelectronic assembly 600F of Figure 6F, the second manufacturing method can proceed to the process of removing the metal coil 410 and adhesive 412 from the first surface 190-1 of the glass substrate 110. Any suitable process, such as any suitable planarization process, may be used to remove the metal coil 410 and adhesive 412. As a result, the conductive filler material 426 in the TGV opening 420 may be exposed on the first surface 190-1, as shown in Figure 6F.

[0067] Next, a layer of seed material 424 can be deposited on the first surface 190-1. The seed material 424 may include any suitable conductive material, such as a metal, a metal alloy, or a combination of metals (e.g., a low-resistance metal such as copper), which can be deposited as a thin layer on a substantially non-conductive surface, such as the first surface 190-1 of the glass substrate 110. The seed material 424 provides a conductive surface for uniform and controlled deposition of the conductive material in a subsequent process of forming conductive contacts on the first surface 190-1. For example, the seed material 424 may function as a base or foundation for electroplating a thicker metal layer onto the first surface 190-1 of a conductive material 427, for example. In some embodiments, the seed material 424 may include one or more metals such as copper, ruthenium, nickel, gold, palladium, platinum, or silver. In various embodiments, the thickness of the seed material 424 layer may be between approximately 5 nanometers and 20 microns, for example between approximately 10 nanometers and 15 microns, or between approximately 10 nanometers and 1 micron, measured, for example, in a direction perpendicular to the first surface 190-1. In various embodiments, the seed material 424 may be deposited using any suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the seed material 424 may be deposited as a conformal layer. In some embodiments, the seed material 424 may include two or more different conductive material layers deposited sequentially on the first surface 190-1. For example, the seed material 424 may include a first material layer deposited on the first surface 190-1 and a second material layer deposited on the first material. The first material may be a conductive material having good adhesive properties with respect to adhesion between the first material and the first surface 190-1, and optionally between the first material and the second material. The second material may be a conductive material that can protect the first material from oxidation before and / or during the deposition of the conductive material in a subsequent process. In some embodiments, (for example, as shown in Figure 7D) there may be an additional material between the seed material 424 and the first surface 190-1 of the glass substrate 110, for example, to improve the adhesion of the seed material 424 to the glass substrate 110.For example, further materials may include titanium, which can act as an adhesion promoter between the seed material 424 and the glass substrate 110. However, if the seed material 424 is a metal with relatively good adhesion to glass, there is no need to use an adhesion promoter between them, and the seed material 424 can come into contact with the glass substrate 110 (e.g., in direct physical contact). In such embodiments, the other side of the seed material 424 can come into contact with the conductive material 427 of the conductive contact 446 (e.g., in direct physical contact).

[0068] In various embodiments, the material compositions of the seed material 424 and the conductive filler material 426 may be the same or different. However, even if the material compositions of the seed material 424 and the conductive filler material 426 are the same, the particle structures of the seed material 424 and the conductive filler material 426 may be different, resulting in the presence of grain boundaries between the seed material 424 and the conductive filler material 426. For example, in some embodiments, the average particle size of the seed material 424 may differ from (e.g., smaller than) the average particle size of the conductive material 426. In some embodiments, the average particle orientation of the seed material 424 may differ from the average particle orientation of the conductive material 426. For example, the seed material 424 may contain particles that are much smaller and more uniformly aligned than those of the conductive filler material 426.

[0069] As shown in the microelectronic assembly 600H in Figure 6H, the second manufacturing method may further include providing the features of the mask material 414 on the seed material 424 on the first surface 190-1. The mask material 414 may include any suitable material that can form conductive contacts on the first surface 190-1 in areas not covered by the features of the mask material 414. For example, as shown in Figure 6H, the features of the mask material 414 can be formed on the first surface 190-1 using a positive or negative photoresist. The features of the mask material 414 of the microelectronic assembly 600H can be formed using any suitable patterning technique such as photolithography or electron beam patterning.

[0070] As shown in the microelectronic assembly 600I of Figure 6I, the second manufacturing method can proceed to a process of depositing the conductive material 427 in openings on the first surface 190-1 that are not covered by the mask material 414, starting from the side of the first surface 190-1. The conductive filler material 427 can be deposited using any suitable deposition technique such as electroplating, ALD, CVD, or PVD. In some embodiments, any two or more material compositions of at least some of the conductive material 427, conductive filler material 426, and seed material 424 may be substantially the same. For example, any two or more material compositions of at least some of the conductive material 427, conductive filler material 426, and seed material 424 may be copper, or may contain copper. In other embodiments, any one or more material compositions of at least some of the conductive material 427, conductive filler material 426, and seed material 424 may be different from any one or more material compositions of at least some of the conductive material 427, conductive filler material 426, and seed material 424.

[0071] As shown in the microelectronic assembly 600J of Figure 6J, the second manufacturing method may further include removing the mask material 414 from the first surface 190-1. Any suitable process such as ashing or photoresist stripping may be used to remove the mask material 414 from the first surface 190-1.

[0072] As shown in the microelectronic assembly 600K of Figure 6K, the second manufacturing method can be completed by removing the portion of the seed material 424 that is exposed by removing the mask material 414 from the first surface 190-1, where the first surface 190-1 is not covered by the conductive material 427. For this purpose, any suitable etching process such as dry etching or wet etching may be used. In the microelectronic assembly 600K, the TGV opening 420, which is at least partially filled with the conductive filler material 426, forms a conductive via in the form of a TGV 445. The TGV 445 is an example of any of the TGV 115 described herein. In the microelectronic assembly 600K, the portions of the conductive material 427 and seed material 424 on the first surface 190-1 form a conductive contact 446 on the underside of the glass substrate 110, while the portions of the conductive filler material 426 located above the TGV opening 420 and above the second surface 190-2 form a conductive contact 448 on the upper side of the glass substrate 110. Thus, TGV445 extends between the conductive contact 446 at the bottom of the glass substrate 110 and the conductive contact 448 at the top of the glass substrate 110, enabling them to be electrically coupled. This is similar to how TGV115 extends between the conductive contact 126 at the bottom of the glass substrate 110 and the conductive contact 128 at the top of the glass substrate 110, enabling them to be electrically coupled.

[0073] Figures 6A to 6K show an ideal structure produced by the second manufacturing method, for example, a linear shape with flat walls and right-angled corners for ease of illustration. Figures 7A to 7D show examples of detectable features in an actual structure produced using the second manufacturing method of Figures 6A to 6K, illustrating that the features of Figures 6A to 6K may not appear so "ideal" when either the structure is examined using, for example, an SEM image or a TEM image. Figures 7A to 7D are schematic side cross-sectional views of exemplary portions of glass substrates, illustrating features of the use of the manufacturing method of Figures 6A to 6K according to some embodiments of the present disclosure. In particular, Figure 7A shows portion 462 indicated by a dashed contour in Figure 6K, Figure 7B shows portion 464 indicated by a dashed contour in Figure 6K, Figure 7C shows portion 466 indicated by a dashed contour in Figure 6K, and Figure 7D shows portion 468 indicated by a dashed contour in Figure 6K.

[0074] Figure 7A shows that in some embodiments, one or more voids 702 may exist between the conductive filler material 426 and one or more sidewalls 194 of TGV445. Figure 7A shows several such voids along the sidewall 194. The description of voids 502 also applies to voids 702, so for brevity, it will not be repeated.

[0075] Figure 7B shows that in some embodiments, the taper of the conductive contact 448 may be much smaller than the taper of the conductive contact 438 in Figure 5B, and that when a taper is present, the width of the conductive contact 448 may be wider in the direction away from the glass substrate 110. Thus, as shown in Figure 7B, the conductive contact 448 may be wider at the top (the side furthest from the glass substrate 110) and narrower at the bottom (the side closest to the glass substrate 110). However, in other embodiments, the direction of the taper may be opposite to the direction shown in Figure 7B (i.e., similar to the direction shown in Figure 5B, but with a smaller taper). In some embodiments, the angle between the sidewall of the conductive contact 448 and the first surface 190-1 of the glass substrate 110 may be between approximately 85° and approximately 95°.

[0076] Similar to Figure 7B, Figure 7C shows that in some embodiments, the taper of the conductive contact 446 may be much smaller than the taper of the conductive contact 436 in Figure 5C, and where a taper is present, the width of the conductive contact 446 may widen in the direction away from the glass substrate 110. Thus, as shown in Figure 7C, the conductive contact 446 may be narrower at the top (the side closest to the glass substrate 110) and wider at the bottom (the side furthest from the glass substrate 110). However, in other embodiments, the direction of the taper may be opposite to the direction shown in Figure 7C (i.e., similar to the direction shown in Figure 5C, but with a smaller taper). In some embodiments, the angle between the sidewall of the conductive contact 446 and the second surface 190-2 of the glass substrate 110 may be the same as the angle between the sidewall of the conductive contact 448 and the first surface 190-1 of the glass substrate 110, and these two angles may be the same, but do not need to be the same.

[0077] In some embodiments, the sidewall profiles of the conductive contacts 446 and 448 formed by the mSAP process shown in Figures 6A to 6K may be determined by factors such as photoresist swelling, whether positive or negative photoresist is used, and which brand of photoresist is used to form the conductive contacts 446 and 448. Furthermore, the presence of seed material 424 on the first surface 190-1 of the glass substrate 110, but the absence of seed material 424 on the second surface 190-2 and the sidewall 194 of the TGV 445 (for example, the absence of seed material 424 between the conductive contact 448 and the TGV 445) may also be a characteristic of the method shown in Figures 6A to 6K. For example, as shown in Figure 7B, the conductive contact 448 is in contact (e.g., in direct physical contact) with a portion of the TGV 445 on the second surface 190-2 of the glass substrate 110 (i.e., there is no seed material 424 between the conductive contact 448 and the TGV 445 on the second surface 190-2 of the glass substrate 110). On the other hand, as shown in Figure 7C, the seed material 424 may be present between a portion of the TGV 445 on the first surface 190-1 of the glass substrate 110 and the conductive contact 446.

[0078] Furthermore, Figures 7B and 7C show exemplary footer undercuts 449 that may be present on the sidewalls of the portions of the conductive contacts 446 and 448 closest to the glass substrate 110. In some embodiments, the width of such footer undercuts 449 (e.g., measured horizontally in the plane of the drawing) may be between approximately 500 nanometers and 800 nanometers, for example between approximately 580 nanometers and 750 nanometers. The presence of footer undercuts 449 may also be a feature indicating the use of the mSAP process shown in Figures 6A to 6K.

[0079] The portion 468 shown in Figure 7D illustrates an example in which an additional material 470 exists between the seed material 424 and the first surface 190-1 of the glass substrate 110. For example, the additional material 470 may first be deposited on the first surface 190-1, and then the seed material 424 may be deposited on the additional material 470. The additional material 470 may be a conductive material having good adhesion to glass, and can adhere to the first surface 190-1 of the glass substrate 110, and possibly also to the seed material 424. In some embodiments, the seed material 424 may be a conductive material that can protect the additional material 470 from oxidation before and / or during the deposition of the conductive material 426 in a subsequent process. In some embodiments, the additional material 470 may contain titanium, while the seed material 424 may contain copper. In some embodiments, the additional material 470 may further exist between the seed material 424 and the conductive filler material 426 of TGV 445.

[0080] Moving on to the third manufacturing method, Figures 8A to 8H are schematic side cross-sectional views of exemplary microelectronic assemblies including a glass substrate 110 at various stages in the manufacturing of a TGV formed by bottom-up plating with a fluid cavity-filling material, according to several embodiments of the present disclosure.

[0081] As shown in the microelectronic assembly 800A in Figure 8A, the third manufacturing method may begin by providing a glass substrate 110 with one or more TGV openings 420 and a cavity 421 extending between the first surface 190-1 and the second surface 190-2 of the glass substrate 110, with a metal coil 410 attached to the first surface 190-1 of the glass substrate 110, and sometimes an adhesive 412 being used between the metal coil 410 and the first surface 190-1. The description of the microelectronic assembly 400A in Figure 4A is also applicable to the microelectronic assembly 800A in Figure 8A and will not be repeated for brevity.

[0082] In embodiments where the adhesive 412 is a non-conductive adhesive or an adhesive unsuitable for electroplating conditions, as shown in the microelectronic assembly 800B of Figure 8B, the third manufacturing method can proceed by removing the adhesive 412 from the bottom of the TGV opening 420 to expose the metal coil 410 located at the bottom of the TGV opening 420. The description of the microelectronic assembly 400B in Figure 4B is also applicable to the microelectronic assembly 800B in Figure 8B and will not be repeated for brevity. Figure 8B shows that the adhesive 412 remains at the bottom of the cavity 421, but in other embodiments, the adhesive 412 may also be removed from the bottom of the cavity 421 (for example, as shown in Figure 4A).

[0083] As shown in the microelectronic assembly 800C in Figure 8C, the third manufacturing method may further include providing the features of the mask 434 on the second surface 190-2 of the glass substrate 110, covering the TGV opening 420 while leaving the cavity 421 open. In some embodiments, as shown in Figure 8C, the features of the mask 434 may be formed using a positive or negative photoresist, as well as the mask material 414. In other embodiments, the mask 434 may be a metal mask. In some embodiments, the features of the mask 434 of the microelectronic assembly 800C can be formed using any suitable patterning technique, such as photolithography or electron beam patterning.

[0084] As shown in the microelectronic assembly 800D of Figure 8D, the third manufacturing method can then proceed to a process of depositing the fluid cavity filler material 430 into all openings not covered by the mask 434. Thus, as shown in Figure 8D, the fluid cavity filler material 430 can be deposited to seal the cavity 421. Figure 8D also shows how the fluid cavity filler material 430 over the cavity 421 extends slightly beyond the second surface 190-2 of the glass substrate 110. In various embodiments, the fluid cavity filler material 430 may include any dielectric material having sufficient fluidity to fill the cavity 421. In some embodiments, the fluid cavity filler material 430 may include an oxide material or epoxy material having high fluidity. The fluid cavity filler material 430 is different from ABF, which also includes epoxy material. In particular, ABF includes a combination of epoxy material, glass filler particles, and a curing agent material. Glass-filled particles help the ABF maintain a desired coefficient of thermal expansion (CTE) (e.g., a CTE close to that of the glass substrate 110) and electrical performance characteristics (e.g., low loss). In the ABF, the epoxy resin binds the fillers together. In contrast, the fluid cavity filler material 430 contains far fewer, or substantially no, glass-filled particles compared to the ABF, thus providing much higher fluidity than the ABF, allowing the fluid cavity filler material 430 to conform to and fill any gaps in the cavity 421. In some embodiments, filling the cavity 421 with the fluid cavity filler material 430 is performed by applying epoxy paste through a mask 434 using a squeegee, and in some cases, a back vacuum may be used to assist in ensuring that the fluid cavity filler material 430 flows through the cavity 421 without creating voids. In this case, the presence of the mask 434 prevents the TGV opening 420 from being filled with the fluid cavity filler material 430. After filling the cavity 421 with the fluid cavity filling material 430, the fluid cavity filling material 430 can be softened and mechanically hardened, allowing it to be polished or flattened later.

[0085] As shown in the microelectronic assembly 800E in Figure 8E, once the fluid cavity filling material 430 is deposited and the cavity 421 is sealed, the mask 434 can be removed to open the TGV opening 420.

[0086] Next, the third manufacturing method can proceed to the implementation of bottom-up plating, in which the conductive filler material 426 is deposited in the opening of the microelectronic assembly 800E. The opening of the microelectronic assembly is the TGV opening 420, as cavity 421 is blocked with fluid cavity filler material 430, and the bottom-up plating is started from the bottom of the TGV opening 420 and gradually fills the TGV opening 420 to the top, and possibly beyond. Figure 8F shows that as a result of bottom-up plating, the TGV opening 420 (cavity 421 is not filled because cavity 421 is blocked with fluid cavity filler material 430) can be filled with the conductive filler material 426.

[0087] As shown in the microelectronic assembly 800G of Figure 8G, the third manufacturing method can then proceed to the planarization process of the second surface 190-2 of the glass substrate 110. Since the fluid cavity filler material 430 is different from the ABF, the fluid cavity filler material 430 and the conductive filler material 426 can be planarized in a single process, which has the advantage of reducing the number of planarization steps in manufacturing. As a result, the fluid cavity filler material 430 and the conductive filler material 426 can be substantially coplanar on the second surface 190-2 of the glass substrate 110.

[0088] The microelectronic assembly 800H shown in Figure 8H demonstrates that in some embodiments of the third manufacturing method, the fluid cavity filler material 430 can be substantially removed from the cavity 421, although some of it may still remain on the sidewall and possibly at the bottom of the cavity 421. In some embodiments, the thickness of the remaining fluid cavity filler material 430 may be between about 10 microns and about 2 to 3 mm, for example between about 20 microns and about 500 microns, or between about 50 microns and about 100 microns, when measured substantially perpendicular to the sidewall of the cavity 421. In the microelectronic assembly 800H, the TGV opening 420, at least partially filled with the conductive filler material 426, forms conductive vias in the form of TGV 475. TGV 475 is one example of any of the TGV 115 described herein.

[0089] Although not specifically shown in this figure, the third manufacturing method may also include a process of removing the metal coil 410 and adhesive 412 from the first surface 190-1 of the glass substrate 110, as described with reference to the microelectronic assembly 600F in Figure 6F. In such an embodiment, the fluid cavity filler material 430 and the conductive filler material 426 may be substantially coplanar on the first surface 190-1 of the glass substrate 110.

[0090] Figures 8A to 8H show an ideal structure produced by the third manufacturing method, for example, a linear shape with flat walls and right-angled corners for ease of illustration. Figures 9A to 9B show some examples of features detectable in an actual structure produced using the third manufacturing method of Figures 8A to 8H. Figures 9A to 9B are schematic side cross-sectional views of a portion of an exemplary glass substrate, illustrating features of the use of the manufacturing method of Figures 8A to 8H according to some embodiments of the present disclosure. In particular, Figure 9A shows portion 482, which is identified by a dashed contour in Figure 8H, and Figure 9B shows portion 484, which is identified by a dashed contour in Figure 8H.

[0091] Figure 9A shows that in some embodiments, one or more voids 902 may exist between the conductive filler material 426 and one or more sidewalls 194 of TGV475. Figure 9A shows multiple such voids along the sidewall 194. The description of voids 502 is also applicable to voids 902 and will not be repeated for brevity.

[0092] Figure 9B shows that in some embodiments, the fluid cavity filling material 430 may have zero or more glass filling particles 486, but far fewer than the amount of ABF. In some embodiments, the total volume of glass filling particles 486 in a given volume of the fluid cavity filling material 430 may be less than about 70%, for example less than about 60%, less than about 50%, or less than about 15%.

[0093] As described above, all three techniques for bottom-up plating described herein can be further modified by including a liner in the sidewall of the TGV that functions as a buffer layer between the glass substrate and the conductive material in the TGV. Figures 10A to 10H show the first modified manufacturing method of Figures 4A to 4F, Figures 11A to 11M show the second modified manufacturing method of Figures 6A to 6K, and Figures 12A to 12J show the third modified manufacturing method of Figures 8A to 8H.

[0094] Moving on to the modified first manufacturing method, Figures 10A to 10H are schematic side cross-sectional views of an exemplary microelectronic assembly including a glass substrate 110 at various stages in the manufacturing of a TGV formed by bottom-up plating with SE in combination with the use of a liner 422, according to several embodiments of the present disclosure.

[0095] As shown in the microelectronic assembly 1000A in Figure 10A, the modified first manufacturing method can begin by providing the glass substrate 110 with one or more TGV openings 420 extending between the first surface 190-1 and the second surface 190-2 of the glass substrate 110, and optionally a cavity 421, as described with reference to Figure 4A. However, the microelectronic assembly 1000A may not yet include the metal coil 410 and adhesive 412 on the first surface 190-1 of the glass substrate 110.

[0096] As shown in the microelectronic assembly 1000B of Figure 10B, the modified first manufacturing method can then proceed to a process of depositing the liner 422 on at least the sidewalls 194 of the TGV opening 420 and the cavity 421. In various embodiments, the liner 422 can be deposited using any suitable deposition technique such as CVD, ALD, or PVD. In some embodiments, the liner 422 may be deposited not only as a liner within the TGV opening 420 and the cavity 421, but also on a first surface 190-1, a second surface 190-2, or both surfaces 190-1 and 190-2 (as shown in Figure 10B and subsequent drawings), depending on the deposition technique used to form the liner 422. In such embodiments, the liner 422 deposited on the first surface 190-1 and / or the second surface 190-2 may be materially continuous with the liner 422 on the sidewalls of the TGV opening 420 and the cavity 421. In some embodiments, a portion of the liner 422 on the sidewalls of the TGV opening 420 and cavity 421 may be in contact with (e.g., in direct physical contact with) the sidewalls of the TGV opening 420 and cavity 421 (e.g., in contact with the glass substrate 110 at the sidewalls of the TGV opening 420 and cavity 421). In some embodiments, the thickness of the liner 422 may be between about 200 nanometers and about 10 microns, for example between about 200 nanometers and about 5 microns, or between about 500 nanometers and about 1 micron. In some embodiments, the liner 422 may be deposited as a conformal layer, i.e., conform to the shape of the substrate surface on which the liner 422 is deposited.

[0097] The liner 422 may include any suitable material that separates the glass material of the sidewalls of the TGV opening 420 and cavity 421 of the glass substrate 110 from the conductive filler material 426 later deposited in the TGV opening 420 and cavity 421, smooths the glass surface of the sidewalls of the TGV opening 420 and cavity 421, and resists tensile stress caused by the shrinkage of the metal subsequently filled into the TGV opening 420 and cavity 421. In some embodiments, the liner 422 may include any suitable material that can serve as a stress-absorbing layer between the glass material of the sidewalls of the TGV opening 420 and cavity 421 of the glass substrate 110 and the conductive filler material 426 later deposited in the TGV opening 420 and cavity 421. In some embodiments, the liner 422 may include a material having a relatively low modulus of elasticity. For example, the Young's modulus is less than about 30 GPa, for example less than about 10 GPa, for example between about 1 GPa and 30 GPa, between about 3 GPa and 30 GPa, between about 1 GPa and 20 GPa, or between about 1 GPa and 15 GPa, where Young's modulus can be defined as the ratio of stress to strain in the material being deformed. In some embodiments, the liner 422 may include a material with a lower modulus than the glass substrate 110 and / or a material with a lower modulus than the conductive filler material 426 deposited in a later process.

[0098] In some embodiments, the liner 422 may contain a polymer material, such as an organic polymer such as polyimide (PI). In other embodiments, the liner 422 may contain an organic material other than a polymer, such as a monomer or oligomer. In some embodiments, the liner 422 may contain a homopolymer, which is a polymer consisting of repeating units of a single type of monomer. Organic liners with simple signal chemistry systems, such as homopolymers, are relatively easy to manufacture and readily adaptable as liners 422, and therefore may be particularly advantageous for use as liners 422. In some embodiments, the liner 422 may contain parylene N, parylene C, parylene D, or halogen-free polyparaxylylene (commonly also called "parylene"). In other embodiments, the liner 422 may contain a heteropolymer, which is a polymer consisting of repeating units of two or more types of monomers or oligomers. For example, the liner 422 may contain a heteropolymer such as polyester (PET), polyurethane (PU), polycarbonate (PC), polyvinyl chloride (PVC), or polybenzoxazole (PBO).

[0099] In other embodiments, the liner 422 may include materials other than polymers, such as inorganic nonpolymer materials. In some such embodiments, the liner 422 may include inorganic materials such as carbon-doped oxides (CDOs), low modulus SiOx, silicon oxycarbide (SiOC), or other low dielectric constant dielectrics.

[0100] In some embodiments, the CTE of the liner 422 is lower than that of the conductive filler material 426, for example, less than about 17 ppm / K, or less than about 15 ppm / K or 10 ppm / K. For example, the CTE of a material with a relatively high modulus of elasticity may be between about 3 ppm / K and about 12 ppm / K, or between about 3 ppm / K and about 10 ppm / K. By arranging a material with such a relatively low CTE as the material in contact with the side walls of the TGV opening 420 and the cavity 421, the CTE difference between the glass material of the glass substrate 110 and the metal of the conductive filler material 426 can be reduced, which may help reduce stress caused by the CTE mismatch.

[0101] In some embodiments, the liner 422 may include two or more layers of different materials (for example, the liner material may include two or more layers of materials having different material compositions). For example, the liner 422 may include a layer of material having a relatively high modulus and a layer of material having a relatively low modulus. Examples of materials having a relatively low modulus include any of the materials described above for the liner 422. Examples of materials having a relatively high modulus include a Young's modulus greater than about 30 GPa, for example greater than about 50 GPa, for example between about 85 GPa and about 190 GPa, or between about 100 GPa and about 600 GPa. Examples of materials having a relatively high modulus include a material having a modulus greater than the modulus of the glass substrate 110, and / or a material having a modulus greater than the modulus of the conductive filler material 426 deposited in a later process (e.g., Young's modulus). Examples of materials that can be used as materials with a relatively high modulus of elasticity in liner 422 include inorganic materials, for example, inorganic materials containing silicon and oxygen (e.g., silicon oxide), materials containing silicon and nitrogen (e.g., silicon nitride), materials containing silicon, oxygen, and nitrogen (e.g., silicon oxynitride), or materials containing one or more metals and oxygen (e.g., metal oxides such as aluminum oxide or hafnium oxide). Examples of other materials that can be used as materials with a relatively high modulus of elasticity include organosilicates such as methylsiloxane (dimethylsiloxane), phenylsiloxane (diphenylsiloxane), or polysilsesquioxane (e.g., materials whose chemical structure contains both organic (carbon-based) and inorganic (e.g., silicon-based) components).

[0102] In some embodiments, the liner 422 includes a layer of material having a relatively high modulus and a layer of material having a relatively low modulus, the material having the relatively high modulus may be closer to the glass substrate 110 than the material having the relatively low modulus. Using a material with a higher modulus in the portion of the liner 422 that is in direct contact with the glass can help reduce tensile stress caused, for example, by shrinkage of the metal subsequently filled into the TGV opening 420 and cavity 421. In some embodiments, the material having the relatively high modulus may have a relatively low CTE (e.g., a CTE between about 3 ppm / K and about 10-12 ppm / K), which can be particularly advantageous in reducing stress caused by mismatches in CTE. Furthermore, a material with a relatively high modulus positioned directly along the sidewalls of the TGV opening 420 and cavity 421 can help smooth the glass surface of the sidewalls. By placing a low modulus material in the liner 422 closer to the metal subsequently filled into the TGV than the high modulus material portion, it may be possible to reduce compressive stress caused, for example, by the expansion of the metal subsequently filled into the TGV. A material with a relatively low modulus can function as a stress absorption layer. In some embodiments, a material with a relatively low modulus may have a higher CTE than a material with a relatively high modulus (e.g., CTE greater than about 15 ppm / K), while in other embodiments, a material with a relatively low modulus may have a lower CTE. In some embodiments, an inorganic material such as silicon oxide or silicon nitride may be an example of a material with a relatively high modulus, while an organic material such as parylene may be an example of a material with a relatively low modulus. In some embodiments, the thickness of the material with a relatively low modulus or the material with a relatively high modulus may be between about 200 nanometers and about 10 microns, for example between about 200 nanometers and about 5 microns, or between about 500 nanometers and about 1 micron. In some embodiments, a material with a relatively low modulus can be deposited as a conformal layer on top of a material with a relatively high modulus.

[0103] After depositing the liner 422, the modified first manufacturing method can proceed to the process of the first manufacturing method described above, in which the liner 422 is applied to the glass substrate 110. Thus, Figure 10C shows a microelectronic assembly 1000C which is substantially the same as the microelectronic assembly 400A but includes the liner 422, Figure 10D shows a microelectronic assembly 1000D which is substantially the same as the microelectronic assembly 400B but includes the liner 422, and Figure 10E shows a microelectronic assembly 1000E which is substantially the same as the microelectronic assembly 400C but includes the liner 422 (in particular, the liner 422 is applied to the side wall 194 of the TGV opening 420). (In the case where the conductive filler material 426 is present between the glass substrate 110), Figure 10F shows a microelectronic assembly 1000F which is substantially the same as the microelectronic assembly 400D but includes a liner 422, Figure 10G shows a microelectronic assembly 1000G which is substantially the same as the microelectronic assembly 400E but includes a liner 422, and Figure 10H shows a microelectronic assembly 1000H which is substantially the same as the microelectronic assembly 400F but includes a liner 422.

[0104] Moving on to the modified second manufacturing method, Figures 11A–11M are schematic side cross-sectional views of an exemplary microelectronic assembly including a glass substrate 110 at various stages in the manufacturing of a TGV formed by bottom-up plating with mSAP in combination with the use of a liner 422, according to several embodiments of the present disclosure.

[0105] As shown in the microelectronic assembly 1100A in Figure 11A, the modified second manufacturing method can begin by providing the glass substrate 110 with one or more TGV openings 420 extending between the first surface 190-1 and the second surface 190-2 of the glass substrate 110, and optionally a cavity 421, as described with reference to Figure 6A, but the microelectronic assembly 1100A may not yet include the metal coil 410 and adhesive 412 on the first surface 190-1 of the glass substrate 110.

[0106] As shown in the microelectronic assembly 1100B of Figure 11B, the modified second manufacturing method can then proceed to the process of depositing the liner 422 on at least the sidewalls 194 of the TGV opening 420 and the cavity 421. The description of the liner 422 given with respect to the modified first manufacturing method is also applicable to the modified second manufacturing method and will not be repeated for brevity.

[0107] After depositing the liner 422, the modified second manufacturing method can proceed to the process of the second manufacturing method as described above, but with the liner 422 applied to the glass substrate 110. Thus, Figure 11C shows a microelectronic assembly 1100C that is substantially the same as microelectronic assembly 600A but includes the liner 422, Figure 11D shows a microelectronic assembly 1100D that is substantially the same as microelectronic assembly 600B but includes the liner 422, Figure 11E shows a microelectronic assembly 1100E that is substantially the same as microelectronic assembly 600C but includes the liner 422, Figure 11F shows a microelectronic assembly 1100F that is substantially the same as microelectronic assembly 600D but includes the liner 422, Figure 11G shows a microelectronic assembly 1100G that is substantially the same as microelectronic assembly 600E but includes the liner 422, and Figure 11H shows a microelectronic assembly 1100G that is substantially the same as microelectronic assembly 600F. Figure 11I shows a microelectronic assembly 1100I that is substantially the same as microelectronic assembly 600G but includes liner 422, Figure 11J shows a microelectronic assembly 1100J that is substantially the same as microelectronic assembly 600H but includes liner 422, Figure 11K shows a microelectronic assembly 1100K that is substantially the same as microelectronic assembly 600I but includes liner 422, Figure 11L shows a microelectronic assembly 1100L that is substantially the same as microelectronic assembly 600J but includes liner 422, and Figure 11M shows a microelectronic assembly 1100M that is substantially the same as microelectronic assembly 600K but includes liner 422.

[0108] Moving on to the modified third manufacturing method, Figures 12A–12J are schematic side cross-sectional views of an exemplary microelectronic assembly including a glass substrate 110 at various stages in the manufacture of a TGV formed by a combination of bottom-up plating with a fluid cavity filling material and the use of a liner 422, according to several embodiments of the present disclosure.

[0109] As shown in the microelectronic assembly 1200A in Figure 12A, the modified third manufacturing method can begin by providing the glass substrate 110 with one or more TGV openings 420 extending between the first surface 190-1 and the second surface 190-2 of the glass substrate 110, and optionally a cavity 421, as described with reference to Figure 8A, but the microelectronic assembly 1200A may not yet include the metal coil 410 and adhesive 412 on the first surface 190-1 of the glass substrate 110.

[0110] As shown in the microelectronic assembly 1200B of Figure 12B, the modified third manufacturing method can then proceed to the process of depositing the liner 422 on at least the sidewalls 194 of the TGV opening 420 and the cavity 421. The description of the liner 422 given with respect to the modified first manufacturing method is also applicable to the modified third manufacturing method and will not be repeated for brevity.

[0111] After depositing the liner 422, the modified third manufacturing method can proceed to the process of the third manufacturing method described above, but with the liner 422 applied to the glass substrate 110. Thus, Figure 12C shows a microelectronic assembly 1200C that is substantially the same as microelectronic assembly 800A but includes the liner 422, Figure 12D shows a microelectronic assembly 1200D that is substantially the same as microelectronic assembly 800B but includes the liner 422, Figure 12E shows a microelectronic assembly 1200E that is substantially the same as microelectronic assembly 800C but includes the liner 422, and Figure 12F shows a microelectronic assembly 1200F that is substantially the same as microelectronic assembly 800D but includes the liner 422. Figure 12G shows a microelectronic assembly 1200G that is substantially the same as microelectronic assembly 800E but includes liner 422; Figure 12H shows a microelectronic assembly 1200H that is substantially the same as microelectronic assembly 800F but includes liner 422; Figure 12I shows a microelectronic assembly 1200I that is substantially the same as microelectronic assembly 800G but includes liner 422; and Figure 12J shows a microelectronic assembly 1200J that is substantially the same as microelectronic assembly 800H but includes liner 422.

[0112] Any of the microelectronic assemblies described with reference to Figures 4 to 12 can be included in any of the microelectronic assemblies 100 described with reference to Figures 1 to 2. For example, any of the microelectronic assemblies described with reference to Figures 4 to 12 can be used in place of the glass substrate 110 in Figures 1 to 2.

[0113] Various embodiments of glass substrates having TGVs manufactured using the bottom-up plating technique described herein can, advantageously, be readily manufactured in parallel with conventional glass substrate manufacturing techniques. The various arrangements of the microelectronic assembly 100 and glass substrate 110 shown in Figures 1 to 12 do not represent an exhaustive set of microelectronic assemblies and glass substrates capable of mounting one or more TGVs manufactured using the bottom-up plating technique described herein, but merely illustrate some exemplary examples. In particular, the number and position of various elements shown in Figures 1 to 12 are purely illustrative, and in various other embodiments, different numbers of these elements may be arranged in different positions relative to each other, in accordance with the general architectural considerations described herein. For example, although not specifically shown in these figures, in some embodiments the microelectronic assembly 100 may include a redistribution layer (RDL) between any pair of layers shown in Figures 1 and 2, the RDL including multiple interconnection structures (e.g., conductive wires and conductive vias) to assist in routing signals and / or power between components. As another example, although not specifically shown in these figures, in some embodiments the package substrate 102 of the microelectronic assembly 100 may include one or more recesses. In such embodiments, the underside of the recess of the package substrate 102 may be provided by the solid material of the package substrate 102. The recess may be formed in the package substrate 102 by any suitable method (e.g., 3D printing, laser cutting, or drilling the recess into an existing package substrate). At least a portion of the substrate 107 or glass substrate 110 may be positioned on or at least partially within such a recess. As yet another example, any one feature of Figures 1 to 12 may be combined with any one feature of Figures 1 to 12. For example, in some embodiments, a portion of the glass substrate 110 may include one or more TGVs manufactured using the methods shown in Figures 4A to 4F, while the other portion of the glass substrate 110 may include one or more TGVs manufactured using the methods shown in Figures 6A to 6K and / or Figures 8A to 8H.

[0114] The microelectronic assemblies 100 and / or glass substrates 110 disclosed herein, in particular the glass substrates 110 having one or more TGVs manufactured using the bottom-up plating technique described herein, may be included in any suitable electronic component. Figures 13 to 16 show various examples of devices that may, or could, include any of the microelectronic assemblies 100 and / or glass substrates 110 disclosed herein.

[0115] Figure 13 is a top view of a wafer 1500 and a die 1502 that may be included in any of the microelectronic assemblies 100 described herein. For example, die 1502 may be any of the dies 114 described herein. The wafer 1500 is made of semiconductor material and may include one or more dies 1502 having IC structures formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product containing any suitable IC. After the manufacturing of the semiconductor product is complete, the wafer 1500 may undergo a singulation process to separate the dies 1502 from each other to provide individual “chips” of the semiconductor product. Die 1502 may include one or more transistors (e.g., part of transistor 1640 in Figure 14, described later), and / or support circuits for sending electrical signals to the transistors, as well as other IC components. In some embodiments, the wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive random access RAM (RRAM) devices, conductive bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or other suitable circuit elements. Multiple of these devices can be combined on a single die 1502. For example, a memory array formed by multiple memory devices can be formed on the same die 1502 as a processing unit (e.g., processing unit 1802 in Figure 16), or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0116] Figure 14 is a side cross-sectional view of an IC device 1600 that may be included in any of the microelectronic assemblies 100 described herein. For example, the IC device 1600 may be mounted on or inside any of the dies 114 described herein. The IC device 1600 may be formed on a substrate 1602 (e.g., wafer 1500 in Figure 13) and included in a die (e.g., die 1502 in Figure 13). The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system (or a combination thereof). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) structure. In some embodiments, the substrate 1602 may be formed using alternative materials, whether or not they are combined with silicon. Examples of alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Group III-V materials (i.e., Group III and V materials of the periodic table), Group II-VI materials (i.e., Group II and IV materials of the periodic table), or Group IV materials (i.e., Group IV materials of the periodic table) can also be used to form the substrate 1602. While some examples of materials that can form the substrate 1602 are given here, any material capable of functioning as the base for the IC device 1600 may be used. The substrate 1602 may be part of a fragmented die (e.g., die 1502 in Figure 13) or a wafer (e.g., wafer 1500 in Figure 13).

[0117] The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 that controls the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 that route electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional features not shown for clarity, such as device isolation regions and gate contacts. The transistor 1640 is not limited to the type and configuration shown in Figure 14 and may include various types and configurations of transistors, such as planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around gate transistors or all-around gate transistors such as nanoribbon transistors and nanowire transistors.

[0118] Each transistor 1640 may include a gate 1622 formed from at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-dielectric-constant dielectric materials. High-dielectric-constant (high-k) dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-dielectric-constant (high-k) dielectric materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k dielectric material, the gate dielectric may be annealed to improve the quality of the gate dielectric.

[0119] The gate electrode is formed on the gate dielectric and may include at least one P-type work function metal or an N-type work function metal, depending on whether the transistor 1640 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode consists of a stack of two or more metal layers, one or more of which are work function metal layers, and at least one of which is a filler metal layer. Further metal layers, such as barrier layers, may be included for other purposes. In the case of a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and metals described below for NMOS transistors (e.g., for adjusting the work function). In the case of NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and the metals mentioned above for PMOS transistors (e.g., for adjusting the work function).

[0120] In some embodiments, when viewed as a cross-section along the source-channel-drain direction of transistor 1640, the gate electrode may consist of a U-shaped structure including a lower portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one metal layer forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0121] In some embodiments, a pair of sidewall spacers may be formed on the opposite side of the gate stack so as to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on the opposite side of the gate stack.

[0122] The S / D region 1620 can be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D region 1620 may be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, the S / D region 1620 can be formed by ion implanting a dopant such as boron, aluminum, antimony, phosphorus, or arsenic into the substrate 1602. After the ion implantation process, an annealing process can be performed to activate the dopant and diffuse it further into the substrate 1602. In the latter process, the substrate 1602 can first be etched to form a recess at the location of the S / D region 1620. Then, an epitaxial deposition process can be performed to fill the recess with the material used to manufacture the S / D region 1620. In some embodiments, the S / D region 1620 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, dopants such as boron, arsenic, or phosphorus can be doped in situ into the epitaxially deposited silicon alloy. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials such as germanium, III-V materials, or alloys. In further embodiments, one or more metal layers and / or metal alloy layers may be used to form the S / D region 1620.

[0123] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and from the device on the device layer 1604 (e.g., transistor 1640) via one or more interconnection layers (shown as interconnection layers 1606, 1608, and 1610 in Figure 14) located on the device layer 1604. For example, conductive features of the device layer 1604 (e.g., gate 1622 and S / D contact 1624) can be electrically coupled to the interconnection structure 1628 of interconnection layers 1606, 1608, and 1610. One or more interconnection layers 1606, 1608, and 1610 can form a metallization stack (also called an "ILD stack") 1619 of the IC device 1600.

[0124] The interconnect structure 1628 is located within the interconnect layers 1606-1610 and can route electrical signals according to various designs (in particular, the arrangement is not limited to the specific configuration of the interconnect structure 1628 shown in Figure 14). Figure 14 shows a specific number of interconnect layers 1606, 1608, and 1610, but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those shown.

[0125] In some embodiments, the interconnection structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as metal. Lines 1628a may be arranged to route electrical signals in a plane substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, lines 1628a may route electrical signals in the in-plane and out-of-plane direction as viewed from the viewpoint of Figure 14. Vias 1628b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnection layers 1606, 1608, and 1610 together.

[0126] As shown in Figure 14, interconnection layers 1606, 1608, and 1610 may include dielectric material 1626 disposed between interconnection structures 1628. In some embodiments, the dielectric material 1626 disposed between interconnection structures 1628 in different layers of interconnection layers 1606, 1608, and 1610 may have different compositions. In other embodiments, the composition of the dielectric material 1626 between different interconnection layers 1606, 1608, and 1610 may be the same.

[0127] A first interconnection layer 1606 can be formed on the device layer 1604. In some embodiments, the first interconnection layer 1606 may include lines 1628a and / or vias 1628b, as shown in the figure. Lines 1628a of the first interconnection layer 1606 can be coupled to contacts of the device layer 1604 (e.g., S / D contacts 1624).

[0128] A second interconnection layer 1608 can be formed on top of the first interconnection layer 1606. In some embodiments, the second interconnection layer 1608 may include vias 1628b for connecting lines 1628a of the second interconnection layer 1608 to lines 1628a of the first interconnection layer 1606. For clarity, lines 1628a and vias 1628b are structurally separated by lines within each interconnection layer (e.g., within the second interconnection layer 1608), but in some embodiments, lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0129] A third interconnection layer 1610 (and additional interconnection layers as needed) can be formed continuously on the second interconnection layer 1608 according to the same techniques and configurations as described in relation to the second interconnection layer 1608 or the first interconnection layer 1606. In some embodiments, interconnection layers that are "higher up" (i.e., further away from the device layer 1604) in the metallization stack 1619 of the IC device 1600 may be thicker.

[0130] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606, 1608, and 1610. In Figure 14, the conductive contacts 1636 are shown as being in the form of bond pads. The conductive contacts 1636 may be electrically connected to the interconnect structure 1628 and configured to route electrical signals from transistor 1640 to other external devices. For example, by forming solder joints on one or more conductive contacts 1636, the chip containing the IC device 1600 can be mechanically and / or electrically coupled to other components (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for routing electrical signals from interconnect layers 1606, 1608, and 1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0131] Figure 15 is a side cross-sectional view of an IC device assembly 1700 including a glass substrate having one or more TGVs manufactured using a bottom-up plating technique according to any embodiment disclosed herein. The IC device assembly 1700 includes a plurality of components arranged on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components arranged on a first surface 1740 of the circuit board 1702 and a second surface 1742 on the opposite side of the circuit board 1702. Generally, components may be arranged on one or both of surfaces 1740 and 1742. Any IC package discussed below with reference to the IC device assembly 1700 can take the form of any embodiment of the microelectronic assembly 100 discussed above, and may include, for example, one or more microelectronic assemblies 100 discussed with reference to Figures 1 and 2, and / or may include one or more glass substrates discussed with reference to Figures 3 to 10.

[0132] In some embodiments, the circuit board 1702 may be a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed with a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a substrate other than a PCB.

[0133] The IC device assembly 1700 shown in Figure 15 includes a package-on-interposer structure 1736 bonded to the first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 can electrically and mechanically bond the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 15), male and female sockets, adhesive, underfill material, and / or other suitable electrical and / or mechanical bonding structures.

[0134] The package-on-interposer structure 1736 may include an IC package 1720 coupled to the package interposer 1704 by a coupling component 1718. The coupling component 1718 can take any form suitable for the application, such as the form discussed above with respect to the coupling component 1716. Figure 15 shows a single IC package 1720, but multiple IC packages can be coupled to the package interposer 1704, and furthermore, additional interposers can be coupled to the package interposer 1704. The package interposer 1704 can provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be, for example, a die (die 1502 in Figure 5), an IC device (e.g., any of the IC devices described herein, or any combination of such IC devices), or other suitable components, or may include them. Generally, the package interposer 1704 can spread connections to a wider pitch or rewire connections to other connections. For example, the package interposer 1704 can couple an IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of a coupling component 1716 for coupling to a circuit board 1702. In the embodiment shown in Figure 15, the IC package 1720 and the circuit board 1702 are mounted on opposite sides of the package interposer 1704. In other embodiments, the IC package 1720 and the circuit board 1702 may be mounted on the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected via the package interposer 1704.

[0135] In some embodiments, the package interposer 1704 may be formed as a glass substrate containing one or more TGVs manufactured using the bottom-up plating technique described herein, for example, as any embodiment of the glass substrate 110 described herein. In some embodiments, the package interposer 1704 may be formed as a PCB. In some embodiments, the package interposer 1704 may be formed from a polymer material such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin containing inorganic fillers, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed from an alternative rigid or flexible material, which may include the same materials as above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. In any of these embodiments, the package interposer 1704 may include a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. The package interposer 1704 may include metal lines 1710 and vias 1708 (including, but not limited to, conductive vias 1706). If the package interposer 1704 is a glass substrate (e.g., the glass substrate 110 described herein), then the conductive via 1706 may be a TGV 115 described herein (e.g., a conductive via manufactured using the bottom-up plating technique described herein). The package interposer 1704 may further include embedded devices 1714 which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, memory devices, etc. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may be formed on the package interposer 1704. The package-on-interposer structure 1736 can take any form of package-on-interposer structure known in the art.

[0136] The IC device assembly 1700 may include an IC package 1724 coupled to the first surface 1740 of a circuit board 1702 by a coupling component 1722. The coupling component 1722 can take the form of any embodiment discussed above with respect to the coupling component 1716, and the IC package 1724 can take the form of any embodiment discussed above with respect to the IC package 1720.

[0137] The IC device assembly 1700 shown in Figure 15 includes a package-on-package structure 1734 coupled to the second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732 coupled together by a coupling component 1730, thereby positioning IC package 1726 between the circuit board 1702 and IC package 1732. The coupling components 1728 and 1730 can take the form of any embodiment of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 can take the form of any embodiment of the IC package 1720 discussed above. The package-on-package structure 1734 can be configured according to any package-on-package structure known in the art.

[0138] Figure 16 is a block diagram showing an exemplary communication device 1800, which may include one or more microelectronic assemblies 100 and / or one or more glass substrates 110, according to any embodiment disclosed herein. Examples of the communication device 1800 include a handheld communication device or a laptop communication device. Any suitable components of the communication device 1800 may include one or more of the microelectronic assemblies 100, IC packages 1720, 1724, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. In particular, any suitable components of the communication device 1800 may include one or more glass substrates 110 as described herein, for example, as part of the microelectronic assembly 100 as described herein. Figure 16 shows some components included in the communication device 1800, but one or more of these components may be omitted or duplicated depending on the application. In some embodiments, some or all of the components included in the communication device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0139] Furthermore, in various embodiments, the communication device 1800 may not include one or more components shown in Figure 16, but may include interface circuits for coupling with one or more components. For example, the communication device 1800 may not include the display device 1806, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1806 can be coupled. In another example, the communication device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1824 or the audio output device 1808 can be coupled.

[0140] The communication device 1800 may include a processing unit 1802 (e.g., one or more processing units). In this specification, the terms “processing unit” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processing unit 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing units. The communication device 1800 may include a memory 1804, which itself may include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, the memory 1804 may include memory that shares a die with the processing unit 1802. This memory can be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0141] In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured to manage wireless communication for data transfer to and from the communication device 1800. The term “wireless” and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation over a non-solid medium. This term does not mean that the device in question is wire-free, although in some embodiments it may be wire-free. The communication module 1812 may be any of the microelectronic assemblies 100 disclosed herein, or may include them.

[0142] The 1812 communication module can implement any of a number of wireless standards or protocols, including, but not limited to, IEEE standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and the LTE (Long-Term Evolution) project (including its amendments, updates, and / or revisions, e.g., the Advanced LTE project, the Ultra-Mobile Broadband (UMB) project (also known as "3GPP2")). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks. This is a Worldwide certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. It is an acronym for Interoperability for Microwave Access. The communication module 1812 supports GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), and UMTS (Universal Mobile Telecommunications System), HSPA (High-Speed It can operate according to Packet Access, E-HSPA (Evolved HSPA), or LTE networks. The communication module 1812 supports EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial The communication module 1812 can operate according to Radio Access Network (Radio Access Network) or E-UTRAN (Evolved UTRAN). Multiple Access), DECT(Digital Enhanced Cordless) The communication module 1812 can operate in accordance with Telecommunications, EV-DO (Evolution-Data Optimized), and their derivative standards, as well as other radio protocols designated as 3G, 4G, 5G, and later standards. In other embodiments, the communication module 1812 can operate in accordance with other radio protocols. The communication device 1800 may include an antenna 1822 for facilitating wireless communication and / or receiving other wireless communications (such as AM or FM radio broadcasts). The antenna 1822 may include one or more microelectronic assemblies 100 and / or one or more glass substrates 110 as described herein, for example, as part of the microelectronic assembly 100 as described herein.

[0143] In some embodiments, the communication module 1812 may manage wired communications such as electrical, optical, or other suitable communication protocols (e.g., Ethernet). As described above, the communication module 1812 may include multiple communication modules. For example, the first communication module 1812 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication module 1812 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, or EV-DO. In some embodiments, the first communication module 1812 may be dedicated to wireless communications, and the second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may support millimeter-wave communications.

[0144] The communication device 1800 may include a battery / power supply circuit 1814. The battery / power supply circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for connecting components of the communication device 1800 to an energy source separate from the communication device 1800 (e.g., an AC line power supply).

[0145] The communication device 1800 may include a display device 1806 (or the corresponding interface circuit discussed above). The display device 1806 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0146] The communication device 1800 may include an audio output device 1808 (or the corresponding interface circuit discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headset, or earphone.

[0147] The communication device 1800 may include an audio input device 1824 (or the corresponding interface circuit discussed above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a MIDI Digital Interface (MIDI) output).

[0148] The communication device 1800 may include a GPS device 1818 (or the corresponding interface circuit discussed above). The GPS device 1818 can communicate with a satellite-based system and receive the position of the communication device 1800, as is known in the art.

[0149] The communication device 1800 may include other output devices 1810 (or corresponding interface circuits discussed above). Examples of other output devices 1810 include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0150] The communication device 1800 may include other input devices 1820 (or the corresponding interface circuits discussed above). Examples of other input devices 1820 include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, QR (Quick Response) code readers, any sensors, or radio frequency identification (RFID) readers.

[0151] The communication device 1800 can have any desired form factor, such as a handheld or mobile communication device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device for processing data.

[0152] The following paragraphs illustrate examples of various embodiments disclosed herein.

[0153] Example 1 provides a microelectronic assembly comprising: a glass substrate having a first face and a second face opposite the first face (e.g., a glass core or glass layer, e.g., a glass layer containing a volume substantially of a right-angle prism, possibly having rounded or beveled edges); a TGV in the glass substrate extending between the first and second faces and containing a conductive material; a first conductive contact to the TGV on the first face of the glass substrate; and a second conductive contact to the TGV on the second face of the glass substrate; wherein a seed material is present between the first conductive contact and a portion of the TGV on the first face of the glass substrate, and the second conductive contact is in contact with a portion of the TGV on the second face of the glass substrate (e.g., in direct physical contact) (i.e., no seed material is present between the TGV and the conductive contact on the second face of the glass substrate).

[0154] Example 2 provides the microelectronic assembly described in Example 1, further comprising a void between the conductive material and a portion of the sidewall of the TGV.

[0155] Example 3 provides the microelectronic assembly described in Example 2, wherein the void width is between approximately 20 nanometers (nm) and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0156] Example 4 provides the microelectronic assembly described in Example 2 or 3, wherein the void is one of several voids between the conductive material and different portions of the sidewall of the TGV.

[0157] Example 5 provides a microelectronic assembly according to any one of the above examples, further comprising a liner material between the conductive material and the glass substrate in the TGV.

[0158] Example 6 provides the microelectronic assembly described in Example 5, wherein the liner material is in contact (e.g., in direct physical contact) with the side wall of the TGV.

[0159] Example 7 provides the microelectronic assembly described in Example 6, further including a void between the conductive material and the liner material in a portion of the sidewall of the TGV.

[0160] Example 8 provides the microelectronic assembly described in Example 7, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0161] Example 9 provides the microelectronic assembly described in Example 7 or 8, wherein the void is one of several voids between the conductive material and the liner material in different parts of the sidewall of the TGV.

[0162] Example 10 provides a microelectronic assembly described in any one of Examples 5 to 9, wherein the thickness of the liner material is between approximately 200 nanometers and approximately 10 microns, for example, between approximately 200 nanometers and approximately 5 microns, or between approximately 500 nanometers and approximately 1 micron.

[0163] Example 11 provides a microelectronic assembly described in any one of Examples 5 to 10, wherein the elastic modulus (e.g., Young's modulus) of the liner material is less than about 30 gigapascals (GPa), for example, between about 1 GPa and 30 GPa, or between about 1 GPa and 20 GPa, or between about 1 GPa and 15 GPa.

[0164] Example 12 provides a microelectronic assembly described in any one of Examples 5 to 11, wherein the coefficient of thermal expansion (CTE) of the liner material is smaller than that of the conductive material.

[0165] Example 13 provides a microelectronic assembly described in any one of Examples 5 to 12, wherein the liner material is a polymer material.

[0166] Example 14 provides a microelectronic assembly described in any one of Examples 5 to 13, wherein the liner material is homopolymer-containing / homopolymer.

[0167] Example 15 provides a microelectronic assembly described in any one of Examples 5 to 14, wherein the liner material is polyparaxylylene / polyparaxylylene.

[0168] Example 16 provides a microelectronic assembly described in any one of Examples 5 to 13, wherein the liner material is a heteropolymer.

[0169] Example 17 provides a microelectronic assembly described in any one of Examples 5-13 or 16, wherein the liner material comprises / is at least one of polyester (PET), polyurethane (PU), polycarbonate (PC), polyvinyl chloride (PVC), or polybenzoxazole (PBO).

[0170] Example 18 provides a microelectronic assembly described in any one of Examples 5 to 12, wherein the liner material is a nonpolymer material.

[0171] Example 19 provides a microelectronic assembly described in any one of Examples 5-12 or 18, wherein the liner material includes / is an inorganic nonpolymer material.

[0172] Example 20 provides a microelectronic assembly described in any one of Examples 5 to 19, wherein the liner material comprises two or more layers of material having different material compositions.

[0173] Example 21 provides a microelectronic assembly described in any one of the above examples, wherein the particle structure of the seed material differs from the particle structure of the conductive material.

[0174] Example 22 provides a microelectronic assembly according to any one of the above examples, wherein the average particle size of the seed material is different from the average particle size of the conductive material.

[0175] Example 23 provides a microelectronic assembly according to any one of the above examples, wherein the average particle size of the seed material is smaller than the average particle size of the conductive material.

[0176] Example 24 provides a microelectronic assembly described in any one of the above examples, wherein the average grain orientation of the seed material differs from that of the conductive material.

[0177] Example 25 provides a microelectronic assembly according to any one of the above examples, further comprising a grain boundary between the seed material and the conductive material.

[0178] Example 26 provides a microelectronic assembly according to any one of the above examples, wherein there is no seed material between the second conductive contact and the TGV portion on the second surface of the glass substrate.

[0179] Example 27 provides a microelectronic assembly described in any one of Examples 1 to 26, further comprising additional material between the seed material and the first surface of the glass substrate.

[0180] Example 28 provides the microelectronic assembly described in Example 27, further comprising titanium as a material.

[0181] Example 29 provides the microelectronic assembly described in Example 27 or 28, wherein further materials are present between the seed material and the conductive material.

[0182] Example 30 provides a microelectronic assembly according to any one of Examples 1 to 29, wherein the seed material has a first surface and a second surface opposite to the first surface, the first surface of the seed material is in contact (e.g., in direct physical contact) with a first conductive contact, and the second surface of the seed material is in contact (e.g., in direct physical contact) with a portion of the TGV on the first surface of the glass substrate.

[0183] Example 31 provides a microelectronic assembly comprising: a glass substrate having a first surface and a second surface opposite the first surface; a TGV within the glass substrate extending between the first surface and the second surface and comprising a conductive material; a first conductive contact to the TGV on the first surface of the glass substrate; and a second conductive contact to the TGV on the second surface of the glass substrate, wherein the material composition of the first conductive contact is different from the material composition of the conductive material, and the material composition of the second conductive contact is substantially the same as that of the conductive material.

[0184] Example 32 provides the microelectronic assembly described in Example 31, further comprising a void between the conductive material and a portion of the sidewall of the TGV.

[0185] Example 33 provides the microelectronic assembly described in Example 32, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0186] Example 34 provides the microelectronic assembly described in Example 32 or 33, wherein the void is one of several voids between the conductive material and different portions of the sidewall of the TGV.

[0187] Example 35 provides a microelectronic assembly described in any one of Examples 31 to 34, further comprising a liner material between the conductive material and the glass substrate in the TGV.

[0188] Example 36 provides the microelectronic assembly described in Example 35, in which the liner material is in contact (e.g., in direct physical contact) with the side wall of the TGV.

[0189] Example 37 provides the microelectronic assembly described in Example 36, further including a void between the conductive material and the liner material in a portion of the sidewall of the TGV.

[0190] Example 38 provides the microelectronic assembly described in Example 37, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0191] Example 39 provides the microelectronic assembly described in Example 37 or 38, wherein the void is one of several voids between the conductive material and the liner material in different parts of the sidewall of the TGV.

[0192] Example 40 provides a microelectronic assembly described in any one of Examples 35 to 39, wherein the thickness of the liner material is between approximately 200 nanometers and approximately 10 microns, for example, between approximately 200 nanometers and approximately 5 microns, or between approximately 500 nanometers and approximately 1 micron.

[0193] Example 41 provides a microelectronic assembly described in any one of Examples 35 to 40, wherein the elastic modulus (e.g., Young's modulus) of the liner material is less than about 30 gigapascals (GPa), for example, between about 1 GPa and 30 GPa, or between about 1 GPa and 20 GPa, or between about 1 GPa and 15 GPa.

[0194] Example 42 provides a microelectronic assembly described in any one of Examples 35-41, wherein the coefficient of thermal expansion (CTE) of the liner material is smaller than that of the conductive material.

[0195] Example 43 provides a microelectronic assembly described in any one of Examples 35-42, wherein the liner material includes / is a polymer material.

[0196] Example 44 provides a microelectronic assembly described in any one of Examples 35-43, wherein the liner material is homopolymer-containing / homopolymer.

[0197] Example 45 provides a microelectronic assembly described in any one of Examples 35 to 44, wherein the liner material is polyparaxylylene / polyparaxylylene.

[0198] Example 46 provides a microelectronic assembly described in any one of Examples 35-43, wherein the liner material is a heteropolymer.

[0199] Example 47 provides a microelectronic assembly described in any one of Examples 35-43 or 46, wherein the liner material comprises / is at least one of polyester (PET), polyurethane (PU), polycarbonate (PC), polyvinyl chloride (PVC), or polybenzoxazole (PBO).

[0200] Example 48 provides a microelectronic assembly described in any one of Examples 35 to 42, wherein the liner material is a nonpolymer material.

[0201] Example 49 provides a microelectronic assembly described in any one of Examples 35-42 or 48, wherein the liner material includes / is an inorganic nonpolymer material.

[0202] Example 50 provides a microelectronic assembly described in any one of Examples 35 to 49, wherein the liner material comprises two or more layers of material having different material compositions.

[0203] Example 51 provides a microelectronic assembly described in any one of Examples 31 to 50, wherein further material is attached to the first surface of the glass substrate, and the further material is not present between the first conductive contact and the conductive material.

[0204] Example 52 provides the microelectronic assembly described in Example 51, wherein some of the additional materials are present between the first conductive contact and the first surface of the glass substrate.

[0205] Example 53 provides a microelectronic assembly described in any one of Examples 31 to 53, wherein there is no seed material on the first surface of the glass substrate, the second surface of the glass substrate, and the sidewalls of the TGV.

[0206] Example 54 provides a microelectronic assembly described in any one of Examples 31 to 53, wherein the angle between the sidewall of the first conductive contact and the first surface of the glass substrate is less than approximately 85°.

[0207] Example 55 provides a microelectronic assembly described in any one of Examples 31 to 54, wherein the angle between the sidewall of the second conductive contact and the second surface of the glass substrate is less than approximately 85°.

[0208] Example 56 provides a microelectronic assembly described in any one of Examples 31 to 55, wherein there are no grain boundaries between the second conductive contact and the conductive material.

[0209] Example 57 provides a microelectronic assembly described in any one of Examples 31 to 56, wherein the width of the first conductive contact is tapered away from the first surface of the glass substrate.

[0210] Example 58 provides a microelectronic assembly described in any one of Examples 31 to 57, wherein the width of the second conductive contact is tapered away from the first surface of the glass substrate.

[0211] Example 59 provides a microelectronic assembly described in any one of Examples 31 to 58, wherein a recess is provided in the side wall of the first conductive contact.

[0212] Example 60 provides a microelectronic assembly described in any one of Examples 31 to 59, wherein a recess is provided in the sidewall of the second conductive contact.

[0213] Example 61 provides a microelectronic assembly comprising: a glass substrate having a first surface and a second surface opposite the first surface; a TGV within the glass substrate, the TGV extending between the first and second surfaces, comprising a liner material and a conductive material, the liner material being positioned between the conductive material and the glass substrate; a first conductive contact connected to the TGV on the first surface of the glass substrate; and a second conductive contact connected to the TGV on the second surface of the glass substrate, wherein the elastic modulus (e.g., Young's modulus) of the liner material is less than about 30 gigapascals (GPa), for example, between about 1 GPa and 30 GPa, or between about 1 GPa and 20 GPa, or between about 1 GPa and 15 GPa.

[0214] Example 62 provides the microelectronic assembly described in Example 61, further comprising a void between the conductive material and a portion of the sidewall of the TGV.

[0215] Example 63 provides the microelectronic assembly described in Example 62, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0216] Example 64 provides the microelectronic assembly described in Example 62 or 63, wherein the void is one of several voids between the conductive material and different portions of the sidewall of the TGV.

[0217] Example 65 provides a microelectronic assembly described in any one of Examples 44 to 61, wherein the liner material is polyparaxylylene / polyparaxylylene.

[0218] Example 66 provides a microelectronic assembly described in any one of Examples 61-65, wherein the liner material comprises / is parylene N, parylene C, parylene D, or halogen-free polyparaxylylene.

[0219] Example 67 provides a microelectronic assembly described in any one of Examples 61-66, wherein the liner material is in contact with the sidewall of the TGV (e.g., in direct physical contact).

[0220] Example 68 provides the microelectronic assembly described in Example 67, further including a void between the conductive material and the liner material in a portion of the sidewall of the TGV.

[0221] Example 69 provides the microelectronic assembly described in Example 68, wherein the void width is between approximately 40 nanometers and approximately 140 nanometers, ranging from approximately 20 nanometers to approximately 200 nanometers.

[0222] Example 70 provides a microelectronic assembly described in any one of Examples 61 to 69, wherein the material composition of the first conductive contact is different from that of the conductive material, and the material composition of the second conductive contact is substantially the same as that of the conductive material.

[0223] Example 71 provides a microelectronic assembly comprising: a glass substrate having a first surface and a second surface opposite the first surface; a TGV within the glass substrate extending between the first surface and the second surface and comprising a conductive material; a cavity within the glass substrate extending from the first surface toward the second surface; and a material on the sidewall of the cavity, wherein the total volume of glass-filling particles in the material is less than about 15% of the total volume of the material on the sidewall of the cavity.

[0224] Example 72 provides the microelectronic assembly described in Example 71, further comprising a void between the conductive material and a portion of the sidewall of the TGV.

[0225] Example 73 provides the microelectronic assembly described in Example 72, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0226] Example 74 provides the microelectronic assembly described in Example 72 or 73, wherein the void is one of several voids between the conductive material and different portions of the sidewall of the TGV.

[0227] Example 75 provides a microelectronic assembly described in any one of Examples 71 to 74, further comprising a liner material between the conductive material and the glass substrate in the TGV.

[0228] Example 76 provides the microelectronic assembly described in Example 75, in which the liner material is in contact (e.g., in direct physical contact) with the side wall of the TGV.

[0229] Example 77 provides the microelectronic assembly described in Example 76, further including a void between the conductive material and the liner material in a portion of the sidewall of the TGV.

[0230] Example 78 provides the microelectronic assembly described in Example 77, wherein the void width is between approximately 20 nanometers and approximately 200 nanometers, for example, between approximately 40 nanometers and approximately 140 nanometers.

[0231] Example 79 provides the microelectronic assembly described in Example 77 or 78, wherein the void is one of several voids between the conductive material and the liner material in different parts of the sidewall of the TGV.

[0232] Example 80 provides a microelectronic assembly described in any one of Examples 75 to 79, wherein the thickness of the liner material is between approximately 200 nanometers and approximately 10 microns, for example, between approximately 200 nanometers and approximately 5 microns, or between approximately 500 nanometers and approximately 1 micron.

[0233] Example 81 provides a microelectronic assembly described in any one of Examples 75 to 80, wherein the elastic modulus (e.g., Young's modulus) of the liner material is less than about 30 gigapascals (GPa), for example, between about 1 GPa and 30 GPa, or between about 1 GPa and 20 GPa, or between about 1 GPa and 15 GPa.

[0234] Example 82 provides a microelectronic assembly described in any one of Examples 75 to 81, wherein the coefficient of thermal expansion (CTE) of the liner material is smaller than that of the conductive material.

[0235] Example 83 provides a microelectronic assembly described in any one of Examples 75-82, wherein the liner material includes / is a polymer material.

[0236] Example 84 provides a microelectronic assembly according to any one of claims 75 to 83, wherein the liner material is homopolymer-containing / homopolymer.

[0237] Example 85 provides a microelectronic assembly described in any one of Examples 75 to 84, wherein the liner material is polyparaxylylene / polyparaxylylene.

[0238] Example 86 provides a microelectronic assembly described in any one of Examples 75-83, wherein the liner material is a heteropolymer.

[0239] Example 87 provides a microelectronic assembly described in any one of Examples 75-83 or 86, wherein the liner material comprises / is at least one of polyester (PET), polyurethane (PU), polycarbonate (PC), polyvinyl chloride (PVC), or polybenzoxazole (PBO).

[0240] Example 88 provides a microelectronic assembly described in any one of Examples 75-82, wherein the liner material is a nonpolymer material.

[0241] Example 89 provides a microelectronic assembly described in any one of Examples 75-82 or 88, wherein the liner material includes / is an inorganic nonpolymer material.

[0242] Example 90 provides the microelectronic assembly described in any one of Examples 75 to 89, and the liner material includes two or more materials having different material compositions.

[0243] Example 91 provides the microelectronic assembly described in any one of Examples 71 to 90, and the material includes / is a polymer material.

[0244] Example 92 provides the microelectronic assembly described in any one of Examples 71 to 91, and the material includes / is an epoxy.

[0245] Example 93 provides the microelectronic assembly described in any one of Examples 71 to 92, and the thickness of the material on the sidewall of the cavity is between about 10 microns and about 2 - 3 mm.

[0246] Example 94 provides the microelectronic assembly described in any one of Examples 71 to 93, and the conductive material and the material are in the same plane on the first surface of the glass substrate.

[0247] Example 95 provides the microelectronic assembly described in any one of Examples 71 to 94, and the conductive material and the material are in the same plane on the second surface of the glass substrate.

[0248] Example 96 provides the microelectronic assembly described in any one of the above examples, and the cross-section of the glass substrate in a plane perpendicular to the surface of the component is substantially rectangular.

[0249] Example 97 provides the microelectronic assembly described in any one of the above examples, and the cross-section of the glass substrate in a plane parallel to the surface of the component is substantially rectangular.

[0250] Example 98 provides the microelectronic assembly described in any one of the above examples, and the glass substrate is a solid layer of glass.

[0251] Example 99 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer containing at least 23% by weight of silicon.

[0252] Example 100 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer containing at least 26% by weight of oxygen.

[0253] Example 101 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer containing at least 23% by weight of silicon and at least 26% by weight of oxygen.

[0254] Example 102 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer containing at least 5% by weight of aluminum.

[0255] Example 103 provides a microelectronic assembly described in any one of the above examples, wherein the glass substrate is a glass layer that does not contain an organic adhesive or organic material.

[0256] Example 104 provides a microelectronic assembly described in any one of the above examples, wherein the glass substrate has a thickness in the range of 50 microns (μm) to 1.4 millimeters (mm), a first length in the range of 10 mm to 250 mm, a second length in the range of 10 mm to 250 mm, and the first length is perpendicular to the second length.

[0257] Example 105 provides a microelectronic assembly described in any one of the above examples, wherein the glass substrate is a glass layer having a thickness in the range of 50 μm to 1.4 mm.

[0258] Example 106 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer having a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0259] Example 107 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer containing the volume of a rectangular prism.

[0260] Example 108 provides a microelectronic assembly according to any one of the above examples, wherein the glass substrate is a glass layer comprising a volume of a right-angle prism having a first side and a second side substantially perpendicular to the first side, the length of the first side in the range of 10 mm to 250 mm.

[0261] Example 109 provides the microelectronic assembly described in Example 108, wherein the length of the second side is in the range of 10 mm to 250 mm.

[0262] The above description of the illustrated embodiments of the Disclosure, including the contents described in the Abstract, is not exhaustive and is not intended to limit the Disclosure to the form in which it is disclosed. Specific embodiments and examples of the Disclosure have been described herein for illustrative purposes only, but various equivalent modifications are possible within the scope of the Disclosure, as those skilled in the art will understand. These modifications can be made in light of the above detailed description.

Claims

1. A microelectronic assembly, said microelectronic assembly is A glass substrate having a first surface and a second surface opposite to the first surface, A glass through-via (TGV) in the glass substrate, extending between the first surface and the second surface, comprising a conductive material, A first conductive contact to the TGV on the first surface of the glass substrate, The glass substrate includes a second conductive contact to the TGV on the second surface, The seed material is present between the first conductive contact on the first surface of the glass substrate and a portion of the TGV. The second conductive contact is in contact with a portion of the TGV on the second surface of the glass substrate. Microelectronic assembly.

2. The microelectronic assembly according to claim 1, further comprising a void between the conductive material and a portion of the side wall of the TGV.

3. The microelectronic assembly according to claim 2, wherein the width of the void is between approximately 20 nanometers (nm) and approximately 200 nm.

4. The microelectronic assembly according to claim 2, wherein the void is one of a plurality of voids between the conductive material and different portions of the side wall of the TGV.

5. The microelectronic assembly according to claim 1, wherein the TGV further includes a liner material between the conductive material and the glass substrate.

6. The microelectronic assembly according to claim 5, wherein the liner material is in contact with the side wall of the TGV, and the microelectronic assembly further includes a void between the conductive material and the liner material in a portion of the side wall of the TGV.

7. The microelectronic assembly according to claim 5, wherein the elastic modulus of the liner material is less than about 30 gigapascals (GPa).

8. The microelectronic assembly according to claim 5, wherein the liner material comprises or is polyparaxylylene.

9. The microelectronic assembly according to claim 1, wherein the average particle size of the seed material is smaller than the average particle size of the conductive material.

10. The microelectronic assembly according to any one of claims 1 to 9, further comprising a further material between the seed material and the first surface of the glass substrate, wherein the further material comprises titanium.

11. It is a package, and the package is A glass substrate having a first surface and a second surface opposite to the first surface, A glass through-via (TGV) in the glass substrate, extending between the first surface and the second surface, comprising a conductive material, A first conductive contact to the TGV on the first surface of the glass substrate, The glass substrate includes a second conductive contact to the TGV on the second surface, The material composition of the first conductive contact differs from the material composition of the conductive material. A package in which the material composition of the second conductive contact and the material composition of the conductive material are substantially the same.

12. Between the conductive material and the glass substrate, the liner material in the TGV and, A portion of the side wall of the TGV further includes a void between the conductive material and the liner material, The package according to claim 11, wherein the width of the void is between approximately 20 nm and approximately 200 nm.

13. The package according to claim 12, wherein the elastic modulus of the liner material is less than about 15 GPa.

14. The package according to claim 11, wherein an additional material is attached to the first surface of the glass substrate, and the additional material is not present between the first conductive contact and the conductive material.

15. The package according to claim 11, wherein the seed material is not present on the first surface of the glass substrate, the second surface of the glass substrate, and the sidewall of the TGV.

16. The package according to claim 11, wherein the angle between the side wall of the first conductive contact and the first surface of the glass substrate is less than approximately 85°.

17. The package according to any one of claims 11 to 16, wherein the side wall of the first conductive contact has a recess.

18. A semiconductor package, said semiconductor package is A glass substrate having a first surface and a second surface opposite to the first surface, A glass through-glass via (TGV) in the glass substrate, the TGV extending between the first surface and the second surface, comprising a liner material and a conductive material, wherein the liner material is located between the conductive material and the glass substrate, and the TGV A first conductive contact to the TGV on the first surface of the glass substrate, The glass substrate includes a second conductive contact to the TGV on the second surface, The elastic modulus of the liner material is less than approximately 30 GPa. Semiconductor package.

19. The semiconductor package according to claim 18, wherein the liner material comprises parylene N, parylene C, parylene D, or halogen-free polyparaxylylene, or is parylene N, parylene C, parylene D, or halogen-free polyparaxylylene.

20. The material composition of the first conductive contact differs from the material composition of the conductive material. The semiconductor package according to claim 18 or 19, wherein the material composition of the second conductive contact and the material composition of the conductive material are substantially the same.

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