Electro-optical devices and electronic equipment

Abstract

To provide highly reliable electro-optical devices and electronic equipment. [Solution] The electro-optic device has a pixel region having pixel electrodes and a peripheral region located around the pixel region, and comprises a substrate, a plurality of first transistors located in the pixel region, a plurality of second transistors located in the peripheral region, a first insulating layer provided on top of the first transistors and the second transistors, a plurality of first conductive parts located in the pixel region and provided within the first insulating layer and spaced apart from each other, and a plurality of second conductive parts located in the peripheral region and provided within the first insulating layer and spaced apart from each other, wherein in a plan view in the thickness direction of the substrate, the arrangement density of the plurality of second conductive parts in the region occupied by the plurality of second conductive parts is greater than the arrangement density of the plurality of first conductive parts in the region occupied by the plurality of first conductive parts.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In an electronic device such as a projector, for example, an electro-optical device such as a liquid crystal display device capable of changing optical characteristics for each pixel is used.

[0003] The substrate for an electro-optical device described in Patent Document 1 has a pixel region and a peripheral region located around the pixel region. In the pixel region, a transistor is provided for each pixel, and a contact responsible for connection to various wirings is connected to the transistor. In the peripheral region, a peripheral circuit having a transistor arranged in the same layer as the transistor in the pixel region is provided. A contact responsible for connection to various wirings is also connected to the transistor included in the peripheral circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Conventionally, when forming a contact or the like for connecting a transistor to various wirings, a global step or the like may occur between the pixel region and the peripheral region, and there is a risk that the connection by the contact becomes insufficient. As a result of intensive studies by the inventors, it has been found that the step is caused by a planar density difference of contacts or the like in the pixel region and the peripheral region.

Means for Solving the Problems

[0006] One embodiment of the electro-optical apparatus of the present invention is an electro-optical apparatus having a pixel region having pixel electrodes and a peripheral region located around the pixel region, comprising a substrate, a plurality of first transistors located in the pixel region, a plurality of second transistors located in the peripheral region, a first insulating layer provided on top of the first and second transistors, a plurality of first conductive parts located in the pixel region and provided within the first insulating layer and spaced apart from each other, and a plurality of second conductive parts located in the peripheral region and provided within the first insulating layer and spaced apart from each other, wherein, in a plan view in the thickness direction of the substrate, the arrangement density of the plurality of second conductive parts in the region occupied by the plurality of second conductive parts is greater than the arrangement density of the plurality of first conductive parts in the region occupied by the plurality of first conductive parts.

[0007] One embodiment of the electronic device of the present invention comprises an electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of an electro-optical device according to the first embodiment. [Figure 2] This is a cross-sectional view of the AA line of the electro-optical apparatus shown in 1. [Figure 3] This figure schematically shows the peripheral circuits of the electro-optical device shown in Figure 1. [Figure 4] Figure 1 is an equivalent circuit diagram showing the electrical configuration of each pixel in the element substrate. [Figure 5] This is a plan view showing a portion of the pixel region in Figure 1. [Figure 6] This diagram corresponds to the cross-section along line B1-B1 in Figure 7. [Figure 7] This diagram corresponds to the cross-section along line B2-B2 in Figure 4. [Figure 8] This is a plan view showing some of the multiple second transistors in the peripheral circuit shown in Figure 3. [Figure 9] Figure 3 is a cross-sectional view showing multiple second transistors and their vicinity in the peripheral circuit shown. [Figure 10]A cross-sectional view for explaining the relationship between the arrangement densities of the first, second, third, and fourth contacts. [Figure 11] A plan view for explaining the arrangement density of the first contact in FIG. 6. [Figure 12] A plan view for explaining the arrangement density of the second contact in FIG. 9. [Figure 13] A plan view for explaining the arrangement density of the third contact in FIG. 6. [Figure 14] A plan view for explaining the arrangement density of the fourth contact in FIG. 9. [Figure 15] A diagram for explaining the manufacturing method of the insulating layer shown in FIG. 10. [Figure 16] A diagram for explaining the manufacturing method of the third and fourth contacts shown in FIG. 10. [Figure 17] A diagram for explaining the manufacturing method of the third and fourth contacts shown in FIG. 10. [Figure 18] A cross-sectional view showing the fourth contact and the conductive part in the first modification example. [Figure 19] A cross-sectional view showing the fourth contact and the conductive part in the second modification example. [Figure 20] A cross-sectional view showing the first and second contacts of the third modification example. [Figure 21] A diagram for explaining the manufacturing method of the first and second contacts shown in FIG. 20. [Figure 22] A diagram for explaining the manufacturing method of the insulating layer shown in FIG. 20. [Figure 23] A perspective view showing a personal computer, which is an example of an electronic device. [Figure 24] A plan view showing a smartphone, which is an example of an electronic device. [Figure 25] A schematic diagram showing a projector, which is an example of an electronic device.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. Note that the dimensions or scales of each part in the drawings are appropriately different from the actual ones, and there are also some parts schematically shown for easy understanding. Also, the scope of the present invention is not limited to these embodiments unless there is a description to specifically limit the present invention in the following description.

[0010] A. Electro-optical device A1. Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A of the electro-optical device 100 shown in FIG. 1. Hereinafter, for convenience of explanation, the X-axis, Y-axis, and Z-axis orthogonal to each other will be appropriately used for explanation. Also, one direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction. Also, the Z-axis is typically a vertical axis. The Z1 direction is the upper side, and the Z2 direction is the lower side. However, the Z-axis does not have to be a vertical axis.

[0011] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device of an active matrix driving method. The electro-optical device 100 includes a device substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. As shown in FIG. 2, the device substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Also, the shape of the electro-optical device 100 in a plan view shown in FIG. 1 is a quadrilateral, but it may be a polygon other than a quadrilateral or a circle.

[0012] The device substrate 2 shown in FIG. 2 includes a first substrate 21 having light transmissivity, a laminate 22 having light transmissivity, a plurality of pixel electrodes 25 having light transmissivity, and a first alignment film 29 having light transmissivity. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in this order in the Z1 direction. Therefore, the laminate 22 is disposed between the first substrate 21 and the plurality of pixel electrodes 25. Note that "light transmissivity" means transmissivity with respect to visible light, and preferably, the transmittance of visible light is 50% or more.

[0013] The first substrate 21 corresponds to the "substrate". Viewing from the Z1 or Z2 direction, which is the thickness direction of the first substrate 21, is referred to as a "plan view". The first substrate 21 is a translucent and insulating flat plate, and is composed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of translucent insulating films. Various wirings and the like are also provided on the laminate 22. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, transparent conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown in the figures, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in a plan view. The first alignment film 29 is translucent and insulating. The first alignment film 29 aligns the liquid crystal molecules in the liquid crystal layer 5. The first alignment layer 29 is positioned to cover a plurality of pixel electrodes 25. The material of the first alignment layer 29 is, for example, polyimide and silicon dioxide.

[0014] The opposing substrate 3 is positioned opposite the element substrate 2. The opposing substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second orientation film 34. Although not shown in the figures, the opposing substrate 3 also has a light-shielding border that surrounds a plurality of pixel electrodes 25 in a plan view. "Light-shielding" refers to light-shielding properties to visible light, preferably with a visible light transmittance of less than 50%, and more preferably 10% or less.

[0015] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a translucent and insulating plate, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 is translucent and insulating and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode placed on a plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes, for example, transparent conductive materials such as ITO, IZO, and FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide.

[0016] The sealing member 4 is placed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins, such as epoxy resin. The sealing member 4 may also include a gap material made of an inorganic material such as glass.

[0017] The liquid crystal layer 5 is located within a region enclosed by the element substrate 2, the opposing substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optic layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0018] The electro-optical device 100 has a pixel region A10 and a peripheral region A20 located around the pixel region A10 in a plan view. The pixel region A10 is an area for displaying an image and is provided with a plurality of pixels P arranged in a matrix. A plurality of pixel electrodes 25 are arranged one-to-one for the plurality of pixels P. The aforementioned common electrode 33 is provided in common for the plurality of pixels P. The peripheral region A20 surrounds the pixel region A10 in a plan view.

[0019] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Figure 2, an image is displayed by modulating the light LL between the time it is incident on the opposing substrate 3 and the time it is emitted from the element substrate 2. Alternatively, an image may be displayed by modulating the light incident on the element substrate 2 while it is emitted from the opposing substrate 3.

[0020] Furthermore, the electro-optical device 100 is applied to, for example, a color display device such as a personal computer and a smartphone, which will be described later. When applied to such a display device, a color filter is appropriately used for the electro-optical device 100. Also, the electro-optical device 100 is applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light bulb. In this case, a color filter is omitted for the electro-optical device 100.

[0021] A2. Peripheral circuits Figure 3 is a schematic diagram showing the peripheral circuit 10 in the electro-optical device 100 shown in Figure 1. As shown in Figure 3, the peripheral region A20 of the electro-optical device 100 is provided with the peripheral circuit 10 and a plurality of external terminals 13. The plurality of external terminals 13 are connected to wiring (not shown) that is routed from the peripheral circuit 10.

[0022] Furthermore, the pixel region A10 has n scan lines 241 and m data lines 242, where n and m are integers greater than or equal to 2. The n scan lines 241 extend along the X-axis and are spaced equally along the Y-axis. The m data lines 242 extend along the Y-axis and are spaced equally along the X-axis. The n scan lines 241 and m data lines 242 are electrically insulated from each other and are arranged in a grid pattern in a planar view. The region enclosed by two adjacent scan lines 241 and two adjacent data lines 242 corresponds to pixel P.

[0023] Furthermore, the peripheral circuit 10 includes two scan line drive circuits 11, a data line drive circuit 12, a test circuit 14, and a sampling circuit 16.

[0024] In the illustrated example, the two scan line drive circuits 11 are arranged on either side of the pixel area A10. Each scan line drive circuit 11 includes multiple transistors. For example, the scan line drive circuit 11 located on the left side of the pixel area A10 drives the odd-numbered scan lines 241, and the scan line drive circuit 11 located on the right side of the pixel area A10 drives the even-numbered scan lines 241. Alternatively, the same scan line 241 may be driven by scan line drive circuits 11 located on both the left and right sides.

[0025] The inspection circuit 14 is located, for example, on the opposite side of the multiple external terminals 13 of the pixel area A10. Data lines 242 are connected to the inspection circuit 14. The inspection circuit 14 is used to inspect the electro-optical device 100 for operational defects, etc., by detecting the image signal during the manufacturing or shipment of the electro-optical device 100. The inspection circuit 14 has, for example, a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to an inspection line (not shown). In addition, the gate of each transistor is electrically connected to a control signal line (not shown).

[0026] The data line drive circuit 12 and the sampling circuit 16 are arranged, for example, on the opposite side of the pixel region A10 from the inspection circuit 14. The data line drive circuit 12 is electrically connected to m data lines 242 via the sampling circuit 16. The data line drive circuit 12 includes, for example, an inverter circuit and a transmission gate, and has multiple transistors. Based on the sampling signal output from the data line drive circuit 12, the sampling circuit 16 samples the image signal and supplies it to the data lines 242.

[0027] The sampling circuit 16 has a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to a constant potential line (not shown). In addition, the gate of each transistor is electrically connected to a signal line (not shown) to which the sampling signal is supplied.

[0028] A3. Electrical configuration of each pixel P in pixel region A10 Figure 4 is an equivalent circuit diagram showing the electrical configuration of each pixel P in the element substrate 2 of Figure 1. As shown in Figure 4, each pixel P in the pixel region A10 of the element substrate 2 is provided with a first transistor 23, a pixel electrode 25, and a capacitive element 24. Each first transistor 23 includes a gate, source, and drain. The pixel electrode 25 is electrically connected to the drain of the corresponding first transistor 23. In addition, as described above, n scan lines 241 and m data lines 242, as well as n constant potential lines 243, are arranged in the pixel region A10.

[0029] Each of the n scan lines 241 is electrically connected to the gate of a corresponding number of first transistors 23. Scan signals G1, G2, ..., and Gn are supplied to the 1 to n scan lines 241 sequentially from the scan line drive circuit 11.

[0030] Each of the m data lines 242 is electrically connected to the source of a corresponding number of first transistors 23. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m data lines 242 from the aforementioned data line driving circuit 12 via the sampling circuit 16.

[0031] n constant potential lines 243 extend in the X1 direction and are arranged at equal intervals in the Y2 direction. Furthermore, the n constant potential lines 243 are electrically insulated from the n scan lines 241 and m data lines 242, and are spaced apart from them. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitive element 24. The other electrode of each capacitive element 24 is electrically connected to the corresponding pixel electrode 25. Each capacitive element 24 is a holding capacitor for maintaining the potential of the pixel electrode 25. A constant potential Vcom is applied to one electrode of the capacitive element 24, and the other electrode is electrically connected to the drain of the first transistor 23.

[0032] As scanning signals G1, G2, ..., and Gn become active in sequence, and n scanning lines 241 are selected in sequence, the first transistor 23 connected to the selected scanning line 241 turns ON. Then, image signals S1, S2, ..., and Sm, whose magnitudes correspond to the grayscale to be displayed, are taken up via m data lines 242 to the pixel P corresponding to the selected scanning line 241 and applied to the pixel electrode 25. As a result, a voltage corresponding to the grayscale to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in Figure 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. In addition, the applied voltage is maintained by the capacitive element 24. Light is modulated by this change in the orientation of the liquid crystal molecules, making grayscale display possible.

[0033] A4. Configuration of each pixel P in pixel area A10 Figure 5 is a plan view showing a portion of the pixel region A10 in Figure 1. Figure 6 is a diagram corresponding to the B1-B1 cross-section in Figure 7. Figure 7 is a diagram corresponding to the B2-B2 cross-section in Figure 4.

[0034] As shown in Figure 5, the pixel region A10 has multiple aperture regions A11 and a light-shielding region A12. The multiple aperture regions A11 are arranged in a matrix in a plan view. The shape of the light-shielding region A12 in a plan view is a frame shape located between the multiple aperture regions A11. Each aperture region A11 is the region where the pixel electrode 25 is placed and is a region through which light is transmitted. On the other hand, the first transistor 23 is placed in the light-shielding region A12. Although not shown in Figure 5, the light-shielding region A12 also has multiple wirings such as the scan line 241, data line 242, and constant potential line 243 shown in Figure 4, as well as a capacitive element 24.

[0035] As shown in Figures 6 and 7, the laminate 22 of the element substrate 2 has the aforementioned insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. Insulating layers 222 and 223 correspond to the "first insulating layer". Insulating layer 224 corresponds to the "second insulating layer".

[0036] A light-shielding portion 281 is placed on the first substrate 21. The light-shielding portion 281 is provided to prevent light from entering the semiconductor layer 231 of the first transistor 23. The first substrate 21 may have a recess that opens in the Z1 direction. In this case, the light-shielding portion 281 may be placed in the recess.

[0037] A first transistor 23 is placed on the insulating layer 221. The first transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is placed on the insulating layer 221. The gate electrode 232 is placed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. The region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0038] The first transistor 23 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. For example, the first transistor 23 does not necessarily have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. Also, in a plan view, the semiconductor layer 231 overlaps with the light-shielding portion 281.

[0039] The semiconductor layer 231 is formed from, for example, polysilicon. The drain region 231a and the source region 231b are doped with impurities. The gate electrode 232 is formed, for example, by doping polysilicon with impurities that enhance conductivity. The gate electrode 232 may also be formed from conductive materials such as metals, metal oxides, and metal compounds. The gate insulating film 233 is composed of a silicon oxide film formed by, for example, thermal oxidation or CVD (chemical vapor deposition).

[0040] The insulating layers 222 and 223 are provided with first contacts 261 and 262. The first contact 261 is provided corresponding to the first transistor 23. The first contact 261 is a contact connected to the drain region 231a. The first contact 261 has a first column portion 2611 and a first upper portion 2612. The first column portion 2611 is the portion connected to the drain region 231a. The first column portion 2611 is a columnar portion embedded in a hole penetrating the insulating layers 222 and 223. The first upper portion 2612 is connected to the first column portion 2611 and is a flat plate-shaped portion along the XY plane.

[0041] The first contact 262 is provided in correspondence with the first transistor 23. The first contact 262 has a first column portion 2621 and a first upper portion 2622. The first column portion 2621 is the portion connected to the source region 231b. The first column portion 2621 is a columnar portion embedded in a hole penetrating the insulating layers 222 and 223. The first upper portion 2622 is connected to the first column portion 2621 and is a flat plate-shaped portion along the XY plane.

[0042] The insulating layer 224 contains the scan line 241, contact 27, third contact 263, and third contact 264. As described above, the scan line 241 is electrically connected to the gate electrode 232 via contact 27. Also, as shown in Figure 7, contact 27 is connected to the light shield 281. Note that although contact 27 and scan line 241 are formed separately, they may be integrally formed from the same material.

[0043] The third contact 263 is provided in correspondence with the first transistor 23. The third contact 263 has a third column portion 2631 and a third upper portion 2632. The third column portion 2631 is the portion connected to the drain region 231a via the first contact 261. The third column portion 2631 is a columnar portion embedded in a hole penetrating the insulating layer 224. The third upper portion 2632 is connected to the third column portion 2631 and is a flat plate-shaped portion along the XY plane.

[0044] The third contact 264 is provided corresponding to the first transistor 23. The third contact 264 has a third column portion 2641 and a third upper portion 2642. The third column portion 2641 is the portion connected to the source region 231b via the first contact 262. The third column portion 2641 is a columnar portion embedded in a hole penetrating the insulating layer 224. The third upper portion 2642 is connected to the third column portion 2641 and is a flat plate-shaped portion along the XY plane.

[0045] Although the plan view is omitted, in this embodiment, one third contact 263 is provided for each first contact 261. Similarly, one third contact 264 is provided for each first contact 262.

[0046] Furthermore, the first contact 261 and the contact 27 each function as a light-shielding portion that suppresses the incidence of light into the low-concentration drain region 231d of the semiconductor layer 231. By providing the first contact 26, the contact 27, and the light-shielding portion 281, the incidence of light into the low-concentration drain region 231d of the semiconductor layer 231 can be suppressed.

[0047] As shown in Figure 6, relay electrodes 247 and 248 are arranged on the insulating layer 225. Relay electrode 247 is electrically connected to relay electrode 246 via a contact 275 that penetrates the insulating layer 225. The contact 275 is, for example, integrally formed with relay electrode 246 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225. Relay electrode 248 is electrically connected to relay electrode 245 via a contact 274 that penetrates the insulating layer 225. The contact 274 is integrally formed with relay electrode 248 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225.

[0048] A data line 242 is placed on the insulating layer 226. The data line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. The contact 276 is integrally formed with the data line 242 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0049] As shown in Figure 7, a relay electrode 249 is placed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer. The contact 277 is integrally formed with the relay electrode 249 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0050] A capacitive element 24 is placed on the insulating layer 227. The capacitive element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. Electrode 2401 is placed on the insulating layer 227. Electrode 2402 is placed on the insulating layer 228. The dielectric layer 2403 is placed between electrodes 2401 and 2402. Electrode 2401 also serves as the constant potential line 243 in Figure 4. Electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. The contact 278 is integrally formed with electrode 2402 and has a trench structure provided along the inner wall surface of the holes formed in the insulating layers 227 and 228.

[0051] Pixel electrodes 25 are placed on the insulating layer 229. The pixel electrodes 25 are electrically connected to electrodes 2402 via contacts 279 that penetrate the insulating layer 229. The contacts 279 are integrally formed with the pixel electrodes 25 and have a trench structure provided along the inner wall surface of holes formed in the insulating layer 229.

[0052] The aforementioned scan lines 241, data lines 242, and relay electrodes 247, 248, and 249 each include, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or multi-layer. For example, they may be composed of a laminate of an aluminum film and a titanium nitride film.

[0053] Each of the aforementioned first contacts 261, 262, 263, and 264 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or multi-layer.

[0054] Furthermore, each of the aforementioned contacts 274 to 279 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), as well as metal nitrides and metal silicides. Each of the contacts 274 to 279 may be single-layer or multi-layer. Also, each of the contacts 274 to 279 may be integrally formed with the electrode or wiring to be connected, or may be formed separately. Each of the contacts 274 to 279 may be a trench structure or a contact plug.

[0055] Note that the configuration of the element substrate 2 shown in Figures 6 and 7 is just one example. For example, it may include other capacitive elements besides the capacitive element 24. Also, although the scan line 241, data line 242, and capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.

[0056] A5. Peripheral circuits 10 Figure 8 is a plan view showing a portion of the multiple second transistors 15 in the peripheral circuit 10 shown in Figure 3. Figure 9 is a cross-sectional view showing the multiple second transistors 15 and their vicinity in the peripheral circuit 10 shown in Figure 3. Figure 9 corresponds to the cross section B3-B3 in Figure 8. In the following sections, for example, a portion of the scan line drive circuit 11 in the peripheral circuit 10 is illustrated.

[0057] As shown in Figure 9, a light-shielding portion 282 is provided on the first substrate 21 in the peripheral region A20. The light-shielding portion 282 is a light-shielding film. The light-shielding portion 282 is provided to suppress the incidence of light onto the semiconductor layer 151 of the corresponding second transistor 15. The first substrate 21 may have a recess that opens in the Z1 direction. In this case, the light-shielding portion 282 may be placed in the recess. Furthermore, the light-shielding portion 282 may be provided in a one-to-one ratio with respect to the second transistor 15, or it may be provided for every two or more second transistors 15.

[0058] A second transistor 15 is provided on the insulating layer 221. The second transistor 15 has a semiconductor layer 151, a gate electrode 152, and a gate insulating film 153. The gate insulating film is positioned between the semiconductor layer 151 and the gate electrode 152. The semiconductor layer 151 is positioned on the insulating layer 221, and the gate electrode 152 is positioned on the insulating layer 222. The semiconductor layer 151 has a source-drain region 151a, a source-drain region 151b, and a channel region 151c. The channel region 151c is located between the source-drain region 151a and the source-drain region 151b. The "source-drain region" refers to a region that includes either the source or the drain.

[0059] The semiconductor layer 151 is formed from, for example, polysilicon. The source / drain region 151a and source / drain region 151b are doped with impurities. The gate electrode 152 is formed, for example, by doping polysilicon with impurities that enhance conductivity. The gate electrode 152 may also be formed using conductive materials such as metals, metal oxides, and metal compounds. The gate insulating film 153 is composed of a silicon oxide film formed by, for example, thermal oxidation or CVD.

[0060] Furthermore, multiple second transistors 15 are provided, arranged, for example, along the X-axis or Y-axis. Figure 8 illustrates two second transistors 15. In the example shown in Figure 8, the two second transistors 15 share a portion of each other. Specifically, the source and drain regions 151a of the two second transistors 15 are shared.

[0061] As shown in Figure 9, the insulating layers 222 and 223 have second contacts 161 and 162. The second contact 161 is a contact connected to the source / drain region 151a. The second contact 161 is provided corresponding to the second transistor 15. The second contact 161 has a second column portion 1611 and a second upper portion 1612. The second column portion 1611 is the portion connected to the source / drain region 151a. The second column portion 1611 is a columnar portion embedded in a hole penetrating the insulating layers 222 and 223. The second upper portion 1612 is a flat plate-shaped portion connected to the second column portion 1611 and aligned with the XY plane.

[0062] The second contact 162 is provided in correspondence with the second transistor 15. The second contact 162 has a second column portion 1621 and a second upper portion 1622. The second column portion 1621 is the portion connected to the source / drain region 151b. The second column portion 1621 is a columnar portion embedded in a hole that penetrates the insulating layers 222 and 223. The second upper portion 1622 is connected to the second column portion 1621 and is a flat portion along the XY plane.

[0063] As shown in Figure 8, multiple second contacts 161 are provided for one second transistor 15. Similarly, multiple second contacts 162 are provided for one second transistor 15. The multiple second contacts 161 are spaced apart from each other and arranged along the X-axis, and the multiple second contacts 162 are spaced apart from each other and arranged along the X-axis. By providing multiple second contacts 161 and multiple second contacts 162 for one second transistor 15, multiple columns with a high aspect ratio can be provided. Therefore, the increase in resistance of the second contacts 161 and 162 can be suppressed.

[0064] As shown in Figure 9, the insulating layer 224 contains the scan line 241, contact 165, fourth contact 163, and fourth contact 164. As described above, the scan line 241 is electrically connected to the gate electrode 152 via contact 165. Although contact 165 and scan line 241 are formed separately, they may be integrally formed from the same material.

[0065] The fourth contact 163 is provided in correspondence with the second transistor 15. The fourth contact 163 has a fourth column portion 1631 and a fourth upper portion 1632. The fourth column portion 1631 is the portion connected to the source / drain region 151a via the second contact 161. The fourth column portion 1631 is a columnar portion embedded in a hole penetrating the insulating layer 224. The fourth upper portion 1632 is connected to the fourth column portion 1631 and is a flat portion aligned with the XY plane.

[0066] The fourth contact 164 is provided in correspondence with the second transistor 15. The fourth contact 164 has a fourth column portion 1641 and a fourth upper portion 1642. The fourth column portion 1641 is the portion connected to the source / drain region 151b via the second contact 162. The fourth column portion 1641 is a columnar portion embedded in a hole penetrating the insulating layer 224. The fourth upper portion 1642 is connected to the fourth column portion 1641 and is a flat portion aligned with the XY plane.

[0067] Although the plan view is omitted, in this embodiment, one fourth contact 163 is provided for each second contact 161. Similarly, one fourth contact 164 is provided for each second contact 162.

[0068] Although the configuration above the insulating layer 225 is not shown, the fourth contact 164 and the fourth contact 163 are electrically connected to various wirings that are not shown.

[0069] Furthermore, each of the aforementioned second contacts 161, 162, 163, and 164 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or multi-layer.

[0070] A6. Density of conductive parts Figure 10 is a cross-sectional view illustrating the relationship between the arrangement densities of the first contact 260a, the second contact 160a, the third contact 260b, and the fourth contact 160b. Figure 11 is a plan view illustrating the arrangement density of the first contact 260a in Figure 6. Figure 12 is a plan view illustrating the arrangement density of the second contact 160a in Figure 9. Figure 13 is a plan view illustrating the arrangement density of the third contact 260b in Figure 6. Figure 14 is a plan view illustrating the arrangement density of the fourth contact 160b in Figure 9.

[0071] As mentioned above, the pixel region A10 is provided with a plurality of first contacts 261 and a plurality of first contacts 262. The pixel region A10 is also provided with a plurality of third contacts 263 and a plurality of third contacts 264. The peripheral region A20 is provided with a plurality of second contacts 161 and a plurality of second contacts 162. The peripheral region A20 is also provided with a plurality of fourth contacts 163 and a plurality of fourth contacts 164.

[0072] In the following, multiple first contacts 261 and multiple first contacts 262 may be collectively referred to as "multiple first contacts 260a". Multiple third contacts 263 and multiple third contacts 264 may be collectively referred to as "multiple third contacts 260b". Also, multiple second contacts 161 and multiple second contacts 162 may be collectively referred to as "second contact 160a". Multiple fourth contacts 163 and multiple fourth contacts 164 may be collectively referred to as "fourth contact 160b". Multiple first contacts 260a are "multiple first conductive parts". Multiple second contacts 160a are "multiple second conductive parts". Multiple third contacts 260b are "multiple third conductive parts". Multiple fourth contacts 160b are "multiple fourth conductive parts".

[0073] As can be seen by referring to Figures 10, 11, and 12, in a plan view in the thickness direction of the first substrate 21, the arrangement density of multiple second contacts 160a in region S2a occupied by multiple second contacts 160a is greater than the arrangement density of multiple first contacts 260a in region S1a occupied by multiple first contacts 260a. In other words, the arrangement density of multiple second contacts 160a is greater than the arrangement density of multiple first contacts 260a. Arrangement density is the area ratio of first contacts 260a or second contacts 160a per unit area. The arrangement density of multiple first contacts 260a is an indicator of how densely multiple first contacts 260a are located in region S1a. The arrangement density of multiple first contacts 260a is an indicator of how densely multiple second contacts 160a are located in region S2a.

[0074] Region S1a is a closed space formed along the outer edges of several of the outermost first contacts 260a located in the pixel region A10. Region S2a is a closed space formed along the outer edges of several of the outermost second contacts 160a located in the multiple second contacts 160a. An example of region S2a is shown in Figure 3.

[0075] Furthermore, as can be seen by referring to Figures 10, 13, and 14, in a plan view in the thickness direction of the first substrate 21, the arrangement density of the multiple fourth contacts 160b in the region S2b occupied by the multiple fourth contacts 160b is greater than the arrangement density of the multiple third contacts 260b in the region S1b occupied by the multiple third contacts 260b. In other words, the arrangement density of the multiple fourth contacts 160b is greater than the arrangement density of the multiple third contacts 260b.

[0076] Region S2b is a closed space formed along the outer edges of some of the outermost third contacts 260b among the multiple third contacts 260b located in pixel region A10. Region S1b is a closed space formed along the outer edges of some of the outermost fourth contacts 160b among the multiple fourth contacts 160b.

[0077] In this way, the arrangement density of multiple second contacts 160a and multiple fourth contacts 160b can be increased, and global steps during manufacturing can be eliminated by thinning. Therefore, the risk of poor conductivity due to the third contact 260b and fourth contact 160b can be reduced. Thus, the reliability of the electro-optical device 100 can be improved.

[0078] The scan line 241 is a conductive wiring placed in the insulating layer 224. However, the scan line 241 spans both the peripheral region A20 and the pixel region A10. Therefore, the scan line 241 does not affect the relative magnitude of the difference in placement density described above, and is therefore not considered.

[0079] Figure 15 is a diagram illustrating the manufacturing method of the insulating layer 224 shown in Figure 10. Figures 16 and 17 are diagrams illustrating the manufacturing methods of the third contact 260b and the fourth contact 160b shown in Figure 10, respectively.

[0080] As shown in Figure 15, when a planarization treatment such as CMP (Chemical Mechanical Polishing) is applied after the insulating layer 224 is deposited, a global step is created on the upper surface of the insulating layer 224. The global step is a step that occurs between the pixel region A10 and the peripheral region A20. The arrangement density of the multiple second contacts 160a is greater than the arrangement density of the multiple first contacts 260a. Therefore, due to the planarization treatment, the upper part of the insulating layer 224 where the multiple second contacts 160a are located rises higher than the upper part of the insulating layer 224 where the multiple first contacts 260a are located.

[0081] Next, as shown in Figure 16, multiple third contacts 260b and multiple fourth contacts 160b are formed in the insulating layer 224. The upper surfaces of the multiple second contacts 160a in the insulating layer 224 are located above the upper surfaces of the multiple first contacts 260a in the insulating layer 224. Therefore, the upper surfaces of the multiple third contacts 260b are located above the upper surfaces of the multiple fourth contacts 160b. In this state, a planarization treatment such as CMP is applied to the multiple third contacts 260b and the multiple fourth contacts 160b. As a result, as shown in Figure 17, the upper part of each fourth contact 160b is removed by thinning. Because the arrangement density of the multiple fourth contacts 160b is greater than the arrangement density of the multiple third contacts 260b, the multiple fourth contacts 160b are easier to remove by thinning than the multiple third contacts 260b. This thinning process causes the upper surfaces of the multiple fourth contacts 160b and the multiple third contacts 260b to be approximately the same in position along the Z-axis. As a result, the step difference on the insulating layer 224 is eliminated.

[0082] In this way, the arrangement density of multiple second contacts 160a and multiple fourth contacts 160b can be increased, and steps on the insulating layer 224 can be eliminated by thinning. As a result, the machinability of the various contacts arranged on top of the multiple third contacts 260b and multiple fourth contacts 160b can be improved. Therefore, connection failures between the multiple third contacts 260b, multiple fourth contacts 160b and various contacts can be made less likely.

[0083] Furthermore, it is preferable that the distance between the centers of two adjacent second contacts 160a among the multiple second contacts 160a is smaller than the distance between the centers of two adjacent first contacts 260a among the multiple first contacts 260a. Similarly, it is preferable that the distance between the centers of two adjacent fourth contacts 160b among the multiple fourth contacts 160b is smaller than the distance between the centers of two adjacent third contacts 260b among the multiple third contacts 260b. With this relationship between the center distances, as described above, steps on the insulating layer 224 can be effectively eliminated by thinning.

[0084] Furthermore, as shown in Figure 10, each of the multiple second contacts 162 has a second column portion 1621 and a second upper portion 1622. The planar area of ​​the second upper portion 1622 is larger than that of the second column portion 1621. Having such a second upper portion 1622 makes it easier to establish electrical conductivity between the second contact 162 and the fourth contact 164. In other words, the second upper portion 1622 can function as an intermediate electrode.

[0085] Similarly, multiple second contacts 161 have a second column portion 1611 and a second upper portion 1612. Therefore, the same effects as those of the second contact 162 are achieved with respect to the second contacts 161.

[0086] Furthermore, as shown in Figure 10, each of the multiple first contacts 262 has a first column portion 2621 and a first upper portion 2622. The planar area of ​​the first upper portion 2622 is larger than that of the first column portion 2621. Having such a first upper portion 2622 makes it easier to establish electrical conductivity between the first contact 262 and the third contact 264. In other words, the first upper portion 2622 can function as an intermediate electrode.

[0087] Similarly, each of the multiple first contacts 261 has a first column portion 2611 and a first upper portion 2612. Therefore, the first contacts 261 exhibit the same effects as the first contacts 262.

[0088] The arrangement density of the second upper parts 1612 and 1622 is greater than the arrangement density of the first upper parts 2612 and 2622. With this configuration, a global step can be provided in the insulating layer 223 such that the peripheral region A20 of the insulating layer 223 is raised above the pixel region A10 of the insulating layer 223.

[0089] Furthermore, as shown in Figure 10, each of the four fourth contacts 164 has a fourth column portion 1641 and a fourth upper portion 1642. The planar area of ​​the fourth upper portion 1642 is larger than that of the fourth column portion 1641. Having such a fourth upper portion 1642 makes it easier to establish electrical conductivity between the fourth contact 164 and the contacts located above it. In other words, the fourth upper portion 1642 can function as a relay electrode.

[0090] Similarly, multiple fourth contacts 163 have a fourth column portion 1631 and a fourth upper portion 1632. Therefore, the same effects as those of the fourth contact 164 are achieved with respect to the fourth contacts 163.

[0091] Furthermore, as shown in Figure 10, each of the multiple third contacts 264 has a third column portion 2641 and a third upper portion 2642. The planar area of ​​the third upper portion 2642 is larger than that of the third column portion 2641. Having such a third upper portion 2642 makes it easier to establish electrical conductivity between the third contact 264 and the contacts located above it. In other words, the third upper portion 2642 can function as an intermediate electrode.

[0092] Similarly, multiple third contacts 263 have a third column portion 2631 and a third upper portion 2632. Therefore, the same effects as those of the third contact 264 are achieved with respect to the third contacts 263.

[0093] The arrangement density of the fourth upper parts 1632 and 1642 is greater than that of the third upper parts 2632 and 2642. This configuration allows the step on the upper surface of the insulating layer 224 to be eliminated by thinning.

[0094] Furthermore, because thinning is used, the thickness of the fourth upper section 1642 along the Z-axis is thinner than the respective thicknesses of the third upper sections 2642 and 2632 along the Z-axis. Similarly, the thickness of the fourth upper section 1632 along the Z-axis is thinner than the respective thicknesses of the third upper sections 2642 and 2632 along the Z-axis.

[0095] Furthermore, each third contact 260b is plug-shaped and embedded in a through-hole formed in the insulating layer 224. Similarly, each fourth contact 160b is plug-shaped and embedded in a through-hole formed in the insulating layer 223. As mentioned above, the plug shape of the third contact 260b and the fourth contact 160b makes it easier to eliminate global steps in the insulating layer 224 by thinning. Also, because they are plug-shaped, it is easier to achieve high precision compared to the case where they are trench-shaped and arranged along the wall surface constituting the through-hole.

[0096] Furthermore, it is preferable that each third contact 260b contains tungsten. Similarly, it is preferable that each fourth contact 160b contains tungsten. The inclusion of tungsten in the third contact 260b and the fourth contact 160b can improve the embedding ability of the through-holes.

[0097] Furthermore, the insulating layer 224 is preferably an inorganic material containing silicon, such as silicon oxide and silicon oxynitride. Including such a material makes it easier to induce thinning due to the difference in polishing speed during CMP, etc., with the fourth contact 160b which contains tungsten. Therefore, the global step can be eliminated by utilizing the thinning.

[0098] Furthermore, the difference in arrangement density between the multiple first contacts 260a and the multiple second contacts 160a is not particularly limited. Similarly, the difference in arrangement density between the multiple third contacts 260b and the multiple fourth contacts 160b is not particularly limited. It can be set appropriately according to the amount of the global step and the thinning amount.

[0099] B. Variations The embodiments illustrated above can be modified in various ways. Specific examples of modifications that can be applied to the aforementioned embodiments are given below. Two or more embodiments arbitrarily selected from the following examples can be combined as appropriate, to the extent that they do not contradict each other.

[0100] B1. First variation Figure 18 is a cross-sectional view showing the fourth contact 160b and conductive portion 169 in the first modified example. As shown in Figure 18, the insulating layer 224 is provided with a conductive portion 169. The conductive portion 169 corresponds to the "fourth conductive portion". Therefore, in this modified example, the "multiple fourth conductive portions" include the fourth contact 160b and the conductive portion 169. Also, the conductive portion 169 is at a different potential than the fourth contact 160b. In this modified example, the conductive portion 169 is in a floating state. The conductive portion 169 is provided at the same position as the fourth upper portion 1642 in the Z-axis. The conductive portion 169, like the fourth upper portion 1642, is a flat plate extending in the XY plane.

[0101] The conductive portion 169 is provided for adjusting the thinning amount. If the desired thinning amount cannot be obtained with the fourth contact 160b alone, the arrangement density of the "multiple fourth conductive portions" can be adjusted by providing the conductive portion 169. Therefore, global steps can be effectively eliminated by utilizing thinning.

[0102] B2. Second variation Figure 19 is a cross-sectional view showing the fourth contact 160b and the conductive part 169A in the second modified example. As shown in Figure 19, the conductive part 169A is provided. Unlike the conductive part 169 in the first modified example, the conductive part 169A is connected to a relay electrode 168 which is located above the conductive part 169A. The conductive part 169A is at a different potential than the fourth contact 160b. For example, the conductive part 169A is at the power supply potential or the reference potential. The reference potential is the potential that serves as the reference for the potential supplied to each pixel P.

[0103] With this conductive portion 169A, global steps can be effectively eliminated by using thinning.

[0104] B3. Third Variation Figure 20 is a cross-sectional view showing the first contact 260a and the second contact 160a of the third modified example. In Figure 20, the upper surface of the insulating layer 223 has a step. In this modified example, the upper surfaces of the multiple second contacts 160a are located below the upper surfaces of the multiple first contacts 260a. In addition, a portion of the second contacts 160a is exposed above the insulating layer 223.

[0105] Figure 21 is a diagram illustrating the manufacturing method of the first contact 260a and the second contact 160a shown in Figure 20. Figure 22 is a diagram illustrating the manufacturing method of the insulating layer 223 shown in Figure 20.

[0106] In the first embodiment described above, the global step in the insulating layer 223 caused by the difference in the arrangement density of the first contact 260a and the second contact 160a is eliminated, and the step on the upper surface of the insulating layer 224 is eliminated by the difference in the amount of thinning caused by the difference in the arrangement density of the third contact 260b and the fourth contact 160b. In contrast, in this modified example, the step on the upper surface of the insulating layer 224 is eliminated by utilizing thinning during the manufacturing of multiple second contacts 160a and multiple first contacts 260a, taking into account the global step in the film formation of the insulating layer 224.

[0107] As shown in Figure 21, a step is created on the upper surface of the insulating layer 223 due to the difference in thinning amount caused by the difference in the arrangement density of the first contact 260a and the second contact 160a. For this reason, for example, a part of the second upper part 1622 is removed by CMP or the like. After the planarization treatment by CMP or the like, a part of the second upper part 1622 and the first upper part 2622 are formed. Then, as shown in Figure 22, the insulating layer 224 is deposited. At this time, the step on the upper surface of the insulating layer 224 is eliminated by the global step of the insulating layer 224 caused by the difference in arrangement density of the third contact 260b and the fourth contact 160b.

[0108] In this modified example, as in the first embodiment, the arrangement density of the multiple second contacts 160a is greater than the arrangement density of the multiple first contacts 260a. Therefore, considering the global step difference in the deposition of the insulating layer 224, thinning is used during the manufacturing of the multiple second contacts 160a and the multiple first contacts 260a. As a result, the step difference on the upper surface of the insulating layer 224 can be eliminated. Thus, in this modified example, as in the first embodiment, the risk of poor conductivity due to the third contact 260b and the fourth contact 160b can be reduced. Therefore, the reliability of the electro-optical device 100 can be improved.

[0109] B4. Other variations In the embodiments described above, an active-matrix electro-optical device 100 is exemplified, but the device is not limited thereto, and the driving method of the electro-optical device 100 may be, for example, a passive-matrix method.

[0110] The driving method for the "electro-optical device" is not limited to a longitudinal electric field method, but may also be a transverse electric field method. An example of a transverse electric field method is the IPS (In Plane Switching) mode. Examples of longitudinal electric field methods include the TN (Twisted Nematic) mode, VA (Vertical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode.

[0111] C.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0112] Figure 23 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main unit 2010 in which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0113] Figure 24 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0114] Figure 25 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. Electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b, corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and memory, and controls the operation of the electro-optical devices 100.

[0115] The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is the light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator, such as a light bulb, that modulates the monochromatic light supplied from the illumination optical system 4001 according to the displayed image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0116] The above electronic device comprises the aforementioned electro-optical device 100 and control units 2003, 3002, or 4005. The aforementioned electro-optical device 100 is highly reliable. Therefore, by including the electro-optical device 100, it is possible to provide a highly reliable personal computer 2000, smartphone 3000, or projection display device 4000.

[0117] Furthermore, the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices, but include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of Sale) terminals. In addition, electronic devices to which the present invention is applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0118] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added.

[0119] Furthermore, while the above description described a liquid crystal display device as an example of the electro-optical device of the present invention, the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to image sensors and the like. [Explanation of symbols]

[0120] 21...Element substrate, 10...Peripheral circuit, 11...Scan line drive circuit, 12...Data line drive circuit, 13...External terminal, 14...Test circuit, 15...Transistor, 16...Sampling circuit, 23...Transistor, 25...Pixel electrode, 26...First contact, 27...First contact, 100...Electro-optic device, 151...Semiconductor layer, 152...Gate electrode, 160a...Second contact, 160b...Fourth contact, 161...Second contact, 162...Second contact, 163...Fourth contact, 164...Fourth contact, 169...Conductive part, 223...Insulating layer (first insulating layer), 224...Insulating layer (second insulating layer), 231...Semiconductor layer, 232...Gate electrode, 233...Gate insulating film, 241...Scanning 1631…2nd column, 1632…2nd upper section, 1631…2nd column, 1632…2nd upper section, 1631…4th column, 1632…4th upper section, 1631…2nd column, 1632…4th upper section, 16 41...Fourth column section, 1642...Fourth upper section, 2611...First column section, 2612...First upper section, 2621...First column section, 2622...First upper section, 2631...Third column section, 2632...Third upper section, 2641...Third column section, 2642...Third upper section, A10...Pixel area, A20...Peripheral area, P...Pixel, S1a...Area, S1b...Area, S2a...Area, S2b...Area.

Claims

1. An electro-optical device having a pixel region having pixel electrodes and a peripheral region located around the pixel region, circuit board and A plurality of first transistors located in the aforementioned pixel region, Multiple second transistors located in the aforementioned peripheral region, A first insulating layer provided on the upper layer of the first transistor and the second transistor, A plurality of first conductive portions located in the pixel region and provided within the first insulating layer, spaced apart from each other, A plurality of second conductive portions located in the peripheral region and provided within the first insulating layer, spaced apart from each other, Equipped with, In a plan view of the substrate in the thickness direction, the arrangement density of the plurality of second conductive parts in the region occupied by the plurality of second conductive parts is greater than the arrangement density of the plurality of first conductive parts in the region occupied by the plurality of first conductive parts. An electro-optical apparatus characterized by the following features.

2. The plurality of second conductive portions include a plurality of second contacts provided corresponding to the plurality of second transistors, The plurality of second contacts include a second column portion and a second upper portion located above the second column portion and having a larger planar area than the planar area of ​​the second column portion. The electro-optical apparatus according to claim 1.

3. The plurality of first conductive portions include a plurality of first contacts provided corresponding to the plurality of second contacts, The plurality of first contacts include a first column portion and a first upper portion located above the first column portion and having a larger planar area than the planar area of ​​the first column portion. The arrangement density of the second upper part is greater than the arrangement density of the first upper part. The electro-optical apparatus according to claim 2.

4. A second insulating layer is provided in contact with the first insulating layer and on top of the first insulating layer, A plurality of third conductive portions located in the pixel region and provided within the second insulating layer, spaced apart from each other, A plurality of fourth conductive portions located in the peripheral region and provided within the second insulating layer, spaced apart from each other, In a plan view of the substrate in the thickness direction, the arrangement density of the plurality of fourth conductive parts in the region occupied by the plurality of fourth conductive parts is greater than the arrangement density of the plurality of third conductive parts in the region occupied by the plurality of third conductive parts. The electro-optical apparatus according to claim 1.

5. The plurality of fourth conductive portions include a plurality of fourth contacts provided corresponding to the plurality of second conductive portions. The plurality of fourth contacts include a fourth column portion and a fourth upper portion located above the fourth column portion and having a larger surface area than the surface area of ​​the fourth column portion. The electro-optical apparatus according to claim 4.

6. The plurality of third conductive parts include a plurality of third contacts provided corresponding to the plurality of first conductive parts. The plurality of third contacts include a third column portion and a third upper portion located above the third column portion and having a larger planar area than the planar area of ​​the third column portion. The arrangement density of the fourth upper part is greater than the arrangement density of the third upper part. The electro-optical apparatus according to claim 5.

7. The plurality of fourth conductive parts further include a plurality of conductive parts having a different potential from the fourth contact. The electro-optical apparatus according to claim 5.

8. Each of the plurality of third conductive parts is embedded in a through hole formed in the second insulating layer. Each of the plurality of fourth conductive parts is embedded in a through hole formed in the second insulating layer. The electro-optical apparatus according to claim 5.

9. Each of the plurality of third conductive parts contains tungsten, Each of the aforementioned plurality of fourth conductive parts contains tungsten, The electro-optical apparatus according to claim 8.

10. The second insulating layer is an inorganic material containing silicon. The electro-optical apparatus according to claim 9.

11. The electro-optical apparatus described in claim 1, An electronic device characterized by having a control unit that controls the operation of the electro-optical device.

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