Manufacturing method of wiring devices

Abstract

The present invention provides a method for manufacturing wiring devices that can improve performance. [Solution] A method for manufacturing a wiring device, comprising the steps of: preparing a substrate; forming a first insulating layer on the upper surface of the substrate; removing a part of the first insulating layer to form a groove; forming a first conductor layer so as to fill the groove of the first insulating layer; and cutting a part of the first insulating layer and a part of the first conductor layer to form a first wiring layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring device.

Background Art

[0002] In recent years, there is a technology called chiplet integration, in which the functions of a semiconductor chip are divided into a plurality of chips (chiplets), and they are combined into one module. Thereby, a high-performance chip module is configured and provided.

[0003] In order to realize chiplet integration, studies are being conducted on the structure of chip modules and on interposers, bridge chips, etc. for connection.

[0004] For example, Patent Document 1 (U.S. Patent Application Publication No. 2021 / 0005542) describes a module structure using a bridge for connecting between chips and wiring.

[0005] Patent Document 2 (International Publication No. 2023 / 022179) describes a module structure using a bridge, a PSB (Pillar Suspended Bridge) structure and a manufacturing method that have a simpler structure and can connect between chips with higher precision.

[0006] Patent Document 3 (Japanese Patent Laid-Open No. 2012-060100) uses an insulating layer having grooves similar to the damascene process, and a first film formation is performed on this groove portion with a metal such as Ti, Cr, Ta, and Pd, and a second film formation is performed with a metal such as copper having a lower hardness than that. A method of performing planarization by arranging a cutting edge at a place where the first metal film is naturally interrupted and performing cutting with the cutting edge instead of CMP (Chemical Mechanical Polishing) is described.

[0007] Patent document 4 (International Publication No. 2017 / 038110) describes a manufacturing method in which an organic material is used to create a rectangular panel-shaped organic substrate with an insulating layer having grooves similar to those of the damascene method, wiring is formed by embedding copper paste in the grooves, and planarization is performed by fly cutting rather than CMP.

[0008] Patent Document 5 (International Publication No. 2017 / 163743) describes a manufacturing method in which an organic material is used in an insulating layer having grooves similar to those of the damascene method to produce a rectangular panel-shaped organic substrate, a first barrier layer made of a metal, one of Ti, Ni, Pd, Cr, Ta, W, and Au, is formed on the side walls and bottom surfaces of the grooves, the grooves are filled with metal plating such as copper to form wiring, the substrate is planarized by CMP or fly cutting, and a second barrier layer is formed on the upper surface of the wiring by electroplating of a metal such as Ni. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0005542 [Patent Document 2] International Publication No. 2023 / 022179 [Patent Document 3] Japanese Patent Publication No. 2012-060100 [Patent Document 4] International Publication No. 2017 / 038110 [Patent Document 5] International Publication No. 2017 / 163743 [Overview of the project] [Problems that the invention aims to solve]

[0010] The performance of the wiring devices needs to be further improved. [Means for solving the problem]

[0011] A method for manufacturing a wiring device according to one embodiment comprises: (a) a step of preparing a substrate; (b) a step of forming a first insulating layer on the upper surface of the substrate; (c) a step of removing a part of the first insulating layer to form a groove; (d) a step of forming a first conductor layer so as to fill the groove of the first insulating layer; and (e) a step of cutting a part of the first insulating layer and a part of the first conductor layer to form a first wiring layer. [Effects of the Invention]

[0012] According to the above embodiment, a method for manufacturing a wiring device that can improve performance can be provided. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment. [Figure 2] Figure 2 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 1. [Figure 3] Figure 3 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment, following Figure 2. [Figure 4] Figure 4 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 3. [Figure 5] Figure 5 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 4. [Figure 6] Figure 6 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 5. [Figure 7] Figure 7 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 6. [Figure 8] Figure 8 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 7. [Figure 9] Figure 9 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment, following Figure 8. [Figure 10] Figure 10 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment following Figure 9. [Figure 11] Figure 11 is an enlarged view of the steps of the manufacturing method of the wiring device shown in FIG. 2. [Figure 12] Figure 12 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment. [Figure 13] Figure 13 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 12. [Figure 14] Figure 14 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 13. [Figure 15] Figure 15 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 14. [Figure 16] Figure 16 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 15. [Figure 17] Figure 17 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 16. [Figure 18] Figure 18 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 17. [Figure 19] Figure 19 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 18. [Figure 20] Figure 20 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 19. [Figure 21] Figure 21 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 20. [Figure 22] Figure 22 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 21. [Figure 23] Figure 23 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 22. [Figure 24] Figure 24 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 23. [Figure 25] Figure 25 is a cross-sectional view showing the steps of the manufacturing method of the wiring device according to another embodiment following FIG. 24. [Figure 26] Figure 26 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 25. [Figure 27] Figure 27 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 26. [Figure 28] Figure 28 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 27. [Figure 29] Figure 29 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 28. [Figure 30] Figure 30 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 29. [Figure 31] Figure 31 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 30. [Figure 32] Figure 32 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 31. [Figure 33] Figure 33 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment following Figure 32. [Figure 34] Figure 34 is a cross-sectional view showing the steps of a semiconductor device manufacturing method according to one embodiment. [Figure 35] Figure 35 is a cross-sectional view of a wiring device according to one embodiment. [Figure 36] Figure 36 is an enlarged view of the wiring device shown in Figure 35. [Figure 37] Figure 37 is a cross-sectional view showing a wiring device according to another embodiment. [Figure 38] Figure 38 is a plan view of the wiring device shown in Figure 37. [Figure 39] Figure 39 is a cross-sectional view showing a wiring device according to another embodiment. [Figure 40] Figure 40 is a cross-sectional view showing a wiring device according to another embodiment. [Figure 41] Figure 41 is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 42]Figure 42 is an enlarged view of the semiconductor device shown in Figure 41. [Modes for carrying out the invention]

[0014] First, let's explain the challenges of the background technology. Modules using chiplet integration technology require wiring chips to bridge multiple chips together. Wiring chips require multiple layers of fine wiring to be stacked on the chip to form the wiring layer. Methods for manufacturing wiring include SAP (Semi Additive Process) and damascene incorporation.

[0015] The SAP method involves forming a thin metal film on a substrate to serve as a seed layer for electroplating, creating a resist layer with openings in the areas where wiring will be formed, forming metal conductive wiring in the openings by electroplating, removing the resist layer, and then removing the seed layer remaining outside the wiring areas by etching.

[0016] The damascene method is a technique for forming and stacking fine wiring for semiconductor chips. It involves creating grooves in an insulating layer, mainly made of inorganic material, and then embedding metal conductors into these grooves to form the wiring.

[0017] One method used for flattening the surface when performing the damascene method is the CMP (Chemical Mechanical Polishing) method. The CMP method is a method of polishing the surface of the wiring layer after embedding metal conductors using a slurry or chemical solution that acts as an abrasive.

[0018] The CMP (Chemical Polishing) method requires expensive equipment, slurry materials, and special chemicals. Furthermore, after polishing, numerous steps are required to remove the chemicals and treat the wastewater.

[0019] In the SAP method, when the seed layer is removed by etching, the wiring is also etched at the same time, which can cause the wiring to thin. Therefore, the risk of wire breakage increases, especially with very fine wiring, such as 2 μm in thickness.

[0020] Next, one aspect of the present invention will be described.

[0021] In each figure of the embodiment, identical or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions are generally not repeated.

[0022] Furthermore, in attached drawings, hatching or similar markings may be omitted even in cross-sections if it would make the drawing unnecessarily complicated or if the distinction from voids is clear. In connection with this, background contour lines may be omitted even for holes that are closed in plan view, if it is clear from the explanation, etc. Moreover, hatching or dot patterns may be added even to areas that are not voids or to indicate the boundaries of an area, even if they are not cross-sections.

[0023] <Manufacturing method for wiring devices> First, a method for manufacturing a wiring device according to one embodiment will be described. Figure 1 is a cross-sectional view showing the steps of the method for manufacturing a wiring device according to one embodiment. As shown in Figure 1, the method for manufacturing a wiring device according to this embodiment includes a step of preparing a substrate 20. The substrate 20 has an upper surface 20a. The upper surface 20a of the substrate 20 is a flat surface. The surface roughness of the upper surface 20a of the substrate 20 is, for example, Ra 0.01 μm or more and Ra 0.05 μm or less. In plan view, the substrate 20 is circular. The substrate 20 is, for example, a circular wafer. The substrate 20 is, for example, an inorganic substrate made of silicon or glass.

[0024] In this embodiment, no electronic circuits, such as transistor circuits or integrated circuits, are formed on the substrate 20.

[0025] Figure 2 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 2, the method for manufacturing a wiring device according to this embodiment includes a step of applying an organic insulating material OM1 onto the upper surface 20a of a substrate 20. The organic insulating material OM1 is applied to the upper surface 20a of the substrate 20, for example, by spin coating. The thickness of the organic insulating material OM1 applied to the upper surface 20a of the substrate 20 is, for example, 4 μm or more and 6 μm or less.

[0026] In this embodiment, the organic insulating material OM1 is an insulating resin. Examples of insulating resins include photosensitive liquid insulating resins. The main component of a photosensitive liquid insulating resin is, for example, an organic material such as PBO (polybenzoxazole) or PI (polyimide).

[0027] Figure 3 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 3, the method for manufacturing a wiring device according to this embodiment includes a step of removing a portion of the organic insulating material OM1 to form a groove G1. In this embodiment, a portion of the organic insulating material OM1 applied to the upper surface 20a of the substrate 20 is removed.

[0028] Patterning is one method for removing a portion of the organic insulating material OM1. Specifically, the organic insulating material OM1, which is a photosensitive liquid insulating resin, is exposed using a stepper exposure machine with a photomask. After that, the exposed organic insulating material OM1 is developed and cured to form grooves G1 that will serve as wiring in the organic insulating material OM1. In other words, a portion of the organic insulating material OM1 is removed by exposure and development processes to form grooves G1. In the example shown in Figure 3, multiple grooves G1 are formed. As shown in Figure 3, after a portion of the organic insulating material OM1 is removed, the upper surface 20a of the substrate 20 is exposed from the grooves G1. The grooves G1 are grooves for providing wiring. The width of the grooves G1 is, for example, 2 μm or less. Also, the width of the organic insulating material OM1 sandwiched between adjacent grooves G1 is, for example, 2 μm or less.

[0029] Figure 4 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 4, the method for manufacturing a wiring device according to this embodiment includes a step of forming a seed layer BM1 so as to cover the organic insulating material OM1. As shown in Figure 4, the seed layer BM1 is formed after removing a portion of the organic insulating material OM1. The seed layer BM1 is formed so as to cover the organic insulating material OM1 and the upper surface 20a of the substrate 20. The seed layer BM1 functions as a barrier metal. The step of forming the seed layer BM1 is not essential.

[0030] The seed layer BM1 is made of metal. At least one of Ti, Ni, and Cu can be used as the metal constituting the seed layer BM1. Furthermore, the seed layer BM1 is a single layer of Ti, Ni, or Cu, or a layer constructed by stacking at least two of these layers. For example, sputtering can be used to form the metallic seed layer BM1. The thickness of the seed layer BM1 is, for example, 0.06 μm or less. If the seed layer BM1 includes a Ti layer, the thickness of the Ti layer should be 0.03 μm or less. For example, by forming a 0.02 μm thin film of Ti using sputtering, and then sputtering Cu on top of it, a seed layer BM1 with a combined thickness of 0.05 μm can be formed.

[0031] Figure 5 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 5, the method for manufacturing a wiring device according to this embodiment includes a step of applying a resist FR1 so as to cover the organic insulating material OM1. The resist FR1 is applied so as to cover the organic insulating material OM1 and the upper surface 20a of the substrate 20. In the example shown in Figure 5, the resist FR1 covers the organic insulating material OM1 and the upper surface 20a of the substrate 20 via a seed layer BM1. In this embodiment, the resist FR1 is a photoresist. A method for applying the resist FR1 is spin coating.

[0032] Figure 6 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 6, the method for manufacturing a wiring device according to this embodiment includes a step of removing a portion of the resist FR1 to expose the grooves G1 of the organic insulating material OM1. After removing a portion of the resist FR1, the resist FR1 covers the upper surface 20a of the substrate 20, which will become the dicing street DS. As shown in Figure 6, the dicing street DS is a portion of the upper surface 20a of the substrate 20. Also, after removing a portion of the resist FR1, the grooves G1 of the organic insulating material OM1 are exposed from the resist FR1. Patterning is one method for removing the resist FR1.

[0033] Figure 7 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 7, the method for manufacturing a wiring device according to this embodiment includes the step of forming a conductor layer ML1 so as to fill the grooves G1 of the organic insulating material OM1. The height of the formed conductor layer ML1 is greater than the height of the organic insulating material OM1. The difference between the height of the conductor layer ML1 and the height of the organic insulating material OM1 is, for example, 1 μm or more and 10 μm or less. In this embodiment, the height of the conductor layer ML1 is the height from the upper surface 20a of the substrate 20. As shown in Figure 7, the conductor layer ML1 is formed so as to cover the organic insulating material OM1. Also, the height of the formed conductor layer ML1 is less than the height of the resist FR1.

[0034] One method for forming the conductive layer ML1 is electroplating. In the example shown in Figure 7, the seed layer BM1 is used as the seed layer for electroplating. The metal constituting the conductive layer ML1 is, for example, Cu.

[0035] Figure 8 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 8, the method for manufacturing a wiring device according to this embodiment includes a step of removing the resist FR1 to expose the upper surface 20a of the substrate 20. The resist FR1 covering the upper surface 20a of the substrate 20, which will become the dicing street DS, is removed. This removes all of the resist FR1. One method for removing the resist FR1 is to use a stripping agent.

[0036] Even after removing the resist FR1, the upper surface 20a of the substrate 20, which will become the dicing street DS, is covered by the seed layer BM1. Therefore, the seed layer BM1, which is exposed after removing the resist FR1, is removed. After removing the seed layer BM1, the upper surface 20a of the substrate 20, which will become the dicing street DS, is exposed from the organic insulating material OM1, the conductive layer ML1, and the seed layer BM1. Etching is one method for removing the seed layer BM1.

[0037] Figure 9 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to one embodiment. Figure 9 shows the state during the cutting process using the cutting blade 80. Figure 9 also schematically shows an example of the direction in which the substrate 20 is moved using arrows. As shown in Figure 9, the manufacturing method for a wiring device according to this embodiment includes a step of cutting a part of the conductor layer ML1 and a part of the organic insulating material OM1 using the cutting blade 80. After cutting, the remaining conductor layer ML1 becomes the wiring. Also, after cutting, the remaining organic insulating material OM1 becomes an organic insulating layer for insulating the wiring from each other.

[0038] One method of cutting is the planing method. The planing method is a cutting method in which a non-rotating cutting blade 80 is used, and either the cutting blade 80 or the substrate 20 to be cut is moved linearly and brought into contact with it. Specifically, there are four methods of planing: In the first method, cutting is performed by moving the substrate 20 linearly and bringing it into contact with the fixed cutting blade 80. In the second method, cutting is performed by moving the cutting blade 80 linearly and bringing it into contact with the fixed substrate 20. In the third method, cutting is performed by rotating the substrate 20 and bringing it into contact with the fixed cutting blade 80. In the fourth method, the cutting blade 80 is fixed to a turntable larger than the substrate 20, and cutting is performed by moving the substrate 20 linearly and bringing it into contact with the cutting blade 80 while the turntable is rotating. In the fourth method, the cutting blade 80 cuts while drawing an arc trajectory. However, in each region of the substrate 20 that forms the wiring device, the cutting can be described as a curve that is close to a straight line.

[0039] By cutting, the organic insulating material OM1, which was covered by the conductive layer ML1, is exposed. After cutting, the height of the organic insulating material OM1 is, for example, 2 μm or less. Also, after cutting, the height from the upper surface 20a of the substrate 20 to the upper surface ML1a of the conductive layer ML1 is, for example, 2 μm or less. By cutting, the upper surface ML1a of the conductive layer ML1 and the upper surface OM1a of the organic insulating material OM1 are flattened. After cutting, the upper surface OM1a of the organic insulating material OM1 and the upper surface ML1a of the conductive layer ML1 are located on the same plane. Also, after cutting, the surface roughness of the surface including the upper surface OM1a of the organic insulating material OM1 and the upper surface ML1a of the conductive layer ML1 is, for example, Ra 0.01 μm or more and Ra 0.05 μm or less.

[0040] When a portion of the seed layer BM1 is removed by cutting, the organic insulating material OM1 is exposed. As a result, the upper surface OM1a of the organic insulating material OM1, the upper surface ML1a of the conductor layer ML1, and the exposed surface of the seed layer BM1 are located on the same plane. Furthermore, after cutting, the surface roughness of the surface including the upper surface OM1a of the organic insulating material OM1, the upper surface ML1a of the conductor layer ML1, and the exposed surface of the seed layer BM1 is, for example, Ra 0.01 μm or more and Ra 0.05 μm or less.

[0041] Incidentally, one method for cutting a portion of the conductive layer ML1 and a portion of the organic insulating material OM1 involves pressing a rotating cutting blade against the workpiece to perform the cutting process. This type of cutting method is called fly cutting or milling, and it differs from the cutting method in this embodiment in that the cutting blade is rotated. When cutting is performed by milling, the rotating cutting blade forms rough machining marks that resemble a series of circles.

[0042] When a cutting blade is rotated and pressed against a workpiece, the cutting resistance increases. Furthermore, this, combined with increased heat generation, increases the residual stress remaining in the workpiece, causing warping and distortion. On the other hand, according to this embodiment, the cutting blade 80 itself is not rotated, but the cutting blade 80 and the substrate 20 are brought into contact by linear movement to perform the cutting process. In this case, the value of residual stress in the workpiece can be reduced. As a result, warping deformation or distortion of the substrate 20 after cutting can be suppressed.

[0043] The shavings produced by planing are similar to those of a wood shaving. Therefore, removing the shavings is easier than removing the slurry or special chemicals that remain on the surface of the wiring device when using the CMP method. Also, because the shavings themselves are large, shavings are less likely to accumulate even when grinding is performed with the upper surface 20a of the substrate 20, which will become the dicing street DS, exposed.

[0044] Figure 10 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to one embodiment. As shown in Figure 10, the method for manufacturing a wiring device according to this embodiment includes a step of cutting the dicing street DS, which is the portion of the upper surface 20a of the substrate 20 that is exposed. By cutting the dicing street DS, the wiring device can be made into individual pieces. In the example shown in Figure 10, a blade 90 is used to perform the cutting.

[0045] As shown in Figure 10, a portion of the dicing street DS remains even after cutting. In other words, a portion of the upper surface 20a of the substrate 20 remains exposed from the conductor layer ML1, the organic insulating material OM1, and the seed layer BM1. After cutting, the side surface 20c of the substrate 20 is formed. After cutting, a stepped portion 70 is formed by the substrate 20 and the organic insulating material OM1.

[0046] Next, the effects of the manufacturing method for the wiring device according to this embodiment will be described. The manufacturing method for the wiring device according to this embodiment includes a step of cutting the portion of the upper surface 20a of the substrate 20 that is exposed. Even after cutting, a portion of the upper surface 20a of the substrate 20 remains uncut. As a result, a stepped portion 70 is formed by the substrate 20 and the organic insulating material OM1. Therefore, when the wiring device is sealed with an encapsulant such as resin, the contact area between the encapsulant and the wiring device can be increased. As a result, the encapsulant and the wiring device can be strongly bonded. Therefore, the mounting reliability of the wiring device can be improved.

[0047] Furthermore, since the cutting is performed on the exposed portion of the upper surface 20a of the substrate 20, the blade 90 does not cut the conductor layer ML1 and the seed layer BM1 during cutting. Because the metal parts are not cut, cutting is easy and less stress is applied to the substrate 20. In addition, since no minute metal powder is generated by dicing the metal parts, the reduction in cutting force due to metal powder adhering to the blade 90 is less likely to occur.

[0048] In the manufacturing method of the wiring device according to this embodiment, the upper surface ML1a of the conductor layer ML1 and the upper surface OM1a of the organic insulating material OM1 are flattened by cutting a part of the conductor layer ML1 and a part of the organic insulating material OM1 using a cutting blade 80. As a result, the upper surface ML1a of the conductor layer ML1 and the upper surface OM1a of the organic insulating material OM1 are substantially on the same plane and are flat. This makes it possible to reduce variations in the thickness of the wiring formed on top of the conductor layer ML1 and the organic insulating material OM1. As a result, even if the wiring formed on top is thin, it is possible to prevent the wiring from breaking.

[0049] As explained earlier, CMP (Chemical Polishing) can be used to planarize the organic insulating material OM1 and the conductive layer ML1. However, CMP requires expensive equipment and slurry materials, as well as the control of complex processing conditions.

[0050] The manufacturing method for the wiring device according to this embodiment involves removing and planarizing a portion of the conductor layer ML1 and the organic insulating material OM1 by cutting. Therefore, it does not require CMP, which requires expensive materials and equipment, as well as complex processes and processing conditions. As a result, planarization can be performed at a low cost.

[0051] Next, other effects of the manufacturing method of the wiring device according to this embodiment will be described. In the SAP method, a thin metal film that serves as a seed layer BM1 is provided in the wiring section. Excess seed layer BM1 is removed by etching after the resist FR1 has been removed and the wiring is exposed. However, since the wiring is also affected by the etching process and dissolves, the possibility of wiring breakage increases.

[0052] On the other hand, in the manufacturing method of the wiring device according to this embodiment, a portion of the seed layer BM1 is removed using a cutting blade 80 to insulate adjacent conductor layers ML1. Furthermore, when the seed layer BM1 on the dicing street DS is removed by etching, the sides of the conductor layer ML1 are sealed with an organic insulating material OM1. Therefore, the conductor layer ML1 that forms the wiring is less affected by the etching process. Thus, even with thin wiring such as 2 μm or less, disconnections due to the etching process are less likely to occur.

[0053] Next, modified examples of the manufacturing method of the wiring device according to this embodiment and their effects will be described.

[0054] In the manufacturing method of the wiring device according to this embodiment, it is preferable that the substrate 20 does not have an electronic circuit provided on it.

[0055] One possible approach is to use a wafer on which transistor circuits and integrated circuits for semiconductor chips are formed as a substrate for creating wiring. However, electrodes and polyimide layers are formed on the surface of the semiconductor chip, creating steps. Therefore, when stacking fine wiring on the surface of the semiconductor chip to form a wiring layer, the underside of the insulating layer formed directly above the semiconductor chip may not be flat. As a result, variations in the thickness of the insulating layer are more likely to occur. This can lead to problems when processing the insulating layer and wiring layer to be thin.

[0056] In the manufacturing method of the wiring device according to this embodiment, since no electronic circuits are provided on the substrate 20, the upper surface 20a of the substrate 20 can be made flat. Therefore, variations in the thickness of the organic insulating material OM1 and the conductor layer ML1 can be further reduced.

[0057] The thickness of the seed layer BM1 is preferably 0.06 μm or less. Furthermore, if the seed layer BM1 includes a Ti layer, the thickness of the Ti layer is preferably 0.03 μm or less. This reduces the load on the cutting blade 80 and suppresses wear.

[0058] Figure 11 is an enlarged view of the groove portion of the organic insulating material shown in Figure 2. As shown in Figure 11, it is preferable that the side wall G1c of the groove portion G1 of the organic insulating material OM1 is tapered. The width of the groove portion G1 increases as it moves away from the upper surface 20a of the substrate 20. The angle α formed by the side wall G1c of the groove portion G1 and the bottom portion OM1b of the organic insulating material OM1 is preferably 80° or more and less than 90°.

[0059] When the side wall G1c of the groove G1 is perpendicular to the upper surface 20a of the substrate 20, the film may not adhere as well to the vertical side wall G1c of the groove G1 compared to the flat side wall G1b of the groove G1. For example, when attempting to form a seed layer BM1 by sputtering, the thickness of the seed layer BM1 on the vertical side wall G1c of the groove G1 may be smaller than that on the flat side wall G1b of the groove G1. Therefore, in order to form a seed layer BM1 of the required thickness on both the flat side wall G1b and the side wall G1c of the groove G1, it is necessary to form the seed layer BM1 to a certain thickness.

[0060] However, when using a hard metal such as Ti as the seed layer BM1 for machining, if the thickness of the seed layer BM1 is large, the load on the cutting blade 80 may increase. This can make machining difficult and shorten the lifespan of the cutting blade 80.

[0061] When the angle α between the side wall G1c of the groove G1 and the bottom OM1b of the organic insulating material OM1 is less than 90°, when attempting to form the seed layer BM1 by sputtering, the film is more likely to adhere to the side wall G1c of the groove G1, and the seed layer BM1 can be made thinner when forming the seed layer BM1 of the required thickness. When the angle α between the side wall G1c of the groove G1 and the bottom OM1b of the organic insulating material OM1 is 80° or more, the difference in dimensions between the width of the upper part of the wiring formed in the groove G1 and the width of the lower part of the wiring can be reduced.

[0062] In the manufacturing method of the wiring device according to this embodiment, the thickness of the organic insulating material OM1 after cutting is preferably 2 μm or less. Furthermore, the height from the upper surface 20a of the substrate 20 to the upper surface ML1a of the conductor layer ML1 is preferably 2 μm or less. This makes it possible to make the aspect ratio of the wiring 1 or less, even when the width of the conductor layer ML1 that forms the wiring is 2 μm or less.

[0063] Furthermore, if a taper is provided on the side wall G1c of the groove G1 of the organic insulating material OM1, the greater the thickness of the conductor layer ML1 embedded in the groove, the greater the difference in width between the upper surface ML1a and the lower surface ML1b of the conductor layer ML1 may become. However, if the height from the upper surface 20a of the substrate 20 to the upper surface ML1a of the conductor layer ML1 is 2 μm or less, even if a taper is provided on the side wall G1c of the groove G1 of the organic insulating material OM1, the difference in width between the upper surface ML1a and the lower surface ML1b of the conductor layer ML1 can be reduced. In addition, even if the spacing between adjacent grooves G1 of the organic insulating material OM1 is reduced to 2 μm or less in order to shorten the wiring spacing, the difference in vertical width of the organic insulating material OM1 between adjacent grooves G1 can be reduced. As a result, high-precision wiring can be formed.

[0064] In this embodiment, a method of applying the organic insulating material OM1 using a liquid resin and spin-coating it is illustrated, but this can be modified to a method of laminating the organic insulating material OM1 using a film-like material. In this case, even if there are depressions or irregularities such as via holes in the area where the organic insulating material OM1 is to be formed, the organic insulating material OM1 can be formed more flatly. Furthermore, if it is necessary to ensure the required thickness, the film-like material is expected to have the effect of making it easier to ensure the required thickness. In addition, a combination of liquid material and film material can also be used.

[0065] Next, a method for manufacturing a wiring device according to another embodiment will be described. The method for manufacturing a wiring device according to another embodiment is the same as the method for manufacturing a wiring device shown in Figures 1 to 9.

[0066] Figure 12 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 12, after the cutting step shown in Figure 9, the process includes a step of applying an interlayer organic insulating material IM1 onto the conductor layer ML1 and the organic insulating material OM1. The interlayer organic insulating material IM1 is applied so as to cover the conductor layer ML1, the organic insulating material OM1, the seed layer BM1, and the upper surface 20a of the substrate 20. The interlayer organic insulating material IM1 is applied, for example, by spin coating. The height of the applied interlayer organic insulating material IM1 from the upper surface OM1a of the organic insulating material OM1 is, for example, 4 μm or more and 6 μm or less.

[0067] In this embodiment, the interlayer organic insulating material IM1 is an insulating resin. Examples of insulating resins include photosensitive liquid insulating resins. The main component of a photosensitive liquid insulating resin is, for example, an organic material such as PBO (polybenzoxazole) or PI (polyimide). The interlayer organic insulating material IM1 can be made from the same material as the organic insulating material OM1 described above.

[0068] Figure 13 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 13, the manufacturing method for a wiring device according to another embodiment includes the step of removing a portion of the interlayer organic insulating material IM1 to form a through-hole TH1. A portion of the interlayer organic insulating material IM1 is removed so that the conductor layer ML1 is exposed from the through-hole TH1. A portion of the interlayer organic insulating material IM1 is removed so that the upper surface 20a of the substrate 20 is exposed from the interlayer organic insulating material IM1. As shown in Figure 13, after removing a portion of the interlayer organic insulating material IM1, a portion of the conductor layer ML1 is exposed from the interlayer organic insulating material IM1, and a portion of the conductor layer ML1 is covered by the interlayer organic insulating material IM1. Patterning is one method for removing a portion of the interlayer organic insulating material IM1.

[0069] Figure 14 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to another embodiment. As shown in Figure 14, the method for manufacturing a wiring device according to another embodiment includes a step of applying an organic insulating material OM2 so as to cover the interlayer organic insulating material IM1. As shown in Figure 13, the organic insulating material OM2 is applied so as to cover the interlayer organic insulating material IM1, the conductor layer ML1, and the upper surface 20a of the substrate 20. In the example shown in Figure 14, the organic insulating material OM2 is applied so as to fill the through-hole TH1. The organic insulating material OM2 is applied, for example, by spin coating. The height of the applied organic insulating material OM2 from above the interlayer organic insulating material IM1 is, for example, 4 μm or more and 6 μm or less. The organic insulating material OM2 can be made from the same material as the interlayer organic insulating material IM1.

[0070] Figure 15 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to another embodiment. As shown in Figure 15, the method for manufacturing a wiring device according to another embodiment includes a step of removing a portion of the organic insulating material OM2 so that the penetration portion TH1 of the interlayer organic insulating material IM1 is exposed from the organic insulating material OM2, thereby forming a groove G2. As shown in Figure 15, multiple grooves G2 are formed.

[0071] As shown in Figure 15, after removing a portion of the organic insulating material OM2, the penetration portion TH1 of the interlayer organic insulating material IM1 is connected to the groove portion G2 of the organic insulating material OM2. Also, after removing a portion of the organic insulating material OM2, the interlayer organic insulating material IM1 is exposed from the groove portion G2 of the organic insulating material OM2. Furthermore, after removing a portion of the organic insulating material OM2, the upper surface 20a of the substrate 20 is exposed from the organic insulating material OM2. The method for removing a portion of the organic insulating material OM2 is the same as the method for removing a portion of the interlayer organic insulating material IM1.

[0072] Figure 16 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 16, the manufacturing method for a wiring device according to another embodiment includes the step of forming a seed layer BM2 so as to cover the conductor layer ML1, the interlayer organic insulating material IM1, and the organic insulating material OM2. As shown in Figure 16, the seed layer BM2 is formed so as to cover the upper surface 20a of the substrate 20. The seed layer BM2 functions as a barrier metal. The seed layer BM2 is formed so as to cover the organic insulating material OM2, the interlayer organic insulating material IM1 exposed from the organic insulating material OM2, and the conductor layer ML1 exposed from the interlayer organic insulating material IM1. The step of forming the seed layer BM2 is not essential. The seed layer BM2 can be formed in the same manner as the seed layer BM1.

[0073] Figure 17 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to another embodiment. As shown in Figure 17, the method for manufacturing a wiring device according to another embodiment includes a step of applying resist FR2 so as to cover the organic insulating material OM2. The resist FR2 is applied so as to cover the organic insulating material OM2 and the upper surface 20a of the substrate 20. In the example shown in Figure 17, the resist FR2 covers the organic insulating material OM2 and the upper surface 20a of the substrate 20 via a seed layer BM2. In this embodiment, the resist FR2 is a photoresist. A method for applying the resist FR2 is spin coating.

[0074] Figure 18 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 18, the manufacturing method for a wiring device according to another embodiment includes a step of removing a portion of the resist FR2 to expose the through-holes TH1 of the interlayer organic insulating material IM1 and the grooves G2 of the organic insulating material OM2. A portion of the resist FR2 is removed so as to leave the resist FR2 covering the upper surface 20a of the substrate 20 which will become the dicing street DS. In other words, after removing a portion of the resist FR2, the resist FR2 covers the upper surface 20a of the substrate 20 which will become the dicing street DS. Also, after removing a portion of the resist FR2, the through-holes TH1 of the interlayer organic insulating material IM1 and the grooves G2 of the organic insulating material OM2 are exposed from the resist FR2. In the example shown in Figure 18, a seed layer BM2 is provided on the upper surface 20a of the substrate 20, so after removing a portion of the resist FR2, the resist FR2 covers the upper surface 20a of the substrate 20 via the seed layer BM2. Patterning is one method for removing the resist FR2.

[0075] Figure 19 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 19, the manufacturing method for a wiring device according to another embodiment includes the step of forming a conductor layer ML2 so as to fill the penetration portion TH1 of the interlayer organic insulating material IM1 and the groove portion G2 of the organic insulating material OM2. The height of the formed conductor layer ML2 is greater than the height of the organic insulating material OM2. The difference between the height of the conductor layer ML2 and the height of the organic insulating material OM2 is, for example, 1 μm or more and 10 μm or less. In this embodiment, the height of the conductor layer ML2 is the height from the upper surface 20a of the substrate 20. The height of the organic insulating material OM2 is the height from the upper surface 20a of the substrate 20. As shown in Figure 19, the conductor layer ML2 is formed so as to cover the organic insulating material OM2. Also, the height of the formed conductor layer ML2 is less than the height of the resist FR2. The height of the resist FR2 is the height from the upper surface 20a of the substrate 20.

[0076] Since the conductor layer ML1 is exposed through the penetration TH1 of the interlayer organic insulating material IM1 and the groove G2 of the organic insulating material OM2, the conductor layer ML2 is electrically connected to the conductor layer ML1. In the example shown in Figure 19, a seed layer BM2 is provided, so the conductor layer ML2 is electrically connected to the conductor layer ML1 via the seed layer BM2.

[0077] One method for forming the conductive layer ML2 is electroplating. In the example shown in Figure 19, a seed layer BM2 is provided, so the seed layer BM2 is used as a seed layer for electroplating, and electroplating is performed. The metal constituting the conductive layer ML2 is, for example, Cu.

[0078] Figure 20 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 20, the manufacturing method for a wiring device according to another embodiment includes a step of removing the resist FR2 to expose the upper surface 20a of the substrate 20. The resist FR2 covering the upper surface 20a of the substrate 20, which will become the dicing street DS, is removed. This removes all of the resist FR2. One method for removing the resist FR2 is to use a stripping agent.

[0079] In this embodiment, since a seed layer BM2 is formed, even after removing the resist FR2, the upper surface 20a of the substrate 20, which will become the dicing street DS, is covered by the seed layer BM2. Therefore, after removing the resist FR2, the seed layer BM2 is removed so that the upper surface 20a of the substrate 20, which will become the dicing street DS, is exposed. Etching is one method for removing the seed layer BM2.

[0080] Figure 21 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 21, the manufacturing method for a wiring device according to another embodiment includes a step of cutting a part of the conductor layer ML2 and a part of the organic insulating material OM2 using a cutting blade 80. After cutting, the remaining conductor layer ML2 becomes the wiring. Also, after cutting, the remaining organic insulating material OM2 becomes an organic insulating layer for insulating the wiring from each other.

[0081] One method of cutting is planing. The same planing method used in Figure 9 can be used.

[0082] By cutting, the organic insulating material OM2, which was covered by the conductive layer ML2, is exposed. After cutting, the thickness of the organic insulating material OM2 is, for example, 2 μm or less. Also, after cutting, the height from the interlayer organic insulating material IM1 to the upper surface ML2a of the conductive layer ML2 is, for example, 2 μm or less. By cutting, the upper surface ML2a of the conductive layer ML2 and the upper surface OM2a of the organic insulating material OM2 are flattened. After cutting, the upper surface OM2a of the organic insulating material OM2 and the upper surface ML2a of the conductive layer ML2 are located on the same plane. Also, after cutting, the surface roughness of the surface including the upper surface OM2a of the organic insulating material OM2 and the upper surface ML2a of the conductive layer ML2 is, for example, Ra 0.01 μm or more and Ra 0.05 μm or less.

[0083] In this embodiment, since a seed layer BM2 is provided, a portion of the seed layer BM2 is cut away, exposing the organic insulating material OM2. After cutting, the upper surface OM2a of the organic insulating material OM2, the upper surface ML2a of the conductor layer ML2, and the exposed surface of the seed layer BM2 are located on the same plane. Furthermore, after cutting, the surface roughness of the surface including the upper surface OM2a of the organic insulating material OM2, the upper surface ML2a of the conductor layer ML2, and the exposed surface of the seed layer BM2 is, for example, Ra 0.01 μm or more and Ra 0.05 μm or less.

[0084] Figure 22 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. Figure 22 shows a wiring device after repeating the steps in Figures 12 to 21 to form two more wiring layers. Interlayer organic insulating material IM2, organic insulating material OM3, interlayer organic insulating material IM3, and organic insulating material OM4 are formed sequentially on organic insulating material OM2. A through-hole TH2 is formed in the interlayer organic insulating material IM2. A groove G3 is formed in the organic insulating material OM3. A conductor layer ML3 is embedded in the through-hole TH2 and groove G3. The conductor layer ML3 is electrically connected to the conductor layer ML2 via a seed layer BM3. Also, a through-hole TH3 is formed in the interlayer organic insulating material IM3. A groove G4 is formed in the organic insulating material OM4. A conductor layer ML4 is embedded in the through-hole TH3 and groove G4. The conductor layer ML4 is electrically connected to the conductor layer ML3 via a seed layer BM4.

[0085] Figure 23 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. Figure 23 shows the steps following those in Figure 22. From Figures 23 to 31, only the portion above the interlayer organic insulating material IM2 shown in Figure 22 will be shown and explained. As shown in Figure 23, the manufacturing method for a wiring device according to another embodiment includes the step of applying an electrode lower insulating material IM0 onto the organic insulating material OM4. The electrode lower insulating material IM0 is applied so as to cover the upper surface OM4a of the organic insulating material OM4 and the upper surface ML4a of the conductor layer ML4. Although not shown in Figure 23, the electrode lower insulating material IM0 is also applied so as to cover the upper surface 20a of the substrate 20.

[0086] The electrode lower insulating material IM0 is an organic material. The electrode lower insulating material IM0 can be made from the same material as the organic insulating material OM2. The method for applying the electrode lower insulating material IM0 can be the same as the method for applying the organic insulating material OM2. The height of the applied electrode lower insulating material IM0 from the upper surface OM4a of the organic insulating material OM4 is, for example, 4 μm or more and 6 μm or less.

[0087] Figure 24 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 24, the manufacturing method for a wiring device according to another embodiment includes a step of removing a portion of the electrode lower insulating material IM0 to form a through-hole TH0. The through-hole TH0 is formed in the electrode lower insulating material IM0 so that the conductor layer ML4 is exposed. Although not shown in Figure 24, a portion of the electrode lower insulating material IM0 is removed so that the upper surface 20a of the substrate 20 is exposed from the electrode lower insulating material IM0. The method for removing a portion of the electrode lower insulating material IM0 is the same as the method for removing a portion of the organic insulating material OM2. The diameter of the through-hole TH0 is, for example, 5 μm or more and 35 μm or less. The diameter of the through-hole TH0 is, for example, 10 μm.

[0088] Figure 25 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 25, the manufacturing method for a wiring device according to another embodiment includes a step of forming a seed layer BM0 so as to cover the conductor layer ML4 and the electrode lower insulating material IM0. Although not shown in Figure 25, the seed layer BM0 is formed so as to cover the upper surface 20a of the substrate 20. The step of forming the seed layer BM0 is not essential.

[0089] The seed layer BM0 can be made from the same material as the seed layer BM2. The method for forming the seed layer BM0 can be the same as the method for forming the seed layer BM2.

[0090] Figure 26 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to another embodiment. As shown in Figure 26, the method for manufacturing a wiring device according to another embodiment includes a step of applying resist FR0 so as to cover the electrode lower insulating material IM0. Although not shown in Figure 26, resist FR0 is applied so as to cover the upper surface 20a of the substrate 20. In the example shown in Figure 26, resist FR0 covers the electrode lower insulating material IM0 and the upper surface 20a of the substrate 20 via a seed layer BM0. In this embodiment, resist FR0 is a photoresist.

[0091] One method for applying resist FR0 is by spin coating.

[0092] Figure 27 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 27, the manufacturing method for a wiring device according to another embodiment includes a step of removing a portion of the resist FR0 to expose the penetration portion TH0 of the electrode lower insulating material IM0. In the example shown in Figure 27, after removing a portion of the resist FR0, a cylindrical hole is formed in the resist FR0 that connects to the penetration portion TH0 of the electrode lower insulating material IM0. Patterning is one method for removing the resist FR0.

[0093] Figure 28 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 28, in the manufacturing method for a wiring device according to another embodiment, an electrode lower via V0 is formed to fill the penetration portion TH0 of the electrode lower insulating material IM0. Also, an electrode 30 is formed to fill the removed resist FR0. Furthermore, a conductive bonding material 40 is formed on the electrode 30 to fill the removed resist FR0. As shown in Figure 28, the electrode lower via V0 and the electrode 30 are formed integrally. The electrode lower via V0 and the electrode 30 are, for example, made of Cu. The conductive bonding material 40 is, for example, solder. In the example shown in Figure 28, the electrode 30 is cylindrical. The diameter of the electrode 30 is, for example, 10 μm or more and 25 μm or less. The height of the electrode 30 is, for example, 10 μm or more and 40 μm or less. The electrode 30 is formed with a pitch of, for example, 20 μm or more and 50 μm or less.

[0094] Figure 29 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 29, the manufacturing method for a wiring device according to another embodiment includes a step of removing the resist FR0. Although not shown in Figure 29, the resist FR0 covering the upper surface 20a of the substrate 20 which will become the dicing street DS is also removed. This removes all of the resist FR0. The resist FR0 is removed, for example, with a stripping agent.

[0095] Figure 30 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 30, the manufacturing method for a wiring device according to another embodiment includes a step of removing the seed layer BM0. Although omitted in Figure 29, in this embodiment, since the seed layer BM0 is formed, even after removing the resist FR0, the upper surface 20a of the substrate 20 which will become the dicing street DS is covered by the seed layer BM0. Therefore, after removing the resist FR0, the seed layer BM0 is removed so that the upper surface 20a of the substrate 20 which will become the dicing street DS is exposed. Etching is one method for removing the seed layer BM0.

[0096] Figure 31 is a cross-sectional view showing the steps of a method for manufacturing a wiring device according to another embodiment. As shown in Figure 31, the method for manufacturing a wiring device according to another embodiment includes a step of reflowing the conductive bonding material 40.

[0097] Figure 32 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. The display range in Figure 32 is expanded compared to Figures 31 and earlier. As shown in Figure 32, the manufacturing method for a wiring device according to another embodiment includes a step of removing a portion of the substrate 20. As shown in Figure 32, the thickness of the substrate 20 is reduced by back-grinding the lower surface S1 of the substrate 20.

[0098] Figure 33 is a cross-sectional view showing the steps of a manufacturing method for a wiring device according to another embodiment. As shown in Figure 33, the manufacturing method for a wiring device according to another embodiment includes a step of cutting the portion of the upper surface 20a of the substrate 20 that is exposed. The portion of the upper surface 20a of the substrate 20 that is exposed becomes a dicing street DS. By cutting the dicing street DS, the wiring device 10A can be divided into individual pieces.

[0099] As shown in Figure 33, after cutting, a portion of the dicing street DS remains. In other words, a portion of the upper surface 20a of the substrate 20 remains exposed. After cutting, a stepped portion 70 is formed by the substrate 20 and the organic insulating material OM1, etc.

[0100] As shown in Figure 22, the manufacturing method of the wiring device according to this embodiment allows the upper surface OM1a of the organic insulating material OM1 and the upper surface ML1a of the conductor layer ML1 to be formed on the same plane. Furthermore, the upper surface OM1a of the organic insulating material OM1 and the upper surface ML1a of the conductor layer ML1 are flat. Therefore, the lower parts of the wiring layers, such as the interlayer organic insulating material IM1 and organic insulating material OM2, formed on the organic insulating material OM1 can be made flat. It is easy to form the thickness of the wiring layers formed on the organic insulating material OM1 to be uniform. As a result, it is possible to prevent disconnection even with thin wiring, such as 2 μm or less.

[0101] In this embodiment, a photosensitive resin was used for the interlayer organic insulating material IM1, but this can be modified to use a non-photosensitive resin and to create the through-hole TH1 by laser processing.

[0102] In this embodiment, a photomask and a stepper exposure machine were used to pattern the grooves G1 of the organic insulating material OM1 and the through-holes TH1 of the interlayer organic insulating material IM1. However, this can be modified to use a direct imaging exposure machine. In this case, the photomask can be omitted, reducing the time and cost of mask production. Furthermore, the effect becomes greater as the number of layers to be stacked increases and the number of masks that can be omitted increases.

[0103] <Manufacturing method for semiconductor devices> Next, a method for manufacturing a semiconductor device according to one embodiment will be described. The method for manufacturing a semiconductor device according to this embodiment uses a wiring device manufactured by the wiring device manufacturing method described above.

[0104] Figure 34 is a cross-sectional view showing the steps of a semiconductor device manufacturing method according to one embodiment. As shown in Figure 34, the semiconductor device manufacturing method according to this embodiment includes a step of electrically connecting a wiring device 10A, a semiconductor chip CP1, and a semiconductor chip CP2. In the example shown in Figure 34, the wiring device 10A, semiconductor chip CP1, and semiconductor chip CP2 are electrically connected by a conductive bonding material 40. The conductive bonding material 40 is, for example, solder. As shown in Figure 34, semiconductor chip CP1 is electrically connected to semiconductor chip CP2 via the wiring device 10A. The electrode pad PD of semiconductor chip CP1 is electrically connected to the conductor layer ML4 via the lead LD, the conductive bonding material 40, and the electrode 31 of the wiring device 10A. Similarly, the electrode pad PD of semiconductor chip CP2 is electrically connected to the conductor layer ML4 via the lead LD, the conductive bonding material 40, and the electrode 32 of the wiring device 10A.

[0105] <Wiring device> Next, a wiring device according to one embodiment will be described. Figure 35 is a cross-sectional view showing a wiring device according to one embodiment of the wiring device described in Figures 1 to 33. Figure 36 is an enlarged view of the portion of the wiring device shown in Figure 35 enclosed by the dotted line. As shown in Figure 35, the wiring device 10A according to this embodiment comprises a substrate 20, a wiring section WP, an electrode 30, and a conductive bonding material 40. Also, as shown in Figure 36, the wiring device 10A according to this embodiment comprises wiring layers WL0 to WL4, an electrode lower insulating layer IL0, interlayer organic insulating layers IL1 to IL3, electrode lower vias V0, vias V1 to V3, and seed layers BM0 to BM4.

[0106] Next, a wiring device according to another embodiment will be described. Figure 37 is a cross-sectional view showing a wiring device according to another embodiment. Figure 38 is a plan view of the wiring device shown in Figure 37. As shown in Figure 37, in two adjacent insulating layers, the outer peripheral surface of the upper insulating layer is located inside the outer peripheral surface of the lower insulating layer in a plan view. For example, the interlayer organic insulating layer IL1 and the organic insulating layer OL2 have stepped portions formed by the positional relationship of their respective outer peripheral surfaces. In other words, in the wiring device 10B, stepped portions are formed in a stepped manner by multiple insulating layers. This makes it possible to further increase the surface area of ​​the side surface of the wiring device 10B. As a result, when the wiring device 10B is sealed with a sealant such as resin, the contact area between the sealant and the wiring device can be further increased. Therefore, the mounting reliability of the wiring device 10B can be further improved. Also, since the lower insulating layer is shaped to protrude from the upper insulating layer, even if a misalignment occurs within the range of processing accuracy during the lamination of the insulating layers, it is possible to prevent the upper insulating layer from protruding from the lower insulating layer. Therefore, it is possible to prevent the upper insulating layer from slipping down. This makes it difficult for the lower insulating layer and the upper insulating layer to separate. Also, as shown in Figure 38, in a plan view, the outer edge of wiring layer WL2 is inward from the outer edge of wiring layer WL1. In Figure 38, only a portion of the stepped portion is shown, but the entire outer edge of wiring layer WL2 may be formed inward from the outer edge of wiring layer WL1.

[0107] Figure 39 is a cross-sectional view showing a wiring device 10C according to another embodiment. As shown in Figure 39, a through-hole TH5 is provided in the substrate 20. A through-electrode V5 is embedded in the through-hole TH5. The through-electrode V5 is electrically connected to the wiring M1. An electrode 33 is provided on the lower surface 20b of the substrate 20. The through-electrode V5 is electrically connected to the electrode 33. In the example shown in Figure 39, a seed layer BM5 is provided between the through-electrode V5 and the substrate 20. Also, a seed layer BM5 is provided between the through-electrode V5 and the wiring M1. In other words, the through-electrode V5 is electrically connected to the wiring M1 via the seed layer BM5. Also, a seed layer BM5 is provided between the electrode 33 and the through-electrode V5. In other words, the through-electrode V5 is electrically connected to the electrode 33 via the seed layer BM5. In this embodiment, the substrate 20 is made of glass.

[0108] In this embodiment, the electrode 33 and the wiring M1 provided on the lower surface 20b of the substrate 20 are electrically connected via the through electrode V5. Therefore, the wiring M1 of the wiring section WP can be electrically connected to the wiring provided on the side of the substrate 20 opposite to the wiring section WP. This allows a semiconductor chip provided on the wiring section WP side of the substrate 20 to be electrically connected to a semiconductor chip provided on the side of the substrate 20 opposite to the wiring section WP side.

[0109] Furthermore, the substrate of the wiring device 10C may have electronic circuits such as transistor circuits or integrated circuits formed on it. This makes it possible to construct a WLCSP (Wafer Level Chip Size Package) with fine wiring. The fine wiring allows for re-wiring by rearranging terminals such as columnar electrodes and solder bumps from the electrode pads PD on the semiconductor chip CP1 onto the wiring device 10C. The wiring section WP of the wiring device 10C is flatter than that of conventional WLCSPs. Therefore, even when stacking multiple wiring layers, wiring can be made finer with a high yield.

[0110] Figure 40 is a cross-sectional view showing a wiring device 10D according to another embodiment. As shown in Figure 40, a conductive bonding material 40 is embedded in the lower insulating layer IL0 of the electrode. Also, the electrode 30 shown in Figure 36 is replaced by the conductive bonding material 40. In this embodiment, the conductive bonding material 40 functions as the electrode 30. The conductive bonding material 40 is, for example, solder. Since the electrode 30 is replaced by the conductive bonding material 40, the step of forming the electrode 30 can be omitted.

[0111] Incidentally, when using silicon as the substrate, although not shown in the diagram, through-silicon vias (TSVs) formed to penetrate the silicon substrate may be provided. A wiring device using a silicon substrate with TSVs is called a silicon bridge. Manufacturing a silicon bridge with TSVs requires very expensive equipment and manufacturing processes, known as the front-end process, for forming semiconductor integrated circuits. Therefore, using glass as the substrate is preferable compared to silicon bridges in that it can reduce manufacturing costs.

[0112] <Semiconductor device> Next, a semiconductor device according to one embodiment will be described. Figure 41 is a cross-sectional view showing a semiconductor device according to one embodiment. Figure 42 is an enlarged view of the semiconductor device shown in Figure 41. As shown in Figure 41, the semiconductor device package according to this embodiment comprises a wiring device 10A, a semiconductor chip CP1, a semiconductor chip CP2, a encapsulant MR, and a plurality of leads LD.

[0113] In this embodiment, the wiring device 10A is the wiring device 10A according to the above-described embodiment.

[0114] The semiconductor chip CP1 is equipped with multiple electrode pads PD. Some of the electrode pads PD are electrically connected to electrodes 30 of the wiring device 10A via leads LD. In addition, some of the leads LD that are electrically connected to the electrode pads PD are exposed from the lower surface MRb of the encapsulant MR.

[0115] The semiconductor chip CP2 is equipped with multiple electrode pads PD. Some of the electrode pads PD are electrically connected to electrodes 30 of the wiring device 10A via leads LD. In addition, some of the leads LD that are electrically connected to the electrode pads PD are exposed from the lower surface MRb of the encapsulant MR.

[0116] The encapsulant MR encapsulates the wiring device 10A, semiconductor chip CP1, semiconductor chip CP2, and multiple leads LD. The encapsulant MR is made of, for example, resin.

[0117] As shown in Figure 42, the electrode pad PD of semiconductor chip CP1 is electrically connected to the electrode pad PD of semiconductor chip CP2 via the wiring section WP of the wiring device 10A. For example, the electrode pad PD of semiconductor chip CP1 is electrically connected to the electrode pad PD of semiconductor chip CP2 via electrode 31, wiring M4, and electrode 32. Note that in Figure 42, hatching of the encapsulant MR and other components has been omitted for clarity.

[0118] Although several representative embodiments have been described above with reference to the drawings, there are various further modifications to the embodiments and modifications described above. Parts of the embodiments can be appropriately modified as long as they do not contradict the above description. Furthermore, for example, parts of the embodiments and modifications described above can be combined with parts of other embodiments. [Explanation of Symbols]

[0119] 10A, 10B, 10C, 10D Wiring Devices 20 circuit boards 20a top surface 20b Bottom side 20c side 30, 31, 32, 33 electrode 40 Conductive bonding material 80 cutting blade 90 blades BM, BM0, BM1, BM1a, BM2, BM2a, BM3, BM3a, BM4, BM5 seed layer CP1, CP2 semiconductor chips DS Dicing Street FR0, FR1, FR1a, FR2, FR3, FR4 Resist G1, G2, G3, G4 Groove G1a top G1b flat part G1c side wall IL0 electrode lower insulating layer IL1, IL2, IL3 Interlayer Organic Insulating Layers IM0 Electrode Lower Insulating Material IM1, IM2, IM3 Interlayer Organic Insulating Materials IM1a top surface LD Lead M1, M2, M3, M4 wiring M1a, M2a, M3a, M4a top surface M1b bottom side ML1, ML2, ML3, ML4 Conductor Layers ML1a, ML2a, ML4a, MLa top surface ML1b, MRb bottom surface MR sealed body OL1, OL2, OL3, OL4 Organic insulating layer OL1a, OL2a, OL3a, OL4a top surface OL1b bottom OM1, OM2, OM3, OM4 Organic Insulating Materials OM1a, OM2a, OM4a top side OM1b bottom PD electrode pads PKG Semiconductor Equipment S1 lower surface TH0, TH1, TH2, TH3, TH5 penetration part V0 electrode lower via V1, V2, V3 Via V5 Through electrode VL1, VL2, VL3 via layers VL1a top side WP wiring section WL1, WL2, WL3, WL4 wiring layers

Claims

1. (a) Steps to prepare the substrate, (b) A step of forming a first insulating layer on the upper surface of the substrate, (c) A step of removing a portion of the first insulating layer to form a groove, (d) A step of forming a first conductor layer so as to fill the grooves of the first insulating layer, (e) A step of cutting a part of the first insulating layer and a part of the first conductor layer to form a first wiring layer, A method for manufacturing a wiring device, comprising:

2. In claim 1, A method for manufacturing a wiring device, wherein the cutting in step (e) is planing.

3. In claim 2, A method for manufacturing a wiring device, wherein the substrate is an inorganic substrate on which no circuits are formed.

4. In claim 2, further, after step (e), (f) A method for manufacturing a wiring device, comprising the step of cutting off the portion of the upper surface of the substrate that is exposed to separate the wiring device into individual pieces.

5. In claim 2, A method for manufacturing a wiring device, wherein the surface roughness of the upper surface of the first wiring layer is Ra 0.01 μm or more and Ra 0.05 μm or less.

6. In claim 1, after step (e), further, (e1) A step of forming a first interlayer insulating layer on the first wiring layer, (e2) A step of forming a penetration in the first interlayer insulating layer such that the first conductor layer is exposed, (e3) A step of forming a second insulating layer on the first interlayer insulating layer, (e4) A step of removing a portion of the second insulating layer to form a groove so that the penetration portion of the first interlayer insulating layer is exposed from the second insulating layer. (e5) A step of forming a second conductor layer so as to fill the penetration portion of the first interlayer insulating layer and the groove portion of the second insulating layer, (e6) The process includes cutting a portion of the second insulating layer and a portion of the second conductor layer to form a second wiring layer, A method for manufacturing a wiring device, wherein the first conductor layer is electrically connected to the second conductor layer.

7. In claim 6, A method for manufacturing a wiring device, wherein the cutting in step (e) and step (e6) is planing.

8. In claim 6, A method for manufacturing a wiring device, wherein, in a plan view, at least a portion of the outer edge of the second wiring layer is located inside the outer edge of the first wiring layer.

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