Glass core with embedded power supply components

Abstract

A glass core with embedded power supply components is disclosed. [Solution] An exemplary apparatus includes a glass layer having an opening, a dielectric material within the opening, a first cluster of inductors extending through the dielectric material, and a second cluster of inductors extending through the dielectric material. The second cluster is spaced apart from the first cluster, and the dielectric material extends continuously from around the first cluster to around the second cluster.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are routinely connected to larger circuit boards such as motherboards and other types of printed circuit boards (PCBs) via package substrates. As the size of IC chips and / or dies shrinks and the interconnect density increases, alternatives to conventional substrate layers have been developed to provide stable transmission of high-frequency data signals between different circuits and / or increased power delivery. One option being pursued is the implementation of package substrates with glass cores. Generally, the implementation of glass cores provides several advantages, including higher plated through-hole (PTH) density, lower signal loss, and lower total thickness variation compared to implementations using conventional epoxy cores.

Brief Description of the Drawings

[0002] [Figure 1] FIG. 1 shows one exemplary integrated circuit (IC) package constructed in accordance with the teachings disclosed herein. [Figure 2] FIG. 2 shows a perspective view of one exemplary first glass core that can be used with the exemplary IC package of FIG. 1. [Figure 3] FIG. 3 is a top view of the exemplary first glass core of FIG. 2, including a power supply. [Figure 4] FIG. 4 is a cross-sectional side view of the exemplary first glass core of FIGS. 2 and 3. [Figure 5] FIG. 5 shows a perspective view of one exemplary second glass core that can be used with the exemplary IC package of FIG. 1. [Figure 6A] FIG. 6A is a cross-sectional side view of the exemplary second glass core of FIG. 5, including a power supply. [Figure 6B] FIG. 6B is a cross-sectional side view of the exemplary second glass core of FIG. 5, including a power supply. [Figure 7] Figure 7 is a top view relating to the exemplary second glass core shown in Figures 5, 6A, and 6B. [Figure 8] Figure 8 is a cross-sectional side view relating to an exemplary third glass core, similar to the exemplary second glass core in Figure 5. [Figure 9] Figure 9 is a top view of a wafer including a die, which may be contained within an IC package, constructed in accordance with the teachings disclosed herein. [Figure 10] Figure 10 is a cross-sectional side view of an IC device that may be contained within an IC package, constructed in accordance with the teachings disclosed herein. [Figure 11] Figure 11 is a cross-sectional side view of an IC device assembly, which may include an IC package, constructed in accordance with the teachings disclosed herein. [Figure 12] Figure 12 is a block diagram relating to an exemplary electrical device, which may include an IC package, constructed according to the teachings disclosed herein.

[0003] Generally, the same reference number is used throughout the drawings and accompanying specifications to refer to the same or similar parts. Drawings are not necessarily to scale. Instead, the thickness of layers or areas may be enlarged in the drawings. While the drawings show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be indistinguishable, blended, and / or irregular. [Modes for carrying out the invention]

[0004] Figure 1 shows an exemplary integrated circuit package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically connected to an underlying substrate 102 via an array of contacts 104 on the package mounting surface 106 of the package (e.g., bottom, outer surface). In some examples, the substrate 102 may be mounted by a package substrate or a printed circuit board (PCB). In the illustrated example, the contacts 104 are represented as pads or lands. However, in some examples, the IC package 100 may include, in addition to or instead of, the indicated pads or lands, balls, pins, and / or any other type of contacts to enable the electrical coupling of the IC package 100 to the substrate 102. In this example, the IC package 100 includes two dies 108, 110 (e.g., silicon dies, semiconductor dies, etc.), also sometimes called chiplets, mounted on a package substrate 112 and surrounded by a package lid 114 (e.g., a mold compound, an integrated heat spreader, IHS). Thus, the package substrate 112 is an exemplary means for supporting the semiconductor dies. While the exemplary IC package 100 in Figure 1 includes two dies 108, 110, in other examples, the IC package 100 may have only one die or three or more dies. In some examples, one of the dies 108, 110 (or separate dies) is embedded in the package substrate 112. The dies 108, 110 can provide any suitable type of function (e.g., data processing, memory storage, etc.). In some examples, one or both of the dies 108, 110 are mounted by a die package containing multiple dies arranged in a stacked configuration. For example, the second die 110 may include a stack of dynamic random access memory (DRAM) dies arranged on top of the memory controller die to form a memory die stack.

[0005] As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the package substrate 112 via an array of corresponding interconnects 116. In Figure 1, the interconnects are shown as bumps. The interconnects 116 may include solder joints, microbumps, a combination of metal (e.g., copper) pillars and solder, etc. In other examples, the interconnects 116 may include directly bonded or "hybrid bonded" metal interconnects. In other examples, the interconnects 116 may be any other type of electrical connection (e.g., balls, pins, pads, pillars, wire bonding, etc.) in addition to or instead of the bumps shown. The electrical connection between the dies 108, 110 and the package substrate 112 (e.g., interconnect 116) may be called a first-level interconnect. In contrast, the electrical connection between the IC package 100 and the substrate 102 (e.g., contacts 104) may be called a second-level interconnect. In some examples, one or both of the dies 108, 110 may be laminated on one or more other dies and / or interposers. In such examples, the dies 108, 110 are coupled to the underlaying dies and / or interposers through a first set of first-level interconnects, and the underlaying dies and / or interposers may be coupled to the package substrate 112 through a separate set of first-level interconnects associated with the underlaying dies and / or interposers. Thus, as used herein, a first-level interconnect refers to an interconnection between a die and the package substrate, or between a die and the underlaying dies and / or interposers (e.g., balls, bumps, pins, pads, wire bonding, etc.).

[0006] As shown in Figure 1, the interconnection 116 of the first level interconnection includes two different types of bumps corresponding to core bumps 118 and bridge bumps 120. As used herein, the core bump 118 is a bump on the dies 108, 110 through which electrical signals pass between the dies 108, 110 and external components of the IC package 100. More specifically, as shown in the illustrated example, when the dies 108, 110 are mounted on the package substrate 112, the core bump 118 is physically coupled and electrically connected to contact pads 124 on the die mounting surface 126 (e.g., top surface, upper surface, etc.) of the package substrate 112. The contact pads 124 on the die mounting surface 126 of the package substrate 112 are electrically connected to the contacts 104 on the package mounting surface 106 of the package substrate 112 (e.g., the surface opposite the die mounting surface 126) (e.g., the bottom surface, outer surface) via internal interconnects 128 within the package substrate 112. As a result, a continuous electrical signal path exists between the core bumps 118 of the dies 108, 110 and the contacts 104 mounted on the substrate 102, passing through the contact pads 124 and the internal interconnects 128 provided between them. As shown in the figure, the package mounting surface 106 and the die mounting surface 126 define opposing outer surfaces of the package substrate 112. While both surfaces are outer surfaces of the package substrate, the die mounting surface 126 is sometimes referred to herein as the inner surface or internal surface relative to the IC package 100. In contrast, in this example, the package mounting surface 106 is the outer surface or external surface of the IC package 100.

[0007] As used herein, a bridge bump 120 is a bump on dies 108, 110 through which electrical signals pass between different dies 108, 110 within the IC package 100. Thus, as shown in the illustrated example, the bridge bump 120 of the first die 108 is electrically connected to the bridge bump 120 of the second die 110 via an interconnect bridge 130 (e.g., a silicon-based interconnect bridge, interconnect die, embedded interconnect bridge (EMIB)) embedded in the package substrate 112. As shown in Figure 1, the core bump 118 is typically larger than the bridge bump 120. In some examples, the interconnect bridge 130 and the associated bridge bump 120 are omitted.

[0008] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors located on the package mounting surface 106 and / or the die mounting surface 126 of the package substrate 112.

[0009] In Figure 1, the package substrate 112 of an exemplary IC package 100 includes a glass core 132 (e.g., glass substrate, glass layer, etc.) between two separate build-up regions 134, 136 (also referred herein as build-up layers, etc.). In some examples, the glass core 132 includes at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, the glass core 132 includes one or more additives. These include, namely, aluminum oxide (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, the glass core 132 contains silicon and oxygen. In some examples, the glass core 132 contains silicon, oxygen, and / or one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, the glass core 132 contains at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, the glass core is a layer of glass containing silicon, oxygen, and aluminum. In some examples, the glass core 132 contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.

[0010] In some examples, the glass core 132 is an amorphous solid glass layer. In some examples, the glass core 132 is a layer of glass that does not contain organic adhesives or organic materials. In some examples, the glass core 132 is a solid layer of glass having a rectangular shape in plan view. In some examples, the glass core 132 includes at least one glass layer as a glass substrate, and does not contain epoxy or glass fibers (e.g., does not contain an epoxy-based prepreg layer with glass cloth). In some examples, the glass core 132 corresponds to a single piece of glass extending across the entire height / thickness of the core. In other examples, the glass core 132 may be silicon, a dielectric material, and / or any other material.

[0011] In some examples, the glass core 132 has a rectangular shape in plan view that is substantially coextensive (e.g., within 10%) with the layers above and / or below the core. In some examples, the glass core 132 has a thickness ranging from about 50 micrometers (μm) to about 1.4 millimeters (mm). In some examples, the glass core 132 may be a multilayer glass substrate (e.g., a coreless substrate), where the glass layers have a thickness ranging from about 25 μm to about 50 μm. In some examples, the glass core 132 may have dimensions ranging from about 10 mm on a side to about 250 mm on a side (e.g., from 10 mm × 10 mm to 250 mm × 250 mm). In some examples, the glass core 132 corresponds to a rectangular volume from which sections (e.g., vias) have been removed and which has been filled with other materials (e.g., metal). In particular, glass cores are advantageous over epoxy-based cores. This is because glass is harder and therefore provides greater mechanical support or strength to the package substrate. The glass core 132 is an exemplary means for reinforcing the package substrate.

[0012] In Figure 1, the build-up regions 134 and 136 are represented as masses / blocks having internal interconnects 128 extending linearly through the build-up regions 134 and 136 (and the glass core 132). However, Figure 1 is simplified for clarity and explanatory purposes. In reality, the interconnects are not necessarily linear. More specifically, in some examples, the build-up regions 134 and 136 are defined by alternating layers of dielectric material and conductive material (e.g., metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnects 128, which are represented in a simplified form by linearity as shown in Figure 1. In some examples, the metal layers are patterned to define electrical wiring or conductive traces, which are electrically connected between different metal layers by conductive (e.g., metal) vias extending through the intervening dielectric layers.

[0013] Using glass as the starting core material (e.g., glass core 132 in Figure 1) offers advantages over using conventional organic core materials (e.g., epoxy prepregs), including mechanical advantages (e.g., reduced warpage, smaller thickness variation), electrical advantages, and design flexibility advantages (e.g., denser through-hole pitch, finer core routing). For example, compared to conventional organic core materials, glass core 132 can support multi-chip packaging (e.g., embedded multi-die interconnect bridge (EMIB), 2.5D / 3D heterogeneous integration, hyperchip stacking (silicon (Si) interposer), etc.), reduced first-level interconnect (FLI) bump pitch (e.g., less than 30 micrometers (μm)), reduced fine line spacing (FLS) (e.g., 2 / 2 μm), higher density interconnects, higher input / output (I / O) density patterning, increased form factor, and reduced package thickness. To further enhance these advantages, the glass core 132 may include through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass core 132 to electrically connect the build-up region 134 to the build-up region 136. While the examples described herein are based on the glass core 132, it should be understood that the teachings of this disclosure are not limited thereto. For example, the teachings of this disclosure are also applicable to organic cores.

[0014] A common type of failure in known glass cores is seware failure. Seware failure results in the separation of the glass core along a crack that propagates from the edge of the glass core along its length and width between two or more of the outer surfaces of the glass core (e.g., top and bottom, front and back, etc.). In other words, seware failure is characterized by the glass core splitting into two separate glass sheets along a line extending approximately parallel to the main plane of the glass core.

[0015] One factor contributing to back crack defects is stress concentration in the glass core's cavities, such as those housing power supply components. Power supply components, such as inductors (e.g., coaxial metal inductor loops, CMILs), through-glass vias (TGVs), and plated through holes (PTHs), are often located within tightly packed cavities in conventional glass cores due to routing and spatial constraints. The formation of densely packed cavities in conventional glass cores creates thin webbing between these densely packed cavities. These cavities and their associated webbing can result in significant stress concentration in the thin glass walls related to the cavity webbing, caused by the load on the substrate. In particular, the corners and / or thin walls related to the webbing in the glass core can cause significant stress concentration, which can lead to cracking and fracture of the glass core.

[0016] Examples disclosed herein overcome some or all of the above problems and include a glass core with embedded power supply components. One exemplary glass core disclosed herein includes a large cavity containing dielectric fillers supporting multiple power supply components. Another exemplary glass core disclosed herein includes a recessed portion containing embedded power supply components. In some of these exemplary glass cores disclosed herein, reducing the thickness of the power supply in the glass core reduces stress concentration in the recessed portion. Some exemplary glass cores disclosed herein include six coaxial metal inductor loop (CMIL) clusters, which are offset to allow for the placement of PTHs between the CMIL clusters. Some exemplary glass cores disclosed herein include a cavity with filleted, beveled, and / or chamfered edges to reduce stress concentration along the edges. Examples disclosed herein substantially reduce the number of failure points associated with embedded power supply components in the glass core compared to conventional glass core designs.

[0017] Figure 2 shows a perspective view of one exemplary first glass core 200 that may be used with the exemplary IC package of Figure 1. More specifically, in some examples, the first glass core 200 of Figure 2 may be used to implement the exemplary glass core 132 of Figure 1. In the example shown in Figure 2, the first glass core 200 includes an exemplary body 202 and an exemplary cavity 204. In the example shown in Figure 2, the cavity 204 is defined by an exemplary inner wall 206 and includes an exemplary edge portion 208 having an exemplary corner 210. In the example shown in Figure 2, the body 202 has an exemplary top surface 212A and an exemplary bottom surface 212B. In the example shown in Figure 2, the top surface 212A is opposite to the bottom surface 212B (for example, surfaces 212A and 212B are opposing surfaces, etc.). In the example shown in Figure 2, surfaces 212A and 212B are the outer surfaces of the main body 202 (for example, the top surface 212A is the first outer surface, the bottom surface 212B is the second outer surface, etc.).

[0018] The body 202 is a structural component of the glass core 200. That is, the body 202 mechanically supports components mounted on the glass core 200 (e.g., dies 108, 110 in Figure 1, build-up regions 134, 136 in Figure 1, etc.). In some examples, the body 202 is a glass layer relating to the substrate of a package substrate (e.g., IC package 100, etc.). The body 202 contains (e.g., contains, composed of, etc.) glass (e.g., one or more of the glass compositions described in relation to the glass core 132 in Figure 1, etc.). In other examples, the body 202 may be composed of different materials. Only a portion of the body 202 is shown in Figure 2, and it should be understood that the body 202 may extend planarly along surfaces 212A, 212B. In some such examples, the body 202 may include additional cavities similar to cavity 204, which may include additional power supply components. As used herein, the body 202 is also referred to as the structural part of the glass core 200.

[0019] The cavity 204 is a through-hole that penetrates the body 202. In the example shown in FIG. 2, the cavity 204 has a generally square cross-section with rounded corners (e.g., corner 210 is rounded, etc.) (e.g., edge portion 208 includes four sides, etc.). In other examples, the cavity 204 may have a cross-section of a different shape (e.g., different polygons, circles, ellipses, etc.). Further, the radius of curvature of the corner 210 may be larger or smaller than that shown in the illustrated example. In the example shown in FIG. 2, the cavity 204 has a constant cross-sectional shape and size between the upper surface 212A and the bottom surface 212B. In other examples, the cavity 204 has a variable cross-section along the thickness of the body 202. For example, the cavity 204 may be conical and / or tapered (e.g., wider at the upper surface 212A than at the bottom surface 212B, wider at the bottom surface 212B than at the upper surface 212A, etc.), hourglass-shaped (e.g., wider at the opposing surfaces 212A, 212B than at the midpoint therebetween, etc.), and / or have any other suitable cross-sectional profile between the surfaces 212A, 212B. In the example shown in FIG. 2, the edge portion 208 is defined by the inner wall 206 and the upper surface 212A. In some examples, the edge portion 208 may be beveled, chamfered, and / or filleted. In some examples, the edge portion between the inner wall 206 and the bottom surface 212B is also beveled, chamfered, and / or filleted. One exemplary glass core having a filleted edge portion is described below in connection with FIG. 8.

[0020] The cavity 204 can support (e.g., house, contain, receive, etc.) the power supply of the glass core 200. One exemplary power supply that may be housed in the cavity 204 is described below in conjunction with FIG. 3. In some examples, the inner wall 206 of the cavity 204 is an interface (e.g., mechanical interface, material interface, etc.) between the body 202 and the power supply disposed in the cavity 204.

[0021] In the example shown in FIG. 2, an exemplary stress concentration map 214 is superimposed on the first glass core 200. The stress concentration map 214 reflects the stress received by the main body 202 when the glass core 200 is subjected to biaxial bending. That is, in the example shown in FIG. 2, the stress concentration map 214 corresponds to the stress that the glass core 200 in an IC package (e.g., the IC package of FIG. 1, etc.) will receive. In the example shown in FIG. 2, the darker portions in the stress concentration map 214 correspond to the regions of the main body 202 that are receiving greater stress, and the lighter portions on the stress concentration map 214 correspond to the regions of the main body 202 that are receiving relatively less stress. In the example shown in FIG. 2, the corner 210 is the only portion of the main body 202 that receives high stress concentration. In some examples, the corner 210 can be further rounded (e.g., the radius of the corner 210 can be increased, etc.) to reduce the stress concentration received thereby.

[0022] FIG. 3 is a top view of the first glass core 200 of FIG. 2, including one exemplary power supply unit 302. In the example shown in FIG. 3, the power supply unit 302 is disposed within the cavity 204 of the main body 202 of FIG. 2. In the example shown in FIG. 3, the power supply unit 302 includes an exemplary dielectric filler 304, an exemplary first CMIL cluster 306A, an exemplary second CMIL cluster 306B, an exemplary third CMIL cluster 306C, an exemplary fourth CMIL cluster 306D, an exemplary fifth CMIL cluster 306E, an exemplary sixth CMIL cluster 306F, and an exemplary PTH cluster 308. In the example shown in FIG. 3, the CMIL clusters 306A, 306B, 306C are disposed in an exemplary first row 310A, and the CMIL clusters 306D, 306E, 306F are disposed in an exemplary second row 310B. In the example shown in FIG. 3, the main body 202 includes a plurality of TGVs 312.

[0023] An exemplary dielectric filler 304 is a nonconductive material that structurally supports and surrounds the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F, and the PTH cluster 308. In the example shown in Figure 3, the dielectric filler 304 is located within the cavity 204 in Figure 2. In some examples, the dielectric filler 304 is an organic epoxy (e.g., organic resin, organic molding material, etc.). In other examples, the dielectric filler 304 may consist of any other suitable type of nonconductive material (e.g., plastic, ceramic, build-up film, etc.).

[0024] CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are clusters of power supply interconnects extending through the glass core 200 between the top surface 212A and the bottom surface 212B. The interconnections of CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F enhance the power supply through the glass core 200. In the example shown in Figure 3, the interconnections of CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are located within the dielectric filler 304 of the power supply unit 302. That is, CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F extend through the dielectric filler 304. In the example shown in Figure 3, the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F extend continuously around and between each of them. That is, the dielectric material 304 is deposited as a single, integrated component around each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F (for example, the dielectric material 304 extends continuously from around the first CMIL cluster 306A to around the second CMIL cluster 306B, etc.). In the example shown in Figure 3, each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F is separated from the others among the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F.

[0025] In the example shown in Figure 3, each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F contains eight CMILs. In other examples, some or all of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F may contain different numbers of CMILs (e.g., one CMIL, two CMILs, etc.). In the example shown in Figure 3, the interconnections of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are arranged in four rows involving two interconnections that are alternately offset. In other examples, some or all of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F may have different arrangements. In the example shown in Figure 3, CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are arranged in two rows (e.g., rows 310A, 310B, etc.). In other examples, CMIL clusters 306A, 306B, 306C, 306E, and 306F are arranged in different configurations (e.g., row 1, row 3, row 5, etc.). In the example shown in Figure 3, the second CMIL cluster 306B is offset from the first CMIL cluster 306A and the third CMIL cluster 306C, resulting in the formation of an exemplary offset gap 314 in the power supply unit 302. That is, the lateral offset of the second CMIL cluster 306B from the first CMIL cluster 306A and the third CMIL cluster 306C in the first row 310A forms an offset gap 314 at the center of the power supply unit 302.In the example shown in Figure 3, each inductor in each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F is closer to its adjacent inductor in the same CMIL cluster than to its nearest inductor in any of the other CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F (for example, each inductor in the first CMIL cluster 306A is spaced a first distance from its adjacent inductor in the first CMIL cluster 306A, and a second distance from its nearest inductor in each of the other CMIL clusters 306B, 306C, 306D, 306E, and 306F, where the second distance is greater than the first distance, etc.).

[0026] In the example shown in Figure 3, the PTH cluster 308 is located within the offset gap 314. That is, the PTH cluster 308 is located at the center of the power supply unit 302 (e.g., the center of the dielectric filler 304, etc.). Similar to the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F, the PTH cluster 308 enhances the power supply through the glass core 200. In the example shown in Figure 3, the PTH cluster 308 is located within the dielectric filler 304 of the power supply unit 302. In the example shown in Figure 3, the PTH cluster 308 includes 12 interconnections. In other examples, the PTH cluster 308 may include any other suitable number of interconnections (e.g., 1 interconnection, 5 interconnections, 10 interconnections, 20 interconnections, etc.). In the example shown in Figure 3, the interconnections of the PTH cluster 308 are arranged in six alternately offset columns relating to two interconnections. In other examples, the interconnection of PTH cluster 308 may have any other suitable arrangement, such as a different number of columns (e.g., 1 column, 2 columns, 10 columns, etc.) and / or a different number of PTHs within a given column (e.g., 1 PTH, 3 PTHs, 5 PTHs, etc.). In other examples, there is no offset gap 314, and CMIL clusters 306A, 306B, 306C are aligned laterally in the first column 310A (e.g., similar to the arrangement of CMIL clusters 306D, 306E, 306F in the second column 310B, etc.). In some such cases, the PTH cluster 308 is absent and / or located elsewhere within the power supply unit 302 (for example, near the edge 208 in Figure 2, laterally between the first CMIL cluster 306A and the fourth CMIL cluster 306D, laterally between the third CMIL cluster 306C and the sixth CMIL cluster 306F, etc.).

[0027] In the example shown in Figure 3, the power supply unit 302 includes CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F, and PTH cluster 308. Additionally or alternatively, the power supply unit 302 may include other power supply components disclosed herein. For example, the power supply unit 302 may include one or more capacitors (e.g., deep trench capacitors (DTCs), thin-film capacitors, etc.), one or more other interconnects (e.g., silicon-based interconnect bridges, interconnect dies, embedded interconnect bridges (EMIBs), etc.), and / or any other components that can be embedded in the glass core 200.

[0028] TGV312 is a glass through-via made of a conductive material (e.g., copper, silver, etc.) extending through the body 202. TGV312 allows electrical signals and / or power to be routed through the body 202 (e.g., between surfaces 212A, 212B, etc.). In the example shown in Figure 3, TGV312 is arranged in an offset grid; that is, in the example shown in Figure 3, TGV312 is arranged in offset rows and columns. In other examples, TGV312 is arranged in other patterns. In some examples, TGV312 is absent.

[0029] Figure 4 is a side cross-sectional view of the exemplary first glass core 200 of Figure 2, including the power supply unit 302 of Figure 3, taken along line AA of Figure 3. In the example shown in Figure 4, the power supply unit 302 includes an exemplary top surface 402A, an exemplary bottom surface 402B, and an exemplary outer wall 404. In the example shown in Figure 4, the top surface 402A is coplanar with the top surface 202A of the body 212, and the bottom surface 402B is coplanar with the bottom surface 202B of the body 212. In other examples, either or both of the surfaces 402A, 402B of the power supply unit 302 are recessed and / or protrude from the surfaces 212A, 212B of the body 202, respectively. In some examples, surfaces 402A, 402B and / or surfaces 212A, 212B are etched, polished, and / or planarized so that surfaces 402A, 402B and / or surfaces 212A, 212B are coplanar.

[0030] In the example shown in Figure 4, the outer wall 404 of the power supply unit 302 and the dielectric filler 304 (e.g., the outer wall of the power supply unit 302, etc.) is adjacent to the inner wall 206 of the cavity 204 of the glass core 200 (e.g., the inner surface of the cavity 204 of the glass core 200, etc.). In the example shown in Figure 4, the outer wall 404 and the inner wall 206 are straight lines (e.g., straight walls, etc.). In the example shown in Figure 4, the outer wall 404 is in contact with the inner wall 206 along the depth of the cavity 204 (e.g., abutting, etc.). In other examples, an adhesive and / or adhesion promoter is placed between the outer wall 404 and the inner wall 206.

[0031] Figure 5 shows a perspective view relating to an exemplary second glass core 500 that may be used with the exemplary IC package of Figure 1. More specifically, in some examples, the second glass core 500 of Figure 2 may be used to implement the exemplary glass core 132 of Figure 1. The second glass core 500 is similar to the first glass core 200 of Figures 2-4 unless otherwise specified. In the example shown in Figure 5, the second glass core 500 includes an exemplary body 502, an exemplary first recess 504, an exemplary first opening 505, an exemplary webbing 506, an exemplary first cavity 508A, an exemplary second cavity 508B, an exemplary third cavity 508C, an exemplary fourth cavity 508D, an exemplary fifth cavity 508E, and an exemplary sixth cavity 508F. In the example shown in Figure 5, the body 502 includes an exemplary edge portion 510 having an exemplary corner 512. Body 502 is a structural component of the second glass core 500. Unless otherwise specified, body 502 is the same as body 202 in Figure 2. As used herein, body 502 is also referred to as a structural component of the second glass core 500.

[0032] In the example shown in Figure 5, the first recess 504 includes an exemplary central platform 514. In the example shown in Figure 5, the body 502 has an exemplary top surface 516A and an exemplary bottom surface 516B. In the example shown in Figure 5, surfaces 516A and 516B are outer surfaces of the body 502 (for example, the top surface 516A is the first outer surface, and the bottom surface 516B is the second outer surface, etc.). In the example shown in Figure 2, the top surface 516A is on the opposite side of the bottom surface 516B (for example, surfaces 516A and 516B are opposing surfaces, etc.). In the example shown in Figure 5, the first recess 504 includes an exemplary first inner surface 518 (for example, a recessed or inset surface). In the example shown in Figure 5, an exemplary stress concentration map 520 is superimposed on the second glass core 500.

[0033] The first recess 504 is part of the second glass core 500, which is enclosed by the main body 502 (for example, spaced apart inside it). That is, the first recess 504 and the first inner surface 518 are inserted from the main body 502 and the top surface 516A by the first opening 505. In the example shown in Figure 5, the first recess 504 includes a webbing 506 and a central platform 514. In the example shown in Figure 5, the webbing 506 includes a plurality of glass walls positioned between cavities 508A, 508B, 508C, 508D, 508E, and 508F (for example, the webbing 506 includes a first glass wall separating the first cavity 508A from the second cavity 508B, the webbing 506 includes a second glass wall separating the first cavity 508A from the fourth cavity 508D, etc.). In the example shown in Figure 5, the webbing 506 and the central platform 514 are integrated with the body 502. In some such examples, the first opening 505 may be formed during the initial formation of the second glass core 500 (e.g., spin coating of the second glass core 500, molding of the second glass core 500, casting of the second glass core 500, etc.). Additionally or alternatively, the first opening 505 may be formed after the initial formation of the second glass core 500 (e.g., via routing, laser-induced etching, etc.). The first recess 504 and the first opening 505 are described below with reference to Figures 6A and 6B. In some examples, the bottom surface 202B of the body 516 includes an opening similar to the first opening 505. In some examples, the first recess 504 is a power supply section for the second glass core 500.

[0034] Cavities 508A, 508B, 508C, 508D, 508E, and 508F are through-holes extending through the main body 502. In some examples, each of cavities 508A, 508B, 508C, 508D, 508E, and 508F may house (e.g., include, surround, etc.) one or more corresponding power supply components (e.g., CMIL clusters, etc.). In the example shown in Figure 5, cavities 508A, 508B, 508C, 508D, 508E, and 508F have a generally rectangular cross-section with rounded corners (e.g., the corners of cavities 508A, 508B, 508C, 508D, 508E, and 508F are rounded, etc.). In other examples, some or all of the cavities 508A, 508B, 508C, 508D, 508E, and 508F may have cross-sectional shapes of different shapes (e.g., square, different polygons, circles, ellipses, etc.). Furthermore, the radius of curvature of the corners 210 may be larger or smaller than that shown in the illustrated example. In the example shown in Figure 5, each of the cavities 508A, 508B, 508C, 508D, 508E, and 508F has a constant cross-sectional shape and size through the recess 504. In other examples, some or all of the cavities 508A, 508B, 508C, 508D, 508E, and 508F have a variable cross-section along the thickness of the body 502. For example, some or all of the cavities 508A, 508B, 508C, 508D, 508E, and 508F may be conical, and / or tapered, hourglass-shaped, and / or have any other suitable cross-sectional area profile.

[0035] In some examples, the first opening 505 and / or cavities 508A, 508B, 508C, 508D, 508E, and 508F are filled with dielectric filler similar to that of the dielectric filler. In some such examples, power supply components (e.g., TGV, PTH, CMIL, etc.) may be placed within the dielectric filler and the first recess 504. A cross-sectional view of the glass core 500 containing dielectric filler similar to that of the dielectric filler 304 in Figure 4 is described below in conjunction with Figures 6A and 6B. It should be understood that the top view of the second glass core 500 is substantially similar to the top view of the glass core 200 in Figure 2 shown in Figure 3.

[0036] The edge portion 510 (e.g., the straight portion and the corner portion 512 of the edge portion 510, etc.) is a transition surface extending around the first recess portion 504. In the example shown in Figure 5, the edge portion 510 is defined between the first recess portion 504 and the top surface 516A. In the example shown in Figure 5, the edge portion 510 is filleted (e.g., rounded, curved, etc.). That is, in the example shown in Figure 5, the edge portion 510 is a curved surface (e.g., a curved transition surface, etc.) between the first recess portion 504 and the body 502. In other examples, the edge portion 510 may be beveled and / or chamfered. In some examples, the edge portion 510 is an interface (e.g., a mechanical interface, a material interface, etc.) between the body 502 and the power supply portion of the second glass core 500 including the first recess portion 504. Edge 510 will be described in more detail below, in conjunction with Figure 6A.

[0037] In the example shown in Figure 5, the central platform 514 of the second glass core 500 is located between cavities 508A, 508B, 508C, 508D, 508E, and 508F. Similar to the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F in Figure 3, cavities 508A, 508B, 508C, 508D, 508E, and 508F are distributed to facilitate the presence of the central platform 514 at the center of the first recess 504 (for example, the central platform 514 corresponds to the offset gap 314 in Figure 3, etc.). That is, the second cavity 508B is offset from the first cavity 508A and the third cavity 508C (for example, the distance between the second cavity 508B and the fifth cavity 508E is greater than the distance between the first cavity 508A and the fourth cavity 508D, and the distance between the third cavity 508C and the sixth cavity 508F, etc.). In some examples, one or more power supply components (e.g., glass through vias, etc.) are formed and positioned within the central platform 514. In the example shown in Figure 5, the central platform 514 is coplanar with the first inner surface 518 of the first recess 504. In other examples, the central platform 514 is coplanar with the top surface 516A.

[0038] In the example shown in Figure 5, the stress concentration map 520 reflects the stresses experienced by the body 502 when the second glass core 500 is subjected to biaxial bending (e.g., the same loads associated with the stress concentration map 214 in Figure 2). In the example shown in Figure 5, darker areas on the stress concentration map 520 correspond to regions of the body 502 experiencing greater stress, while lighter areas on the stress concentration map 520 correspond to regions of the body 502 experiencing relatively smaller stress. In the example shown in Figure 5, the thin walls of the corners 512 and webbing 506 experience stress concentration. In some cases, easing of the first recess 504 and edge 510 (e.g., chamfering of the edge 510, filleting of the edge 510, chamfering of the edge 510, etc.) reduces the relative portion of stress transmitted through the core (e.g., compared to a conventional core without the first recess 504, etc.) and increases the relative portion of stress transmitted through the body 502, which reduces the likelihood of failures occurring at the webbing 506 or corners 512 (e.g., back cracking defects, etc.).

[0039] Figures 6A and 6B are cross-sectional side views of the exemplary second glass core 500 of Figure 5, taken along lines BB and CC of Figure 5, respectively. In the examples shown in Figures 6A and 6B, the second glass core 500 includes an exemplary dielectric filler 600. Unless otherwise specified, the dielectric filler 600 is the same as the dielectric filler 304 of Figure 3. In the examples shown in Figures 6A and 6B, the second glass core 500 includes the first recess 504 of Figure 5, the first opening 505 of Figure 5, and an exemplary second opening 602, which is the same as the first opening 505 except that the second opening 602 is formed on the bottom surface 516B. In the examples shown in Figures 6A and 6B, the dielectric filler 600 is located in the openings 505, 602, and in the cavities 508A, 508B, 508C, 508D, 508E, and 508F. In the example shown in Figure 6A, the dielectric filler 600 is aligned perpendicularly to the recess 504. That is, the dielectric filler 600 is aligned with the recess 504 in a direction perpendicular to (for example, orthogonal to) the surfaces 212A and 212B.

[0040] In the examples shown in Figures 6A and 6B, the second glass core 500 includes the first edge portion 510 and an exemplary second edge portion 604 of Figure 5, which is similar to the first edge portion 510 except that the second edge portion 220 is located between the bottom surface 516B and the exemplary second inner surface 606 of the first recess portion 504. In the example shown in Figure 5, the second opening 602 and the second edge portion 604 each have the same size and shape as the first opening 505 and the first edge portion 510. In other examples, the second opening 602 and the second edge portion 604 each may have different sizes and / or shapes than the first opening 505 and the first edge portion 510. In some cases, the first opening 505 and / or the second opening 602 do not exist (for example, the first inner surface 518 is coplanar with the top surface 516A, the second inner surface 606 is coplanar with the bottom surface 516B, etc.).

[0041] In the example shown in Figure 6A, the body 502 of the second glass core 500 has an exemplary first thickness 608, and the first recess 504 has an exemplary second thickness 610. In the example shown in Figure 6A, the first thickness 608 is approximately 60% of the length of the second thickness 610. In some examples, the first thickness 608 may be between 10% and 90% of the length of the first thickness 608. In some examples, the thickness 608 is 200 microns (for example, each of the openings 505 and 602 has a depth of 100 microns, etc.). In other examples, the first thickness 608 may be any other suitable size.

[0042] In the examples shown in Figures 6A and 6B, the dielectric filler 600 within the first recess 504 includes an exemplary top surface 612A, an exemplary bottom surface 612B, and an exemplary outer wall 614. In the examples shown in Figures 6A and 6B, the dielectric filter 600 extends around the upper end of the glass wall of the webbing 506 (e.g., the end of the glass wall adjacent to the first opening 505, etc.) and the lower end of the glass wall of the webbing 506 (e.g., the end of the glass wall adjacent to the second opening 602, etc.). That is, in the examples shown in Figures 6A and 6B, the dielectric filler 600 is located within the openings 505 and 602, and above and between the glass walls of the webbing 506.

[0043] In the examples shown in Figures 6A and 6B, the upper surface 600A of the dielectric filler 612 is coplanar with the upper surface 516A, and the lower surface 600B of the dielectric filler 612 is coplanar with the lower surface 516B. In some examples, surfaces 516A, 516B and / or surfaces 612A, 612B are etched, polished, and / or planarized so that surfaces 516A, 516B and / or surfaces 612A, 612B are coplanar. In the example shown in Figure 6B, the outer wall 614 of the power supply unit 302 and the dielectric filler 304 are adjacent to the edges 510, 604 of the second glass core 500. In the example shown in Figure 6B, the outer wall 614 is in contact with (e.g., abuts against) the edges 510, 604. In other examples, an adhesive and / or adhesion promoter may be placed between the exterior wall 614 and the edges 510, 604.

[0044] In the example shown in Figure 6B, the second glass core 500 includes exemplary first CMIL cluster 616A, exemplary second CMIL cluster 616B, and exemplary third CMIL cluster 616C, which are respectively located within exemplary first cavity 508A, exemplary second cavity 508B, and exemplary third cavity 508C. Unless otherwise specified, the CMIL clusters 616A, 616B, and 616C are the same as the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F in Figure 3. In the example shown in Figure 6B, the CMIL clusters 616A, 616B, and 616C extend through the openings 505 and 602, and through the dielectric filler 600 within the cavities 508A, 508B, and 508C. In the example shown in Figure 6B, the web of webbing 506 is located between the first CMIL cluster 616A and the second CMIL cluster 616B, and between the second CMIL cluster 616B and the third CMIL cluster 616C.

[0045] Figure 7 is a cross-sectional top view of the exemplary second glass core 500 of Figures 5, 6A, and 6B, taken along the DD line of Figure 6B. In the example shown in Figure 7, the second glass core 500 includes the first CMIL cluster 616A, the second CMIL cluster 616B, the third CMIL cluster 616C, the exemplary fourth CMIL cluster 702A, the exemplary fifth CMIL cluster 702B, the exemplary sixth CMIL cluster 702C, and the exemplary TGV cluster 704 of Figure 6. In the example shown in Figure 7, the body 502 includes the multiple TGV 312 of Figure 3. In other examples, some or all of the multiple TGV 312 are absent.

[0046] Unless otherwise specified, CMIL clusters 702A, 702B, and 702C are the same as CMIL clusters 616A, 616B, and 616C in Figure 6B. In the example shown in Figure 7, CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C have the same external and internal configurations as CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F in Figure 3. In other examples, some or all of CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C may have a different internal configuration, and / or CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C may have a different external configuration.

[0047] In the examples shown in Figures 6B and 7, the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C extend through the dielectric filler 600. In the examples shown in Figures 6B and 7, the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C extend continuously around each of them between the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C and the wall of the webbing 506. That is, the dielectric material 600 is deposited as a single, integrated component around each of the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C, and around the walls of the webbing 506 (for example, the dielectric material 600 extends continuously from around the first CMIL cluster 616A to around the second CMIL cluster 616B, etc.). In the example shown in Figure 3, each of the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C is separated from the others of the CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C.

[0048] In the example shown in Figure 7, the TGV cluster 704 is located within the central platform 514. The TGV cluster 704 enables and enhances power supply through the second glass core 500. In the example shown in Figure 7, the TGV cluster 704 is arranged in a manner similar to that of the PTH cluster 308 in Figure 3. In other examples, the TGV cluster 704 may have any other suitable arrangement. As mentioned above, it is possible to fabricate smaller PTHs with finer pitches by passing through a glass core than by passing through a conventional organic epoxy core. Therefore, the exemplary TGV cluster 704 in Figure 7 is smaller than the exemplary PTH cluster 308 in Figure 3.

[0049] Figure 8 is a cross-sectional side view relating to an exemplary third glass core 800 implemented in accordance with the teachings of this disclosure. In the example shown in Figure 8, the third glass core 800 includes the body 502 of Figure 5 and the dielectric filler 600 of Figure 6. In the example shown in Figure 8, the third glass core 800 includes the surfaces 516A, 516B of Figure 5 and the edges 510, 604 of Figure 6. The third glass core 800 is similar to the second glass core 500 of Figure 5, except that the webbing 506 of Figure 5 is absent. Instead, in the example shown in Figure 8, the edges 510, 604 of the third glass core 800 extend between the surfaces 516A, 516B and the exemplary inner wall 802, respectively. That is, the third glass core 800 includes a through cavity 804 similar to the cavity 204 of Figure 2. In the example shown in Figure 8, the dielectric filler 600 abuts (e.g., is in contact with) the inner wall 802 along the depth of the cavity 804. In other examples, an adhesive and / or adhesion promoter may be placed between the inner wall 802 and the dielectric filler 600. In other words, the exemplary third glass core 800 combines the features of the exemplary first glass core 200 in Figures 2-4 with the features of the exemplary second glass core 500 in Figures 5-7.

[0050] The exemplary IC package 100 in Figure 1, which includes the first glass core 200 in Figure 2, the second glass core 500 in Figure 5, and the third glass core 800 in Figure 8, can be included in any suitable electronic component. Figures 9–12 show various examples of devices that include, or may include, the IC package 100 disclosed herein.

[0051] Figure 9 is a top view relating to a wafer 900 and die 902 that may be included in the IC package 100 of Figure 1 (for example, any suitable die from among dies 108 and 110). The wafer 900 contains semiconductor material and one or more dies 902 having circuits. Each die 902 may be a repeating unit of the semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 900 may undergo a singulation process in which the dies 902 are separated from each other to provide individual “chips”. The die 902 contains one or more transistors (for example, some of the transistors 1840 in Figure 18 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some embodiments, die 902 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, and conductive bridge RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuitry or electronic equipment. Multiple of these devices may be combined on a single die (e.g., die 902, etc.). For example, a memory array of multiple memory circuits may be formed on the same die (e.g., die 902) as a programmable circuit (e.g., processor circuit 2002 in Figure 20) and / or other logic circuits. Such memory may store information for use by the programmable circuit. An exemplary IC package 100 disclosed herein may be manufactured using die-to-wafer assembly technology, where several dies are mounted on a wafer 900 containing other dies, and then the wafer 900 is pulverized.

[0052] Figure 10 is a cross-sectional side view relating to an IC device 1000 that may be contained in an exemplary IC package 100 (e.g., one of dies 108, 110). One or more IC devices 1000 may be contained in one or more dies 902 (Figure 9). The IC device 1000 is formed on a die substrate 1002 (e.g., wafer 900 in Figure 9) and may be contained in a die (e.g., die 902 in Figure 9). The die substrate 1002 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1002 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon. These include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 1002. While some examples of materials from which the die substrate 1002 can be formed are described here, any material that can function as the basis for the IC device 1000 may be used. The die substrate 1002 may be part of a detached die (e.g., die 902 in Figure 9) or part of a wafer (e.g., wafer 900 in Figure 9).

[0053] The IC device 1000 may include one or more device layers 1004 disposed on and / or above the die substrate 1002. The device layer 1004 may include features of one or more transistors 1040 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The device layer 1004 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 that controls the current between the S / D regions 1020, and one or more S / D contacts 1024 that route electrical signals to and from the S / D regions 1020. The transistor 1040 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1040 is not limited to the type and configuration shown in Figure 10 and may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as double-gate or tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0054] Each transistor 1040 may include a gate 1022 comprising a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-K dielectric materials. High-K dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-K materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some cases, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0055] The gate electrode is formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1040 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers, such as barrier layers, may be included. For PMOS transistors, the metals that can be used for the gate electrode are not limited to, but include ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described below for NMOS transistors (e.g., for work function tuning). For NMOS transistors, the metals that can be used for the gate electrode are not limited to these, but include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above for PMOS transistors (e.g., for work function tuning).

[0056] In some examples, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom substantially parallel to the surface of the die substrate 1002 and two sidewalls substantially perpendicular to the first surface of the die substrate 1002. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the first surface of the die substrate 1002 and not comprising sidewall portions substantially perpendicular to the first surface of the die substrate 1002. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar, non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0057] In some examples, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching process operations. In some examples, multiple pairs of spacers may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0058] The S / D region 1020 may be formed in the die substrate 1002 adjacent to the gate 1022 of the corresponding transistor 1040. The S / D region 1020 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1002 to form the S / D region 1020. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 1002. In the latter process, the die substrate 1002 may first be etched to form a recess at the location of the S / D region 1020. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 1020. In some implementations, the S / D region 1020 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, epitaxially deposited silicon alloys can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 1020 can be formed using one or more alternative semiconductor materials such as germanium, or group III-V materials, or alloys. In further examples, one or more layers of metals and / or metallic alloys can be used to form the S / D region 1020.

[0059] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from devices on device layer 1004 (e.g., transistor 1040) via one or more interconnect layers (shown as interconnect layers 1006-1010 in Figure 10) located on device layer 1004. For example, electrically conductive features of device layer 1004 (e.g., gate 1022 and S / D contact 1024) can be electrically connected to interconnect structures 1028 of interconnect layers 1006-1010. One or more interconnect layers 1006-1010 may form a metallization stack (also called an ILD stack) 1019 of the IC device 1000.

[0060] The interconnect structure 1028 can be placed within the interconnect layers 1006-1010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the specific configuration of the interconnect structure 1028 shown in Figure 10). While a certain number of interconnect layers 1006-1010 are shown in Figure 10, examples of the present disclosure include IC devices having more or fewer interconnect layers than shown.

[0061] In some examples, the interconnection structure 1028 may include lines 1028A and / or vias 1028B filled with an electrically conductive material such as metal. Lines 1028A may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1002 on which the device layer 1004 is formed. For example, lines 1028A may route electrical signals in the in-page and / or out-page direction from the viewpoint of Figure 10. Vias 1028B may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed. In some examples, vias 1028B may electrically connect lines 1028A of different interconnection layers 1006-1010 together.

[0062] The interconnection layers 1006-1010 may include dielectric material 1026 disposed between interconnection structures 1028, as shown in Figure 10. In some examples, the dielectric material 1026 disposed between the interconnection structures 1028 of different interconnection layers 1006-1010 may have different compositions. That is, in other examples, the composition of the dielectric material 1026 between different interconnection layers 1006-1010 may be the same.

[0063] The first interconnection layer 1006 (referred to as metal 1 or "M1") may be formed directly on the device layer 1004. In some examples, the first interconnection layer 1006 may include lines 1028A and / or vias 1028B, as shown. Lines 1028A of the first interconnection layer 1006 may be coupled to contacts (e.g., S / D contacts 1024) of the device layer 1004.

[0064] The second interconnection layer 1008 (referred to as metal 2 or "M2") may be formed directly on the first interconnection layer 1006. In some examples, the second interconnection layer 1008 may include vias 1028B for connecting lines 1028A of the second interconnection layer 1008 to lines 1028A of the first interconnection layer 1006. Although lines 1028A and vias 1028B are structurally depicted as lines within each interconnection layer (e.g., within the second interconnection layer 1008) for clarity, lines 1028A and vias 1028B may be structurally and / or materially continuous in some examples (e.g., filled simultaneously during a dual-damascene process).

[0065] The third interconnection layer 1010 (referred to as metal 3 or "M3") (and, if necessary, additional interconnection layers) may be formed consecutively on the second interconnection layer 1008 according to similar techniques and / or configurations described in relation to the second interconnection layer 1008 or the first interconnection layer 1006. In some examples, "higher up" (i.e., further away from device layer 1004) interconnection layers within the metallization stack 1019 in the IC device 1000 may be thicker.

[0066] The IC device 1000 may include a solder resist material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interconnect layers 1006-1010. In Figure 10, the conductive contacts 1036 are shown as bond pads. The conductive contacts 1036 may be electrically connected to the interconnect structure 1028 and configured to route electrical signals from the transistor 1040 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 1036 to mechanically and / or electrically connect the chip containing the IC device 1000 to another component (e.g., a circuit board). The IC device 1000 may include additional or alternative structures for routing electrical signals from the interconnect layers 1006-1010. For example, the conductive contacts 1036 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0067] Figure 11 is a cross-sectional side view of an IC device assembly 1100 which may include an IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1100 includes several components arranged on a circuit board 1102 (which may be, for example, a motherboard). The IC device assembly 1100 includes components arranged on a first surface 1140 of the circuit board 1102 and a second surface 1142 on the opposite side of the circuit board 1102, and generally, components may be arranged on one or both of surfaces 1140 and 1142. Any of the IC packages described below with reference to the IC device assembly 1100 may take the form of the exemplary IC package 100 in Figure 1.

[0068] In some examples, the circuit board 1102 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally together with other metal layers) between components coupled to the circuit board 1102. In other examples, the circuit board 1102 may be a non-PCB board.

[0069] The IC device assembly 1100 shown in Figure 11 includes a package-on-interposer structure 1136 coupled to the first surface 1140 of a circuit board 1102 by a coupling component 1116. The coupling component 1116 electrically and mechanically couples the package-on-interposer structure 1136 to the circuit board 1102 and may include solder balls, male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures (as shown in Figure 11).

[0070] The package-on-interposer structure 1136 may include an IC package 1120 coupled to an interposer 1104 by a coupling component 1118. The coupling component 1118 can take any form suitable for the application, such as the form described above with reference to the coupling component 1116. Although a single IC package 1120 is shown in Figure 11, multiple IC packages may be coupled to the interposer 1104, and in fact, additional interposers may be coupled to the interposer 1104. The interposer 1104 may provide an intervening substrate used to bridge the circuit board 1102 and the IC package 1120. The IC package 1120 may be, for example, a die (die 902 in Figure 9), an IC device (e.g., IC device 1000 in Figure 10), or any other suitable component, or may include them. Generally, the interposer 1104 may spread the connections to a wider pitch or reroute the connections to different connections. For example, the interposer 1104 may couple an IC package 1120 (e.g., a die) to a set of BGA conductive contacts of coupling component 1116 for coupling to a circuit board 1102. In the example shown in Figure 11, the IC package 1120 and the circuit board 1102 are mounted on opposite sides of the interposer 1104, while in other examples, the IC package 1120 and the circuit board 1102 may be mounted on the same side of the interposer 1104. In some examples, three or more components may be interconnected by the interposer 1104.

[0071] In some examples, the interposer 1104 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1104 may be formed from polymer materials such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin containing inorganic fillers, ceramic materials, or polyimide. In some examples, the interposer 1104 may be formed from alternative rigid or flexible materials, which may include the same materials as above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1104 may include vias 1106, which may include metal interconnects 1108 and, but is not limited to, through-silicon vias (TSVs) 1110. The interposer 1104 may further include embedded devices 1114, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1104. The package-on-interposer structure 1136 may take any form of package-on-interposer structure known in the art.

[0072] The IC device assembly 1100 may include an IC package 1124 coupled to the first surface 1140 of a circuit board 1102 by a coupling component 1122. The coupling component 1122 can take any form of the examples described above with reference to the coupling component 1116, and the IC package 1124 can take any form of the examples described above with reference to the IC package 1120.

[0073] The IC device assembly 1100 shown in Figure 11 includes a package-on-package structure 1134 coupled to the second surface 1142 of a circuit board 1102 by a coupling component 1128. The package-on-package structure 1134 may include a first IC package 1126 and a second IC package 1132, which are coupled together by a coupling component 1130 such that the first IC package 1126 is positioned between the circuit board 1102 and the second IC package 1132. The coupling components 1128 and 1130 can take any form of the examples of coupling components 1116 described above, and the IC packages 1126 and 1132 can take any form of the examples of IC packages 1120 described above. The package-on-package structure 1134 may be configured according to any package-on-package structure known in the art.

[0074] Figure 12 is a block diagram relating to one exemplary electrical device 1200, which may include one or more exemplary IC packages 100. For example, any suitable components of the electrical device 1200 may include one or more of the device assemblies 1100, IC devices 1000, or dies 902 disclosed herein, and may be arranged within an exemplary IC package 100. While several components are shown in Figure 12 as being included in the electrical device 1200, any one or more of these components may be omitted or duplicated as is suitable for the application. In some examples, some or all of the components included in the electrical device 1200 may be mounted on one or more motherboards. In some examples, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0075] Additionally, in various examples, the electrical device 1200 does not have to include one or more of the components shown in Figure 12, but it may include interface circuits for coupling to one or more components. For example, the electrical device 1200 does not have to include the display 1206, but it may include a display interface circuit (e.g., a connector and driver circuit) to which the display 1206 can be coupled. In another set of examples, the electrical device 1200 does not have to include an audio input device 1218 (e.g., a microphone) or an audio output device 1208 (e.g., a speaker, headset, earphone, etc.), but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1218 or audio output device 1208 can be coupled.

[0076] The electrical device 1200 may include a programmable circuit 1202 (e.g., one or more processing devices). The programmable circuit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1200 includes a memory 1204, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, the memory 1204 may include memory that shares a die with the programmable circuit 1202. This memory is used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0077] In some examples, the electrical device 1200 may include a communication chip 1212 (e.g., one or more communication chips). For example, the communication chip 1212 may be configured to manage wireless communication for transferring data to or from the electrical device 1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not mean that the device in question is wire-free, although in some examples it may be wire-free.

[0078] The communication chip 1212 may implement any of several wireless standards or protocols. These include, but are not limited to, the Wi-Fi® (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-1105 amendment), and the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra-Mobile Broadband (UMB) project (also known as "3GPP2"), etc.), including Institute of Electrical and Electronics Engineers (IEEE) standards. IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, and a certification mark for products that pass conformity and interoperability tests against the IEEE 802.16 standard. The communication chip 1212 may operate in accordance with Global System for Mobile Communications (GSM), General Purpose Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1212 may operate in accordance with GSM Evolution Extension Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Extended Cordless Telecommunications (DECT), Evolution Data Optimization (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other examples, the communication chip 1212 may operate in accordance with other wireless protocols. The electrical device 1200 may include an antenna 1222 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0079] In some examples, the communication chip 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 1212 may include multiple communication chips. For example, the first communication chip 1212 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth®, and the second communication chip 1212 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communication chip 1212 may be dedicated to wireless communications, and the second communication chip 1212 may be dedicated to wired communications.

[0080] The electrical device 1200 may include a battery / power supply circuit 1214. The battery / power supply circuit 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power).

[0081] The electrical device 1200 may include a display 1206 (or, as described above, a corresponding interface circuit). The display 1206 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0082] The electrical device 1200 may include an audio output device 1208 (or a corresponding interface circuit as described above). The audio output device 1208 may include any device that generates an audible indicator, such as a speaker, headset, or earphones.

[0083] The electrical device 1200 may include an audio input device 1218 (or, as described above, a corresponding interface circuit). The audio input device 1218 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0084] The electrical device 1200 may include a GPS circuit 1216. The GPS circuit 1216 communicates with a satellite-based system and obtains the position of the electrical device 1200 as known in the art.

[0085] The electrical device 1200 may include any other output device 1210 (or a corresponding interface circuit as described above). Examples of other output devices 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0086] The electrical device 1200 may include any other input device 1220 (or, as described above, a corresponding interface circuit). Examples of other input devices 1220 may include an accelerometer, gyroscope, compass, image capture device, cursor control device such as a keyboard or mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0087] The electrical device 1200 may have any desired form factor. These could be a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or a wearable electrical device. In some examples, the electrical device 1200 could be any other electronic device that processes data.

[0088] The terms “including” and “comprising” (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble to any type of claim, it should be understood that additional elements, terms, etc., may exist without departing from the scope of the corresponding claim or description. The phrase “at least” is open-ended, as is the case herein, when used, for example, as a transitional clause in a claim preamble. The term “and / or” refers to any combination or subset relating to (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C, for example, when used in the form of A, B, and / or C. The phrase “at least one of A and B” is intended to refer to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) either at least one A and at least one B.As used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0089] As used herein, singular references (e.g., “one” (“a” or “an”)), “first” (“first”), “second” (“second”), etc.) do not exclude the plural. As used herein, the term “one” (“a” or “an”) object refers to one or more of those objects. The terms “one” (“a” or “an”), “one or more” (“one or more”), and “at least one” (“at least one”) are used interchangeably herein. Furthermore, although listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and inclusion in different examples or claims does not mean that the combination of features is unfeasible and / or unfavorable.

[0090] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. The first part is above the second part if the second part has at least one part between the Earth and the first part. Similarly, as used herein, the first part is “below” the second part if the first part is closer to the Earth than the second part. As described above, the first part may be above or below the second part, with other parts between them, without other parts between them, in contact with the first and second parts, or not in direct contact with each other.

[0091] Notwithstanding the foregoing, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in the process of being manufactured or produced, “above” is not relative to the earth, but rather to the underlying substrate on which the relevant components are manufactured, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise stated or implied by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component in a semiconductor die when that first component is further from the substrate (e.g., a semiconductor wafer) in the process of being manufactured / produced than a second component on which two components are manufactured or otherwise provided. Similarly, unless otherwise stated or suggested by the context, the first component in an IC package (e.g., a semiconductor die) is "above" the second component in the IC package during manufacturing when the first component is further away from the printed circuit board (PCB) on which the IC package is mounted or to which it is to be attached. It should be understood that semiconductor devices are often used in a different orientation than that in which they are manufactured. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of "above" in the previous paragraph (i.e., the term "above" describes the relationship between the two parts relative to the earth) is probably governed by the context of use.

[0092] As used in this patent, to state that any part (e.g., a layer, film, area, region, or plate) is located on another part in any way (e.g., positioned on, situated on, placed on, or formed on, etc.) indicates that the part being referenced is in contact with the other part, or that the part being referenced is on top of the other part and one or more intermediate parts are located between them.

[0093] As used herein, connection references (e.g., attached, joined, connected, and joined) may, unless otherwise specified, include intermediate members between the elements referred to by the connection reference and / or relative movement between those elements. Thus, a connection reference does not necessarily imply that two elements are directly connected and / or are in a fixed relationship with one another. As used herein, the statement that any part is “in contact” with another part is defined to mean that there is no intermediate part between the two parts.

[0094] Unless otherwise specified, descriptors such as “first”, “second”, “third”, etc., are used herein without any implication or indication of priority, physical order, placement in a list, and / or ordering meaning. They are merely used as labels and / or arbitrary names to distinguish elements for the sake of clarity in the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in a detailed description, while the same element may be referred to in a claim using a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are merely used to clearly distinguish those elements in the context of the description (e.g., in a claim) where they otherwise share the same name.

[0095] As used herein, “approximately” and “about” modify their subject / values ​​to acknowledge the potential existence of variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world defects, as would be understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance of + / - 10%, unless otherwise specified herein.

[0096] As used herein, “substantially real time” refers to an occurrence in a nearly instantaneous manner, acknowledging that real-world delays may exist in calculating time, transmission, etc. Therefore, unless otherwise specified, “substantially real time” means real time plus one second.

[0097] As used herein, the phrase “in communication,” including its variations, encompasses direct communication and / or indirect communication through one or more intermediate components, and additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events, rather than requiring direct physical (e.g., wired) communication and / or continuous communication.

[0098] As used herein, “programmable circuitry” is defined to include (i) one or more dedicated electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable using instructions to perform a particular function and / or operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include programmable microprocessors, such as central processing units (CPUs), that can execute a first instruction to perform one or more operations and / or functions; field-programmable gate arrays (FPGAs), which can be programmed using a second instruction to cause configuration and / or structuring of an FPGA to instantiate one or more operations and / or functions corresponding to a first instruction; graphics processor units (GPUs), which can execute a first instruction to perform one or more operations and / or functions; digital signal processors (DSPs), XPUs, network processing units (NPU0s), which can execute a first instruction to perform one or more operations and / or functions; and / or integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and orchestration techniques (e.g., an Application Programming Interface (API)) that allow the computing task to be assigned to any one of the multiple types of programmable circuits that is suitable for performing the computing task and is available.

[0099] As used herein, an integrated circuit / circuit is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of the following: ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate combining multiple circuit elements, system-on-a-chip (SoC), etc.

[0100] From the above, it will be understood that exemplary systems, apparatus, products, and methods for reducing the stress experienced by a glass core during loading have been disclosed. Examples disclosed herein include interfaces that reduce stress concentration in the power supply region of the glass core. Examples disclosed herein enable the packaging of power supply components such as CMIL, PTH, and TGV, while maintaining the structural integrity of the glass core. Examples disclosed herein reduce the back crack defect rate of the glass core, which increases part yield and reduces manufacturing costs.

[0101] Glass cores with embedded power supply components are disclosed herein. Further examples and combinations thereof include:

[0102] Example 1 includes a device comprising a glass layer having an opening, a dielectric material within the opening, a first cluster of inductors extending through the dielectric material, and a second cluster of inductors extending through the dielectric material. The second cluster is spaced apart from the first cluster, and the dielectric material extends continuously from around the first cluster to around the second cluster.

[0103] Example 2 includes an apparatus relating to any prior example, wherein the opening extends through the glass layer from a first surface of the glass layer to a second surface of the glass layer, the second surface being on the opposite side of the first surface.

[0104] Example 3 includes an apparatus relating to any prior example, wherein the opening includes an inner surface, and the dielectric material includes an outer surface in contact with the inner surface.

[0105] Example 4 includes an apparatus relating to any prior example, wherein the apparatus further includes A glass wall is included between the first cluster and the second cluster, and the dielectric material extends around at least one of the upper or lower ends of the glass wall.

[0106] Example 5 includes an apparatus relating to any prior example, wherein the apparatus further includes a transition surface extending between a glass wall and a glass layer.

[0107] Example 6 includes a device relating to any prior example, where the transition surface is a fillet.

[0108] Example 7 includes an apparatus relating to any prior example, wherein the first upper surface of the dielectric material is coplanar with the second upper surface of the dielectric material.

[0109] Example 8 includes a device comprising a semiconductor die and a substrate supporting the semiconductor die. The substrate includes a glass core, a glass core comprising a body including an opening and a dielectric material within the opening, and a first cluster of inductors extending through the dielectric material, wherein adjacent inductors in the first cluster are spaced a first distance apart, and a second cluster of inductors extending through the dielectric material, wherein the first inductors in the first cluster are at least close to the second inductors in the second cluster, as any other inductor in the first cluster is to any inductor in the second cluster, and the first inductors are spaced a second distance apart from the second inductors, the second distance being greater than the first distance, and the dielectric material extending continuously between the first and second inductors, and a second cluster of inductors. device.

[0110] Example 9 includes a device relating to any prior example, where a first cluster of inductors and a second cluster of inductors are arranged in a column, and the column further includes a third cluster of inductors offset from the first cluster of inductors and the second cluster of inductors.

[0111] Example 10 includes a device relating to any prior example, wherein the device further includes a plurality of plated through-holes aligned with a third cluster, the plated through-holes extending through a dielectric material.

[0112] Example 11 includes a device relating to any prior example, wherein the device further includes a glass webbing positioned between a first cluster of inductors and a second cluster of inductors.

[0113] Example 12 includes a device relating to any prior example, wherein the body includes a first outer surface and a second outer surface opposite the first outer surface, and the webbing is recessed from the first and second outer surfaces.

[0114] Example 13 includes a device relating to any prior example, wherein the device further includes a curved surface extending between a first outer surface and a glass core.

[0115] Example 14 includes a device relating to any prior example, wherein the first outer surface is coplanar with the third outer surface of the glass core.

[0116] Example 15 includes a device relating to any prior example, wherein the opening includes an inner surface, the dielectric material includes an outer surface in contact with the inner surface, and the inner surface is a straight wall.

[0117] Example 16 includes a device comprising a glass core, a structural part, a power supply part, and an interface between the structural part and the power supply part, the interface between the recess of the power supply part and the outer surface of the glass core, the interface including at least one of (i) a material interface or (ii) a curved transition surface, and a plurality of coaxial metal inductor loop clusters in the power supply part.

[0118] Example 17 includes an apparatus relating to any prior example, wherein a plurality of coaxial metal inductor loop clusters are arranged in a first row and a second row, the first row including a first cluster, a second cluster, and a third cluster, the third cluster being offset from the first and second clusters.

[0119] Example 18 includes a device relating to any prior example, wherein the outer surface is a first outer surface, and the second outer surface of the power supply unit is coplanar with the first outer surface.

[0120] Example 19 includes an apparatus relating to any prior example, wherein the power supply unit includes a dielectric filler, and the recess is aligned with the dielectric filler in a direction perpendicular to the outer surface.

[0121] Example 20 includes an apparatus relating to any prior example, wherein the structural portion has a first thickness, and the recessed portion has a second thickness that is at least 10% of the first thickness. The subsequent claims are incorporated by this reference into this detailed description. While certain exemplary systems, apparatuses, articles, and methods have been disclosed herein, the scope of this patent is not limited to them. Rather, this patent encompasses all systems, apparatuses, articles, and methods that fairly fall within the scope of the claims of this patent.

Claims

1. It is a device, A glass layer having an opening, The dielectric material in the opening, A first cluster of inductors extending through the dielectric material, A second cluster of inductors extending through the dielectric material, Includes, The second cluster is separated from the first cluster. The dielectric material extends continuously from the periphery of the first cluster to the periphery of the second cluster. Device.

2. The opening extends through the glass layer from the first surface to the second surface of the glass layer. The second surface is located on the opposite side of the first surface. The apparatus according to claim 1.

3. The aforementioned opening includes the inner surface, The dielectric material includes an outer surface that is in contact with the inner surface, The apparatus according to claim 2.

4. The aforementioned device further, A glass wall is included between the first cluster and the second cluster. The dielectric material extends around at least one of the upper or lower ends of the glass wall. The apparatus according to claim 1.

5. The aforementioned device further, It includes a transition surface that extends between the glass wall and the glass layer. The apparatus according to claim 4.

6. The transition surface is a fillet. The apparatus according to claim 5.

7. The first upper surface of the dielectric material is coplanar with the second upper surface of the dielectric material. The apparatus according to any one of claims 1 to 6.

8. It is a device, Semiconductor die and The substrate supporting the semiconductor die includes, The aforementioned substrate is It has a glass core, The main body including the opening, The dielectric material in the opening, Includes a glass core and This is a first cluster of inductors extending through the dielectric material, In the first cluster, adjacent inductors are spaced apart by a first distance. The first cluster of inductors, This is a second cluster of inductors extending through the dielectric material, The first inductor in the first cluster is at least close to the second inductor in the second cluster, just as any other inductor in the first cluster is close to any inductor in the second cluster. The first inductor is spaced a second distance away from the second inductor. The second distance is greater than the first distance. The dielectric material extends continuously between the first inductor and the second inductor. The second cluster of inductors, including, device.

9. The first cluster of inductors and the second cluster of inductors are arranged in a single row. The row further includes a third cluster of inductors, offset from the first cluster of inductors and the second cluster of inductors. The device according to claim 8.

10. The aforementioned device further, It includes a plurality of plated through-holes aligned with the third cluster, The plated through-hole extends through the dielectric material. The device according to claim 9.

11. The aforementioned device further, This includes a glass webbing positioned between the first cluster of inductors and the second cluster of inductors. The device according to claim 9.

12. The body includes a first outer surface and a second outer surface opposite to the first outer surface. The webbing is recessed from the first outer surface and the second outer surface. The device according to claim 11.

13. The aforementioned device further, Including a curved surface extending between the first outer surface and the glass core, The device according to claim 12.

14. The first outer surface is coplanar with the third outer surface of the glass core. The device according to claim 12.

15. The opening includes the inner surface, The dielectric material includes an outer surface that is in contact with the inner surface, The aforementioned inner surface is a straight wall. The device according to claim 9.

16. It is a device, It has a glass core, structural part, Power supply unit, and, The interface between the structural part and the power supply part, Between the recess of the power supply unit and the outer surface of the glass core, there is at least one of (i) a material interface or (ii) a curved transition surface, interface, Includes a glass core and Multiple coaxial metal inductor loop clusters in the power supply unit, A device including a device.

17. The aforementioned multiple coaxial metal inductor loop clusters are arranged in the first and second rows, The first line is, Cluster 1, The second cluster, and, The third cluster is offset from the first and second clusters, including, The apparatus according to claim 16.

18. The aforementioned outer surface is the first outer surface, and The second outer surface of the power supply unit is coplanar with the first outer surface. The apparatus according to claim 16.

19. The power supply unit includes a dielectric filler, The recess portion is aligned with the dielectric filler in a direction perpendicular to the outer surface. The apparatus according to any one of claims 16 to 18.

20. The aforementioned structural part has a first thickness, and The recess portion has a second thickness which is at least 10% of the first thickness. The apparatus according to claim 19.

Images