Manufacturing method of wiring boards

Abstract

Providing a wiring board equipped with fine wiring. [Solution] The method for manufacturing a wiring board according to the embodiment includes forming a photosensitive resin layer, forming an insulating layer 20 by exposing the photosensitive resin layer to light, and forming a conductor layer 30 on the insulating layer 20, which includes a pattern placement area 301 and a pattern non-placement area 302. Forming the insulating layer 20 includes exposing the photosensitive resin layer to light such that the degree of hardening of the region of the photosensitive resin layer that overlaps with the pattern non-placement area 302 in a plan view is higher than the degree of hardening of the region of the photosensitive resin layer that overlaps with the pattern placement area 301 in a plan view.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board using an exposure apparatus that modulates a light beam emitted from a light source according to an exposed pattern and performs direct drawing exposure without using a photomask. The exposure apparatus includes two light sources that emit light of different wavelengths.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, peeling of wiring from an interlayer material may occur. When the adhesion between the interlayer material and the wiring is high, there is a possibility that a short circuit may occur between the wirings.

Means for Solving the Problems

[0005] The method for manufacturing a wiring board of the present invention includes forming a photosensitive resin layer, forming an insulating layer by exposing the photosensitive resin layer, and forming a conductor layer including a pattern arrangement portion and a non-pattern arrangement portion on the insulating layer. Forming the insulating layer includes exposing the photosensitive resin layer such that the degree of curing of the region of the photosensitive resin layer that overlaps with the non-pattern arrangement portion in plan view is higher than the degree of curing of the region of the photosensitive resin layer that overlaps with the pattern arrangement portion in plan view.

[0006] According to embodiments of the present invention, it is possible to form a wiring substrate having a fine wiring pattern that exhibits good adhesion to the interlayer material and is less prone to short-circuit failures. [Brief explanation of the drawing]

[0007] [Figure 1] A partial cross-sectional view showing an example of a wiring board manufactured by the manufacturing method of one embodiment of the present invention. [Figure 2A] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2B] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2C] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2D] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2E] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2F] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2G] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2H] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 2I] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Modes for carrying out the invention]

[0008] The method for manufacturing a wiring board of the present invention will be described below with reference to the drawings. Note that the drawings referenced below are not intended to show the precise proportions of each component, but are drawn in a way that facilitates understanding of the features of the present invention. A wiring board 1, an example of a wiring board manufactured by one embodiment of the manufacturing method, is a wiring board including a laminated structure composed of multiple alternately stacked conductor layers and insulating layers. Conductor layers facing each other with a single insulating layer in between are electrically connected by via conductors that penetrate the insulating layer in the thickness direction. The number of conductor layers and insulating layers included in the manufactured wiring board is not limited and can be selected as appropriate. The laminated structure of the wiring board is also not limited.

[0009] Figure 1 shows a cross-sectional view of a part of a wiring board 1, which is an example of a wiring board according to this embodiment. The wiring board 1 in the illustrated example comprises an insulating layer 20 formed on a conductor layer 10, a conductor layer 30 formed on the insulating layer 20 and the conductor layer 10 so as to face the conductor layer 10 with the insulating layer 20 in between, and via conductors 35 connecting the conductor layer 10 and the conductor layer 30. The conductor layer 30 has a predetermined wiring pattern formed thereon, including a pattern arrangement portion 301 on which wiring 33 is formed and a pattern non-arrangement portion 302. The via conductors 35 and the wiring 33 in the wiring pattern are composed of a metal film layer 31 and a plating film layer 32 on the metal film layer 31.

[0010] In the description of the wiring board 1 of this embodiment, in relation to the conductor layer 10 and the insulating layer 20, the conductor layer 10 side, i.e., the lower side on the page, is referred to as the "lower side" or simply "bottom," and the insulating layer 20 side is referred to as the "upper side" or simply "top."

[0011] The wiring board 1 is merely an example of a wiring board in this embodiment. Although four wirings 33 are shown in Figure 1, the number of wirings 33 is not limited and can be formed in any desired pattern. Similarly, the number of via conductors 35 is not limited. The via conductors 35 of the wiring board 1 in this embodiment can be formed in any desired number at any desired location, depending on the wiring patterns contained in the upper and lower conductor layers to which they are connected.

[0012] The insulating layer 20 is formed, for example, by exposing a photosensitive resin layer, which is formed from any photosensitive resin, to light. Examples of photosensitive resins used to form the insulating layer 20 include, but are not limited to, photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. In the illustrated example, the insulating layer 20 is described as not containing inorganic fillers such as silica, but an insulating layer containing inorganic fillers may be used to change the properties of the insulating layer 20. Examples of inorganic fillers include fillers consisting of fine particles such as silica (SiO2), alumina, or mullite. The insulating layer 20 can be formed from any material that provides photosensitivity and insulation to the conductor layer 10 and the conductor layer 30, and that can support or cover the conductor layer 10 and the conductor layer 30. The number of conductor layers and insulating layers formed below and above the insulating layer 20 in the wiring board 1 is not limited.

[0013] As shown in Figure 1, the insulating layer 20 is formed from a first region 21 that overlaps in plan view with the pattern placement portion 301 in the wiring pattern of the conductor layer 30 or around the vias (land portion 351) of the via conductor 35, and a second region 22 that overlaps in plan view with the pattern non-placement portion 302 in the wiring pattern of the conductor layer 30. The second region 22 is exposed from the wiring pattern of the conductor layer 30 in plan view. The upper surface 21a of the first region 21 is formed lower than the upper surface 22a of the second region 22. For example, the upper surface 21a of the first region 21 is about 0.5 μm lower than the upper surface 22a of the second region 22. Here, "plan view" means viewing the object with a line of sight parallel to the thickness direction of the wiring board 1.

[0014] The insulating layer 20 is formed such that the Young's modulus of the first region 21 in the insulating layer 20 is 5% or more and 95% or less of the Young's modulus of the second region 22 in the insulating layer 20. That is, in the wiring board 1 of the embodiment, the first region 21 of the insulating layer 20 on which the land portion 351 of the wiring 33 or via conductor 35 is formed is formed of a resin with a smaller Young's modulus than the second region 22, i.e., a softer resin.

[0015] As described above, on the upper surface 21a of the first region 21, a land portion 351 of the wiring 33 or the via conductor 35 in the wiring pattern of the conductor layer 30 is formed. As the conductor constituting the conductor layers 10, 30, and the via conductor 35, any conductive metal may be used, and examples thereof include copper and nickel. Preferably, the conductor layers 10, 30, and the via conductor 35 are formed of copper. As described above, in the example of FIG. 1, the conductor layer 30 including the via conductor 35 and the wiring 33 has a two-layer structure including the metal film layer 31 and the plating film layer 32 (preferably an electrolytic plating film layer). The conductor layer 30 is integrally formed with the via conductor 35. Therefore, the via conductor 35 is formed by the same metal film layer 31 and plating film layer 32 as the conductor layer 30. The conductor layer 30 is patterned to have a predetermined wiring pattern.

[0016] In FIG. 1, the conductor layer 10 is shown as a single-layer structure, but it may have a multilayer structure of two or more layers. Similar to the conductor layer 30, the conductor layer 10 may be formed from a metal film layer and a plating film layer. Further, the conductor layer 10 may have a three-layer structure including a metal foil such as a copper foil, a metal film layer (for example, a copper sputtering film or an electroless copper plating film), and an electrolytic plating film layer (for example, an electrolytic copper plating film). The conductor layer 10 may be patterned to have a predetermined conductor pattern.

[0017] In this embodiment, the metal film layer 31 of the conductor layer 30 may be, as an example, a sputtering film layer. Preferably, the sputtering film layer is a copper sputtering film layer. When sputtering is used to form the metal film layer 31, in the collision of metal particles (copper particles) with the upper surface 20a of the insulating layer 20 (see FIG. 2D) during sputtering, the metal particles penetrate deeper into the soft, i.e., the region 21 with a small Young's modulus, of the insulating layer 20 than into the region 22 with a large Young's modulus. Therefore, the upper surface of the insulating layer 20 after the formation of the metal film layer 31 is formed by the upper surface 21a of the first region 21 with a lower height formed by the deeper penetration of the metal particles and the upper surface 22a of the second region 22 having substantially the same height as the upper surface 20a of the insulating layer 20 before sputtering because of the less penetration of the metal particles. Therefore, the height of the upper surface 22a of the second region 22 of the insulating layer 20 is higher than the height of the upper surface 21a of the first region 21.

[0018] In this embodiment, in the pattern arrangement portion 301 for forming the wiring 33 of the conductor layer 30 and the land portion 351 of the via conductor 35, a conductor layer 30 is formed in which the metal forming the metal film layer 31 has deeply penetrated into the insulating layer 20. The adhesion of the metal film layer 31 to the insulating layer 20 is enhanced. A wiring substrate with improved adhesion between the wiring 33 of the wiring pattern and the insulating layer 20 and less likely to cause peeling or the like can be obtained. Even when the wiring 33 of the conductor layer 30 is formed with a fine pitch, peeling of the wiring 33 from the insulating layer 20 is prevented. A wiring substrate including a fine wiring pattern is formed with good yield.

[0019] Next, taking the wiring substrate 1 in FIG. 1 as an example, the manufacturing method of the wiring substrate of the embodiment will be specifically described with reference to FIGS. 2A to 2I.

[0020] As shown in Figure 2A, an insulating resin layer 200, which will become the insulating layer 20, is formed on the upper surface 10F of the conductor layer 10. A photosensitive resin is preferred as the material for the insulating resin layer 20. That is, the insulating resin layer 200 can be a photosensitive resin layer. The insulating layer 20 is formed by exposing the photosensitive resin layer to light. Examples of photosensitive resins that can be used include photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. For example, a liquid photosensitive resin is applied to the upper surface 10F of the conductor layer 10. Alternatively, a photosensitive resin film formed in film form may be attached to the upper surface 10F of the conductor layer 10.

[0021] In the manufacturing method of this embodiment, the Young's modulus of the insulating resin layer 200 is adjusted by performing an exposure treatment on the insulating resin layer 200. For example, by changing the number of exposures at a specific location, the insulating resin layer 200 can be photosensitive so that multiple regions with different degrees of hardening are formed. Therefore, it is preferable that the photosensitive resin used as the material for the insulating resin layer 200 be of the negative type. Since a higher degree of hardening can be obtained in regions of the insulating resin layer 200 that are exposed more times, the hardness of the insulating resin layer 200 can be controlled by the number of exposures.

[0022] For example, the exposure process of this embodiment may include a first exposure step and a second exposure step. Specifically, in the first exposure step, the entire surface of the insulating resin layer 200 is exposed to light, excluding the area corresponding to the portion penetrated by the via conductor 35 (see Figure 1). Then, in the second exposure step, only the portion 201 of the insulating resin layer 200 that was exposed in the first exposure step, which is not covered by the wiring 33 and the land portion 351 (see Figure 1) of the via conductor 35, is additionally exposed. Through the two exposure processes, the insulating resin layer 200 is formed with the softest, unexposed region, the hardened region obtained as a result of the first exposure process, and the hardest region obtained as a result of the second exposure process.

[0023] In the wiring board 1 of this embodiment, the hardness of the insulating layer 20 is expressed by Young's modulus. The Young's modulus of the insulating resin layer 201 (see Figure 2B) cured by the first exposure treatment is, for example, 0.5 GPa or more and 1.9 GPa or less. The Young's modulus of the region of the insulating resin layer 200 (second region 22, see Figure 2C) cured by the second exposure treatment is, for example, 2.0 GPa or more and 4.0 GPa or less.

[0024] Specifically, the entire surface of the insulating resin layer 200, excluding the area corresponding to the portion penetrated by the via conductor 35 (see Figure 1), is exposed (first exposure step), thereby forming an uncured area A and a first cured area B in the insulating resin layer 200, as shown in Figure 2B. The first exposure step can be performed by any exposure method, but a direct imaging exposure method is sometimes preferred. In direct imaging exposure, laser light is directly irradiated onto the insulating resin layer 200 along the exposure pattern without using an exposure mask, and a first cured area B (insulating resin layer 201) is formed in the insulating resin layer 200. Since the entire area of ​​the wiring board can be scanned by the irradiated light in a single exposure, the increase in man-hours in the exposure process is suppressed, and therefore, the yield of wiring board manufacturing may be improved.

[0025] For direct imaging exposure, a semiconductor laser with a wavelength of 350 nm to 410 nm or a high-pressure mercury lamp can be used as the light source for illumination. The exposure amount can be determined by the illuminance of the exposure light source and the scanning speed of the illumination light.

[0026] Next, the area of ​​the first cured region B that is not covered by the land portions 351 (see Figure 1) of the wiring 33 and via conductor 35 is exposed (second exposure step). As shown in Figure 2C, a first region 21 is formed from the insulating resin layer 201 cured in the first exposure step, and a second region 22 is formed when the insulating resin layer 201 is further cured in the second exposure step. That is, in this embodiment, the insulating layer 20 is formed such that the area on which the land portions 351 (see Figure 1) of the wiring 33 and via conductor 35 are formed (first region 21) is a softer resin layer than the other areas (second region 22). For example, the Young's modulus of the area on which the land portions 351 (see Figure 1) of the wiring 33 and via conductor 35 are formed is 5% or more and 95% or less of the Young's modulus of the area on which the land portions 351 (see Figure 1) of the wiring 33 and via conductor 35 are not formed.

[0027] The second exposure step can be performed using any exposure method, but preferably, it can be performed using a direct imaging exposure method. Compared to the case in which an exposure mask is used, direct imaging exposure has the effect of suppressing the increase in the number of steps in the exposure step, and due to its high resolution, when the wiring 33 is formed with a fine pitch, exposure can be performed with a fine pattern that matches the fine pitch.

[0028] The exposure conditions in the first exposure step and the second exposure step may be the same or different. For example, the illuminance of the exposure light source may differ between the first exposure step and the second exposure step. Also, the exposure time, i.e., the scanning speed of the irradiation light, may differ. Each exposure condition can be appropriately selected and adjusted so that the degree of curing of each region in the insulating layer 20 is as desired.

[0029] Next, as shown in Figure 2D, the uncured region A (see Figure 2C) of the insulating resin layer 200 is removed by development. A through hole 35a is formed inside which the via conductor 35 (see Figure 1) is formed.

[0030] Next, by baking, an insulating layer 20 is formed in which the degree of hardening and height differ between the region where the land portions 351 (see Figure 1) of the wiring 33 and via conductors 35 are formed (first region 21) and the other region (second region 22). As shown in Figure 2E, the height of the first region 21, which is soft and has a lower Young's modulus, exposed only in the first exposure step, is lower than the height of the second region 22, which has a higher Young's modulus, exposed in both the first and second exposure steps. Next, as shown in Figure 2E, a metal film layer 31 is formed on the upper surface 20a (see Figure 2D) of the insulating layer 20, the side walls of the through holes 35a, and on the conductor layer 10 exposed from the insulating layer 20 (on the inner wall of the through holes 35a). The metal film layer 31 is preferably formed by sputtering. Examples of sputtering targets include copper, copper alloys, nickel, nickel alloys, titanium, or titanium alloys. Preferably, the sputtering is copper sputtering, and the metal film layer 31 is a copper sputtering film layer.

[0031] By forming the metal film layer 31 by sputtering, a thin and uniform metal film layer 31 is obtained. Furthermore, as shown in this embodiment, if the insulating layer 20 that serves as the base for sputtering has different degrees of hardening depending on the region, the metal particles produced by sputtering penetrate the insulating layer 20 to different degrees between regions, depending on the degree of hardening in each region. In the first region 21, which is softer and has a lower Young's modulus, the metal particles can penetrate deeply into the insulating layer 20. Therefore, the metal film layer 31 adheres to the insulating layer 20 with a high degree of adhesion in the first region 21. On the other hand, in the second region 22, which has a higher Young's modulus, the metal particles cannot penetrate deeply into the insulating layer 20, and therefore the metal film layer 31 adheres to the insulating layer 20 in the second region 22 with a lower degree of adhesion than in the first region 21. Due to the deep penetration of the metal particles into the insulating layer 20, the height of the upper surface 21a of the first region 21 may be formed lower than before sputtering. In the second region 22, since there is little penetration of metal particles into the insulating layer 20, the height of the upper surface 22a of the second region 22 is formed to be approximately the same height as before sputtering.

[0032] Next, a resist layer 40 is laminated on the upper surface 20a of the insulating layer 20 via the metal film layer 31. As the resist layer 40, any photosensitive resin, such as a dry film resist of a photosensitive epoxy resin, polyhydroxy ether resin, phenol resin, or polyimide resin, can be used. The resist layer 40 is exposed and developed using a mask having an aperture pattern corresponding to the wiring pattern of the conductor layer 30 (see Figure 1). As shown in Figure 2F, a resist layer 40 is formed having apertures 40a at positions corresponding to the wiring 33 and via conductors 35 of the conductor layer 30.

[0033] Next, as shown in Figure 2G, a plating film layer 32 is formed within the opening 40a of the resist layer 40. At the same time, the through hole 35a is filled with the plating film layer 32. The plating film layer 32 is preferably formed by electroplating with a metal film layer 31 as the power supply layer. In other words, in this embodiment, the metal film layer 31 is a seed layer.

[0034] Next, the resist layer 40 is removed using, for example, an alkaline stripping solution. As a result of removing the resist layer 40, the metal film layer 31 is exposed in the pattern-free areas 302, as shown in Figure 2H.

[0035] Next, the exposed portion of the metal film layer 31 is removed, for example, by quick etching. As described above, the second region 22 of the insulating layer 20 below the pattern-less portion 302 is formed to have a large Young's modulus, and the penetration of metal particles constituting the metal film layer 31 into the insulating layer 20 is small. The metal film layer 31 adheres to the upper surface 22a of the second region 22 of the insulating layer 20 with a small degree of adhesion. Therefore, the metal film layer 31 on the second region 22 is easily removed.

[0036] By removing the metal film layer 31 on the second region 22, a conductor layer 30 is formed that includes a predetermined wiring pattern, including a pattern arrangement portion 301 where wiring 33 is formed and a pattern non-arrangement portion 302, as shown in Figure 2I. At the same time, via conductors 35 are formed that penetrate the insulating layer 20 and connect the conductor layer 10 and the conductor layer 30. Both the conductor layer 30 and the via conductors 35 are formed as a two-layer structure consisting of a metal film layer 31 and a plating film layer 32.

[0037] As described above, the metal particles constituting the metal film layer 31 penetrate deep into the insulating layer 20 in the first region 21 of the insulating layer 20 below the pattern placement area 301. Because the metal film layer 31 adheres to the upper surface 21a of the first region 21 of the insulating layer 20 with a high degree of adhesion, there is no risk of the wiring 33 peeling off from the insulating layer 20. By adjusting the hardness of the insulating layer 20 formed below the pattern placement area 301, even when fine wiring 33 is included, a wiring substrate can be manufactured in which the wiring 33 and the insulating layer 20 adhere well and there is no risk of peeling. Furthermore, since the metal film layer 31 on the upper surface 22a of the region 22 which is the pattern non-placement area 302 can be easily removed, short circuits between adjacent wiring 33 and short circuits between wiring 33 and via conductors 35 can be suppressed.

[0038] The method for manufacturing the wiring board in the embodiment is not limited to the method described with reference to the drawings. For example, the first exposure step and the second exposure step may be performed in reverse order, with the first exposure step being performed after the second exposure step. That is, only the insulating resin layer 200 corresponding to the area of ​​the insulating layer 20 not covered by the land portions 351 of the wiring 33 and via conductors 35 may be exposed first, and then the entire surface of the insulating resin layer 200, excluding the area where the via conductors 35 are formed, may be additionally exposed. In this case as well, preferably, the exposure step may be performed by direct imaging exposure. Alternatively, the first exposure step may be a step in which the insulating resin layer 200 is exposed by irradiating the entire surface using a mask that covers only the area where the via conductors 35 are formed, and then, as the second exposure step, only the area of ​​the insulating resin layer 200 corresponding to the area of ​​the insulating layer 20 not covered by the land portions 351 of the wiring 33 and via conductors 35 may be additionally exposed by direct imaging exposure.

[0039] The methods for forming each conductor layer and insulating layer are also not limited to those described with reference to Figures 2A to 2I. The manufacturing method of the wiring board in the embodiment may include additional steps other than those described above, and some of the aforementioned steps may be omitted. [Explanation of Symbols]

[0040] 1 Wiring board 10 Conductor Layers 20 Insulating layer 200 Insulating resin layer 21 First area 21a Upper surface of the first region 22 Second area 22a Upper surface of the second region 30 Conductor Layers 31. Metal film layer (seed layer) 32 Plating film layer 33 Wiring 301 Pattern placement section 302 Pattern-less area 35 via conductors 351 Land Department 35a through hole 40 resistance layers

Claims

1. Forming a photosensitive resin layer, An insulating layer is formed by exposing the aforementioned photosensitive resin layer to light, A conductive layer including a patterned area and a non-patterned area is formed on the insulating layer. A method for manufacturing a wiring board, including, Forming the insulating layer includes exposing the photosensitive resin layer to light such that the degree of curing of the region of the photosensitive resin layer that overlaps with the pattern-less portion in a plan view is higher than the degree of curing of the region of the photosensitive resin layer that overlaps with the pattern-placed portion in a plan view.

2. A method for manufacturing a wiring board according to claim 1, Forming the conductor layer includes forming a seed layer on the insulating layer and removing the seed layer in the areas where the pattern is not placed.

3. A method for manufacturing a wiring board according to claim 2, Forming the insulating layer includes forming through holes by removing the unexposed region of the photosensitive resin layer. Forming the conductor layer includes forming the seed layer on the inner wall of the through hole and forming a via conductor by filling the through hole with a plating film layer.

4. A method for manufacturing a wiring board according to claim 1, The aforementioned photosensitivity is photosensitivity by direct imaging exposure.

5. A method for manufacturing a wiring board according to claim 1, The aforementioned photosensitive resin layer contains a negative-type photosensitive resin.

6. A method for manufacturing a wiring board according to claim 1, The Young's modulus of the insulating layer in the region overlapping with the patterned portion in a plan view is 5% or more and 95% or less of the Young's modulus of the insulating layer in the region overlapping with the non-patterned portion in a plan view.

7. A method for manufacturing a wiring board according to claim 2, The aforementioned seed layer is formed by sputtering.

8. A method for manufacturing a wiring board according to claim 7, The sputtering described above is copper sputtering.

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