A substrate with interconnections in the core layer configured for skew matching.

Abstract

This invention provides a means for skew matching using interlayer connection vias in a multilayer wiring board. [Solution] A package comprising an integrated device and a substrate 202, wherein the integrated device is bonded to the substrate. The substrate includes a core layer 203, at least one first dielectric layer 240 bonded to a first surface of the core layer, and at least one second dielectric layer 260 bonded to a second surface of the core layer. The substrate includes a match structure 207 disposed within the core layer. The match structure includes at least one first match interconnect 251 extending vertically and horizontally within the match structure. The match structure also includes at least one second match interconnect 253 extending vertically within the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Description

Claim of Priority

[0001] Claim of Priority to Related Applications / Cross-References

[0001] This application claims the benefit and priority of U.S. Non-Provisional Application No. 17 / 148,257, filed on January 13, 2021, which is hereby incorporated by reference in its entirety for all applicable purposes as if fully set forth herein below.

Technical Field

[0002]

[0002] Various features relate to packages and substrates, and more particularly, to substrates including interconnects.

Background Art

[0003]

[0003] FIG. 1 shows a package 100 including a substrate 102, an integrated device 106, and an integrated device 108. The integrated device 106 is coupled to a surface of the substrate 102. The integrated device 108 is coupled to a surface of the substrate 102. The first substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. A plurality of solder interconnects 130 are coupled to the substrate 102. The interconnects in the substrate 102 may occupy a lot of space, and there is a current need to improve and optimize the design of the interconnects in the substrate 102.

Summary of the Invention

[0004]

[0004] Various features relate to packages and substrates, and more particularly, to substrates including interconnects.

[0005]

[0005] One example provides a substrate comprising a core layer, at least one first dielectric layer bonded to a first surface of the core layer, and at least one second dielectric layer bonded to a second surface of the core layer. The substrate includes a match structure disposed in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the core layer. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured to provide skew matching.

[0006]

[0006] Another example provides a package comprising a substrate and an integrated device bonded to the substrate. The substrate comprises a core layer, at least one first dielectric layer bonded to a first face of the core layer, and at least one second dielectric layer bonded to a second face of the core layer. The substrate includes a match structure disposed within the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally within the match structure. The match structure also includes at least one second match interconnect extending vertically within the match structure. The at least one first match interconnect and the at least one second match interconnect are configured to provide skew matching.

[0007]

[0007] Another example provides an apparatus comprising a core layer, means for skew matching, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The means for skew matching is located in the core layer. The means for skew matching includes at least one first match interconnect extending vertically and horizontally in the means for skew matching, and at least one second match interconnect extending vertically in the means for skew matching. The at least one first match interconnect and the at least one second match interconnect are configured to provide time signal matching between a first signal and a second signal.

[0008]

[0008] Another example provides a method for manufacturing a substrate. The method provides at least one cavity in a core layer. The method places a match structure in at least one cavity in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure, and at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured to provide skew matching. The method forms at least one first dielectric layer on a first surface of the core layer. The method forms at least one second dielectric layer on a second surface of the core layer.

[0009]

[0009] Various features, properties, and advantages may become apparent from the detailed description below when read together with the drawings, which are identified by similar reference numerals throughout. [Brief explanation of the drawing]

[0010] [Figure 1]

[0010] A diagram showing a package including a substrate and an integrated device. [Figure 2]

[0011] Exemplary cross-sectional view of a substrate including interconnects in a core layer configured for skew matching. [Figure 3]

[0012] A diagram of interconnection pairs configured for skew matching. [Figure 4]

[0013] A diagram illustrating how pairs of interconnections can be configured for skew matching. [Figure 5]

[0014] Exemplary cross-sectional view of a substrate including interconnects in a core layer configured for skew matching. [Figure 6]

[0015] Cross-sectional view of an exemplary package including a substrate with interconnects in a core layer configured for skew matching. [Figure 7A]

[0016] A diagram illustrating an exemplary sequence for fabricating a substrate containing interconnects within a core layer configured for skew matching. [Figure 7B] A diagram illustrating an exemplary sequence for fabricating a substrate containing interconnects within a core layer configured for skew matching. [Figure 7C] A diagram illustrating an exemplary sequence for fabricating a substrate containing interconnects within a core layer configured for skew matching. [Figure 7D] A diagram illustrating an exemplary sequence for fabricating a substrate containing interconnects within a core layer configured for skew matching. [Figure 8]

[0017] An illustrative flowchart shows a method for fabricating a substrate that includes interconnects in a core layer configured for skew matching. [Figure 9A]

[0018] A diagram illustrating an exemplary sequence for fabricating a match structure with pairs of interconnects configured for skew matching. [Figure 9B] A diagram illustrating an exemplary sequence for fabricating a match structure with pairs of interconnects configured for skew matching. [Figure 9C]A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 9D] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10A]

[0019] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10B] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10C] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10D] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10E] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 10F] A diagram showing an exemplary sequence for fabricating a match structure comprising a pair of interconnected pairs configured for skew matching. [Figure 11]

[0020] A diagram showing various electronic devices that can integrate the dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits, and / or PCBs described herein.

Best Mode for Carrying Out the Invention

[0011]

[0021] The following description provides specific details to give a complete understanding of the various aspects of this disclosure. However, it will be understood by those skilled in the art that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring the aspects of this disclosure.

[0012]

[0022] This disclosure describes a package comprising a substrate and at least one integrated device coupled to the substrate. The substrate comprises a core layer, at least one first dielectric layer coupled to a first face of the core layer, and at least one second dielectric layer coupled to a second face of the core layer. The substrate comprises a match structure disposed within the core layer. The match structure comprises at least one first match interconnect extending vertically and horizontally within the match structure. The match structure also comprises at least one second match interconnect extending vertically within the match structure. The at least one first match interconnect and the at least one second match interconnect are configured to provide skew matching (e.g., skew matching for differential signal pairs). The match structure may comprise at least one dielectric layer. The match structure may comprise a structural core layer and at least one dielectric layer. The at least one first match interconnect may be configured to provide an electrical path for a first signal (e.g., a positive signal). At least one second match interconnect may be configured to provide an electrical path for a second signal (for example, a negative signal). The positive and negative signals may constitute a differential signal pair. The second signal may be the inverse of the first signal, and vice versa. Exemplary package with matched structure in the core layer of the substrate

[0023] Figure 2 shows a substrate 202 including at least one match structure having interconnects configured to provide skew matching and / or signal-time matching. The substrate 202 may be mounted in a package with at least one integrated device. The substrate 202 includes a core layer 203, at least one first dielectric layer 240, a first plurality of interconnects 241, at least one second dielectric layer 260, a second plurality of interconnects 261, a match structure 205, a match structure 207, a first core interconnect 231, and a second core interconnect 233.

[0013]

[0024] Match structure 205 is located in core layer 203. Match structure 207 is located in core layer 203. A first core interconnect 231 and a second core interconnect 233 are located in core layer 203 and extend through core layer 203. The first core interconnect 231 and the second core interconnect 233 may be part of a pair of electrical paths configured for a differential signal pair. At least one first dielectric layer 240 and a plurality of first interconnects 241 are coupled to a first surface (e.g., top surface) of core layer 203. At least one second dielectric layer 260 and a plurality of second interconnects 261 are coupled to a second surface (e.g., bottom surface) of core layer 203.

[0014]

[0025] The first multiple interconnections 241 are coupled (for example, electrically coupled) to the match structure 205, the match structure 207, the first core interconnection 231, and / or the second core interconnection 233. The second multiple interconnections 261 are coupled (for example, electrically coupled) to the match structure 205, the match structure 207, the first core interconnection 231, and / or the second core interconnection 233.

[0015]

[0026] Match structures 205 and / or 207 can assist in skew matching and / or signal-time matching in differential signaling. Match structures 205 and / or 207 can be means for skew matching. The use of differential signaling (e.g., a pair of differential signals) offers several advantages. For example, differential signaling is more resistant to electromagnetic interference (EMI) and / or crosstalk. Differential signaling also reduces outgoing EMI and crosstalk. Differential signaling can operate at lower voltages than single-ended signals. However, in differential signaling, the distance each signal travels must match (or be as close to) each other as possible. Thus, if the first signal travels a distance X, the second signal, which is part of a pair of differential signals, should ideally travel a distance X or as close to X as possible. For example, if the electrical path between two terminals for a first signal has an effective distance / length X, then another electrical path between two other terminals for a second signal has an effective distance / length X (or as close to X as possible) (for example, the difference between the two effective distances / lengths is within 2% of the effective distance / length X). In a differential signaling pair, at least one matching structure (e.g., 205, 207) may be used to ensure that the first signal travels the same distance as the second signal, and vice versa. Different implementations may define terminals differently. Terminals may be part of an integrated device. The electrical path between two terminals may be an electrical path between two integrated devices. In a differential signaling pair, each signal may be coupled to a different pair of terminals for the same pair of integrated devices.For example, (i) a first signal between a first integrated device and a second integrated device may travel through a first electrical path configured to couple (e.g., electrically couple) between a first terminal of the first integrated device and a first terminal of the second integrated device, and (ii) a second signal between the first integrated device and a second integrated device may travel through a second electrical path configured to couple (e.g., electrically couple) between a second terminal of the first integrated device and a second terminal of the second integrated device, where the first signal and the second signal are part of a differential signal pair.

[0016]

[0027] The match structure 205 includes at least one dielectric layer 250 (e.g., a structural dielectric layer), a first plurality of match interconnects 251, and a second plurality of match interconnects 253. The first plurality of match interconnects 251 extend through at least one dielectric layer 250 of the match structure 205 (e.g., extending vertically). The second plurality of match interconnects 253 extend through at least one dielectric layer 250 of the match structure 205 (e.g., extending vertically and / or horizontally).

[0017]

[0028] The first multiple match interconnect 251 and the second multiple match interconnect 253 are a differential pair of interconnects. The first multiple match interconnect 251 is configured to provide an electrical path for a first signal. The second multiple match interconnect 253 is configured to provide an electrical path for a second signal. The first and second signals may be high-speed signals. The first and second signals may be a differential signal pair. The first signal may be a positive signal and the second signal may be a negative signal. The second signal may be a positive signal and the first signal may be a negative signal. The second signal may be the opposite of the first signal, and vice versa. The second signal may be the inverted signal of the first signal, and vice versa.

[0018]

[0029] The first multiple match interconnect 251 has a first electrical path length (e.g., a first effective electrical path length). The second multiple match interconnect 253 has a second electrical path length (e.g., a second effective electrical path length). The first multiple match interconnect 251 has an electrical path length smaller than that of the second multiple match interconnect 253. The first multiple match interconnect 251 is part of a first electrical path between two first terminals (e.g., a first terminal of the first integrated device and a first terminal of the second integrated device). The second multiple match interconnect 253 is part of a second electrical path between two second terminals (e.g., a second terminal of the first integrated device and a second terminal of the second integrated device). The second multiple match interconnect 253 may have a serpentine design with various turns in the match structure 205. The match structure 205 helps ensure that the length of the first electrical path between two first terminals is the same as or approximately the length of the second electrical path between two second terminals. The two first terminals may be a pair of terminals between two integrated devices. The two second terminals may be a pair of terminals between the same two integrated devices. The two integrated devices may be coupled to substrate 202, other substrates and / or boards (e.g., printed circuit boards).

[0019]

[0030] The match structure 207 includes a structural core layer 270, a dielectric layer 272 (e.g., a structural dielectric layer), a dielectric layer 274 (e.g., a structural dielectric layer), a dielectric layer 276 (e.g., a structural dielectric layer), a dielectric layer 278 (e.g., a structural dielectric layer), a first plurality of match interconnects 271, and a second plurality of match interconnects 273. The first plurality of match interconnects 271 extend through the dielectric layers of the match structure 207 (e.g., extending vertically). The second plurality of match interconnects 273 extend through the dielectric layers of the match structure 207 (e.g., extending vertically and / or horizontally).

[0020]

[0031] The first multiple match interconnect 271 and the second multiple match interconnect 273 are a differential pair of interconnects. The first multiple match interconnect 271 is configured to provide an electrical path for a third signal. The second multiple match interconnect 273 is configured to provide an electrical path for a fourth signal. The third and fourth signals may be high-speed signals. The third and fourth signals may be a differential signal pair. The third signal may be a positive signal and the fourth signal may be a negative signal. The fourth signal may be a positive signal and the third signal may be a negative signal. The fourth signal may be the opposite of the third signal, and vice versa. The fourth signal may be the inverted signal of the third signal, and vice versa.

[0021]

[0032] The first multiple match interconnect 271 has a third electrical path length (e.g., a third effective electrical path length). The second multiple match interconnect 273 has a fourth electrical path length (e.g., a fourth effective electrical path length). The third multiple match interconnect 271 has an electrical path length smaller than that of the second multiple match interconnect 273. The first multiple match interconnect 271 is part of a third electrical path between two first terminals. The second multiple match interconnect 273 is part of a fourth electrical path between two second terminals. The second multiple match interconnect 273 may have a meandering design with various turns in the match structure 207. The match structure 207 helps ensure that the third electrical path length between two first terminals is the same as or approximately the same as the fourth electrical path length between two second terminals. The two first terminals may be a pair of terminals between two integrated devices. The two second terminals could be a pair of terminals between the same two integrated devices. The two integrated devices may be coupled to substrate 202, other substrates and / or boards (e.g., printed circuit boards).

[0022]

[0033] Figure 3 shows an exemplary pair of interconnections that are part of a differential signaling pair. Figure 3 shows a first plurality interconnection 301 and a second plurality interconnection 303. The first plurality interconnection 301 may be a representation of the first plurality match interconnection 251 and / or the first plurality match interconnection 271. The first plurality interconnection 303 may be a representation of the second plurality match interconnection 253 and / or the second plurality match interconnection 273.

[0023]

[0034] The first plurality of interconnects 301 includes interconnect 310 (e.g., a pad), interconnect 311 (e.g., a via), interconnect 312 (e.g., a pad), interconnect 313 (e.g., a via), interconnect 314 (e.g., a pad), interconnect 315 (e.g., a via), and interconnect 316 (e.g., a pad). The plurality of interconnects 301 extend vertically. In some implementations, the first plurality of interconnects 301 are part of a first electrical path between two first terminals (e.g., a first terminal of a first integrated device and a first terminal of a second integrated device).

[0024]

[0035] The second set of interconnects 303 includes interconnect 330 (e.g., a pad), interconnect 331 (e.g., a via), interconnect 332 (e.g., a trace, a pad), interconnect 333 (e.g., a via), interconnect 334 (e.g., a trace, a pad), interconnect 335 (e.g., a via), and interconnect 336 (e.g., a pad). The set of interconnects 303 extends vertically and horizontally. In some implementations, the second set of interconnects 303 is part of a second electrical path between two second terminals (e.g., a second terminal of a first integrated device and a second terminal of a second integrated device).

[0025]

[0036] Figure 4 illustrates how implementing a matched structure helps improve the package and / or substrate. Figure 4 shows a first design 400 of substrate 402 and a second design 401 of substrate 402. Design 400 of substrate 402 includes at least one interconnect 410, at least one interconnect 412, multiple interconnects 414, at least one interconnect 420, at least one interconnect 422, multiple interconnects 424, and a solder resist layer 430. At least one interconnect 410 and at least one interconnect 412 may include pads on various metal layers. At least one interconnect 410, at least one interconnect 412, and multiple interconnects 414 are part of a first electrical path for a first signal from a differential signal pair. At least one interconnect 420 and at least one interconnect 422 may include pads on various metal layers. At least one interconnection 420, at least one interconnection 422, and multiple interconnections 424 are part of a second electrical path for a second signal from a pair of differential signals. The multiple interconnections 424 are formed on the dielectric layer of the substrate 402 to ensure that the total length (e.g., effective length) of the second electrical path matches the total length (e.g., effective length) of the first electrical path.

[0026]

[0037] Design 401 of the substrate 402 includes at least one interconnection 410, at least one interconnection 412, multiple interconnections 414, at least one interconnection 420, at least one interconnection 422, multiple interconnections 426, and a solder resist layer 430. Design 401 may be similar to design 400, except that the multiple interconnections 424 of design 400 are implemented as multiple interconnections 426. Multiple interconnections 426 may be implemented in the core layer of the substrate 402. Multiple interconnections 426 may be implemented as multiple interconnections 303, multiple match interconnections 253, and / or multiple match interconnections 273.

[0027]

[0038] At least one interconnection 420, at least one interconnection 422, and multiple interconnections 426 are part of a second electrical path for a second signal from a differential signal pair. The multiple interconnections 426 are formed in the core layer of the substrate 402 to ensure that the total length (e.g., effective length) of the second electrical path matches the total length (e.g., effective length) of the first electrical path. Design 401 creates space 450 in the substrate 402 that can be used for routing other interconnections. Figure 4 shows how the meandering design in the core layer can result in improved overall routing of interconnections on the substrate by creating additional space for any additional interconnections of the circuit.

[0028]

[0039] Different match structures may have different designs and / or shapes. Figure 5 shows a substrate 502 including at least one match structure having interconnects configured to provide skew matching and / or signal-time matching. The substrate 502 may be mounted in a package with at least one integrated device. The substrate 502 is similar to the substrate 202 described in Figure 2. The substrate 502 may include the same or similar components as the substrate 202. The substrate 502 includes a match structure different from the match structure described for the substrate 202.

[0029]

[0040] As shown in Figure 5, the substrate 502 includes match structures 505 and 507. Match structures 505 and / or 507 may be means for skew matching. Match structures 505 and 507 include interconnects having a different design from the interconnects of match structures 205 and / or 207. For example, match structures 205 and / or 207 include interconnects having a different number of turns. Match structures 505 and 507 are located in the core layer 203. Match structures 505 and / or 507 are coupled to a first plurality of interconnects 241 and / or a second plurality of interconnects 261.

[0030]

[0041] The match structure 505 includes at least one dielectric layer 250, a first plurality of match interconnects 551, and a second plurality of match interconnects 553. The first plurality of match interconnects 551 extend through at least one dielectric layer 250 of the match structure 505 (for example, extending vertically). The second plurality of match interconnects 553 extend through at least one dielectric layer 250 of the match structure 505 (for example, extending vertically and / or horizontally).

[0031]

[0042] The first multiple match interconnect 551 and the second multiple match interconnect 553 are a differential pair of interconnects. The first multiple match interconnect 551 is configured to provide an electrical path for a first signal. The second multiple match interconnect 553 is configured to provide an electrical path for a second signal. The first and second signals may be high-speed signals. The first and second signals may be a differential signal pair. The first signal may be a positive signal and the second signal may be a negative signal. The second signal may be a positive signal and the first signal may be a negative signal. The second signal may be the opposite of the first signal, and vice versa. The second signal may be the inverted signal of the first signal, and vice versa.

[0032]

[0043] The first multiple match interconnect 551 has a first electrical path length. The second multiple match interconnect 553 has a second electrical path length. The first multiple match interconnect 551 has an electrical path length smaller than that of the second multiple match interconnect 553. The first multiple match interconnect 551 is part of a first electrical path between two first terminals. The second multiple match interconnect 553 is part of a second electrical path between two second terminals. The second multiple match interconnect 553 may have a meandering design with various turns. The match structure 505 helps ensure that the first electrical path length between two first terminals is the same as or approximately the same as the second electrical path length between two second terminals. The two first terminals may be a pair of terminals between two integrated devices. The two second terminals may be a pair of terminals between the same two integrated devices. The two integrated devices may be coupled to substrate 502, other substrates and / or boards (e.g., printed circuit boards).

[0033]

[0044] The match structure 507 includes a structural core layer 270, a dielectric layer 272, a dielectric layer 274, a dielectric layer 276, a dielectric layer 278, a dielectric layer 572 (e.g., a structural dielectric layer), a dielectric layer 574 (e.g., a structural dielectric layer), a first plurality of match interconnects 571, and a second plurality of match interconnects 573. The first plurality of match interconnects 571 extend through at least one dielectric layer of the match structure 507 (e.g., extending vertically). The second plurality of match interconnects 573 extend through the dielectric layers of the match structure 507 (e.g., extending vertically and / or horizontally).

[0034]

[0045] The first multiple match interconnect 571 and the second multiple match interconnect 573 are a differential pair of interconnects. The first multiple match interconnect 571 is configured to provide an electrical path for a third signal. The second multiple match interconnect 573 is configured to provide an electrical path for a fourth signal. The third and fourth signals may be high-speed signals. The third and fourth signals may be a differential signal pair. The third signal may be a positive signal and the fourth signal may be a negative signal. The fourth signal may be a positive signal and the third signal may be a negative signal. The fourth signal may be the opposite of the third signal, and vice versa. The fourth signal may be the inverted signal of the third signal, and vice versa.

[0035]

[0046] The first multiple match interconnect 571 has a third electrical path length. The second multiple match interconnect 573 has a fourth electrical path length. The third multiple match interconnect 571 has an electrical path length smaller than that of the second multiple match interconnect 573. The first multiple match interconnect 571 is part of a third electrical path between two first terminals. The second multiple match interconnect 573 is part of a fourth electrical path between two second terminals. The second multiple match interconnect 573 may have a meandering design with various turns. The match structure 507 helps ensure that the third electrical path length between two first terminals is the same as or approximately the same as the fourth electrical path length between two second terminals. The two first terminals may be a pair of terminals between two integrated devices. The two second terminals may be a pair of terminals between the same two integrated devices. The two integrated devices may be coupled to substrate 502, other substrates and / or boards (e.g., printed circuit boards).

[0036]

[0047] Figure 6 shows a package 600 including a substrate 202, an integrated device 304, and an integrated device 308. Integrated device 304 is coupled to the substrate 202 through a plurality of solder interconnects 340. Integrated device 308 is coupled to the substrate 202 through a plurality of solder interconnects 380.

[0037]

[0048] In some implementations, the integrated device 304 may be configured to be electrically coupled to another integrated device through a match structure 205 as a differential signaling pair. For example, the integrated device 304 may be configured to be electrically coupled to a plurality of solder interconnects 340, a first plurality of interconnects 241, the interconnects of the match structure 205, and a second plurality of interconnects 261. The match structure 205 may be configured to provide skew matching and / or signal-time matching to pairs of signals going to and / or from the integrated device 304. For example, the match structure 205 helps ensure that a first signal going to the integrated device 304 arrives simultaneously with a second signal going to the integrated device 304, where the first and second signals are a pair of differential signals. In another example, the match structure 205 helps ensure that a first signal traveling from integrated device 304 arrives at another integrated device simultaneously with a second signal traveling from integrated device 304, where the first and second signals are a pair of differential signals. The other integrated device configured to receive and / or transmit the first and second signals to / from integrated device 304 through the match structure 205 may be coupled to substrate 302, another substrate, or a board (e.g., a printed circuit board).

[0038]

[0049] In some implementations, the integrated device 308 may be configured to be electrically coupled to another integrated device through a match structure 207 as a differential signaling pair. For example, the integrated device 308 may be configured to be electrically coupled to a plurality of solder interconnects 380, a second plurality of interconnects 241, the interconnects of the match structure 207, and a second plurality of interconnects 261. The match structure 207 may be configured to provide skew matching and / or signal-time matching to pairs of signals going to and / or from the integrated device 308. For example, the match structure 207 helps ensure that a first signal going to the integrated device 308 arrives simultaneously with a second signal going to the integrated device 308, where the first and second signals are a pair of differential signals. In another example, the match structure 207 helps ensure that a first signal traveling from integrated device 308 arrives at another integrated device simultaneously with a second signal traveling from integrated device 308, where the first and second signals are a pair of differential signals. The other integrated device configured to receive and / or transmit the first and second signals to / from integrated device 308 through the match structure 207 may be coupled to substrate 302, another substrate, or a board (e.g., a printed circuit board).

[0039]

[0050] It should be noted that any of the substrates described in this disclosure (e.g., 502) can be mounted together with a package. It should also be noted that any of the match structures (e.g., 205, 207, 505, 507) can be mounted on the substrate. Furthermore, it should be noted that the substrate may contain any number of match structures and / or different combinations of different match structures. Having described various substrates with various match structures, the process for manufacturing the substrate will now be described below. Exemplary sequence for fabricating a substrate containing a match structure

[0051] In some implementations, fabricating a substrate containing a match structure involves several processes. Figures 7A–7D show exemplary sequences for providing or fabricating a substrate containing at least one match structure. In some implementations, the sequences in Figures 7A–7D may be used to provide or fabricate the substrate 202 of Figure 2. However, the processes in Figures 7A–7D may be used to fabricate any of the substrates described herein.

[0040]

[0052] It should be noted that the sequences in Figures 7A to 7D may be combinations of one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of this disclosure.

[0041]

[0053] Stage 1 shows the state after the core layer 203 has been prepared, as shown in Figure 7A. The core layer 203 may include a metal layer (for example, foil).

[0042]

[0054] Stage 2 shows the state after multiple cavities 701 have been formed in the core layer 203. The multiple cavities 701 may extend through the core layer 203. A laser process (e.g., laser ablation) may be used to form the multiple cavities 701.

[0043]

[0055] Stage 3 shows the state after the core layer 203 has been bonded to the tape 710, or vice versa. The tape 710 may include an adhesive tape.

[0044]

[0056] Stage 4 shows the state after at least one match structure 205 is placed in cavity 701 and at least one match structure 207 is placed in another cavity 701. Different implementations may place different match structures (e.g., 505, 507) in the cavity 701. Different implementations may place different numbers of match structures and / or different combinations of match structures in the cavity. A pick-and-place process may be used to place the match structures in the cavity 701 of the core layer 203. Examples of how the match structures are fabricated are illustrated and explained in Figures 9A–9D and / or Figures 10A–10F.

[0045]

[0057] Stage 5 shows the state after the dielectric layer 720 has been formed on the first surface (e.g., the top surface) of the core layer 203, the match structure 205, and the match structure 207, as shown in Figure 7B. A deposition process may be used to form the dielectric layer 720.

[0046]

[0058] Stage 6 shows the state after the tape 710 has been separated from the core layer 203 and the dielectric layer 730 has been formed on the second surface (e.g., the bottom surface) of the core layer 203, and on the match structure 205 and the match structure 207. A deposition process may be used to form the dielectric layer 730.

[0047]

[0059] Stage 7 shows the state after multiple cavities 721 have been formed through the dielectric layer 720, multiple cavities 723 have been formed through the core layer 203, and multiple cavities 733 have been formed through the dielectric layer 730. A laser process (e.g., laser ablation) may be used to form the cavities.

[0048]

[0060] Stage 8 shows the state after multiple interconnections 722, multiple interconnections 732, and multiple interconnections 724 have been formed. Multiple interconnections 724 are formed in the cavity 723. A plating process or a pasteuring process may be used to form the interconnections 722, 724, and / or 732.

[0049]

[0061] Stage 9 shows the state after dielectric layer 740 and dielectric layer 750 have been formed, as shown in Figure 7C. A deposition process may be used to form dielectric layer 740. Dielectric layer 740 may include dielectric layer 720. A deposition process may be used to form dielectric layer 750. Dielectric layer 750 may include dielectric layer 730.

[0050]

[0062] Step 10 shows the state after multiple cavities 741 have been formed in the dielectric layer 740 and multiple cavities 751 have been formed in the dielectric layer 750. Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), and / or etching processes may be used to form the cavities 741 and 751.

[0051]

[0063] Step 11 shows the state after (i) a plurality of interconnections 742 have been formed in and / or on the dielectric layer 740, and (ii) a plurality of interconnections 752 have been formed in and / or on the dielectric layer 750. Patterning and plating processes may be used to form the interconnections 742 and 752. Some of the interconnections 742 may be formed in the cavity 741. Some of the interconnections 752 may be formed in the cavity 751. The plurality of interconnections 742 and 752 may include vias, pads, and / or traces.

[0052]

[0064] Step 12 shows the state after dielectric layer 760 and dielectric layer 770 have been formed, as shown in Figure 7D. Dielectric layer 760 is formed on dielectric layer 740. Dielectric layer 770 is formed on dielectric layer 750. A deposition process may be used to form dielectric layer 760. A deposition process may be used to form dielectric layer 770.

[0053]

[0065] Step 13 shows the state after multiple cavities 761 have been formed in the dielectric layer 760 and multiple cavities 771 have been formed in the dielectric layer 770. Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), and / or etching processes may be used to form the cavities 761 and 771.

[0054]

[0066] Step 14 shows the state after (i) a plurality of interconnections 762 have been formed in and / or on the dielectric layer 760, and (ii) a plurality of interconnections 772 have been formed in and / or on the dielectric layer 770. Patterning and plating processes may be used to form the interconnections 762 and 772. Some of the interconnections 762 may be formed in the cavity 761. Some of the interconnections 772 may be formed in the cavity 771. The interconnections 762 and 772 may include vias, pads, and / or traces.

[0055]

[0067] Step 14 may represent a substrate 202 including match structures 205 and 207. Dielectric layers 740 and 760 may be represented by at least one first dielectric layer 240. Multiple interconnections 742 and 762 may be represented by the first multiple interconnections 241. Dielectric layers 750 and 770 may be represented by at least one second dielectric layer 260. Multiple interconnections 752 and 772 may be represented by the second multiple interconnections 261. Exemplary flowchart of a method for fabricating a substrate containing a matched structure.

[0068] In some implementations, fabricating a substrate containing at least one matched structure involves several processes. Figure 8 shows an illustrative flowchart of Method 800 for providing or fabricating a substrate containing at least one matched structure. In some implementations, Method 800 of Figure 8 may be used to provide or fabricate the substrate 202 of Figure 2. However, Method 800 may also be used to fabricate any substrate described herein.

[0056]

[0069] Note that the sequence in Figure 8 may be a combination of one or more processes to simplify and / or clarify the method for providing or fabricating the substrate. In some implementation configurations, the order of the processes may be changed or modified.

[0057]

[0070] The method provides a core layer (e.g., 203) (in 805). The core layer may include at least one metal layer. The core layer may be a core substrate. Step 1 in Figure 7A illustrates and describes an example of providing a core layer.

[0058]

[0071] The method involves forming multiple cavities 701 in the core layer 203 (at 810). The multiple cavities 701 may extend through the core layer 203. A laser process may be used to form the multiple cavities 701. Step 2 in Figure 7A illustrates and describes an example of forming cavities in the core layer.

[0059]

[0072] The method involves bonding the core layer 203 to the tape 710 (in 815). Step 3 in Figure 7A illustrates and describes an example of bonding the core layer to the tape. The method also involves placing at least one match structure (e.g., 205, 207, 505, 507) in the cavity (e.g., 701) of the core layer 203 (in 815). A pick-and-place process may be used to place at least one match structure. Step 4 in Figure 7A illustrates and describes an example of placing the match structure in the cavity of the core layer.

[0060]

[0073] The method involves forming dielectric layers on a core layer and a match structure (in 820). A deposition process may be used to form the dielectric layers (e.g., 720, 730). Dielectric layers may be formed on a first surface of the core layer 203 and on a first surface of at least one match structure. Another dielectric layer may be formed on a second surface of the core layer 203 and on a second surface of at least one match structure. In some packaging configurations, a tape (e.g., 710) may be separated from the core layer 203 before the dielectric layers are formed on the surface of the core layer. Steps 5-6 in Figure 7B illustrate and describe an example of dielectric layer formation and tape separation.

[0061]

[0074] The method involves forming cavities in the core layer (e.g., 203) and dielectric layers (e.g., 720, 730) (in 825). Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), and / or etching processes may be used to form the cavities (e.g., 721, 723, 731). Step 7 in Figure 7B illustrates and describes an example of forming a cavity.

[0062]

[0075] The method involves forming interconnections in the core layer (e.g., 203) and dielectric layers (e.g., 720, 730) (in 830). Patterning and plating processes may be used to form the interconnections (e.g., 722, 724, 732). Step 8 in Figure 7B illustrates and describes an example of forming interconnections.

[0063]

[0076] The method involves forming additional dielectric layers (e.g., 740, 760, 750, 770) and interconnects (e.g., 742, 752, 762, 772) on top of the dielectric layer (e.g., 720, 730) (in 835). Forming the additional dielectric layers and interconnects may include a plating process for depositing the dielectric layers, forming cavities in the dielectric layers, and forming the interconnects. Steps 9–14 in Figures 7C–7D illustrate and illustrate the formation of the additional dielectric layers and interconnects. Exemplary sequence for creating match structures

[0077] In some implementations, fabricating a match structure involves several processes. Figures 9A–9D show exemplary sequences for providing or fabricating a match structure. In some implementations, the sequences in Figures 9A–9D may be used to provide or fabricate the match structure 207 of Figure 2. However, the processes in Figures 9A–9D may be used to fabricate any of the match structures described in this disclosure.

[0064]

[0078] It should be noted that the sequences in Figures 9A to 9D may be combinations of one or more steps to simplify and / or clarify the sequences for providing or creating a match structure. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of this disclosure.

[0065]

[0079] Stage 1 shows the state after the core layer 270 has been prepared, as shown in Figure 9A. The core layer 270 may include metal layers (e.g., 910, 920).

[0066]

[0080] Stage 2 shows the state after multiple cavities 901 have been formed through the metal layer 910, core layer 270, and metal layer 920. A laser process (e.g., laser ablation) may be used to form the cavities 901.

[0067]

[0081] Stage 3 shows the state after the first dry film 930 has been formed on the first surface of the core layer 270 and / or the metal layer 910. Stage 3 also shows the state after the second dry film 940 has been formed on the second surface of the core layer 270 and / or the metal layer 920. A deposition process may be used to form the dry films (e.g., 930, 940).

[0068]

[0082] Stage 4 shows the state after multiple cavities 901 have been formed through the dry film 930, the metal layer 910, the core layer 270, the metal layer 920, and the dry film 940. Stage 4 also shows the state after multiple cavities 931 have been formed through the dry film 930 and multiple cavities 941 have been formed through the dry film 940. A laser process (e.g., laser ablation) may be used to form the cavities. Forming the cavities may include dry film exposure and development.

[0069]

[0083] Stage 5 shows the state after multiple interconnects 912 have been formed in and on the core layer 270, as shown in Figure 9B. A plating process or a pasteuring process may be used to form the interconnects 912. Stage 5 shows the state after the dry films (e.g., 930, 940) have been removed.

[0070]

[0084] Step 6 shows the state after dielectric layer 272 and dielectric layer 274 have been formed. A deposition process may be used to form dielectric layers 272 and 274. Step 6 also shows metal layer 972 formed on dielectric layer 272 and metal layer 974 formed on dielectric layer 274. Metal layers 972 and 974 may include foil.

[0071]

[0085] Stage 7 shows the state after multiple cavities 973 have been formed through the metal layer 972 and the dielectric layer 272. Stage 7 also shows multiple cavities 975 formed through the metal layer 974 and the dielectric layer 274. Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), and / or etching processes may be used to form cavities 973 and 975.

[0072]

[0086] Step 8 shows the state after the first dry film 950 has been formed on the dielectric layer 272 and the metal layer 972, and the second dry film 960 has been formed on the dielectric layer 274 and the metal layer 974, as shown in Figure 9C. A deposition process may be used to form the dry films (e.g., 950, 960).

[0073]

[0087] Stage 9 shows the state after multiple cavities 951 have been formed through the dry film 950 and multiple cavities 961 have been formed through the dry film 960. A laser process (e.g., laser ablation) may be used to form the cavities. Forming the cavities may include dry film exposure and development.

[0074]

[0088] Step 10 shows the state after multiple interconnects 952 have been formed in and on the dielectric layer 272 and multiple interconnects 962 have been formed in and on the dielectric layer 274, as shown in Figure 9D. A plating process or a pasteuring process may be used to form the interconnects 952 and 962. Step 10 shows the state after the dry films (e.g., 950, 960) have been removed.

[0075]

[0089] Step 11 shows the state after dielectric layer 276 has been formed on dielectric layer 272 and dielectric layer 278 has been formed on dielectric layer 274. A deposition process may be used to form dielectric layers 276 and 278. Dielectric layers 272, 274, 276 and / or 278 may include prepregs. Vias in dielectric layers 272 and / or 274 may have a thickness in the range of 25 micrometers to 80 micrometers. Vias in core layer 270 may have a thickness in the range of 40 micrometers to 250 micrometers.

[0076]

[0090] Stage 12 shows the post-sungulation state, which forms several match structures, such as match structure 207a and match structure 207b. Match structure 207a includes a first plurality of match interconnections 271 and a second plurality of match interconnections 273. Match structure 207b includes a first plurality of match interconnections 271 and a second plurality of match interconnections 273. Exemplary sequence for creating match structures

[0091] In some implementations, fabricating a match structure involves several processes. Figures 10A–10F show exemplary sequences for providing or fabricating a match structure. In some implementations, the sequences in Figures 10A–10F may be used to provide or fabricate the match structure 205 in Figure 2. However, the processes in Figures 10A–10F may be used to fabricate any of the match structures described in this disclosure.

[0077]

[0092] It should be noted that the sequences in Figures 10A to 10F may be combinations of one or more steps to simplify and / or clarify the sequence for providing or creating a match structure. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of this disclosure.

[0078]

[0093] Stage 1 shows the state after the dielectric layer 1000 has been prepared, as shown in Figure 10A. The dielectric layer 1000 may include metal layers (e.g., 1002, 1004). The dielectric layer 1000 may include a prepreg. The metal layers (e.g., 1002, 1004) may include copper foil.

[0079]

[0094] Stage 2 shows the state after multiple cavities 1003 have been formed through the metal layer 1002 and the dielectric layer 1000. A laser process (e.g., laser ablation) may be used to form the cavities 1003.

[0080]

[0095] Stage 3 shows the state after the dry film 1006 has been formed on the metal layer 1002 and the dielectric layer 1000. A deposition process may be used to form the dry film 1006. Stage 3 also shows the state after multiple cavities 1005 have been formed through the dry film 1006. Forming the cavities may involve dry film exposure and development.

[0081]

[0096] Stage 4 shows the state after multiple interconnects 1007 have been formed in and on the dielectric layer 1000. A plating process or a pasteuring process may be used to form the interconnects 1007. Stage 4 shows the state after the dry film 1006 has been removed.

[0082]

[0097] Stage 5 shows the state after the dielectric layer 1010 has been formed on top of the dielectric layer 1000 and the multiple interconnections 1007, as shown in Figure 10B. A deposition process may be used to form the dielectric layer 1010.

[0083]

[0098] Stage 6 shows the state after multiple cavities 1013 have been formed through the dielectric layer 1010. Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), or etching processes may be used to form the cavities 1013.

[0084]

[0099] Step 7 shows the state after the dry film 1016 has been formed on the dielectric layer 1010. A deposition process may be used to form the dry film 1016.

[0085]

[0100] Step 8 shows the state after multiple cavities 1015 have been formed through the dry film 1016, as shown in Figure 10C. Forming the cavities 1015 may include dry film exposure and development.

[0086]

[0101] Stage 9 shows the state after multiple interconnects 1017 have been formed in and on the dielectric layer 1010. A plating process or a pasteuring process may be used to form the interconnects 1017. Stage 9 shows the state after the dry film 1016 has been removed.

[0087]

[0102] Step 10 shows the state after the dielectric layer 1020 has been formed on the dielectric layer 1010 and the multiple interconnections 1017. A deposition process may be used to form the dielectric layer 1020.

[0088]

[0103] Step 11 shows the state after multiple cavities 1023 have been formed through the dielectric layer 1020, as shown in Figure 10D. Laser processes (e.g., laser ablation), lithography processes (e.g., exposure and development), or etching processes may be used to form the cavities 1023.

[0089]

[0104] Step 12 shows the state after the dry film 1026 has been formed on the dielectric layer 1020. A deposition process may be used to form the dry film 1026.

[0090]

[0105] Step 13 shows the state after multiple cavities 1025 have been formed through the dry film 1026. Forming the cavities may include dry film exposure and development.

[0091]

[0106] Step 14 shows the state after multiple interconnects 1027 have been formed in and on the dielectric layer 1020, as shown in Figure 10E. A plating process or a pasteuring process may be used to form the interconnects 1027. Step 14 shows the state after the dry film 1026 has been removed.

[0092]

[0107] Step 15 shows the state after multiple interconnects 1029 have been formed on the dielectric layer 1000. A plating process or a paste-forming process may be used to form the interconnects 1029. The interconnects 1029 may include a metal layer 1004. In some configurations, the metal layer 1004 may be removed before forming the interconnects 1029.

[0093]

[0108] Step 16 shows the state after dielectric layer 1030 has been formed on dielectric layer 1020 and dielectric layer 1040 has been formed on dielectric layer 1000, as shown in Figure 10F. A deposition process may be used to form dielectric layers 1030 and 1040.

[0094]

[0109] Step 17 describes a post-singulation state that forms several match structures, such as match structure 205a and match structure 205b. Match structure 205a includes at least one dielectric layer 250, a first plurality of match interconnects 251, and a second plurality of match interconnects 253. The at least one dielectric layer 250 may represent dielectric layers 1000, 1010, 1020, 1030, and / or 1040. Dielectric layers 1000, 1010, 1020, 1030, and / or 1040 may include prepregs. Vias in dielectric layers 1000, 1010, and / or 1020 may have a thickness in the range of 25 micrometers to 80 micrometers. The first plurality of match interconnects 251 may include first interconnects from plurality of interconnects 1007, 1017, 1027, and / or 1029. The second multiple match interconnection 253 may include second interconnections from multiple interconnections 1007, 1017, 1027 and / or 1029. Exemplary electronic device

[0110] Figure 11 shows various electronic devices that can be integrated with any of the above-mentioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or an automated vehicle 1110 may include a device 1100 as described herein. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108 and the vehicle 1110 shown in Figure 11 are illustrative examples only. Other electronic devices may also characterize device 1100, including, but not limited to, mobile devices, portable data units such as handheld personal communication system (PCS) units and personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof, including devices (e.g., electronic devices).

[0095]

[0111] One or more of the components, processes, features, and / or functions shown in Figures 2-6, 7A-7D, 8, 9A-9D, 10A-10F, and / or Figure 11 may be reconfigured into a single component, process, feature, or function and / or combined, or may be embodied in several components, processes, or functions. Additional components, components, processes, and / or functions may also be added without departing from this disclosure. Note that Figures 2-6, 7A-7D, 8, 9A-9D, 10A-10F, and / or Figure 11 in this disclosure and their corresponding descriptions are not limited to dies and / or ICs. In some implementations, Figures 2–6, 7A–7D, 8, 9A–9D, 10A–10F, and / or Figure 11 and their corresponding descriptions may be used to manufacture, create, supply, and / or generate devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, heat dissipation devices, and / or interposers.

[0096]

[0112] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to a constant scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various elements and / or components in the figures may be optional.

[0097]

[0113] The word “exemplary” is used herein to mean “acting as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C may still be considered coupled to each other, even if they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled to each other so that an electric current (e.g., signal, power, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything beyond the fourth) is optional. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulate” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are optional. A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is optionally defined.In another example, the first component may be located on (e.g., above) the first face of the second component, and the third component may be located on (e.g., below) the second face of the second component, with the second face facing the first face. It should be further noted that the term “over” as used in this application in the context of one component being located on another component may be used to mean a component that is on and / or in (e.g., on the surface of or embedded within) another component. Thus, for example, a first component over a second component may mean that (1) the first component is over the second component but is not in direct contact with the second component, (2) the first component is on (e.g., on its surface) the second component, and / or (3) the first component is in (e.g., embedded within) the second component. A first component located within a second component may be partially located within the second component or fully located within the second component. As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within 10 percent of 'value X'. For example, a value of about 1 or approximately 1 means a value within the range of 0.9 to 1.1.

[0098]

[0114] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnections. In some implementations, an interconnect may include electrically conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes may be used to form an interconnect.

[0099]

[0115] Furthermore, it should be noted that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations may occur in parallel or simultaneously. In addition, the order of operations may be rearranged. A process terminates when its operations are completed.

[0100]

[0116] Further examples are described below to facilitate understanding of the present invention.

[0101]

[0117] Embodiment 1: A substrate comprising a core layer, a match structure disposed within the core layer, at least one first dielectric layer bonded to a first surface of the core layer, and at least one second dielectric layer bonded to a second surface of the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally within the match structure, and at least one second match interconnect extending vertically within the match structure, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

[0102]

[0118] Embodiment 2: The substrate of Embodiment 1, wherein the match structure further comprises at least one structural dielectric layer.

[0103]

[0119] Embodiment 3: The substrate of Embodiment 1, wherein the match structure further comprises a structural core layer and at least one structural dielectric layer.

[0104]

[0120] Embodiment 4: A substrate according to embodiments 1 to 3, wherein at least one first match interconnect is configured to provide an electrical path for a positive signal, and at least one second match interconnect is configured to provide an electrical path for a negative signal.

[0105]

[0121] Embodiment 5: The circuit board according to Embodiment 4, wherein a positive signal and a negative signal are configured as a differential signal pair.

[0106]

[0122] Embodiment 6: A substrate according to Embodiments 1 to 5, wherein at least one first match interconnect and at least one second match interconnect are configured as a differential pair of match interconnects.

[0107]

[0123] Embodiment 7: A substrate according to Embodiments 1 to 6, wherein at least one second match interconnect includes at least one turn of interconnect.

[0108]

[0124] Embodiment 8: A substrate according to Embodiments 1 to 7, wherein the first electrical path distance between two first terminals, including at least one first match interconnection, is approximately the same as the second electrical path distance between two second terminals, including at least one second match interconnection.

[0109]

[0125] Embodiment 9: A substrate according to Embodiments 1 to 8, wherein at least one first match interconnection extends vertically and horizontally within the structural dielectric layer of the match structure, and at least one second match interconnection extends vertically within the structural dielectric layer of the match structure.

[0110]

[0126] Embodiment 10: A circuit board according to Embodiments 1 to 9, wherein the circuit board is incorporated into a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants (PDAs), fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

[0111]

[0127] Embodiment 11: A package comprising an integrated device and a substrate coupled to the integrated device. The substrate includes a core layer, a match structure disposed within the core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally within the match structure, and at least one second match interconnect extending vertically within the match structure, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

[0112]

[0128] Embodiment 12: The package of Embodiment 11, wherein the match structure further comprises at least one structural dielectric layer.

[0113]

[0129] Embodiment 13: The package of Embodiment 11, wherein the match structure further comprises a structural core layer and at least one structural dielectric layer.

[0114]

[0130] Embodiment 14: Packages of embodiments 11-13, wherein at least one first match interconnect is configured to provide an electrical path for a positive signal, and at least one second match interconnect is configured to provide an electrical path for a negative signal.

[0115]

[0131] Embodiment 15: The package of Embodiment 14, wherein a positive signal and a negative signal are configured as a differential signal pair.

[0116]

[0132] Embodiment 16: A package according to Embodiments 11-15, wherein at least one first match interconnect and at least one second match interconnect are configured as a differential pair of interconnects.

[0117]

[0133] Embodiment 17: A package according to embodiments 11-16, wherein the first electrical path distance between two first terminals, including at least one first match interconnect, is approximately the same as the second electrical path distance between two second terminals, including at least one second match interconnect.

[0118]

[0134] Embodiment 18: Apparatus comprising a core layer, means for skew matching disposed within the core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The means for skew matching includes at least one first match interconnect extending vertically and horizontally within the means for skew matching, and at least one second match interconnect extending vertically within the means for skew matching, wherein the at least one first match interconnect and the at least one second match interconnect are configured to provide time-signal matching between a first signal and a second signal.

[0119]

[0135] Embodiment 19: The apparatus of Embodiment 18, wherein at least one first match interconnect is configured to provide an electrical path for a positive signal, and at least one second match interconnect is configured to provide an electrical path for a negative signal.

[0120]

[0136] Embodiment 20: The apparatus of Embodiments 18-19, wherein the first electrical path distance between two first terminals including at least one first match interconnection is substantially the same as the second electrical path distance between two second terminals including at least one second match interconnection.

[0121]

[0137] Embodiment 21: Method for manufacturing a substrate. The method provides at least one cavity in a core layer. The method places a match structure in at least one cavity in the core layer. The match structure comprises at least one first match interconnect extending vertically and horizontally within the match structure, and at least one second match interconnect extending vertically within the match structure, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching. The method forms at least one first dielectric layer on a first surface of the core layer. The method forms at least one second dielectric layer on a second surface of the core layer.

[0122]

[0138] Embodiment 22: The method of Embodiment 21, wherein the match structure further comprises a structural core layer and at least one structural dielectric layer.

[0123]

[0139] Embodiment 23: The method of Embodiments 21-22, wherein at least one first match interconnect is configured to provide an electrical path for a positive signal, and at least one second match interconnect is configured to provide an electrical path for a negative signal.

[0124]

[0140] Embodiment 24: The method of Embodiments 21-23, wherein the first electrical path distance between two first terminals including at least one first match interconnection is approximately the same as the second electrical path distance between two second terminals including at least one second match interconnection.

[0125]

[0141] Various features of the Disclosure described herein may be implemented in different systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are illustrative and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the claims. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. It is a substrate, The core layer, The match structure disposed in the core layer, and the match structure At least one first match interconnection extending vertically and horizontally within the match structure, The match structure comprises at least one second match interconnect extending vertically, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching. At least one first dielectric layer bonded to the first surface of the core layer, At least one second dielectric layer bonded to the second surface of the core layer, A substrate comprising the above.

2. The substrate according to claim 1, wherein the match structure further comprises at least one structural dielectric layer.

3. The aforementioned match structure is, Structural core layer, At least one structural dielectric layer, The substrate according to claim 1, further comprising:

4. The at least one first match interconnect is configured to provide an electrical path for a positive signal. The at least one second match interconnect is configured to provide an electrical path for a negative signal. The substrate according to claim 1.

5. The substrate according to claim 4, wherein the positive signal and the negative signal are configured as a differential signal pair.

6. The substrate according to claim 1, wherein the at least one first match interconnect and the at least one second match interconnect are configured as a differential pair of match interconnects.

7. The substrate according to claim 1, wherein the at least one second match interconnection includes at least one turn of interconnection.

8. The substrate according to claim 1, wherein the first electrical path distance between two first terminals including the at least one first match interconnect is substantially the same as the second electrical path distance between two second terminals including the at least one second match interconnect.

9. The at least one first match interconnection extends vertically and horizontally within the structural dielectric layer of the match structure. The at least one second match interconnection extends vertically within the structural dielectric layer of the match structure. The substrate according to claim 1.

10. The circuit board according to claim 1, wherein the circuit board is incorporated into a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants (PDAs), fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

11. It is a package, Integrated devices and The integrated device comprises a substrate coupled to the said integrated device, and the substrate is The core layer, The match structure disposed in the core layer, and the match structure At least one first match interconnection extending vertically and horizontally within the match structure, The match structure comprises at least one second match interconnect extending vertically, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching. At least one first dielectric layer bonded to the first surface of the core layer, At least one second dielectric layer bonded to the second surface of the core layer, A package that includes the following features.

12. The package according to claim 11, wherein the match structure further comprises at least one structural dielectric layer.

13. The aforementioned match structure is, Structural core layer, At least one structural dielectric layer, The package according to claim 11, further comprising:

14. The at least one first match interconnect is configured to provide an electrical path for a positive signal. The at least one second match interconnect is configured to provide an electrical path for a negative signal. The package according to claim 11.

15. The package according to claim 14, wherein the positive signal and the negative signal are configured as a pair of differential signals.

16. The package according to claim 11, wherein the at least one first match interconnect and the at least one second match interconnect are configured as a differential pair of interconnects.

17. The package according to claim 11, wherein the first electrical path distance between two first terminals including the at least one first match interconnect is substantially the same as the second electrical path distance between two second terminals including the at least one second match interconnect.

18. It is a device, The core layer, The means for skew matching arranged in the core layer, and the means for skew matching, The means for skew matching includes at least one first match interconnection extending vertically and horizontally, and The means for skew matching comprises at least one second match interconnect extending vertically, wherein the at least one first match interconnect and the at least one second match interconnect are configured to provide time signal matching between a first signal and a second signal. At least one first dielectric layer bonded to the first surface of the core layer, At least one second dielectric layer bonded to the second surface of the core layer, A device equipped with the following features.

19. The at least one first match interconnect is configured to provide an electrical path for a positive signal. The at least one second match interconnect is configured to provide an electrical path for a negative signal. The apparatus according to claim 18.

20. The apparatus according to claim 18, wherein the first electrical path distance between the two first terminals including the at least one first match interconnection is substantially the same as the second electrical path distance between the two second terminals including the at least one second match interconnection.

21. A method for manufacturing a circuit board, To provide at least one cavity in the core layer, The matching structure is placed in the at least one cavity of the core layer, and the matching structure is At least one first match interconnection extending vertically and horizontally within the match structure, The match structure comprises at least one second match interconnect extending vertically, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching. Forming at least one first dielectric layer on the first surface of the core layer, Forming at least one second dielectric layer on the second surface of the core layer, A method that includes [a certain feature].

22. The aforementioned match structure is, Structural core layer, At least one structural dielectric layer, The method according to claim 21, further comprising:

23. The at least one first match interconnect is configured to provide an electrical path for a positive signal. The at least one second match interconnect is configured to provide an electrical path for a negative signal. The method according to claim 21.

24. The method according to claim 21, wherein the first electrical path distance between two first terminals including the at least one first match interconnection is substantially the same as the second electrical path distance between two second terminals including the at least one second match interconnection.

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