Imaging device

Abstract

This technology provides a suitable method for protecting pixel areas. [Solution] The imaging device 1A includes a semiconductor substrate 2b, a pixel region 71, and a pad region 75. The pixel region 71 includes a pixel array 11. The pad region 75 includes a pad 63. The pad 63 is located above the semiconductor substrate 2b. The upper end portion 75h of the pad region 75 is located above the upper end portion 71h of the pixel region 71.

Description

Technical Field

[0006]

[0001] This disclosure relates to an imaging device.

Background Art

[0002] The pixel region of an imaging device includes a photoelectric conversion section. There are various types of photoelectric conversion sections. In the imaging device of Patent Document 1, a photodiode is provided in a semiconductor substrate. In the imaging device of Patent Document 2, a photoelectric conversion layer is provided outside the semiconductor substrate.

Prior Art Documents

Patent Documents

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

Means for Solving the Problems

Effects of the Invention

Brief Description of the Drawings

[0007] [Figure 1] It is a circuit diagram of an imaging device according to Embodiment 1. [Figure 2] It is a circuit diagram of a pixel according to Embodiment 1. [Figure 3] It is a cross-sectional view of an imaging device according to Embodiment 1. [Figure 4] It is a plan view showing the positional relationship of a photoelectric conversion film, an electrode, and a pad. [Figure 5] It is a plan view showing a wafer device according to Embodiment 1. [Figure 6] It is a cross-sectional view showing a unit region according to Embodiment 1. [Figure 7] It is a cross-sectional view showing a unit region according to Reference Embodiment 1. [Figure 8] It is a cross-sectional view showing tape peeling according to Reference Embodiment 1. [Figure 9] It is a plan view showing a wafer device according to Embodiment 1. [Figure 10] It is a plan view showing a wafer device according to Embodiment 2. [Figure 11] It is a plan view showing a wafer device according to Embodiment 3. [Figure 12] It is a cross-sectional view of an imaging device according to Embodiment 4. [Figure 13] It is a cross-sectional view of an imaging device according to Embodiment 5. [Figure 14] It is a cross-sectional view of an imaging device according to Embodiment 6. [Figure 15] It is a cross-sectional view of an imaging device according to Embodiment 7. [Figure 16] It is a cross-sectional view of an imaging device according to Embodiment 8. [Figure 17] It is a cross-sectional view of an imaging device according to Embodiment 9. [Figure 18] A configuration example of a camera system according to Embodiment 10 is schematically shown.

Modes for Carrying Out the Invention

[0008] In the embodiments described below, terms such as "up", "down", and "height" are used solely to specify the relative positions of elements. These terms are not intended to limit the orientation of the imaging device during use. "Height" refers to the position in the vertical direction. The "upper end" is the portion located at the uppermost position. In the embodiments, unless otherwise inconsistent, "connection" and "electrically connected" may be read interchangeably. The metal may be a single metal or a metal compound. That the materials are the same means that the compositions are the same.

[0009] (Embodiment 1) FIG. 1 is a circuit diagram of an imaging device 1A according to Embodiment 1. The imaging device 1A includes a pixel region 71 and a peripheral region 72. In a plan view, the peripheral region 72 is located outside the pixel region 71. The pixel region 71 includes a pixel array 11. The pixel array 11 includes a plurality of pixels 10. The peripheral region 72 includes peripheral circuits. In Embodiment 1, "plan view" refers to the view when seen from the thickness direction of the semiconductor substrate 2b.

[0010] In the pixel array 11, the plurality of pixels 10 are arranged two-dimensionally in the row direction and the column direction. In FIG. 1, four pixels 10 arranged in two rows and two columns are typically shown. However, the actual pixel array 11 may include more pixels 10. In the pixel array 11, the plurality of pixels 10 may be arranged one-dimensionally. In this case, the imaging device 1A can be used as a line sensor.

[0011] A power supply voltage is supplied to each pixel 10 via a power supply wiring 22. In each pixel 10, a photoelectric conversion unit photoelectrically converts incident light to generate a signal, and a signal detection circuit detects the signal. A voltage is supplied to each pixel 10 via an accumulation control line 17.

[0012] The peripheral circuits of the imaging device 1A include a vertical scanning circuit 16, a plurality of load circuits 19, a plurality of column signal processing circuits 20, a plurality of inverting amplifiers 24, and a horizontal signal reading circuit 21. The load circuits 19, the column signal processing circuits

[0013] The vertical scanning circuit 16 selects multiple pixels 10 arranged in each row row by applying a voltage to the address signal line 30. By selecting multiple pixels 10 row by row, the signal voltage of the selected pixels 10 is read out and the signal charge is reset. The vertical scanning circuit 16 forms a feedback loop that negatively feeds back the output of the pixels 10 by applying a voltage to the feedback control line 28. Negative feedback can reduce kTC noise. The vertical scanning circuit 16 may apply a voltage to the reset signal line 26 when resetting the signal charge and when forming the feedback loop. The vertical scanning circuit 16 may supply voltage to multiple pixels 10 via the sensitivity adjustment line 32.

[0014] Each column of pixels 10 is provided with a vertical signal line 18 and a feedback line 25. Each vertical signal line 18 connects the corresponding pixel 10 to a load circuit 19, a column signal processing circuit 20, and an inverting amplifier 24. The column signal processing circuit 20 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 21 is connected to the column signal processing circuit 20. The horizontal signal readout circuit 21 sequentially reads signals from multiple column signal processing circuits 20 to a horizontal common signal line 23. The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18. A voltage Vref is supplied to the positive input terminal of the inverting amplifier 24. Vref is, for example, a positive voltage of 1V or near 1V. The output terminal of the inverting amplifier 24 is connected to a pixel 10 connected to the negative input terminal of the inverting amplifier 24 via the corresponding feedback line 25.

[0015] Figure 2 is a circuit diagram of a pixel 10 according to Embodiment 1. The pixel 10 includes a photoelectric conversion unit 15 and a signal detection circuit 12. The imaging device 1A includes a feedback circuit 13 that provides negative feedback to the output of the signal detection circuit 12. A feedback loop is formed in the feedback circuit 13.

[0016] The photoelectric conversion unit 15 includes a counter electrode 15a, a photoelectric conversion film 15b, and a pixel electrode 15c. The photoelectric conversion film 15b is positioned between the counter electrode 15a and the pixel electrode 15c. The counter electrode 15a is connected to a storage control line 17. The pixel electrode 15c is connected to a charge storage node 44.

[0017] The counter electrode 15a is transparent. Light passes through the counter electrode 15a and reaches the photoelectric conversion film 15b. By controlling the potential of the counter electrode 15a via the storage control line 17, a charge of one polarity from the positive and negative charge pairs generated by photoelectric conversion in the photoelectric conversion film 15b can be collected by the pixel electrode 15c. The positive and negative charge pairs are typically hole-electron pairs. When using holes as signal charges, the potential of the counter electrode 15a should be higher than that of the pixel electrode 15c. The following example illustrates the case where holes are used as signal charges. For example, a voltage of about 10V is applied to the counter electrode 15a via the storage control line 17. As a result, signal charges are stored in the charge storage node 44. Electrons may also be used as signal charges.

[0018] The signal detection circuit 12 includes an amplifying transistor 34, a reset transistor 36, a feedback transistor 38, an address transistor 40, a first capacitance element 41, and a second capacitance element 42. The amplifying transistor 34 outputs a signal corresponding to the amount of signal charge stored in the charge storage node 44. The reset transistor 36 resets the signal charge in the charge storage node 44. The feedback transistor 38 works in cooperation with the amplifying transistor 34 and the inverting amplifier 24 to form a feedback circuit 13. The address transistor 40 determines the timing at which the amplifying transistor 34 outputs a signal. The capacitance value of the second capacitance element 42 is smaller than the capacitance value of the first capacitance element 41.

[0019] The following describes an example in which N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as the amplification transistor 34, reset transistor 36, feedback transistor 38, and address transistor 40.

[0020] The gate of the amplification transistor 34 is connected to the charge storage node 44. The drain of the amplification transistor 34 is connected to the power supply wiring 22, which acts as a source follower power supply. The source of the amplification transistor 34 is connected to the vertical signal line 18. The amplification transistor 34 and the load circuit 19 (see Figure 1) constitute a source follower circuit.

[0021] An address transistor 40 is connected between the source of the amplifying transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When signal charge is accumulated in the charge storage node 44, a voltage corresponding to the amount of accumulated signal charge is applied to the gate of the amplifying transistor 34. The amplifying transistor 34 amplifies this voltage. When the address transistor 40 is turned on, the voltage amplified by the amplifying transistor 34 is selectively read out as the signal voltage.

[0022] One of the electrodes of the first capacitance element 41 is connected to a sensitivity adjustment wire 32. Typically, the potential of the sensitivity adjustment wire 32 is fixed at a constant potential, such as 0V. The sensitivity adjustment wire 32 can control the potential of the charge storage node 44. The other electrode of the first capacitance element 41 is connected to a reset drain node 46.

[0023] One electrode of the second capacitance element 42 is connected to the reset drain node 46. The other electrode of the second capacitance element 42 is connected to the charge storage node 44, and therefore to the pixel electrode 15c. A reset transistor 36 is connected in parallel with the second capacitance element 42.

[0024] One of the source and drains of the feedback transistor 38 is connected to the reset drain node 46. The other of the source and drains of the feedback transistor 38 is connected to the feedback line 25. The gate of the feedback transistor 38 is connected to the feedback control line 28.

[0025] Figure 3 is a cross-sectional view of the imaging device 1A according to Embodiment 1. The imaging device 1A includes a pixel region 71 and a peripheral region 72. In a plan view, the peripheral region 72 is located outside the pixel region 71. The peripheral region 72 includes a transition region 73, a light-shielding region 74, and a pad region 75. In a plan view, the light-shielding region 74 is located outside the transition region 73. In a plan view, the pad region 75 is located outside the light-shielding region 74.

[0026] The imaging device 1A includes a semiconductor substrate 2a, an insulating layer 4a, a semiconductor substrate 2b, and an insulating layer 4b. The semiconductor substrate 2a, insulating layer 4a, semiconductor substrate 2b, and insulating layer 4b are stacked in this order from bottom to top. In the semiconductor substrate 2b, the top surface is the front surface and the bottom surface is the back surface. The semiconductor substrate 2a, insulating layer 4a, semiconductor substrate 2b, and insulating layer 4b extend across the pixel region 71, the transition region 73, the light-shielding region 74, and the pad region 75.

[0027] For example, silicon substrates can be used as semiconductor substrates 2a and 2b. For example, silicon oxide layers can be used as insulating layers 4a and 4b. Insulating layers 4a and 4b can be formed using, for example, TEOS (Tetra Ethoxy Silane).

[0028] An electrode 50a is provided in the insulating layer 4a. Multiple pixel electrodes 15c, a control electrode 15d, an electrode 50b, an electrode 50c, an electrode 50d, and an electrode 52 are provided in the insulating layer 4b. Through electrodes 53a and 53b are provided so as to penetrate the semiconductor substrate 2b. Through electrodes 53a and 53b electrically connect the portion above and below the semiconductor substrate 2b. Electrode 50a extends across the light-shielding region 74 and the pad region 75. Multiple pixel electrodes 15c extend in the pixel region 71. The control electrode 15d, electrode 50b, electrode 50c, and electrode 52 extend in the light-shielding region 74. Electrode 50d extends in the pad region 75.

[0029] For example, electrodes containing metal can be used as the pixel electrode 15c and the control electrode 15d. The metal includes, for example, at least one selected from the group consisting of titanium nitride, copper, tungsten, titanium, tantalum, and aluminum. In Embodiment 1, the pixel electrode 15c and the control electrode 15d contain the same material. A continuous film is formed, and the continuous film can be processed into the pixel electrode 15c and the control electrode 15d by etching.

[0030] For example, electrodes containing metal can be used as electrodes 50a, 50b, 50c, 50d, 52, through electrode 53a, and through electrode 53b. The metal includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. The same applies to electrode 50e in Embodiment 4 (see Figure 12), which will be described later.

[0031] Above the semiconductor substrate 2b, specifically above the insulating layer 4b, are provided a photoelectric conversion film 15b, a counter electrode 15a, a protective layer 54, a light-shielding film 55, a protective layer 56, a color filter 57, a partition wall 58, a microlens 59, a photoelectric conversion film 61, a specific layer 62, a pad 63, and a specific layer 64. The microlens 59 and the specific layer 64 constitute a continuous layer.

[0032] In each pixel 10 within the pixel region 71, the pixel electrode 15c, photoelectric conversion film 15b, counter electrode 15a, protective layer 54, color filter 57, and microlens 59 are stacked from bottom to top in this order. The color filters 57 of adjacent pixels 10 are separated by partitions 58.

[0033] In the transition region 73, the pixel electrode 15c, photoelectric conversion film 15b, counter electrode 15a, protective layer 54, color filter 57, and specific layer 64 are stacked from bottom to top in this order.

[0034] The light-shielding region 74 includes an inner portion 74a and an outer portion 74b. In a plan view, the outer portion 74b is located outside the inner portion 74a. In the inner portion 74a, the pixel electrode 15c, photoelectric conversion film 15b, counter electrode 15a, protective layer 54, light-shielding film 55, protective layer 56, color filter 57, and specific layer 64 are stacked from bottom to top in this order. In the outer portion 74b, the control electrode 15d, light-shielding film 55, protective layer 56, color filter 57, and specific layer 64 are stacked from bottom to top in this order.

[0035] The pad region 75 includes a first portion 75a and a second portion 75b. In a plan view, the second portion 75b is surrounded by the first portion 75a. In the first portion 75a, the photoelectric conversion film 61, specific layer 62, protective layer 56, pad 63, color filter 57, and specific layer 64 are stacked from bottom to top in this order. In the second portion 75b, the electrode 50d and the pad 63 are stacked from bottom to top. Specifically, in the second portion 75b, the insulating layer 4b includes a recess that is lowered, and the electrode 50d is provided on the upper surface of the recess. The electrode 50d and the pad 63 are in contact with each other. The second portion 75b is provided with a pad hole 65. The pad hole 65 exposes the pad 63 upwards.

[0036] The color filter 57 extends across the pixel area 71, the transition area 73, the light-shielding area 74, and the pad area 75. The specific layer 64 extends across the transition area 73, the light-shielding area 74, and the pad area 75. The protective layer 56 extends across the light-shielding area 74 and the pad area 75.

[0037] In Embodiment 1, part or all of the peripheral circuitry, through electrode 53a, electrode 50b, electrode 52, electrode 50a, and control electrode 15d are located below the light-shielding film 55, overlap with the light-shielding film 55 in a plan view, and can be shielded from light by the light-shielding film 55. The light-shielding film 55 is conductive and is electrically connected to the counter electrode 15a by contacting the side surface of the counter electrode 15a. A potential can be applied to the counter electrode 15a via the pad 63 and the light-shielding film 55.

[0038] In the example shown in Figure 3, the imaging device 1A has an electrical path 66 electrically and physically connected to the pad 63. The electrical path 66 extends across the pad area 75 and the pixel area 71, specifically across the pad area 75, the light-shielding area 74, the transition area 73, and the pixel area 71. The electrical path 66 includes, in order from the pad 63 side, electrode 50d, through electrode 53b, electrode 50a, through electrode 53a, electrode 50c, electrode 52, electrode 50b, control electrode 15d, light-shielding film 55, and counter electrode 15a. At least a portion of the electrical path 66 is located within the insulating layer 4b.

[0039] For example, a film containing organic material can be used as the photoelectric conversion film 15b and the photoelectric conversion film 61. The organic material includes, for example, an organic semiconductor material. In Embodiment 1, the photoelectric conversion film 15b and the photoelectric conversion film 61 contain the same material. A continuous film is formed, and the continuous film can be processed into the photoelectric conversion film 15b and the photoelectric conversion film 61 by etching.

[0040] For example, a film containing a metal can be used as the counter electrode 15a and the specific layer 62. The metal includes, for example, at least one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). In Embodiment 1, the counter electrode 15a and the specific layer 62 contain the same material. A continuous film is formed, and the continuous film can be processed into the counter electrode 15a and the specific layer 62 by etching.

[0041] For example, protective layers 54 and 56 can be films containing an insulator. The insulator includes, for example, at least one selected from the group consisting of silicon oxide and silicon nitride. Specifically, the insulator may be silicon oxynitride. In Embodiment 1, protective layers 54 and 56 contain the same material.

[0042] For example, a layer containing resin can be used as the color filter 57. The resin may include, for example, acrylic resin. For example, a wall containing at least one selected from the group consisting of metal, carbon, and insulating material can be used as the partition wall 58.

[0043] For example, a layer containing resin can be used as the microlens 59 and the specific layer 64. The resin may include, for example, acrylic resin. In Embodiment 1, the microlens 59 and the specific layer 64 contain the same material. In other words, the microlens 59 contains lens material, and the specific layer 64 also contains the lens material. In Embodiment 1, the portion of the continuous layer having a lens shape constitutes the microlens 59, and the portion located outside the microlens 59 in a plan view constitutes the specific layer 64. The specific layer 64 may be a flat layer.

[0044] For example, a pad containing metal can be used as the pad 63. The metal includes, for example, at least one selected from the group consisting of titanium nitride, titanium, tungsten, and aluminum.

[0045] Figure 4 is a plan view showing the positional relationship between the photoelectric conversion film 15b, the photoelectric conversion film 61, the electrode 50d, and the pad 63 in Embodiment 1. In Figure 4, the counter electrode 15a, the specific layer 62, etc., are omitted from the illustration. In the plan view, the contours of the counter electrode 15a and the protective layer 54 coincide with the contour of the photoelectric conversion film 15b. In the plan view, the contour of the specific layer 62 coincides with the contour of the photoelectric conversion film 61.

[0046] Multiple through-holes 61t are provided in the photoelectric conversion film 61. An electrode 50d is positioned below each of the multiple through-holes 61t. Multiple pads 63, shown by dotted lines in Figure 4, are provided corresponding to the multiple through-holes 61t and the multiple electrodes 50d. Specifically, each of the multiple pads 63 covers the photoelectric conversion film 61 from above and contacts the corresponding electrode 50d through the corresponding through-hole 61t.

[0047] In the example shown in Figure 4, in a plan view, the photoelectric conversion film 61 is provided so as to surround the through-hole 61t, and the pad 63 is provided so as to straddle the through-hole 61t and the photoelectric conversion film 61 from above. This configuration may be advantageous from the viewpoint of stably providing the pad 63.

[0048] In Embodiment 1, the upper end 75h of the pad area 75 is located above the upper end 71h of the pixel area 71. This configuration is suitable for protecting the pixel area 71. The reasons for this will be explained below.

[0049] Firstly, from the perspective of the imaging device 1A as a final product, this configuration is suitable for protecting the pixel area 71. This is because, in a plan view, foreign matter moving from the outside to the inside of the pad area 75 is blocked by the pad area 75, thereby protecting the pixel area 71. Also, large-area foreign matter moving from above to below contacts the upper end 75h of the pad area 75 before contacting the pixel area 71, thereby protecting the pixel area 71.

[0050] Secondly, as will be explained with reference to Figures 5 to 8 below, this configuration is suitable for protecting the pixel area 71 in the manufacture of the imaging device 1A.

[0051] Figure 5 is a plan view showing a wafer device 9A according to Embodiment 1. The wafer device 9A includes a plurality of unit regions 70. Figure 5 also shows an enlarged view of one of the unit regions 70. Figure 6 is a cross-sectional view showing a unit region 70 according to Embodiment 1.

[0052] The wafer device 9A includes a semiconductor wafer 6A. The wafer device 9A is diced and separated into chips, each containing 70 unit regions. Each chip corresponds to one imaging device 1A. In this way, multiple imaging devices 1A are manufactured using the wafer device 9A.

[0053] The portion of the semiconductor wafer 6A belonging to each unit region 70 constitutes the semiconductor substrate 2b of one imaging device 1A. Each unit region 70 includes a pixel region 71 and a peripheral region 72. The peripheral region 72 includes a pad region 75.

[0054] Each unit region 70 of the wafer device 9A includes a microlens 59 in the pixel region 71, a first portion 75a in the pad region 75, and a low-profile portion 76 in the peripheral region 72. The upper end of the low-profile portion 76 is located below the upper end of the first portion 75a. The upper end 75h of the pad region 75 is located above the upper end 71h of the pixel region 71. Specifically, the upper end 75h is the upper end of the first portion 75a, and the upper end 71h is the upper end of the microlens 59. Although not shown in Figures 5 and 6, the unit region 70 includes multiple elements located above the semiconductor substrate 2b, such as the photoelectric conversion film 15b. In Figure 6, for ease of drawing, the first portion 75a in the pad region 75 is emphasized.

[0055] In the manufacturing of multiple imaging devices 1A using wafer devices 9A, steps 1 through 4 are performed. In reality, there may be a step in which the wafer devices 9A are physically inverted, but such a step will be omitted from the description below. In the following description, terms such as "top," "bottom," and "height" are used solely to specify the relative arrangement of elements.

[0056] In the first step, the tape 82 is pressed onto the wafer device 9A from above using a pressure roller 81. The tape 82 is a so-called back-grind tape. During roller pressing, the tape 82 adheres to the upper end 75h of the pad area 75, but it is difficult to adhere to the upper end 71h of the pixel area 71. This is because the upper end 75h is located above the upper end 71h. Specifically, during roller pressing, the tape 82 adheres to the first portion 75a, but it is difficult to adhere to the microlens 59.

[0057] Next, in the second step, the semiconductor wafer 6A is ground from its underside (back side). This reduces the thickness of the semiconductor wafer 6A to the thickness of the semiconductor substrate 2b while protecting the upper side (front side) of the wafer device 9A with the tape 82. The grinding in the second step is what is known as back grinding.

[0058] Next, in the third step, the tape 82 is peeled off from the pad area 75, specifically from the first portion 75a. Then, in the fourth step, the wafer device 9A is diced and separated into chips, one unit area 70 at a time.

[0059] Figure 7 is a cross-sectional view showing a unit region 70 according to Reference Embodiment 1. The unit region 70 according to Reference Embodiment 1 does not include the first portion 75a. During roller pressing, the tape 82 is adhered to the low-profile portion 76 in the peripheral region 72 and the microlens 59 in the pixel region 71. Figure 8 is a cross-sectional view showing tape removal according to Reference Embodiment 1. In Reference Embodiment 1, when the tape 82 is peeled off, the adhesive of the tape 82 tends to remain on the microlens 59 in the pixel region 71. This can worsen the yield in mass production of imaging devices.

[0060] In contrast, as described above, in Embodiment 1, the upper end portion 75h of the pad region 75 is located above the upper end portion 71h of the pixel region 71. The tape 82 is less likely to adhere to the pixel region 71, and therefore less adhesive from the tape 82 remains on the pixel region 71. Specifically, the tape 82 is less likely to adhere to the microlens 59, and therefore less adhesive from the tape 82 remains on the microlens 59. This can improve the yield in the mass production of the imaging device 1A.

[0061] The height difference between the upper edge 75h of the pad area 75 and the upper edge 71h of the pixel area 71 is, in one example, 1 μm to 10 μm, and in one specific example, 3 μm to 5 μm.

[0062] Returning to Figure 3, in Embodiment 1, the upper end portion 75h of the pad region 75 is the portion that overlaps with the pad 63 in a plan view. The height of the pad region 75 is increased by the pad 63. Specifically, the upper end portion 75h is the upper end portion of the first portion 75a, and the upper end portion 71h is the upper end portion of the microlens 59.

[0063] In Embodiment 1, the pad region 75 includes a laminated portion 77. The laminated portion 77 includes a photoelectric conversion film 61, a specific layer 62, a protective layer 56, a pad 63, a color filter 57, and a specific layer 64. The upper end portion 75h of the pad region 75 is the upper end portion of the laminated portion 77. In Embodiment 1, the laminated portion 77 is a first portion 75a.

[0064] In Embodiment 1, the upper end portion 63h of the pad 63 in the pad region 75 is located above the upper end portion 71h of the pixel region 71. The upper end portion 57h of the color filter 57 in the pad region 75 is located above the upper end portion 71h. The upper end portion 64h of the specific layer 64 in the pad region 75 is located above the upper end portion 71h. The upper end portion 75h of the pad region 75 is the upper end portion 64h of the specific layer 64.

[0065] In Embodiment 1, the pad region 75 has an upper surface located above the upper end portion 71h of the pixel region 71. In the illustrated example, the area of ​​the upper surface of the pad region 75 in a plan view is larger than the area of ​​the pixel 10 in a plan view. In the illustrated example, the upper surface of the pad region 75 includes the upper end portion 75h of the pad region 75.

[0066] In Embodiment 1, the pad 63 has an upper surface located above the upper end 71h of the pixel region 71. In the illustrated example, the area of ​​the upper surface of the pad 63 in a plan view is larger than the area of ​​the pixel 10 in a plan view. In the illustrated example, the upper surface of the pad 63 includes the upper end 63h of the pad 63.

[0067] In Embodiment 1, the color filter 57 has an upper surface located above the upper end 71h of the pixel region 71. In the illustrated example, the area of ​​the upper surface of the color filter 57 in a plan view is larger than the area of ​​the pixel 10 in a plan view. In the illustrated example, the upper surface of the color filter 57 includes the upper end 57h of the color filter 57.

[0068] In Embodiment 1, the specific layer 64 has an upper surface located above the upper end portion 71h of the pixel region 71. In the illustrated example, the area of ​​the upper surface of the specific layer 64 in a plan view is larger than the area of ​​the pixel 10 in a plan view. In the illustrated example, the upper surface of the specific layer 64 includes the upper end portion 64h of the specific layer 64.

[0069] In Embodiment 1, the stacked portion 77 has an upper surface located above the upper end portion 71h of the pixel region 71. In the illustrated example, the area of ​​the upper surface of the stacked portion 77 in a plan view is larger than the area of ​​the pixel 10 in a plan view. In the illustrated example, the upper surface of the stacked portion 77 includes the upper end portion of the stacked portion 77.

[0070] In Embodiment 1, the pad 63 includes an exposed portion 63e that is exposed upward. The exposed portion 63e includes a reference portion 63r and a recessed portion 63b. The recessed portion 63b is recessed downward from the reference portion 63r. For example, an electrical connection between an external terminal and the pad 63 may be made via wire bonding to the recessed portion 63b. In the example in Figure 3, the reference portion 63r is the upper end portion 63h.

[0071] As described above, in Embodiment 1, the pixel region 71 includes a microlens 59 containing lens material. The peripheral region 72 includes a specific layer 64 containing the lens material. The microlens 59 and the specific layer 64 are continuous with each other. In Embodiment 1, the upper end of the microlens 59 and the upper end 64h of the specific layer 64 are exposed upwards. In the manufacture of the imaging device 1A having this configuration, it is not necessary to form a layer above the microlens 59 and the specific layer 64. Therefore, it is possible to avoid situations in which foreign matter adheres to the microlens 59 due to the formation of an upper layer. In addition, it is possible to avoid situations in which foreign matter penetrates the microlens 59 and reaches the photoelectric conversion film 15b, causing damage to the photoelectric conversion film 15b, such as during roller pressing of the tape 82. These are advantageous from the viewpoint of protecting the microlens 59 and the photoelectric conversion film 15b. In the manufacture of the above-mentioned upper layer, for example, the base layer is formed with a coater, then the base layer is processed by etching, and then cleaning is performed. According to Embodiment 1, it is possible to avoid situations where etching and cleaning residues adhere to the microlens 59 or reach the photoelectric conversion film 15b.

[0072] Figure 9 is a plan view showing a wafer device 9A according to Embodiment 1. In Figure 9, four unit regions 70 are typically shown. However, the actual wafer device 9A may contain more unit regions 70. The wafer device 9A is diced along the dicing line 83. In Figure 9, the position of the dicing line 83 is indicated by an arrow. Although Figure 9 shows the pixel array 11, it is not essential that the pixel array 11 is completed at the stage of the wafer device 9A during the manufacturing of the imaging device 1A.

[0073] In a plan view, in each unit region 70, a row 79 of pads 63 is formed in the pad region 75. The upper end of each portion that overlaps with each pad 63 in the row 79 in a plan view is located above the upper end 71h of the pixel region 71. Specifically, each of the above portions includes a first portion 75a.

[0074] Similarly, in a plan view, a row 79 of pads 63 is formed in the pad area 75 of the imaging device 1A as the final product. The upper end of each portion of the row 79 that overlaps with each pad 63 in a plan view is located above the upper end 71h of the pixel area 71. Specifically, each of the above portions includes the first portion 75a.

[0075] In a plan view, the pixel array 11 in the pixel region 71 of the imaging device 1A is arranged to form a rectangle as a whole. In a plan view, the row 79 in the imaging device 1A extends along at least one side of the rectangle formed by the pixel array 11, more specifically along at least two sides of the rectangle, more specifically along at least two adjacent sides of the rectangle, and even more specifically surrounding the rectangle.

[0076] In Figure 9 and the examples in Figures 10 and 11 described later, the edges of the pixel array 11 refer to a column of pixels 10 located at the ends in the row direction of the pixel array 11, or a column of pixels 10 arranged in the row direction at the ends in the column direction of the pixel array 11. In Figures 9 to 11, the pixels 10 that make up the edges of the pixel array 11 are drawn as white rectangles. In Figures 9 to 11, the row direction and column direction are the left-right direction and the up-down direction, respectively.

[0077] Other embodiments will be described below. In the following, elements common to embodiments already described and those described later will be given the same reference numerals, and their descriptions may be omitted. The descriptions of each embodiment may be mutually applicable, as long as they do not technically contradict each other. As long as they do not technically contradict each other, each embodiment may be combined with each other.

[0078] (Embodiment 2) Figure 10 is a plan view showing a wafer device 9B according to Embodiment 2. As can be seen from Figure 10, in Embodiment 2, in a plan view, the row 79 in the final imaging device extends along only two adjacent sides of the rectangle formed by the pixel array 11, forming an L-shape.

[0079] (Embodiment 3) Figure 11 is a plan view showing a wafer device 9C according to Embodiment 3. As can be seen from Figure 11, in Embodiment 3, in a plan view, the row 79 in the final product imaging device extends along only one side of the rectangle formed by the pixel array 11, forming an I-shape.

[0080] (Embodiment 4) Figure 12 is a cross-sectional view of the imaging device 1D according to Embodiment 4. The imaging device 1D does not include the semiconductor substrate 2a, insulating layer 4a, electrodes 50a, 50b, 50c, 52, through-electrode 53a, through-electrode 53b, etc., as described in Embodiment 1 (see Figure 3). On the other hand, the imaging device 1D includes electrode 50e. Electrode 50e is provided on the insulating layer 4b. Electrode 50e extends across the light-shielding region 74 and the pad region 75. The electrical path 66 includes, in order from the pad 63 side, electrode 50d, electrode 50e, control electrode 15d, light-shielding film 55, and counter electrode 15a.

[0081] The first portion 75a of the imaging device 1D does not include the photoelectric conversion film 61, specific layer 62, color filter 57, and specific layer 64 of Embodiment 1. In the first portion 75a, the protective layer 56 and the pad 63 are stacked from bottom to top. The upper end 75h of the pad area 75 is the upper end 63h of the pad 63. The upper end 63h of the pad 63 is located above the upper end 71h of the pixel area 71.

[0082] (Embodiment 5) Figure 13 is a cross-sectional view of the imaging device 1E according to Embodiment 5. The imaging device 1E does not include the electrodes 50a, 50c, through-electrode 53b, etc. of Embodiment 1. Electrode 50d extends across the light-shielding region 74 and the pad region 75. The electrical path 66 includes, in order from the pad 63 side, electrode 50d, electrode 52, electrode 50b, control electrode 15d, light-shielding film 55, and counter electrode 15a. The first part 75a of the imaging device 1E is the same as in Embodiment 4.

[0083] (Embodiment 6) Figure 14 is a cross-sectional view of the imaging device 1F according to Embodiment 6. The first part 75a of the imaging device 1F is the same as in Embodiment 4.

[0084] (Embodiment 7) Figure 15 is a cross-sectional view of the imaging device 1G according to Embodiment 7. The first part 75a of the imaging device 1G does not include the photoelectric conversion film 61, specific layer 62, and specific layer 64 of Embodiment 1. In the first part 75a, the protective layer 56, pad 63, and color filter 57 are stacked in this order from bottom to top. The upper end 75h of the pad area 75 is the upper end 57h of the color filter 57. The upper end 57h of the color filter 57 is located above the upper end 71h of the pixel area 71.

[0085] (Embodiment 8) Figure 16 is a cross-sectional view of the imaging device 1H according to Embodiment 8. The first part 75a of the imaging device 1H does not include the photoelectric conversion film 61, specific layer 62, and color filter 57 of Embodiment 1. In the first part 75a, the protective layer 56, pad 63, and specific layer 64 are stacked in this order from bottom to top. The upper end 75h of the pad area 75 is the upper end 64h of the specific layer 64. The upper end 64h of the specific layer 64 is located above the upper end 71h of the pixel area 71.

[0086] (Embodiment 9) Figure 17 is a cross-sectional view of the imaging device 1I according to Embodiment 9. The first part 75a of the imaging device 1I does not include the color filter 57 and the specific layer 64 of Embodiment 1. In the first part 75a, the protective layer 56, the photoelectric conversion film 61, the specific layer 62, and the pad 63 are stacked in this order from bottom to top. The upper end 75h of the pad area 75 is the upper end 63h of the pad 63. The upper end 63h of the pad 63 is located above the upper end 71h of the pixel area 71.

[0087] As can be understood from Embodiments 1 to 9, various imaging devices can be configured.

[0088] The first part 75a may or may not include a specific layer 64, a color filter 57, a specific layer 62, a photoelectric conversion film 61, and a protective layer 56. The first part 75a may be a laminated portion 77, or a single layer portion of the pad 63.

[0089] The upper end 63h of the pad 63 may be located above the upper end 71h of the pixel area 71, at the same height as the upper end 71h, or below the upper end 71h. The lower end of the pad 63 may be located above the upper end 71h of the pixel area 71, at the same height as the upper end 71h, or below the upper end 71h. A through electrode 53b may or may not be located below the pad 63 and overlapping with the pad 63 in a plan view. The photoelectric conversion unit 15 may be a photodiode provided in the semiconductor substrate 2a or the semiconductor substrate 2b. The number of semiconductor substrates included in the imaging device may be one or more.

[0090] In the example shown in Figure 4 above, in a plan view, a single continuous photoelectric conversion film 61 extends across multiple pads 63. However, it is also possible that multiple photoelectric conversion films 61 and multiple pads 63 that are separated from each other are associated one-to-one, and in a plan view, at least a portion of each of the multiple photoelectric conversion films 61 overlaps with at least a portion of the pad 63 associated with it. The same applies to the specific layer 62.

[0091] In the example shown in Figure 10 above, column 79 extends along only two adjacent sides of the rectangle formed by the pixel array 11. However, column 79 may also extend along only two opposite sides of the rectangle formed by the pixel array 11. Column 79 may have at least one of the first and second configurations. The first configuration is one in which column 79 extends along at least two adjacent sides of the rectangle formed by the pixel array 11. The second configuration is one in which column 79 extends along at least two opposite sides of the rectangle formed by the pixel array 11.

[0092] (Embodiment 10) Referring to Figure 18, the camera system 90 according to Embodiment 3 will be described.

[0093] Figure 18 schematically shows an example configuration of a camera system 90 according to Embodiment 10. The camera system 90 includes a lens optical system 91, an imaging device 92, a system controller 93, and a camera signal processing circuit 94. The camera system 90 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0094] The lens optical system 91 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The lens optical system 91 focuses light onto the imaging plane of the imaging device 92. As the imaging device 92, imaging devices according to embodiments 1 to 9 described above and their modifications can be widely used.

[0095] The system controller 93 controls the entire camera system 90. The system controller 93 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0096] The camera signal processing circuit 94 has the function of processing the output signal from the imaging device 92. The camera signal processing circuit 94 receives output data from the imaging device 92 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 92 and the camera signal processing circuit 94 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 92 as part can be made smaller. The camera signal processing circuit 94 may be, for example, a DSP (Digital Signal Processor).

[0097] (Note) This disclosure provides for the following technologies:

[0098] (Technology 1) Semiconductor substrate and A pixel region including a pixel array, The pad area including the pad, Equipped with, The pad is located above the semiconductor substrate, The upper end of the pad region is located above the upper end of the pixel region. Imaging device.

[0099] (Technology 2) The upper end of the pad region is the portion that overlaps with the pad in a plan view. The imaging device described in Technical 1.

[0100] (Technology 3) The upper end of the pad is located above the upper end of the pixel region. An imaging apparatus as described in Technology 1 or 2.

[0101] (Technology 4) In the aforementioned pad region, a row of the pads is formed, The upper end of each portion that overlaps with each pad in the row in a plan view is located above the upper end of the pixel region. An imaging device as described in any one of the three technical specifications (1 to 3).

[0102] (Technology 5) The row extends along at least one side of the pixel array, The imaging device described in Technical 4.

[0103] (Technology 6) The row extends along at least two sides of the pixel array, The at least two sides include two adjacent sides of the pixel array and / or two opposite sides of the pixel array. An imaging apparatus as described in Technical 4 or 5.

[0104] (Technology 7) The aforementioned column extends so as to surround the pixel array. An imaging device as described in any one of the technical items 4 to 6.

[0105] (Technology 8) The pad region includes a laminated portion, The laminated portion includes the pad and the color filter, An imaging device as described in any one of the technical items 1 to 7.

[0106] (Technology 9) The pad region includes a laminated portion, The aforementioned pixel region includes a microlens, The aforementioned microlens includes a lens material, The laminated portion includes the pad and the specific layer, The aforementioned specific layer includes the lens material, An imaging device as described in any one of the technical items 1 to 8.

[0107] (Technology 10) The pad region includes a laminated portion, The laminated portion includes the pad and the photoelectric conversion film, An imaging apparatus as described in any one of the technical items 1 to 9.

[0108] (Technology 11) Located outside the aforementioned pixel region, and comprising a peripheral region including the aforementioned pad region, The aforementioned pixel region includes a microlens, The aforementioned microlens includes a lens material, The aforementioned peripheral region includes a specific layer, The aforementioned specific layer includes the lens material, The upper end of the microlens and the upper end of the specific layer are exposed upward. An imaging apparatus as described in any one of the technical items 1 to 10.

[0109] (Technology 12) An imaging apparatus as described in any one of the technical items 1 to 11, The imaging device comprises a lens optical system that focuses light onto the imaging surface, A camera signal processing circuit that processes the output signal from the imaging device, Equipped with, Camera system. [Industrial applicability]

[0110] The design of the imaging device described herein can improve the yield in mass production of the imaging device. [Explanation of Symbols]

[0111] 1A, 1D, 1E, 1F, 1G, 1H, 1I Imaging device 2a, 2b Semiconductor substrates 10 pixels 11-pixel array 50a, 50b, 50c, 50d, 50e, 52, 53a, 53b electrode 57 Color Filters 57h, 63h, 64h, 71h, 75h Upper end 59 Microlenses 15b, 61 Photoelectric conversion film 61t through hole 62, 64 Specific layer 63 pads 71 pixel area 72 Peripheral area 75 Pad Area 77 Laminated section 79 columns

Claims

1. Semiconductor substrate and A pixel region including a pixel array, The pad area including the pad, Equipped with, The pad is located above the semiconductor substrate, The upper end of the pad region is located above the upper end of the pixel region. Imaging device.

2. The upper end of the pad region is the portion that overlaps with the pad in a plan view. The imaging apparatus according to claim 1.

3. The upper end of the pad is located above the upper end of the pixel region. The imaging apparatus according to claim 1.

4. In the aforementioned pad region, a row of the pads is formed, The upper end of each portion that overlaps with each pad in the row in a plan view is located above the upper end of the pixel region. The imaging apparatus according to claim 1.

5. The row extends along at least one side of the pixel array, The imaging apparatus according to claim 4.

6. The row extends along at least two sides of the pixel array, The at least two sides include two adjacent sides of the pixel array and / or two opposite sides of the pixel array. The imaging apparatus according to claim 4.

7. The aforementioned column extends so as to surround the pixel array. The imaging apparatus according to claim 4.

8. The pad region includes a laminated portion, The laminated portion includes the pad and the color filter, The imaging apparatus according to claim 1.

9. The pad region includes a laminated portion, The aforementioned pixel region includes a microlens, The aforementioned microlens includes a lens material, The laminated portion includes the pad and the specific layer, The aforementioned specific layer includes the lens material, The imaging apparatus according to claim 1.

10. The pad region includes a laminated portion, The laminated portion includes the pad and the photoelectric conversion film, The imaging apparatus according to claim 1.

11. Located outside the aforementioned pixel region, and comprising a peripheral region including the aforementioned pad region, The aforementioned pixel region includes a microlens, The aforementioned microlens includes a lens material, The aforementioned peripheral region includes a specific layer, The aforementioned specific layer includes the lens material, The upper end of the microlens and the upper end of the specific layer are exposed upward. The imaging apparatus according to claim 1.

Images