Drive circuit board and method for manufacturing a drive circuit board

Abstract

The unit drive circuits included in the drive circuit board are made more precise. [Solution] The drive circuit board (1) includes an island-shaped first semiconductor layer (3), a first insulating layer (4) provided on the first semiconductor layer (3), a first gate electrode (G) and second counter electrode (CE1) provided on the first insulating layer (4) so ​​as to overlap with a first channel region (3JD1) and a part of the first source region (3ND2), which is the first counter electrode (CE2) in a plan view, a first drain electrode (D) electrically connected to the first drain region (3ND1), a first source electrode (S) electrically connected to the first source region (3ND2), and a holding capacitor (Cs) including the first counter electrode (CE2) and the second counter electrode (CE1), and comprises a plurality of unit drive circuits including the first transistor (T1).

Description

Technical Field

[0001] The present disclosure relates to a drive circuit board and a method for manufacturing the drive circuit board.

Background Art

[0002] In recent years, a unit drive circuit including a plurality of transistors provided in a drive circuit board has been frequently used as a pixel circuit for displaying in a display area of a display device or as a drive driver provided in a non-display area of the display device for driving the pixel circuit in the field of display devices. Also, in fields other than display devices, for example, since it can be applied to various fields such as 3D printers and fingerprint sensors, its research and development have been actively carried out.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Documents 1 and 2 describe that a drive circuit board including a plurality of unit drive circuits including drive transistors and selection transistors is used as a pixel circuit for displaying in a display area of a display device.

[0005] In the field of display devices, in order to achieve an improvement in image quality, a higher definition of the unit drive circuit is required for the drive circuit board.

[0006] However, Patent Documents 1 and 2 do not describe a configuration or method for making the unit drive circuit included in the drive circuit board higher definition.

[0007] One aspect of this disclosure aims to provide a drive circuit board that can achieve high resolution in a unit drive circuit and a method for manufacturing a drive circuit board. [Means for solving the problem]

[0008] The drive circuit board of this disclosure solves the above-mentioned problems, A first semiconductor layer in the shape of an island, comprising a first channel region, a first source region containing impurities, and a first drain region, A first insulating layer provided on the first semiconductor layer, In a plan view, a first gate electrode and second counter electrode are provided on the first insulating layer so as to overlap the first channel region and a part of the first source region which is the first counter electrode, A first drain electrode electrically connected to the first drain region, A first source electrode electrically connected to the first source region, A first transistor comprising a holding capacitor including the first counter electrode and the second counter electrode, The device comprises multiple unit drive circuits, each including the first transistor.

[0009] The method for manufacturing a drive circuit board according to this disclosure solves the above-mentioned problems. A first step of forming an island-shaped first semiconductor layer included in a first transistor having a holding capacitor including a first counter electrode and a second counter electrode, A second step of forming a first insulating layer on the first semiconductor layer, A third step involves forming a resist film of a predetermined shape on the first insulating layer, and using the resist film as a mask, injecting impurities into a part of the first semiconductor layer to form a first channel region, a first source region and a first drain region having a higher impurity concentration than the first channel region. A fourth step involves removing the resist film and then forming a first gate electrode and second counter electrode on the first insulating layer such that, in a plan view, it overlaps the first channel region and a part of the first source region which is the first counter electrode. A fifth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region, and forming a plurality of unit drive circuits including the first transistor.

Advantages of the Invention

[0010] According to one aspect of the present disclosure, it is possible to provide a drive circuit board capable of high-definition of a unit drive circuit and a method for manufacturing the drive circuit board.

Brief Description of the Drawings

[0011] [Figure 1] It is a circuit diagram of a unit drive circuit provided on the drive circuit board of Embodiment 1. [Figure 2] It is a plan view showing a schematic configuration of the drive circuit board of Embodiment 1. [Figure 3] It is a cross-sectional view showing a schematic configuration of the drive circuit board of Embodiment 1. [Figure 4] It is a diagram showing some steps in the method for manufacturing the drive circuit board of Embodiment 1. [Figure 5] It is a diagram showing some other steps in the method for manufacturing the drive circuit board of Embodiment 1. [Figure 6] It is a diagram showing still some other steps in the method for manufacturing the drive circuit board of Embodiment 1. [Figure 7] It is a plan view showing a schematic configuration of the drive circuit board of Comparative Example 1. [Figure 8] It is a cross-sectional view showing a schematic configuration of the drive circuit board of Comparative Example 1. [Figure 9] It is a diagram showing the difference between the order of some steps in the method for manufacturing the drive circuit board of Embodiment 1 and the order of some steps in the method for manufacturing the drive circuit board of Comparative Example 1. [Figure 10] It is a plan view showing a schematic configuration of the drive circuit board of Embodiment 2. [Figure 11] It is a cross-sectional view showing a schematic configuration of the drive circuit board of Embodiment 2. [Figure 12]It is a diagram showing some steps in the manufacturing method of the drive circuit board of Embodiment 2. [Figure 13] It is a diagram showing some other steps in the manufacturing method of the drive circuit board of Embodiment 2. [Figure 14] It is a diagram showing some further other steps in the manufacturing method of the drive circuit board of Embodiment 2. [Figure 15] It is a plan view showing a schematic configuration of the drive circuit board of Embodiment 3. [Figure 16] It is a cross-sectional view showing a schematic configuration of the drive circuit board of Embodiment 3.

Embodiments for Carrying Out the Invention

[0012] Regarding the embodiments of the present disclosure, if explained based on FIGS. 1 to 16, it is as follows. Hereinafter, for the sake of convenience of explanation, for configurations having the same functions as those explained in specific embodiments, the same reference numerals may be added, and the explanation thereof may be omitted.

[0013] 〔Embodiment 1〕 FIG. 1 is a circuit diagram of the unit drive circuit DRU provided on the drive circuit board 1 of Embodiment 1. FIG. 2 is a plan view of the drive circuit board 1 of Embodiment 1 as viewed from above, and is a diagram showing a schematic configuration of the drive circuit board 1. In FIG. 2, the barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown. FIG. 3 is a cross-sectional view showing a schematic configuration of the drive circuit board 1 of Embodiment 1. Note that FIG. 3 is a cross-sectional view of the drive circuit board 1 cut along the X1-X1' line and the X2-X2' line shown in FIG. 2, respectively.

[0014] As shown in Figures 1, 2, and 3, each of the multiple unit drive circuits DRU provided on the drive circuit board 1 includes a first transistor T1 equipped with a retaining capacitor Cs including a first counter electrode CE2 and a second counter electrode CE1. As shown in Figure 3, the first transistor T1 equipped with the retaining capacitor Cs includes an island-shaped first semiconductor layer 3, a first counter electrode CE2 which is part of the first semiconductor layer 3, a first insulating layer 4 provided on the first semiconductor layer 3, a first gate electrode G and second counter electrode CE1 provided on the first insulating layer 4, a first drain electrode D, and a first source electrode S. The island-shaped first semiconductor layer 3 includes a first channel region 3JD1, a first source region 3ND2 containing impurities, and a first drain region 3ND1. The first gate electrode G and second counter electrode CE1 is provided on the first insulating layer 4 so as to overlap the first channel region 3JD1 and a part of the first source region 3ND2 which is the first counter electrode CE2 in a plan view. The first drain electrode D is electrically connected to the first drain region 3ND1, and the first source electrode S is electrically connected to the first source region 3ND2.

[0015] As shown in Figures 2 and 3, the first transistor T1, which is equipped with a retaining capacitor Cs in each of the multiple unit drive circuits DRU provided on the drive circuit board 1, has a first gate electrode G that also serves as a second counter electrode CE1. Therefore, there is no need to separately form contact holes for electrically connecting the first gate electrode G and the second counter electrode CE1, and the area of ​​the first transistor T1 can be reduced by not forming contact holes. Consequently, the unit drive circuits DRU on the drive circuit board 1 can be made highly detailed. On the other hand, in the case of the drive circuit board 50 which includes the first transistor T1' equipped with a retaining capacitor Cs as in Comparative Example 1, where the first gate electrode G and the second counter electrode CE1 are provided on different layers (see Figures 7 and 8), it is necessary to separately form contact holes CON8 and CON9 in the second insulating layer 5 for electrically connecting the first gate electrode G and the second counter electrode CE1. As a result of forming the contact holes CON8 and CON9, the area of ​​the first transistor T1' becomes larger.

[0016] In this embodiment, the first channel region 3JD1 is made of polysilicon, which is a semiconductor free of impurities, for example, while the first source region 3ND2 and the first drain region 3ND1, which contain impurities, are formed by implanting impurities into polysilicon, which is a semiconductor free of impurities. In this embodiment, the first source region 3ND2 and the first drain region 3ND1, which contain impurities, are formed by implanting P (phosphorus ions), which are N-type impurities, as the impurities. However, the embodiment is not limited to this, and for example, they may be formed by implanting As (arsenide ions), which are N-type impurities, or by implanting B (boron ions), which are P-type impurities.

[0017] In this embodiment, as shown in Figure 1, we will explain using the example where the unit drive circuit DRU is composed of a drive transistor T1, a selection transistor T2, and a holding capacitor Cs. However, the embodiment is not limited to this, as long as the unit drive circuit DRU includes a first transistor T1 equipped with a holding capacitor Cs.

[0018] In this embodiment, each of the multiple unit drive circuits DRU provided on the drive circuit board 1 includes a second transistor T2. As shown in Figure 3, the second transistor T2 includes an island-shaped second semiconductor layer 3', a first insulating layer 4 provided on the second semiconductor layer 3', a second gate electrode G' provided on the first insulating layer 4, a second drain electrode D', and a second source electrode S'. The island-shaped second semiconductor layer 3' includes a second channel region 3JD1'·3JD2', and a second source region 3ND1' and a second drain region 3ND3' containing impurities. The second gate electrode G' is provided on the first insulating layer 4 so as to overlap with the second channel region 3JD1'·3JD2' in a plan view. As shown in Figures 2 and 3, the second drain electrode D' is electrically connected to the second drain region 3ND3' and the first gate electrode G / second counter electrode CE1, and the second source electrode S' is electrically connected to the second source region 3ND1'.

[0019] In this embodiment, the second channel regions 3JD1' and 3JD2' are made of polysilicon, a semiconductor free of impurities, similar to the first channel region 3JD1. The second source region 3ND1' and the second drain region 3ND3', which contain impurities, are formed by implanting impurities into polysilicon, a semiconductor free of impurities, similar to the first source region 3ND2 and the first drain region 3ND1, which also contain impurities. In this embodiment, the second source region 3ND1', the high-concentration region 3ND2', and the second drain region 3ND3', which contain impurities, are formed by implanting P (phosphorus ions), an N-type impurity, as the impurity. However, the embodiment is not limited to this, and for example, they may be formed by implanting As (arsenide ions), an N-type impurity, or by implanting B (boron ions), a P-type impurity.

[0020] As shown in Figure 3, the island-shaped first semiconductor layer 3 and the island-shaped second semiconductor layer 3' are provided on the barrier layer 2. The barrier layer 2 is a layer that prevents foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2, and can be composed of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a laminate of these, formed by the CVD method. The thickness of the barrier layer 2 is not particularly limited as long as it can prevent foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2.

[0021] In this embodiment, the first island-shaped semiconductor layer 3 and the second island-shaped semiconductor layer 3' are described as being composed of polysilicon formed at low temperature with a film thickness of 40 nm, but are not limited to this, and may be composed of oxide semiconductors (for example, In-Ga-Zn-O semiconductors) or polysilicon formed at high temperature. The first source region 3ND2 and the first drain region 3ND1 in the first semiconductor layer 3, which contain impurities, and the second source region 3ND1' and the second drain region 3ND3' in the second semiconductor layer 3', which contain impurities, are regions formed by implanting impurities into a semiconductor that does not contain impurities.

[0022] The first insulating layer 4 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate of these, formed by the CVD method. In this embodiment, a silicon nitride film with a thickness of 85 nm was used as the first insulating layer 4.

[0023] The first gate electrode G and second counter electrode CE1 of the first transistor T1 and the second gate electrode G' of the second transistor T2, as shown in Figure 3, can be formed as the same layer from the same material. For example, they can be composed of a single-layer or multilayer film of a metal containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, or copper. In this embodiment, a MoW film, which is a molybdenum-tungsten alloy film with a thickness of 300 nm, was used for both the first gate electrode G and second counter electrode CE1 and the second gate electrode G'.

[0024] In this embodiment, as shown in Figure 3, the second drain electrode D' of the second transistor T2 and the first gate electrode G and second counter electrode CE1 of the first transistor T1, which is equipped with a holding capacitor Cs, are formed as different layers. Therefore, the drive circuit board 1 includes a second insulating layer 5 provided to cover the first gate electrode G and second counter electrode CE1 and the second gate electrode G' in order to ensure insulation between the layer forming the second drain electrode D' of the second transistor T2 and the layer forming the first gate electrode G and second counter electrode CE1 of the first transistor T1. The second insulating layer 5 can be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate of these, formed by the CVD method. In this embodiment, a laminate of a silicon oxide film formed with a thickness of 680 nm and a silicon nitride film formed with a thickness of 160 nm was used as the second insulating layer 5. As shown in Figure 2, the second drain electrode D' of the second transistor T2 and the first gate electrode G and second counter electrode CE1 of the first transistor T1, which is equipped with a holding capacitor Cs, are electrically connected via a contact hole CON1 formed in the second insulating layer 5.

[0025] The first drain electrode D and first source electrode S of the first transistor T1 and the second drain electrode D' and second source electrode S' of the second transistor T2, as shown in Figure 3, can be formed as the same layer from the same material. For example, they can be composed of a single-layer or multilayer film of a metal containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, or copper. In this embodiment, the first drain electrode D, first source electrode S, second drain electrode D', and second source electrode S' are each made of a multilayer film of titanium with a thickness of 30 nm, aluminum with a thickness of 300 nm, and titanium with a thickness of 20 nm.

[0026] As shown in Figure 3, the drive circuit board 1 is provided with a passivation film 6 so as to cover the first drain electrode D, the first source electrode S, the second drain electrode D', and the second source electrode S', and the second insulating layer 5. The passivation film 6 may be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate of these, formed by the CVD method, or it may be composed of a coatable organic material such as polyimide or acrylic. In this embodiment, a silicon nitride film with a thickness of 300 nm was used as the passivation film 6.

[0027] In this embodiment, as shown in Figures 2 and 3, the case in which the second transistor T2 is a double-gate type transistor is used as an example for explanation, but the embodiment is not limited to this, and the second transistor T2 may be a single-gate type transistor. Since the second transistor T2 is a double-gate type transistor, as shown in Figure 3, it comprises a second semiconductor layer 3' having two second channel regions 3JD1'·3JD2', and two second gate electrodes G' that overlap with each of the two second channel regions 3JD1'·3JD2' in a plan view.

[0028] In this embodiment, as shown in Figure 3, the second drain electrode D' of the second transistor T2 and the first gate electrode G and second counter electrode CE1 of the first transistor T1 equipped with a retaining capacitor Cs are formed as different layers. Therefore, as shown in Figure 2, the second drain electrode D' of the second transistor T2 and the first gate electrode G and second counter electrode CE1 of the first transistor T1 equipped with a retaining capacitor Cs are electrically connected via a contact hole CON1 formed in the second insulating layer 5. However, this is not the only possible configuration. As described in Embodiment 2 later, the second drain electrode D' of the second transistor T2 and the first gate electrode G and second counter electrode CE1 of the first transistor T1 equipped with a retaining capacitor Cs may be formed as the same layer and of the same material. Furthermore, as described in Embodiment 3 later, the second drain electrode D' may be provided in contact with the second drain region 3ND3' via a contact hole CON3, and the first gate electrode G and second counter electrode CE1 may be provided in contact with the second drain region 3ND3' via a contact hole.

[0029] In this embodiment, as shown in Figure 1, a light-emitting element is provided as a functional part FEL electrically connected to each unit drive circuit DRU, as an example. However, the embodiment is not limited to this, and the functional part FEL electrically connected to the unit drive circuit DRU may, for example, be an anode electrode. In this embodiment, the case where the light-emitting element is an OLED (organic light-emitting diode) is used as an example, but the embodiment is not limited to this, and the light-emitting element may, for example, be a QLED (quantum dot light-emitting diode). The functional part FEL can be provided, for example, on a passivation film 6 shown in Figure 3, and the functional part FEL can be electrically connected to the first drain electrode D of the first transistor T1 via a contact hole formed in the passivation film 6 (not shown).

[0030] Contact hole CON1 shown in Figures 2 and 3 is a contact hole formed in the second insulating layer 5, and contact holes CON2 to CON7 shown in Figures 2 and 3 are contact holes formed in the first insulating layer 4 and the second insulating layer 5.

[0031] As shown in Figure 1, in the unit drive circuit DRU and the functional unit FEL, the drain electrode D of the first transistor T1, which is the drive transistor, is electrically connected to one electrode of the light-emitting element, which is the functional unit FEL, for example, the anode electrode (not shown), and the first counter electrode CE2 of the holding capacitor Cs. The gate electrode G of the first transistor T1 is electrically connected to the second counter electrode CE1 of the holding capacitor Cs and the drain electrode D' of the second transistor T2, which is the selection transistor. The source electrode S of the first transistor T1 is connected to the high-potential-side power supply voltage line V to which the high-potential-side power supply voltage is supplied. DD It is electrically connected to the following. The other electrode of the light-emitting element, which is the functional part FEL, for example, the cathode electrode (not shown), is electrically connected to the low-potential power supply line to which the low-potential power supply voltage is supplied, for example, the grounded low-potential power supply line. In addition, the source electrode S' of the second transistor T2, which is the selection transistor, is connected to the data signal line V to which the data signal is supplied. DATA It is electrically connected to the scan signal line V, and the gate electrode G' of the second transistor T2 is connected to the scan signal line V to which the scan signal is supplied. SELThe drain electrode D' of the second transistor T2 is electrically connected to the gate electrode G of the first transistor T1 and the second counter electrode CE1 of the holding capacitor Cs. In this embodiment, as shown in Figure 1, each unit drive circuit DRU is equipped with a current-driven light-emitting element as a functional part FEL electrically connected to the unit drive circuit DRU. Therefore, it is preferable that the first transistor T1 provided in each of the multiple unit drive circuits DRU on the drive circuit board 1 has high current driving capability, and that the current driving capability of the first transistor T1 is stable. On the other hand, the second transistor T2 supplies a voltage corresponding to the data signal to the first transistor T1 according to the timing of the scanning signal and changes the voltage of the first transistor T1. Therefore, it is preferable that the second transistor T2 has transistor characteristics with low leakage current.

[0032] In NMOS transistors such as the first transistor T1 and the second transistor T2 described above, electron carriers move from the source region to the drain region. However, they gain high kinetic energy in the channel region due to the high electric field and are accelerated, reaching their fastest speed near the drain region. Some of these electrons, with excessive momentum, may enter the first insulating film 4, and even enter the first gate electrode G / second counter electrode CE1 and the second gate electrode G'. In such cases, the electrical characteristics of the first transistor T1 and the second transistor T2 will fluctuate, leading to a decrease in their driving capability, among other issues.

[0033] Therefore, in this embodiment, a low-concentration region LDD (Lightly Doped Drain) is provided in the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 3' of the second transistor T2. The low-concentration region LDD is a region formed by injecting ions with a lower concentration than the impurity concentration in the source and drain regions, to a depth shallower than the depth of the source and drain regions, between the channel region and the source region and between the channel region and the drain region. When electrons, which are carriers that have gained high kinetic energy and been accelerated, reach the low-concentration region LDD, which is the low-concentration part of the impurity, just before the drain, they decelerate and their momentum weakens, which can prevent them from entering the first gate electrode G and second counter electrode CE1 and the second gate electrode G'. Here, since an NMOS type transistor is used, the case of electrons has been explained as an example, but in a PMOS type transistor, it is necessary to have a configuration that prevents holes, which are carriers, from entering the first gate electrode G and second counter electrode CE1 and the second gate electrode G'.

[0034] When a low-concentration region LDD is provided for the purpose of electric field relaxation, equivalent functionality can be maintained even if it is provided only on the drain region side. Therefore, in this embodiment, as shown in Figures 2 and 3, the first semiconductor layer 3 provided on the first transistor T1 is composed of a first channel region 3JD1, a first source region 3ND2, a first drain region 3ND1, and a first low-concentration region 3LD1 provided between the first drain region 3ND1 and the first channel region 3JD1, but it is not limited to this. The first low-concentration region 3LD1 contains impurities, and its impurity concentration is lower than that of the first source region 3ND2 and the first drain region 3ND1, respectively. Also, the first gate electrode G and the second counter electrode CE1 do not overlap with the first low-concentration region 3LD1 in a plan view.

[0035] In this embodiment, as shown in Figures 2 and 3, the second transistor T2 is a double-gate type transistor. Therefore, as an example, the second semiconductor layer 3' provided in the second transistor T2 is composed of a second channel region 3JD1'·3JD2', a second source region 3ND1' containing a high concentration of impurities, a high-concentration region 3ND2' containing a high concentration of impurities, a second drain region 3ND3' containing a high concentration of impurities, and a second low-concentration region 3LD1'·3LD2'·3LD3'·3LD4' containing a low concentration of impurities. However, the embodiment is not limited to this example. The second low-concentration region 3LD1' is formed between the second channel region 3JD1' and the second source region 3ND1', the second low-concentration region 3LD2' is formed between the second channel region 3JD1' and the high-concentration region 3ND2', the second low-concentration region 3LD3' is formed between the high-concentration region 3ND2' and the second channel region 3JD2', and the second low-concentration region 3LD4' is formed between the second channel region 3JD2' and the second drain region 3ND3'.

[0036] Figure 4 shows some of the steps in the manufacturing method of the drive circuit board 1 of Embodiment 1. Figure 5 shows some other steps in the manufacturing method of the drive circuit board 1 of Embodiment 1. Figure 6 shows yet another set of steps in the manufacturing method of the drive circuit board 1 of Embodiment 1.

[0037] The first step in forming the island-shaped first semiconductor layer 3 included in the first transistor T1, which is equipped with a holding capacitor Cs including a first counter electrode CE2 and a second counter electrode CE1, is steps S1 and S2 shown in Figure 4. In step S1, first, an amorphous silicon layer is formed on the barrier layer 2, then annealing (heat treatment) for dehydrogenation is performed, for example, at 450°C, and then processing is performed with an excimer laser at a relatively low temperature to obtain a polysilicon film PS formed at a low temperature. In step S2, the polysilicon film PS is etched using a resist film to obtain an island-shaped first semiconductor layer 3 composed of impurity-free first channel regions 3JD1.

[0038] The second step, which involves forming a first insulating layer 4 on the first semiconductor layer 3, is step S3 shown in Figure 4. In step S3, the first insulating layer 4 can be obtained by performing annealing (heat treatment) after film formation.

[0039] The third step, step S4 shown in Figure 4, is to form a resist film RM of a predetermined shape on the first insulating layer 4, and then, using the resist film RM as a mask, to inject impurities into a part of the first semiconductor layer 3, thereby forming a first channel region 3JD1 and a first source region 3ND2 and a first drain region 3ND1 with a higher impurity concentration than the first channel region 3JD1. In other words, in step S4, by performing HDP injection of high-concentration impurities using the resist film RM as a mask, a first channel region 3JD1 that is protected by the resist film RM and does not contain impurities, and a first source region 3ND2 and a first drain region 3ND1 that have a higher impurity concentration than the first channel region 3JD1 and contain high-concentration impurities.

[0040] The step for removing the resist film RM is step S5 shown in Figure 4. In step S5 shown in Figure 4, the resist film RM can be removed using a solution that peels off the resist film RM.

[0041] After removing the resist film RM, the fourth step, step S6 shown in Figure 5, is to form a first gate electrode G and second counter electrode CE1 on the first insulating layer 4 so that, in a plan view, it overlaps with the first channel region 3JD1 and a part of the first source region 3ND2, which is the first counter electrode CE2. In this embodiment, in step S6, the first gate electrode G and second counter electrode CE1 is provided in such a way that, in a plan view, it does not overlap with a part of the first drain region 3ND1 side of the first channel region 3JD1. However, the invention is not limited to this, and the first gate electrode G and second counter electrode CE1 may be formed so that, in a plan view, it overlaps with the entire first channel region 3JD1.

[0042] The fifth step, which involves forming a first drain electrode D electrically connected to a first drain region 3ND1 and a first source electrode S electrically connected to a first source region 3ND2, is step S9 shown in Figure 5 and step S10 shown in Figure 6. In step S9, a contact hole CON4 that exposes the first drain region 3ND1 and a contact hole CON5 that exposes the first source region 3ND2 are formed. In step S10, the first drain electrode D is electrically connected to the first drain region 3ND1 via the contact hole CON4 that exposes the first drain region 3ND1, and the first source electrode S is electrically connected to the first source region 3ND2 via the contact hole CON5 that exposes the first source region 3ND2.

[0043] According to the manufacturing method of the drive circuit board 1, which includes the first to fifth steps described above, a drive circuit board 1 can be manufactured in which each of a plurality of unit drive circuits DRUs includes a first transistor T1 that is equipped with a first gate electrode G and a second counter electrode CE1. Since the first gate electrode G and second counter electrode CE1 are equipped, there is no need to separately form a contact hole for electrically connecting the first gate electrode G and the second counter electrode CE1, and the area of ​​the first transistor T1 can be reduced by not forming a contact hole. Therefore, the unit drive circuits DRUs in the drive circuit board 1 can be made highly detailed.

[0044] In this embodiment, in the fourth step described above, that is, step S6 shown in Figure 5, as described above, the first gate electrode G and second counter electrode CE1 are formed in a plan view such that they do not overlap with a part of the first drain region 3ND1 side of the first channel region 3JD1. Subsequently, between the fourth step (step S6 shown in Figure 5) and the fifth step (step S9 shown in Figure 5 and step S10 shown in Figure 6), a step is performed to form the first low-concentration region 3LD1. The step of forming the first low-concentration region 3LD1 is step S7 shown in Figure 5. In step S7, using the first gate electrode G and second counter electrode CE1 as a mask, impurities are injected into a part of the first semiconductor layer 3 to form the first low-concentration region 3LD1, which has a lower impurity concentration than the first source region 3ND2 and the first drain region 3ND1, respectively, and a higher impurity concentration than the first channel region 3JD1. In other words, in step S7, by performing LDP injection of low-concentration impurities using the first gate electrode G and second counter electrode CE1 as a mask, a first low-concentration region 3LD1 can be formed in a part of the first channel region 3JD1 that is not protected by the first gate electrode G and second counter electrode CE1. Note that the first source region 3ND2 and the first drain region 3ND1 already contain high concentrations of impurities, so even if LDP injection of low-concentration impurities is performed, they remain regions containing high concentrations of impurities. When electrons, which are carriers accelerated by gaining high kinetic energy, reach the first low-concentration region 3LD1, which is the low-concentration part of the impurities, just before the drain, they decelerate and their momentum weakens, which can prevent them from entering the first gate electrode G and second counter electrode CE1.

[0045] In this embodiment, in the first step described above, i.e., steps S1 and S2 shown in Figure 4, an island-shaped second semiconductor layer composed of the second channel regions 3JD1'·3JD2' included in the second transistor T2 was formed together with the first semiconductor layer composed of the first channel region 3JD1. Then, in the second step described above, i.e., step S3 shown in Figure 4, a first insulating layer 4 was formed on the first semiconductor layer composed of the first channel region 3JD1 and the second semiconductor layer composed of the second channel regions 3JD1'·3JD2'. Then, in the third step described above, namely step S4 shown in Figure 4, the resist film RM is also formed on the first insulating layer 4 provided on the second semiconductor layer 3', and by using the resist film RM as a mask and injecting impurities into a part of the second semiconductor layer 3', the second channel region 3JD1'·3JD2' and the second source region 3ND1' and second drain region 3ND3', which have higher impurity concentrations than the second channel region 3JD1'·3JD2', are formed. Furthermore, in the fourth step described above, namely step S6 shown in Figure 5, the second gate electrode G' is formed on the first insulating layer 4 so as to overlap with the second channel region 3JD1'·3JD2' in a plan view. Then, in the fifth step described above, namely step S9 shown in Figure 5 and step S10 shown in Figure 6, the second drain electrode D' electrically connected to the second drain region 3ND3' and the first gate electrode G and second counter electrode CE1, the second source electrode S' electrically connected to the second source region 3ND1', the first drain electrode D, and the first source electrode S were formed as the same layer and of the same material. As a result, a drive circuit board 1 equipped with multiple unit drive circuits DRU including the first transistor T1 and the second transistor T2 can be realized.

[0046] Step S8 shown in Figure 5 is a step in which the second insulating layer 5 is formed. After film formation, the second insulating layer 5 can be obtained by performing activation annealing (heat treatment). In the fifth step described above, namely step S9 shown in Figure 5 and step S10 shown in Figure 6, contact holes CON2~CON5 are formed in the first insulating layer 4 and the second insulating layer 5 so that the first source region 3ND2, the first drain region 3ND1, the second source region 3ND1', and the second drain region 3ND3' are exposed. Then, the first source electrode S, the first drain electrode D, the second source electrode D', and the second drain electrode D' are formed, which are electrically connected to the first source region 3ND2, the first drain region 3ND1, the second source region 3ND1', and the second drain region 3ND3', respectively, via the contact holes CON2~CON5. In the process of forming the first source electrode S, the first drain electrode D, the second source electrode D', and the second drain electrode D', the first source electrode S, the first drain electrode D, the second source electrode D', and the second drain electrode D' can each be formed into a predetermined shape by etching using a resist film. Step S11 shown in Figure 6 is the process of forming the passivation film 6.

[0047] Figure 7 is a plan view of the drive circuit board 50 of Comparative Example 1, showing its schematic configuration. Note that the barrier layer 2, first insulating layer 4, second insulating layer 5, and passivation film 6 are not shown in Figure 7. Figure 8 is a cross-sectional view showing the schematic configuration of the drive circuit board 50 of Comparative Example 1. Note that Figure 8 is a cross-sectional view of the drive circuit board 50 cut along the lines X3-X3' and X4-X4' shown in Figure 7. Figure 9 shows the difference between the order of some steps in the manufacturing method of the drive circuit board 1 of Embodiment 1 and the order of some steps in the manufacturing method of the drive circuit board 50 of Comparative Example 1.

[0048] As shown in Figures 7 and 8, in the case of the first transistor T1' provided on the drive circuit board 50 of Comparative Example 1, the gate electrode G and the second counter electrode CE1 are provided on different layers. Therefore, in the drive circuit board 50, it is necessary to provide contact holes CON8 and CON9 in the second insulating layer 5 for electrically connecting the gate electrode G and the second counter electrode CE1. As described above, the formation area of ​​the first transistor T1' provided on the drive circuit board 50 of Comparative Example 1, which is provided with contact holes CON8 and CON9 that were unnecessary in the drive circuit board 1 of Embodiment 1, becomes larger than the formation area of ​​the first transistor T1 provided on the drive circuit board 1 of Embodiment 1. Therefore, in the drive circuit board 50 of Comparative Example 1, it is difficult to increase the resolution of the unit drive circuit DRU compared to the drive circuit board 1 of Embodiment 1. In addition, in the case of the first transistor T1' provided on the drive circuit board 50 of Comparative Example 1, a first low-concentration region 3LD1 is provided on the drain side, and a first low-concentration region 3LD2 is also provided on the source side.

[0049] As shown in Figure 9, in the manufacturing method of the drive circuit board 50 of Comparative Example 1, the steps of forming the first gate electrode G (step S54), forming a low-concentration region 3LD by performing low-concentration impurity injection LDP into the semiconductor layer 3'' using the first gate electrode G as a mask (step S55), and forming the first source region 3ND2 and the first drain region 3ND1 by performing high-concentration impurity injection HDP into the semiconductor layer 3'' using the resist film RM' as a mask (step S56) are performed in this order. On the other hand, in the manufacturing method of the drive circuit board 1 of Embodiment 1, step S4 shown in Figure 4, which corresponds to step S56, is performed first, followed by steps S6 shown in Figure 5, which corresponds to step S54, and steps S7 shown in Figure 5, which corresponds to step S55, in this order.

[0050] As described above, the manufacturing method of the drive circuit board 1 of Embodiment 1 makes it possible to realize a manufacturing method of the drive circuit board 1 that can increase the resolution of the unit drive circuit DRU by only changing some of the process order in the manufacturing method of the drive circuit board 50 of Comparative Example 1.

[0051] [Embodiment 2] Figure 10 is a plan view of the drive circuit board 10 of Embodiment 2, showing its schematic configuration. Note that the barrier layer 2, first insulating layer 4, second insulating layer 5, and passivation film 6 are not shown in Figure 10. Figure 11 is a cross-sectional view showing the schematic configuration of the drive circuit board 10 of Embodiment 2. Note that Figure 11 is a cross-sectional view of the drive circuit board 10 cut along the lines X5-X5' and X6-X6' shown in Figure 10.

[0052] As shown in Figures 10 and 11, each of the multiple unit drive circuits DRU provided on the drive circuit board 10 of Embodiment 2 includes a first transistor T1 and a second transistor T2' which is a single-gate type transistor. The configuration of the second transistor T2' differs from that of the second transistor T2 in Embodiment 1 described above. The second drain electrode D' provided on the second transistor T2' is electrically connected to the second drain region 3ND2' via a contact hole CON10 provided in the first insulating layer 4, and the second drain electrode D' is formed on the same layer as the first gate electrode G and second counter electrode CE1 and is made of the same material as the first gate electrode G and second counter electrode CE1.

[0053] In the case of the drive circuit board 1 shown in Figure 2 and the drive circuit board 50 of Comparative Example 1 shown in Figure 7, described in Embodiment 1 above, the second drain electrode D' and the first gate electrode G and second counter electrode CE1 are formed as different layers. Therefore, it was necessary to provide a contact hole CON1 in the second insulating layer 5 for electrically connecting the second drain electrode D' and the first gate electrode G and second counter electrode CE1. On the other hand, according to the drive circuit board 10 of Embodiment 2, the second drain electrode D' is formed as the same layer as the first gate electrode G and second counter electrode CE1 and is made of the same material as the first gate electrode G and second counter electrode CE1. Therefore, it is not necessary to separately provide a contact hole for electrically connecting the second drain electrode D' and the first gate electrode G and second counter electrode CE1, and the formation area of ​​the first transistor T1 and the second transistor T2' in the unit drive circuit DRU of the drive circuit board 10 can be reduced. Therefore, a drive circuit board 10 that can achieve high resolution in the unit drive circuit DRU can be realized.

[0054] As shown in Figures 10 and 11, the second semiconductor layer 3''' provided in the second transistor T2' includes a second low-concentration region 3LD1' provided between the second drain region 3ND2' and the second channel region 3JD1'. The second low-concentration region 3LD1' contains impurities, and its impurity concentration is lower than that of the second source region 3ND1' and the second drain region 3ND2', respectively. The second gate electrode G' and the second drain electrode D' do not overlap with the second low-concentration region 3LD1' in a plan view. When a low-concentration region LDD is provided to reduce leakage current when the second transistor T2' is off, equivalent functionality can be maintained even if the low-concentration region LDD is provided only on the drain side. Therefore, in this embodiment, the second low-concentration region 3LD1' is provided only on the drain side of the second semiconductor layer 3''' provided in the second transistor T2'. Therefore, without increasing the formation area of ​​the second transistor T2', electrons, which are carriers accelerated by gaining high kinetic energy, can be slowed down when they reach the second low-concentration region 3LD1', which is a low-concentration area of ​​impurities, just before the drain, and their momentum weakens, thus preventing them from entering the second gate electrode G'.

[0055] Figure 12 shows some of the steps in the manufacturing method of the drive circuit board 10 of Embodiment 2. Figure 13 shows some other steps in the manufacturing method of the drive circuit board 10 of Embodiment 2. Figure 14 shows yet another set of steps in the manufacturing method of the drive circuit board 10 of Embodiment 2.

[0056] Steps S21, S22, S23, and S24 shown in Figure 12 are the same as steps S1, S2, S3, and S4 shown in Figure 4 in Embodiment 1 described above, so their explanation is omitted here.

[0057] In this embodiment, in the first step described above, i.e., steps S21 and S22 shown in Figure 12, an island-shaped second semiconductor layer composed of a second channel region 3JD1' included in the second transistor T2 was formed together with a first semiconductor layer composed of a first channel region 3JD1. Then, in the second step described above, i.e., step S23 shown in Figure 12, a first insulating layer 4 was formed on the first semiconductor layer composed of the first channel region 3JD1 and the second semiconductor layer composed of the second channel region 3JD1'. Then, in the third step described above, i.e., step S24 shown in Figure 12, a resist film RM was also formed on the first insulating layer 4 provided on the second semiconductor layer 3', and by using the resist film RM as a mask and injecting impurities into a part of the second semiconductor layer 3', a second channel region 3JD1' and a second source region 3ND1' and a second drain region 3ND2' with a higher impurity concentration than the second channel region 3JD1' were formed. Furthermore, in the step of forming the contact hole CON10, which is performed between the third step and the fourth step described above, i.e., step S25 shown in Figure 12, the contact hole CON10 was formed in the first insulating layer 4 so as to overlap with the second drain region 3ND2' in a plan view. Then, in the fourth step described above, i.e., step S26 shown in Figure 12, the second gate electrode G' was formed on the first insulating layer 4 as part of the same layer as the first gate electrode G and second counter electrode CE1, using the same material as the first gate electrode G and second counter electrode CE1, so as to overlap with the second channel region 3JD1' in a plan view, and the second drain electrode D' was formed, electrically connected to the second drain region 3ND2' via the contact hole CON10. Then, in the fifth step described above, namely steps S29 and S30 shown in Figure 12, the second source electrode S' electrically connected to the second source region 3ND1', the first drain electrode D electrically connected to the first drain region 3ND1, and the first source electrode S electrically connected to the first source region 3ND2 were formed as the same layer and from the same material.

[0058] In this embodiment, in the step of forming the first low-concentration region 3LD1, which is performed between the fourth step and the fifth step described above, i.e., in step S27 shown in Figure 13, impurities are injected into a part of the second semiconductor layer 3'''' using the second gate electrode G' and the second drain electrode D' as masks, thereby forming a second low-concentration region 3LD1' which has a lower impurity concentration than the second source region 3ND1' and the second drain region 3ND2', respectively, and a higher impurity concentration than the second channel region 3JD1'. In other words, in step S27, by performing injection LDP of low-concentration impurities using the second gate electrode G' and the second drain electrode D' as masks, the second low-concentration region 3LD1' can be formed in a part of the second channel region 3JD1' that is not protected by the second gate electrode G' and the second drain electrode D'. Note that the second source region 3ND1' and the second drain region 3ND2' already contain high concentrations of impurities, so even if LDP is performed to inject low concentrations of impurities, they remain regions containing high concentrations of impurities. Step S28, shown in Figure 13, is the process of forming the second insulating layer 5. After film formation, the second insulating layer 5 can be obtained by performing activation annealing (heat treatment). Step S31, shown in Figure 14, is the process of forming the passivation film 6.

[0059] [Embodiment 3] Figure 15 is a plan view showing the schematic configuration of the drive circuit board 20 of Embodiment 3. Note that the barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in Figure 15. Figure 16 is a cross-sectional view showing the schematic configuration of the drive circuit board 20 of Embodiment 3. Note that Figure 16 is a cross-sectional view of the drive circuit board 20 cut along the lines X6-X6' and X7-X7' shown in Figure 15.

[0060] In this embodiment, the drive circuit board 20 shown in Figures 15 and 16 includes a first transistor T1'' which is a double-gate transistor and a second transistor T2 which is a double-gate transistor, which distinguishes it from the drive circuit board 1 of Embodiment 1 shown in Figures 2 and 3, which includes a first transistor T1 which is a single-gate transistor and a second transistor T2 which is a double-gate transistor, and the drive circuit board 10 of Embodiment 2 shown in Figures 10 and 11, which includes a first transistor T1 which is a single-gate transistor and a second transistor T2' which is a single-gate transistor.

[0061] As shown in Figures 15 and 16, the first semiconductor layer 3 provided on the drive circuit board 20 consists of a first source region 3ND2, a first drain region 3ND1, two first channel regions 3JD1 and 3JD2 spaced apart from each other between the first source region 3ND2 and the first drain region 3ND1, a first low-concentration region 3LD1 provided between the first channel region 3JD1 that is closer to the first drain region 3ND1 and the first drain region 3ND1, and a first low-concentration region 3LD2 provided between the first channel region 3JD1 and the first channel region 3JD2. The impurity concentration of the first low-concentration regions 3LD1 and 3LD2 is lower than that of the first drain region 3ND1. The first gate electrode G, which also serves as the second counter electrode CE1, does not overlap with the first low-concentration regions 3LD1 and 3LD2 in a plan view. Furthermore, as shown in Figure 15, the second drain electrode D' only needs to be electrically connected to the second drain region 3ND3' and the first gate electrode G and second counter electrode CE1. In this embodiment, the second drain electrode D' is provided so as to be in contact with the second drain region 3ND3' via the contact hole CON3, and the first gate electrode G and second counter electrode CE1 is provided so as to be in contact with the second drain region 3ND3' via the contact holes CON1, CON4, and CON5.

[0062] The drive circuit board 20 shown in Figures 15 and 16, which includes a first double-gate transistor T1'' and a second double-gate transistor T2, can further improve current stability. The second transistor T2 provided on the drive circuit board 20 has been described above in Embodiment 1, and the manufacturing method of the drive circuit board 20 can be the same as the manufacturing method of the drive circuit board 1 described above in Embodiment 1, so a detailed explanation is omitted here. [Industrial applicability]

[0063] This disclosure can be used for a drive circuit board and a method for manufacturing a drive circuit board. [Explanation of Symbols]

[0064] 1, 10, 20 Drive circuit board 3, 3'' First semiconductor layer 3', 3''' Second semiconductor layer 4. First insulating layer 5. Second insulating layer 6 Passivation membrane 3JD1, 3JD2 First channel area 3JD1', 3JD2' Second channel region 3ND2 First Source Area 3ND1 First Drain Region 3LD1, 3LD2 1st low concentration region 3ND1' Second source area 3ND3' Second drain region 3ND2' High concentration area 3LD1'~3LD4' 2nd low concentration region T1, T1'' First transistor T2, T2' Second transistor Cs holding capacitor S First source electrode D First drain electrode G 1st gate S' Second source electrode D' Second drain electrode G' Second gate electrode CE2 First Counter Electrode CE1 Second counter electrode DRU Unit Drive Circuit CON1~CON12 Contact Holes

Claims

1. A first semiconductor layer in the shape of an island, comprising a first channel region, a first source region containing impurities, and a first drain region, A first insulating layer provided on the first semiconductor layer, In a plan view, a first gate electrode and second counter electrode are provided on the first insulating layer so as to overlap the first channel region and a part of the first source region which is the first counter electrode, A first drain electrode electrically connected to the first drain region, A first source electrode electrically connected to the first source region, The first transistor includes a holding capacitor comprising the first counter electrode and the second counter electrode, A drive circuit board comprising multiple unit drive circuits, each including the first transistor.

2. The first semiconductor layer is composed of a first channel region, a first source region, a first drain region, and a first low-concentration region provided between the first drain region and the first channel region. The first low-concentration region has a lower impurity concentration than the first drain region. The drive circuit board according to claim 1, wherein the first gate electrode and second counter electrode does not overlap with the first low-concentration region in a plan view.

3. The first semiconductor layer comprises a first source region, a first drain region, two first channel regions spaced apart from each other between the first source region and the first drain region, and a first low-concentration region provided between the two first channel regions and between the first channel region closer to the first drain region and the first drain region. The first low-concentration region has a lower impurity concentration than the first drain region. The drive circuit board according to claim 1, wherein the first gate electrode and second counter electrode does not overlap with the first low-concentration region in a plan view.

4. Each of the aforementioned plurality of unit drive circuits includes a second transistor, The aforementioned second transistor is A second semiconductor layer in the shape of an island, comprising a second channel region and a second source region and a second drain region containing the impurities, The first insulating layer provided on the second semiconductor layer, In a plan view, a second gate electrode is provided on the first insulating layer so as to overlap with the second channel region, The second drain region and the second drain electrode electrically connected to the first gate electrode and second counter electrode, A drive circuit board according to any one of claims 1 to 3, comprising a second source electrode electrically connected to the second source region.

5. The second drain electrode is electrically connected to the second drain region via a contact hole provided in the first insulating layer. The drive circuit board according to claim 4, wherein the second drain electrode is formed in the same layer as the first gate electrode and second counter electrode and is made of the same material as the first gate electrode and second counter electrode.

6. The second semiconductor layer includes a second low-concentration region provided between the second drain region and the second channel region. The second low-concentration region has a lower impurity concentration than the second drain region. The drive circuit board according to claim 5, wherein the second gate electrode and the second drain electrode do not overlap with the second low-concentration region in a plan view.

7. A first step of forming an island-shaped first semiconductor layer included in a first transistor which has a holding capacitor including a first counter electrode and a second counter electrode, A second step of forming a first insulating layer on the first semiconductor layer, A third step involves forming a resist film of a predetermined shape on the first insulating layer, and using the resist film as a mask, injecting impurities into a part of the first semiconductor layer to form a first channel region, a first source region and a first drain region having a higher impurity concentration than the first channel region. A fourth step involves removing the resist film and then forming a first gate electrode and second counter electrode on the first insulating layer such that, in a plan view, it overlaps the first channel region and a part of the first source region which is the first counter electrode. The process includes a fifth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region, A method for manufacturing a drive circuit board, comprising forming a plurality of unit drive circuits, each including the first transistor.

8. In the fourth step, in a plan view, the first gate electrode and second opposing electrode are formed so as not to overlap with a part of the first channel region on the first drain region side. The method for manufacturing a drive circuit board according to claim 7, wherein in the step of forming a first low-concentration region performed between the fourth step and the fifth step, the impurity is injected into a part of the first semiconductor layer using the first gate electrode and second counter electrode as a mask, thereby forming a first low-concentration region having a lower impurity concentration than the first source region and the first drain region, and a higher impurity concentration than the first channel region.

9. In the first step, together with the first semiconductor layer, an island-shaped second semiconductor layer is formed in the second transistor. In the second step, the first insulating layer is formed on the first semiconductor layer and the second semiconductor layer. In the third step, the resist film is also formed on the first insulating layer provided on the second semiconductor layer, and the impurities are injected into a part of the second semiconductor layer using the resist film as a mask to form a second channel region and a second source region and a second drain region having a higher impurity concentration than the second channel region. In the fourth step, a second gate electrode is formed on the first insulating layer so as to overlap with the second channel region in a plan view. In the fifth step, the second drain electrode electrically connected to the second drain region and the first gate electrode / second counter electrode, the second source electrode electrically connected to the second source region, the first drain electrode, and the first source electrode are formed as the same layer and of the same material. A method for manufacturing a drive circuit board according to claim 7 or 8, wherein a plurality of unit drive circuits, each including the first transistor and the second transistor, are formed.

10. In the first step, together with the first semiconductor layer, an island-shaped second semiconductor layer is formed in the second transistor. In the second step, the first insulating layer is formed on the first semiconductor layer and the second semiconductor layer. In the third step, the resist film is also formed on the first insulating layer provided on the second semiconductor layer, and the impurities are injected into a part of the second semiconductor layer using the resist film as a mask to form a second channel region and a second source region and a second drain region having a higher impurity concentration than the second channel region. In the step of forming a contact hole performed between the third step and the fourth step, the contact hole is formed in the first insulating layer so as to overlap with the second drain region in a plan view. In the fourth step, the second gate electrode is formed on the first insulating layer as part of the same layer as the first gate electrode and second counter electrode, using the same material as the first gate electrode and second counter electrode, so as to overlap with the second channel region in a plan view, and a second drain electrode is formed which is electrically connected to the second drain region via the contact hole. In the fifth step, the second source electrode electrically connected to the second source region, the first drain electrode, and the first source electrode are formed as the same layer and from the same material. A method for manufacturing a drive circuit board according to claim 8, wherein a plurality of unit drive circuits, each including the first transistor and the second transistor, are formed.

11. A method for manufacturing a drive circuit board according to claim 10, wherein in the step of forming the first low-concentration region performed between the fourth step and the fifth step, the impurities are injected into a part of the second semiconductor layer using the second gate electrode and the second drain electrode as a mask to form a second low-concentration region having a lower impurity concentration than the second source region and the second drain region, and a higher impurity concentration than the second channel region.

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