Semiconductor integrated circuits

Abstract

To provide a semiconductor integrated circuit that can suppress the increase in circuit area. [Solution] The semiconductor integrated circuit includes a test circuit for testing the operation of the semiconductor integrated circuit, a TEG (Test Element Group) circuit that shares at least a portion of the circuit of the test circuit for characterizing the semiconductor integrated circuit or manufacturing process, and a switching circuit that switches between a first operating mode for operating the test circuit in response to a first input signal and a second operating mode for operating the TEG circuit in response to a second input signal.

Description

Technical Field

[0006] , ,

[0003]

[0001] The present invention relates to a semiconductor integrated circuit.

Background Art

[0002] In order to evaluate the characteristics of a semiconductor integrated circuit or a manufacturing process, a TEG (Test Element Group) can be provided on a semiconductor wafer. When the TEG is provided in the chip region of the semiconductor wafer, it is performed to suppress an increase in the circuit area. For example, the electrical characteristic evaluation circuit of the semiconductor device of Patent Document 1 suppresses an increase in the circuit area by laminating each of a plurality of TEGs.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in Patent Document 1, when a test circuit for further testing the operation of the semiconductor device is provided in addition to the TEG circuit, there is a possibility that the circuit area increases.

[0005] Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of suppressing an increase in the circuit area.

Means for Solving the Problems

[0006] One disclosure of this specification provides a semiconductor integrated circuit comprising: a test circuit for testing the operation of the semiconductor integrated circuit; a TEG (Test Element Group) circuit sharing at least a portion of the circuit of the test circuit for characterizing the semiconductor integrated circuit or a manufacturing process; and a switching circuit for switching between a first operating mode for operating the test circuit in response to a first input signal and a second operating mode for operating the TEG circuit in response to a second input signal. [Effects of the Invention]

[0007] According to the present invention, it is possible to realize a semiconductor integrated circuit that can suppress an increase in circuit area. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram of a semiconductor integrated circuit according to the first embodiment. [Figure 2] This figure shows an example of a TEG according to the first embodiment. [Figure 3] This is a circuit diagram of a semiconductor integrated circuit according to the second embodiment. [Figure 4] This figure shows an example of a TEG according to the second embodiment. [Figure 5] This is a circuit diagram of a semiconductor integrated circuit according to the third embodiment. [Figure 6] This figure shows an example of a TEG according to the third embodiment. [Figure 7] This is a block diagram of the equipment according to the fourth embodiment. [Figure 8] This is a block diagram of the equipment according to the fifth embodiment. [Modes for carrying out the invention]

[0009] [First Embodiment] Figure 1 is a circuit diagram of the semiconductor integrated circuit 100 according to this embodiment. In a semiconductor wafer having a plurality of chip regions and dicing regions for separating each of the plurality of chip regions, the semiconductor integrated circuit 100 is formed in the chip regions (semiconductor chips).

[0010] When forming the semiconductor integrated circuit 100, the characteristics of the semiconductor integrated circuit 100 or the manufacturing process are evaluated, and the operation of the semiconductor integrated circuit 100 is tested. The semiconductor integrated circuit 100 includes a test circuit for testing the operation of the semiconductor integrated circuit 100, and a TEG circuit for evaluating the characteristics of the semiconductor integrated circuit 100 or the manufacturing process. The semiconductor integrated circuit 100 further includes a circuit under test (not shown) whose operation of the semiconductor integrated circuit 100 is to be tested.

[0011] The test circuit includes signal line L1, control line L3, multiplexer 10, first flip-flop 20, first multiplexer 30A, second multiplexer 30B, first transmission line 40, and second flip-flop 60.

[0012] The TEG circuit includes signal line L2, control line L3, multiplexer 10, first flip-flop 20, first multiplexer 30A, second multiplexer 30B, second transmission line 50, and second flip-flop 60.

[0013] Note that multiplexer 10, first multiplexer 30A, and second multiplexer 30B are examples of switching circuits. First flip-flop 20 is an example of a first memory element, and second flip-flop 60 is an example of a second memory element.

[0014] The signal line L1 is formed from a conductive material and connected to a first external terminal (not shown) by wire bonding. The signal line L1 is connected via the first external terminal to an external device installed outside the semiconductor integrated circuit 100 and transmits test data (first input signal) from the external device. The test data is data used to test the operation of the circuit under test.

[0015] The signal line L2 is formed of a conductive member and is connected to a second external terminal (not shown) by wire bonding. The signal line L2 is connected to an external device via the second external terminal and transmits TEG data (a second input signal) from the external device. The TEG data is data for evaluating the characteristics of the semiconductor integrated circuit 100 or the manufacturing process.

[0016] The control line L3 is formed of a conductive member and is connected to a third external terminal (not shown) by wire bonding. The control line L3 is connected to an external device via the third external terminal and transmits a switching signal from the external device. The switching signal is a signal for switching between a test mode (a first operation mode) and a TEG mode (a second operation mode). The test mode is a mode for operating a test circuit according to test data. The TEG mode is a mode for operating a TEG circuit according to TEG data.

[0017] The multiplexer 10 receives test data from the signal line L1, receives TEG data from the signal line L2, and receives a switching signal from the control line L3. The multiplexer 10 outputs the test data from the signal line L1 or the TEG data from the signal line L2 to the first flip-flop 20 according to the switching signal.

[0018] The first flip-flop 20 holds the test data or TEG data from the multiplexer 10. The first flip-flop 20 outputs the held test data or TEG data to the first multiplexer 30A.

[0019] A first transmission line 40 and a second transmission line 50 are provided in parallel between the first multiplexer 30A and the second multiplexer 30B. A TEG 51 is disposed on the second transmission line 50. The TEG 51 is a pattern used for evaluating the characteristics of the semiconductor integrated circuit 100 or the manufacturing process.

[0020] The first multiplexer 30A receives test data or TEG data from the first flip-flop 20. The first multiplexer 30A receives a switching signal from control line L3. In response to the switching signal, the first multiplexer 30A outputs the test data from the first flip-flop 20 to the first transmission line 40 and outputs the TEG data from the first flip-flop 20 to the second transmission line 50.

[0021] The second multiplexer 30B receives test data from the first transmission line 40 or TEG data from the second transmission line 50. The second multiplexer 30B receives a switching signal from control line L3. The second multiplexer 30B outputs the test data from the first transmission line 40 or the TEG data from the second transmission line 50 to the second flip-flop 60 according to the switching signal.

[0022] The second flip-flop 60 holds test data from the first transmission line 40 or TEG data from the second transmission line 50. The second flip-flop 60 outputs the test data to the circuit under test and the TEG data to an external device.

[0023] The operation of the semiconductor integrated circuit 100 in test mode will be described. In test mode, the multiplexer 10 outputs test data from signal line L1 to the first flip-flop 20. The first flip-flop 20 holds the test data from the multiplexer 10. The first flip-flop 20 outputs the held test data to the first multiplexer 30A. The first multiplexer 30A outputs the test data from the first flip-flop 20 to the first transmission line 40, and the second multiplexer 30B outputs the test data from the first transmission line 40 to the second flip-flop 60. The second flip-flop 60 holds the test data from the second multiplexer 30B. For example, the first flip-flop 20 and the second flip-flop 60 output test data to the circuit under test. An external device verifies the operation of the circuit under test based on the output signal from the circuit under test.

[0024] The operation of the semiconductor integrated circuit 100 in TEG mode is described below. In TEG mode, the multiplexer 10 outputs TEG data from signal line L2 to the first flip-flop 20. The first flip-flop 20 holds the TEG data from the multiplexer 10. The first flip-flop 20 outputs the held TEG data to the first multiplexer 30A. The first multiplexer 30A outputs the TEG data from the first flip-flop 20 to the second transmission line 50, and the second multiplexer 30B outputs the TEG data from the second transmission line 50 to the second flip-flop 60. The second flip-flop 60 holds the TEG data from the second transmission line 50. The second flip-flop 60 outputs the held TEG data to an external device. The external device evaluates the characteristics of the semiconductor integrated circuit 100 or the manufacturing process based on the TEG data from the second flip-flop 60.

[0025] As described above, according to the semiconductor integrated circuit 100, the TEG circuit shares at least a portion of the test circuit. Specifically, the TEG circuit shares the first flip-flop 20 and the second flip-flop 60 of the test circuit. As a result, the semiconductor integrated circuit 100 can suppress an increase in circuit area compared to the conventional method of configuring the TEG circuit using dedicated flip-flops.

[0026] Furthermore, the semiconductor integrated circuit 100 can share power supplies and power supply pads in both the test circuit and the TEG circuit. This allows the semiconductor integrated circuit 100 to suppress an increase in circuit area compared to the conventional method of providing separate power supplies and power supply pads for each test circuit and TEG circuit. Also, compared to the conventional method of stacking multiple TEGs to suppress an increase in circuit area, the semiconductor integrated circuit 100 can reduce the difficulty of forming the TEG circuit.

[0027] Figures 2(a) to 2(d) show examples of TEG51 according to this embodiment. Figure 2(a) shows wiring 511, and Figure 2(b) shows wiring 512 which is thinner than wiring 511. Figure 2(c) shows a pattern in which wiring 513 and wiring 514 are electrically connected via one via 515, and Figure 2(d) shows a pattern in which wiring 513 and wiring 514 are electrically connected via two vias 515. The characteristics of the manufacturing process can be evaluated by using the patterns in Figures 2(a) to 2(d) as TEG51.

[0028] One or more TEGs 51 may be arranged in the TEG circuit. When multiple TEGs 51 are arranged, multiple transmission lines for the TEGs are provided between the first multiplexer 30A and the second multiplexer 30B. For example, when a third transmission line is provided in parallel with the second transmission line 50, wiring 511 may be arranged in the second transmission line 50 and wiring 512 may be arranged in the third transmission line. Thus, each of the multiple TEGs 51 may be wiring 511, 512 of different thicknesses. Also, each of the multiple TEGs 51 may be vias 515 of different numbers, as shown in Figures 2(c) and (d), or vias of different shapes (not shown).

[0029] Since the TEG51 is placed in the chip region rather than the dicing region of the semiconductor wafer, the semiconductor integrated circuit 100 can suppress film peeling during dicing. Furthermore, compared to the case where the TEG51 is placed in the dicing region, the semiconductor integrated circuit 100 can have a greater degree of freedom in placing the TEG51.

[0030] [Second Embodiment] Figure 3 is a circuit diagram of the semiconductor integrated circuit 200 according to this embodiment. The semiconductor integrated circuit 200 differs from the semiconductor integrated circuit 100 according to the first embodiment in that it comprises a plurality of circuit blocks 201. In this embodiment, the same reference numerals are used for the same components as in the semiconductor integrated circuit 100 according to the first embodiment, and their detailed descriptions are omitted.

[0031] The semiconductor integrated circuit 200 includes signal lines L1 and L2, control line L3, CLK signal line L4, multiplexer 10, first flip-flop 20, multiple circuit blocks 201, and third flip-flop (third memory element) 70.

[0032] Each of the multiple circuit blocks 201 includes a test circuit and a TEG circuit. The test circuit includes a control line L3, a CLK signal line L4, a first multiplexer 30A, a second multiplexer 30B, a first transmission line 40, and a second flip-flop 60. The TEG circuit includes a control line L3, a CLK signal line L4, a first multiplexer 30A, a second multiplexer 30B, a second transmission line 50, and a second flip-flop 60.

[0033] Multiple circuit blocks 201 include the first to the Nth circuit blocks 201, where N is an integer greater than or equal to 2. Each of the first to the Nth circuit blocks 201 is connected in series. Specifically, the second circuit block 201 is connected to the first circuit block 201, the third circuit block 201 is connected to the second circuit block 201, and the Nth circuit block 201 is connected to the (N-1)th circuit block 201.

[0034] More specifically, the first multiplexer 30A of the second circuit block 201 is connected to the second flip-flop 60 of the first circuit block 201. The first multiplexer 30A of the third circuit block 201 is connected to the second flip-flop 60 of the second circuit block 201. The first multiplexer 30A of the Nth circuit block 201 is connected to the second flip-flop 60 of the N-1th circuit block 201. The second flip-flop 60 of the Nth circuit block 201 is connected to the third flip-flop 70. The third flip-flop 70 holds the test data or TEG data output from the final stage circuit block (the Nth circuit block) 201 among the multiple circuit blocks 201. The third flip-flop 70 is connected to an external device and outputs the test data or TEG data from the Nth circuit block 201 to the external device. The first multiplexer 30A of the first circuit block 201 is connected to the first flip-flop 20. The first flip-flop 20, the second flip-flop 60 of the first to Nth circuit blocks 201, and the third flip-flop 70 are connected to the CLK signal line L4 and hold test data or TEG data in response to the CLK signal from the CLK signal line L4.

[0035] This section describes the operation of the semiconductor integrated circuit 200 in test mode. In test mode, multiple flip-flops in the semiconductor integrated circuit 200 are connected in series to form a shift register (scan chain). Specifically, the first flip-flop 20, the second flip-flops 60 of the first to the Nth circuit blocks 201, and the third flip-flop 70 are connected in series to form a shift register. The formation of a shift register is one of the methods used in DFT (Design For Testability). By forming a shift register, test data can be efficiently set in the circuit under test.

[0036] In test mode, the multiplexer 10 outputs test data from signal line L1 to the first flip-flop 20. The first flip-flop 20 holds the test data from the multiplexer 10 according to the CLK signal from CLK signal line L4. The first flip-flop 20 outputs the held test data to the first circuit block 201.

[0037] In the first circuit block 201, the first multiplexer 30A outputs test data from the first flip-flop 20 to the first transmission line 40, and the second multiplexer 30B outputs test data from the first transmission line 40 to the second flip-flop 60. The second flip-flop 60 holds the test data from the second multiplexer 30B in response to the CLK signal and outputs the held test data to the second circuit block 201.

[0038] In the second circuit block 201, the first multiplexer 30A outputs test data from the second flip-flop 60 of the first circuit block 201 to the first transmission line 40. The second multiplexer 30B outputs test data from the first transmission line 40 to the second flip-flop 60. In the second circuit block 201, the second flip-flop 60 holds the test data from the first transmission line 40 in response to the CLK signal and outputs the held test data to the third circuit block 201. The third circuit block 201 to the Nth circuit block 201 operate in the same manner as the first and second circuit blocks 201.

[0039] In this way, the first flip-flop 20, the second flip-flops 60 and 3rd flip-flops 70 of the first to Nth circuit blocks 201 sequentially shift the test data in response to the CLK signal. Each flip-flop holds its own test data. For example, each flip-flop outputs the test data to the circuit under test. The external device verifies the operation of the circuit under test based on the output signal from the circuit under test.

[0040] The operation of the semiconductor integrated circuit 200 in TEG mode will be described. In TEG mode, the first flip-flop 20, the second flip-flop 60 of the first to the Nth circuit blocks 201, and the third flip-flop 70 form a shift register and sequentially shift the TEG data. Specifically, the multiplexer 10 outputs the TEG data from the signal line L2 to the first flip-flop 20. The first flip-flop 20 holds the TEG data from the multiplexer 10 in accordance with the CLK signal and outputs the held TEG data to the first circuit block 201.

[0041] In the first circuit block 201, the first multiplexer 30A outputs the TEG data from the first flip-flop 20 to the first transmission line 40, and the second multiplexer 30B outputs the TEG data from the first transmission line 40 to the second flip-flop 60. The second flip-flop 60 holds the TEG data from the first transmission line 40 in accordance with the CLK signal and outputs the held TEG data to the second circuit block 201.

[0042] In the second circuit block 201, the first multiplexer 30A outputs the TEG data from the second flip-flop 60 of the first circuit block 201 to the first transmission line 40. The second multiplexer 30B outputs the TEG data from the first transmission line 40 to the second flip-flop 60. In the second circuit block 201, the second flip-flop 60 holds the TEG data from the first transmission line 40 in accordance with the CLK signal and outputs the held TEG data to the third circuit block 201. The third circuit block 201 to the (N-1)th circuit block 201 operate in the same manner as the first and second circuit blocks 201.

[0043] In this way, the first flip-flop 20 and the second flip-flops 60 of the first to N-1 circuit blocks 201 sequentially shift the TEG data in response to the CLK signal, and each holds the TEG data.

[0044] Next, in the first to Nth circuit blocks 201, TEG data is transmitted to the second transmission line 50 in order to evaluate the characteristics of the TEG 51. Specifically, in the first circuit block 201, the first multiplexer 30A outputs the TEG data from the first flip-flop 20 to the second transmission line 50, and the second multiplexer 30B outputs the TEG data from the second transmission line 50 to the second flip-flop 60. In the second circuit block 201, the first multiplexer 30A outputs the TEG data from the second flip-flop 60 of the first circuit block 201 to the second transmission line 50. The second multiplexer 30B outputs the TEG data from the second transmission line 50 to the second flip-flop 60. The third to Nth circuit blocks 201 operate similarly.

[0045] Next, in the first to the Nth circuit blocks 201, the TEG data from the second multiplexer 30B is stored in the second flip-flop 60. Specifically, in the first circuit block 201, the second flip-flop 60 stores the TEG data from the second multiplexer 30B in response to the CLK signal. In the second circuit block 201, the second flip-flop 60 stores the TEG data from the second multiplexer 30B in response to the CLK signal. The same operation is performed for the third to the Nth circuit blocks 201.

[0046] Next, the first to Nth circuit blocks 201 sequentially output the TEG data held in the second flip-flop 60. Specifically, the second flip-flop 60 and the third flip-flop 70 of the first to Nth circuit blocks 201 form a shift register. The shift register sequentially transmits the TEG data from the second flip-flop 60 in response to the CLK signal and outputs the TEG data from the third flip-flop 70 to an external device. The external device evaluates the characteristics of the semiconductor integrated circuit 100 or the manufacturing process based on the TEG data of each of the first to Nth circuit blocks 201. According to the semiconductor integrated circuit 200, the above characteristics can be evaluated based on a plurality of TEGs 51.

[0047] Figures 4(a) and 4(b) show an example of the TEG 51 according to this embodiment. Figure 4(a) shows an inverter 516, and Figure 4(b) shows a flip-flop 517. The inverter 516 and the flip-flop 517 have logic functions and are TEGs for evaluating the digital characteristics of the semiconductor integrated circuit 200. Transition faults can be evaluated as digital characteristics of the semiconductor integrated circuit 200. For example, an external device can evaluate a transition fault by detecting that the TEG data of the flip-flop 517 is transitioning from "0" to "1" or from "1" to "0" in response to a CLK signal. Note that the TEG 51 is not limited to these, and for example, the TEG in Figure 2 may be used.

[0048] [Third Embodiment] Figure 5 is a circuit diagram of the semiconductor integrated circuit 300 according to this embodiment. The semiconductor integrated circuit 300 differs from the semiconductor integrated circuit 100 according to the first embodiment in that it does not include the second flip-flop 60 shown in Figure 1. In this embodiment, the same reference numerals are used for the same components as in the semiconductor integrated circuit 100 according to the first embodiment, and their detailed descriptions are omitted.

[0049] The semiconductor integrated circuit 300 includes a test circuit and a TEG circuit. The test circuit includes a signal line L1, a control line L3, a multiplexer 10, a first flip-flop 20, a first multiplexer 30A, a second multiplexer 30B, and a first transmission line 40. The TEG circuit includes a signal line L2, a control line L3, a multiplexer 10, a first flip-flop 20, a first multiplexer 30A, a second multiplexer 30B, and a second transmission line 50.

[0050] In TEG mode, the semiconductor integrated circuit 300 outputs TEG data from the second transmission line 50 to an external device without using a flip-flop. Compared to the case where the semiconductor integrated circuit 100 according to the first embodiment outputs TEG data from the second transmission line 50 to an external device via the second flip-flop 60, the semiconductor integrated circuit 300 is less affected by the analog characteristics of the flip-flop. As a result, the semiconductor integrated circuit 300 can accurately evaluate the analog characteristics of the TEG 51.

[0051] Figures 6(a) to 6(c) show an example of the TEG51 according to this embodiment. Figure 6(a) shows a transistor 518, Figure 6(b) shows a resistor 519, and Figure 6(c) shows a capacitor 520. By using these TEGs, the analog characteristics of the threshold voltage of the transistor 518, the value of the resistor 519, and the capacitance of the capacitor 520 can be evaluated.

[0052] [Fourth Embodiment] The semiconductor integrated circuit in the above-described embodiment is provided in a photoelectric converter, and the photoelectric converter is applicable to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 7 shows a block diagram of a digital still camera as an example of such a device.

[0053] The device 7 shown in Figure 7 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a photoelectric converter). The device 7 further includes a signal processing unit (processing unit) 708, a timing generation unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device 7. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the imaging device 700. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 700 is configured as in the above-described embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device 7. Furthermore, the device 7 may also include a display device (monitor, electronic viewfinder, etc.) for displaying information obtained by the imaging device 700. The device 7 includes at least a photoelectric converter. Furthermore, the device 7 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric converter. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the photoelectric converter.

[0054] Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated by the first photoelectric conversion unit and a pixel signal based on the charge generated by the second photoelectric conversion unit to acquire distance information from the imaging device 700 to the subject.

[0055] [Fifth Embodiment] Figures 8(a) and 8(b) are block diagrams of the device 8 related to the in-vehicle camera in this embodiment. The device 8 includes an imaging device 800 (an example of a photoelectric converter having a semiconductor integrated circuit) and a signal processing device (processing device) that processes signals from the imaging device 800. The device 8 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the device 8. The device 8 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0056] Device 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 8 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination unit 804 determines that there is a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 8 functions as a control means that controls the actions that control the vehicle.

[0057] In this embodiment, the equipment 8 images the area around the vehicle, for example, the front or rear. Figure 8(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends an instruction to the equipment 8 or imaging device 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0058] The above example describes control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, control systems that automatically stay within their lanes, and so on. Furthermore, device 8 can be applied not only to vehicles such as automobiles, but also to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0059] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0060] The above-disclosed embodiment includes the following configuration. (Composition 1) In semiconductor integrated circuits, A test circuit for testing the operation of the aforementioned semiconductor integrated circuit, The test circuit shares at least a portion of its circuits and includes a TEG (Test Element Group) circuit for characterizing the semiconductor integrated circuit or manufacturing process, A semiconductor integrated circuit characterized by comprising a switching circuit that switches between a first operating mode for operating the test circuit in response to a first input signal and a second operating mode for operating the TEG circuit in response to a second input signal. (Configuration 2) The test circuit includes a first memory element that constitutes at least a portion of the circuit and holds the first input signal or the second input signal, and a first transmission line. The TEG circuit includes a second transmission line on which the TEG is located. The semiconductor integrated circuit according to configuration 1, characterized in that the switching circuit transmits a first input signal from the first memory element to the first transmission line in the first operating mode, and transmits a second input signal from the first memory element to the second transmission line in the second operating mode. (Composition 3) The semiconductor integrated circuit according to configuration 1 or 2, characterized in that the test circuit constitutes at least a portion of the circuit and includes a second memory element that holds the first input signal from the first transmission line or the second input signal from the second transmission line. (Composition 4) The switching circuit includes a first multiplexer and a second multiplexer, In the first operating mode, the first multiplexer outputs the first input signal from the first memory element to the first transmission line, and the second multiplexer outputs the first input signal from the first transmission line to the second memory element. The semiconductor integrated circuit according to configuration 3, characterized in that, in the second operating mode, the first multiplexer outputs the second input signal from the first memory element to the second transmission line, and the second multiplexer outputs the second input signal from the second transmission line to the second memory element. (Composition 5) The semiconductor integrated circuit according to any one of configurations 1 to 4, characterized in that the TEG circuit includes a TEG for evaluating the digital characteristics of the semiconductor integrated circuit. (Composition 6) The semiconductor integrated circuit according to any one of configurations 1 to 5, characterized in that the TEG circuit includes a TEG for evaluating the analog characteristics of the semiconductor integrated circuit. (Composition 7) The aforementioned TEG circuit includes multiple TEGs, The semiconductor integrated circuit according to any one of configurations 1 to 6, characterized in that each of the plurality of TEGs is a via that differs from the others in number or shape. (Composition 8) The aforementioned TEG circuit includes multiple TEGs, The semiconductor integrated circuit according to any one of configurations 1 to 7, characterized in that each of the plurality of TEGs is a wiring of a different thickness. (Composition 9) The semiconductor integrated circuit according to any one of configurations 1 to 8, characterized in that the test circuit and the TEG circuit are formed on a semiconductor chip. (Composition 10) A semiconductor integrated circuit according to any one of configurations 1 to 9, characterized by comprising a plurality of circuit blocks, each having the test circuit, the TEG circuit, and the switching circuit. (Composition 11) The semiconductor integrated circuit according to configuration 10, characterized in that the plurality of circuit blocks are connected in series. (Composition 12) The semiconductor integrated circuit according to configuration 10 or 11, further comprising a third memory element that holds the first input signal or the second input signal output from the final stage circuit block among the plurality of circuit blocks. (Composition 13) A photoelectric converter having a semiconductor integrated circuit as described in any of configurations 1 to 12, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter. (Composition 14) The apparatus according to configuration 13, characterized in that the processing device acquires distance information from the photoelectric converter to the object. [Explanation of Symbols]

[0061] 10…Multiplexer (switching circuit) 20...First flip-flop (first memory element) 30A...First multiplexer (switching circuit) 30B...Second multiplexer (switching circuit) 40…First transmission line 50...Second transmission line 51…TEG 60...Second flip-flop (second memory element) 70...Third flip-flop (third memory element) 100, 200, 300... Semiconductor integrated circuits 515... Beer 511, 512… wiring

Claims

1. In semiconductor integrated circuits, A test circuit for testing the operation of the aforementioned semiconductor integrated circuit, Sharing at least a portion of the circuits of the aforementioned test circuit, and a TEG (Test Element Group) circuit for characterizing the semiconductor integrated circuit or manufacturing process, A semiconductor integrated circuit characterized by comprising a first operating mode for operating the test circuit in response to a first input signal, and a switching circuit for switching between a first operating mode for operating the TEG circuit in response to a second input signal.

2. The test circuit includes a first memory element that constitutes at least a portion of the circuit and holds the first input signal or the second input signal, and a first transmission line. The TEG circuit includes a second transmission line on which the TEG is located. The semiconductor integrated circuit according to claim 1, characterized in that the switching circuit transmits a first input signal from the first memory element to the first transmission line in the first operating mode, and transmits a second input signal from the first memory element to the second transmission line in the second operating mode.

3. The semiconductor integrated circuit according to claim 2, characterized in that the test circuit constitutes at least a portion of the circuit and includes a second memory element that holds the first input signal from the first transmission line or the second input signal from the second transmission line.

4. The switching circuit includes a first multiplexer and a second multiplexer, In the first operating mode, the first multiplexer outputs the first input signal from the first memory element to the first transmission line, and the second multiplexer outputs the first input signal from the first transmission line to the second memory element. The semiconductor integrated circuit according to claim 3, characterized in that, in the second operating mode, the first multiplexer outputs the second input signal from the first memory element to the second transmission line, and the second multiplexer outputs the second input signal from the second transmission line to the second memory element.

5. The semiconductor integrated circuit according to claim 1, characterized in that the TEG circuit includes a TEG for evaluating the digital characteristics of the semiconductor integrated circuit.

6. The semiconductor integrated circuit according to claim 1, characterized in that the TEG circuit includes a TEG for evaluating the analog characteristics of the semiconductor integrated circuit.

7. The TEG circuit includes multiple TEGs, The semiconductor integrated circuit according to claim 1, characterized in that each of the plurality of TEGs is a via that differs from the others in number or shape.

8. The TEG circuit includes multiple TEGs, The semiconductor integrated circuit according to claim 1, characterized in that each of the plurality of TEGs is a wire of a different thickness.

9. The semiconductor integrated circuit according to claim 1, characterized in that the test circuit and the TEG circuit are formed on a semiconductor chip.

10. The semiconductor integrated circuit according to claim 1, characterized by comprising a plurality of circuit blocks, each having the test circuit, the TEG circuit, and the switching circuit.

11. The semiconductor integrated circuit according to claim 10, characterized in that the plurality of circuit blocks are connected in series.

12. The semiconductor integrated circuit according to claim 11, further comprising a third memory element that holds the first input signal or the second input signal output from the final stage circuit block among the plurality of circuit blocks.

13. A photoelectric converter having a semiconductor integrated circuit according to any one of claims 1 to 12, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

14. The apparatus according to claim 13, characterized in that the processing device acquires distance information from the photoelectric converter to the object.

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