Efficient autocatalytic metallization of polymer surfaces

Abstract

A semiconductor package and a method for metallizing a non-conductive surface for manufacturing the semiconductor package are provided. In one embodiment, the method includes depositing an adhesion layer on a polymer surface by an electroless deposition process. The polymer surface defines a sidewall of a through-hole via, and the adhesion layer includes a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer replaces a portion of the adhesion layer. The method further includes filling the through-hole via with a copper-containing layer.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to semiconductor packages and methods of manufacturing semiconductor packages. More particularly, the present disclosure relates to metallization of non-conductive surfaces to manufacture semiconductor packages. [Background technology]

[0002] Electronic packaging and assembly are typically used to connect small-dimensioned integrated circuits (ICs) to interconnection substrates, such as printed circuit boards (PCBs). PCBs usually contain several passive components and ICs to construct microelectronic devices. The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, improvements in integration density are achieved by repeatedly reducing minimum feature sizes, allowing more components to be integrated into a given area. Increasing demands for smaller electronic devices have led to the need for smaller semiconductor dies and more creative packaging techniques.

[0003] For the foregoing reasons, there is a need for improved semiconductor packages and methods of manufacturing semiconductor packages. Summary of the Invention

[0004] In one aspect, a method for manufacturing a semiconductor device is provided. The method includes depositing an adhesion layer on a polymer surface by an electroless deposition process. The polymer surface defines a sidewall of a through-hole via, and the adhesion layer includes a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer replaces a portion of the adhesion layer. The method further includes filling the through-hole via with a copper-containing layer.

[0005] Embodiments may include one or more of the following: the polymer surface is exposed to a heat treatment process prior to depositing the adhesion layer, the heat treatment process including exposing the polymer surface to heat at a temperature ranging from about 100°C to about 150°C; the polymer surface is exposed to an activation process prior to the heat treatment process including exposing the polymer surface to a first bath including hydrochloric acid and sodium chloride, exposing the polymer surface to a catalytic bath including hydrochloric acid, tin chloride, and palladium chloride, and exposing the polymer surface to fluoroboric acid; the electroless deposition process includes exposing the polymer surface to an electroless deposition solution including a nickel sulfate solution, a sodium hypophosphite solution, and water; the electroless deposition solution is heated to a temperature ranging from about 80°C to about 90°C; the portion of the adhesion layer replaced by the copper seed layer is about 10 to about 30% of the original thickness of the adhesion layer; the adhesion layer includes NiP, NiWP, CoP, or CoWP. The polymer surface includes polybenzoxazole (PBO), polyimide, polyimide derivatives, epoxy resin, prepreg (PP) material, or a combination thereof.

[0006] In another aspect, a method for manufacturing a semiconductor device is provided. The method includes providing a substrate including an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole via connecting the first major surface and the second major surface. The method further includes depositing an adhesion layer on the insulating material by an electroless deposition process. The insulating material defines sidewalls of the through-hole via, and the adhesion layer includes a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer replaces a portion of the adhesion layer. The method further includes forming a photoresist layer on the copper seed layer formed on at least the first major surface. The photoresist is patterned to form an opening through the photoresist layer. The opening exposes the copper seed layer formed along the sidewall of the through-hole via. The through-hole via and the opening are filled with a copper-containing layer to form an interconnect structure. The photoresist is removed to expose the adhesion layer and copper seed layer formed on at least the first major surface.

[0007] Embodiments may include one or more of the following: the adhesion layer and copper seed layer are removed from the first major surface by an etching process, the etching process removing the copper seed layer and adhesion layer at a faster rate than the copper of the interconnect structure; the etching process including exposing the adhesion layer and copper seed layer to an etchant solution including copper sulfate and sulfuric acid; the etching process including exposing the adhesion layer and copper seed layer to an etchant solution including about 0.5M to about 1.5M CuSO4·5H2O and about 0.02M to 2M H2SO4; the polymer surface is exposed to a heat treatment process prior to depositing the adhesion layer, the heat treatment process including exposing the polymer surface to heat at a temperature ranging from about 100°C to about 150°C. The polymer surface is exposed to an activation process prior to the heat treatment process, the activation process including exposing the polymer surface to a first bath including hydrochloric acid and sodium chloride, exposing the polymer surface to a catalytic bath including hydrochloric acid, tin chloride, and palladium chloride, and exposing the polymer surface to fluoroboric acid.

[0008] In yet another aspect, a semiconductor device is provided. The device includes a substrate including an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole via connecting the first major surface and the second major surface. The device further includes an adhesion layer formed on the insulating material defining sidewalls of the through-hole via, the adhesion layer including a cobalt alloy or a nickel alloy. The device further includes a copper seed layer formed on the adhesion layer. The device further includes a copper interconnect extending through the entire thickness of the substrate, the copper interconnect filling the through-hole via and extending beyond both the first major surface and the second major surface.

[0009] Embodiments may include one or more of the following: The adhesion layer includes NiP, NiWP, CoP, or CoWP. The polymer surface includes polybenzoxazole (PBO), polyimide, a polyimide derivative, an epoxy resin, a prepreg (PP) material, or a combination thereof. The substrate further includes a semiconductor die encapsulated by an insulating material. The substrate is part of a three-dimensional multi-chip module.

[0010] In another aspect, a non-transitory computer-readable medium has stored thereon instructions that, when executed by a processor, cause the process to perform the operations of the apparatus and / or methods described above.

[0011] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope thereof, as other equally effective embodiments may be recognized. [Brief explanation of the drawings]

[0012] [Figure 1A] 1 is a schematic diagram of a three-dimensional multi-chip module (3-D MCM) according to one or more embodiments. [Figure 1B] FIG. 1 is a schematic diagram of a 3-D MCM according to one or more embodiments. [Figure 2] 1 is an exemplary flowchart of a method for metallization of a polymer surface according to one or more embodiments of the present disclosure. [Figure 3A] 1A-1D are cross-sectional views of various stages of metallization of a polymer surface according to one or more embodiments of the present disclosure. [Figure 3B] 1A-1D are cross-sectional views of various stages of metallization of a polymer surface according to one or more embodiments of the present disclosure. [Figure 3C]1A-1D are cross-sectional views of various stages of metallization of a polymer surface according to one or more embodiments of the present disclosure. [Figure 3D] 1A-1D are cross-sectional views of various stages of metallization of a polymer surface according to one or more embodiments of the present disclosure. [Figure 4] 1 is an exemplary flowchart of a method for forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5A] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5B] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5C] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5D] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5E] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5F] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5G] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5H] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. [Figure 5I] 1A-1D are cross-sectional views of various stages in forming a 3-D MCM structure according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014] The present disclosure generally relates to semiconductor packages and methods for manufacturing semiconductor packages. More specifically, the present disclosure relates to metallization of non-conductive surfaces for manufacturing semiconductor packages. Metallization of non-conductive surfaces, such as electroless deposition of copper on polymer surfaces, currently involves a nine-step process involving multiple wet chemical baths. This nine-step process includes pretreatment steps such as desmearing, oxidation, neutralization, and conditioning with corrosive chemicals, which roughen the non-conductive surface by rendering it microporous, thereby improving adhesion. However, the roughness achieved using the nine-step process can limit the ability to scale down. Furthermore, the current nine-step process is time-consuming and expensive.

[0015] The various described embodiments provide an efficient process involving fewer steps for metallizing non-conductive surfaces of interest in advanced packaging applications. This process offers performance advantages over current nine-step processes, including reduced roughness. Reduced roughness enables packaging scaling. In at least one embodiment, non-conductive surfaces are metallized by depositing an electroless alloy layer that acts as an adhesion layer, followed by an immersion (displacement) plating process to form a thin seed layer on the adhesion layer. The adhesion layer comprises a nickel or cobalt alloy, such as NiP, NiWP, CoP, or CoWP. The immersion plating process deposits a copper coating on the adhesion layer from a copper-containing solution. One metal in the adhesion layer is displaced by copper ions, which have a lower oxidation potential than the displaced metal ions. Once the seed layer is formed, electroplating or electroless plating processes can be used to form interconnect structures within features, such as through-hole vias. The electroless nickel or cobalt alloy can be formed on the non-conductive surface without the use of a corrosive pretreatment to roughen the non-conductive surface. Additionally, the immersion copper seed layer formed on the electroless alloy is much less rough, so improved results can be achieved in fewer steps.

[0016] The various described embodiments further provide a wet chemical controlled etch of metal stacks, such as the described adhesion layer / seed layer stacks, useful for patterning advanced packaging interconnects. Patterning interconnects in packaging areas requires controlled removal of a thin layer of copper along with a thicker underlying nickel or cobalt alloy used as a metallization layer, as described above. This removal occurs relative to a thicker adjacent copper layer, such as an interconnect structure. Current etchants are either too fast for copper or do not sufficiently remove it. In at least one embodiment, etchant compositions and optimized process conditions are provided. The etchant and process conditions can etch not only copper but also nickel or cobalt alloys in a controlled manner.

[0017] FIG. 1A shows a schematic diagram of a 3-D MCM 100a according to one or more embodiments. In at least one embodiment, as shown in FIG. 1A, the 3-D MCM 100a is formed from four semiconductor packages 102. Each semiconductor package 102 includes a semiconductor die 104, e.g., a memory chip, embedded in a substrate 106 and encapsulated by an insulating material 108, with a portion of each side in contact with the insulating material 108. In at least one embodiment, the insulating material 108 is formed by curing a ceramic filler-containing epoxy resin, such as an epoxy resin containing silica (SiO) particles. Other examples of ceramic fillers that can be utilized to form the insulating material 108 include aluminum nitride (AlN), aluminum oxide (AlO), silicon carbide (SiC), silicon nitride (SiN), SrCeTiO, and the like. 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12Examples of suitable ceramic fillers include SiO2, magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and the like. The insulating material 108 may be a polymer layer, such as polybenzoxazole (PBO), but may also be any suitable material, such as polyimide or polyimide derivatives, prepreg (PP) materials such as epoxy resins, gallium fiber, resins, and fillers, Ajinomoto Build-Up Film® (ABF) (e.g., epoxy with silica filler), polyethylene terephthalate (PET), or combinations thereof. In one example, the insulating material 108 is formed from ABF. In some examples, the ceramic fillers utilized to form the insulating material 108 have particles ranging in size from about 40 nm to about 1.5 μm, or ranging in size from about 80 nm to about 1 μm, or ranging in size from about 300 nm to about 600 nm. In at least one embodiment, the ceramic filler utilized to form the insulating material 108 includes particles having a size less than about 25% of the width or diameter of a targeted feature, e.g., a via, cavity, or through-assembly via, e.g., less than about 15% of the width or diameter of the targeted feature. One or more interconnects 110 are formed throughout the thickness of each semiconductor package 102. One or more interconnects 112 are formed through the insulating material 108. In at least one embodiment, one or more redistribution connections 114 are formed within the semiconductor package 102 to relocate the interconnect contacts to targeted lateral locations on the surface of the semiconductor package 102.

[0018] The interconnects 110 are in direct contact with one or more solder bumps 116 disposed between the major surfaces 118 and 120 of adjacent semiconductor packages, or are in contact through an optional adhesion layer 122 and / or seed layer 124 formed on the redistribution connections 114 or the insulating material 108. The redistribution connections 114 are formed by any suitable method, including electroplating and electroless deposition. In at least one embodiment, the adhesion layer 122 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In at least one embodiment, the adhesion layer 122 has a thickness of about 10 nm to about 300 nm, such as about 50 nm to about 150 nm. For example, the adhesion layer 122 has a thickness of about 75 nm to about 125 nm, such as about 100 nm. The adhesion layer 122 may be formed by any suitable deposition process, including, but not limited to, CVD, PVD, PECVD, ALD, etc. The seed layer 124 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material, or combinations thereof. In at least one embodiment, the seed layer 124 has a thickness of about 50 nm to about 500 nm, such as about 100 nm to about 300 nm. For example, the seed layer 124 has a thickness of about 150 nm to about 250 nm, such as about 200 nm. In at least one embodiment, the seed layer 124 has a thickness in the range of about 0.1 μm to about 1.5 μm. Like the adhesion layer 122, the seed layer 124 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry processes, wet electroless plating processes, etc. In at least one embodiment, adhesion layer 122 is a molybdenum adhesion layer formed on semiconductor die 104 in combination with seed layer 124, which is a copper seed layer.

[0019] As depicted in the 3-D MCM 100a, four or more solder bumps 116 are disposed between major surfaces 118 and 120 of adjacent semiconductor packages 102 to bridge, e.g., connect or couple, the interconnects 110 of each semiconductor package 102 to the interconnects 110 of adjacent semiconductor packages 102.

[0020] In at least one embodiment, voids between adjacent semiconductor packages 102 connected by solder bumps 116 are filled with encapsulant material 126 to enhance the reliability of the solder bumps 116. The encapsulant material 126 may be any suitable type of encapsulant or underfill. In one example, the encapsulant material 126 includes a pre-assembly underfill material, such as a no-flow underfill (NUF) material, a non-conductive paste (NCP) material, and a non-conductive film (NCF) material. In one example, the encapsulant material 126 includes a post-assembly underfill material, such as a capillary underfill (CUF) material and a molded underfill (MUF) material. In at least one embodiment, the encapsulant material 126 includes a metal such as, for example, SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O 16 , ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12 , including low expansion filled resins such as epoxy resins filled with MgO, TiO2, ZnO, etc.

[0021] In at least one embodiment, the solder bumps 116 are formed of one or more intermetallic compounds, such as tin (Sn) in combination with lead (Pb), silver (Ag), Cu, or any other suitable metal. For example, the solder bumps 116 are formed of solder alloys, such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable materials or combinations thereof. In at least one embodiment, the solder bumps 116 comprise C4 (controlled collapse chip connection) bumps. In at least one embodiment, the solder bumps 116 comprise C2 (chip connection, such as a Cu pillar with a solder cap) bumps. Utilizing C2 solder bumps can enable a smaller pitch between contact pads, improving the thermal and / or electrical properties of the 3-D MCM 100a. In at least one embodiment, the solder bumps 116 have a diameter of about 10 μm to about 150 μm, such as a diameter of about 50 μm to about 100 μm. The solder bumps 116 may further be formed by any suitable wafer bumping process, including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0022] 1B shows a schematic diagram of a 3-D MCM structure 100b according to one or more embodiments. The 3-D MCM structure 100b is formed by stacking four semiconductor packages 102 and directly bonding one or more interconnects 110 of each semiconductor package 102 to the interconnects 110 of one or more adjacent semiconductor packages 102. As depicted, the semiconductor packages 102 can be bonded by hybrid bonding, in which the major surfaces 118 and 120 of adjacent packages are planarized and fully contact each other. Thus, the one or more interconnects 110 of each semiconductor package 102 are formed through the entire thickness of each semiconductor package 102 and are in contact with one or more interconnects 112 of at least another adjacent semiconductor package 102.

[0023] Formation of one or more interconnects 110 and one or more interconnects 112 is described.

[0024] FIG. 2 illustrates an exemplary flowchart of a method 200 for polymer surface metallization according to one or more embodiments of the present disclosure. Method 200 can be used to form advanced packaging structures, such as 3-D MCMs as described. FIGS. 3A-3D illustrate cross-sectional views of various stages of polymer surface metallization according to one or more embodiments of the present disclosure. While FIGS. 3A-3D are described in conjunction with method 200, it will be understood that the structures disclosed in FIGS. 3A-3D are not limited to method 200 and may instead exist independently of method 200. Similarly, while method 200 is described in conjunction with FIGS. 3A-3D, it will be understood that method 200 is not limited to the structures disclosed in FIGS. 3A-3D and may instead exist independently of the structures disclosed in FIGS. 3A-3D.

[0025] FIG. 3A shows a cross-sectional view of a portion of a structure 300, such as a 3-D MCM structure 100a, 100b, at an intermediate stage of fabrication corresponding to operation 210, according to some embodiments. The structure 300 includes a substrate 106 having an insulating material 108 formed thereon. The substrate 106 includes a front side 106f (also referred to as a front side) and a back side 106b opposite the front side 106f. The insulating material 108 is formed on the front side 106f of the substrate 106. The insulating material 108 includes a polymer surface 108f (also referred to as a front side) and a back side 108b opposite the polymer surface 108f. Although FIG. 3A shows the insulating material 108 formed on the substrate 106, the method 200 may be performed on the insulating material 108 without the substrate 106 being present.

[0026] During operation 210, an activation pretreatment process is performed to prepare the polymer surface 108f for electroless deposition. In at least one embodiment, the activation pretreatment process of operation 210 is preceded by a cleaning operation. The cleaning operation can begin with a cleaner conditioner designed to remove organics and condition the multiple circuit layers (or circuit board) having one or more through-holes for subsequent incorporation of a catalyst. The cleaner conditioner can include an alkaline solution.

[0027] In at least one embodiment, the activation process of operation 210 includes a pre-activation operation, an activation operation, and a post-activation operation. During the pre-activation operation, the polymer surface 108f is exposed to a first bath, typically containing hydrochloric acid and, optionally, sodium chloride. In at least one embodiment, during the activation process of operation 210, the polymer surface 108f is exposed to a catalytic bath containing hydrochloric acid, tin chloride, and palladium chloride. Sn +2 The ion is Pd +2 is reduced to Pd, which is deposited on the polymer surface 108f. During the post-activation process of operation 210, the remaining Sn +2 and Sn +4 is selectively removed by a promoter (also called a post-activator). Suitable promoters include fluoroboric acid.

[0028] FIG. 3B shows a cross-sectional view of a portion of structure 300 at an intermediate stage of fabrication corresponding to operation 220, according to some embodiments. During operation 220, structure 300 is optionally exposed to a heat treatment process. The heat treatment process of operation 220 is believed to improve adhesion of a subsequently deposited adhesion layer to polymer surface 108f. During operation 220, structure 300 is exposed to heat at a temperature of 180°C or less, e.g., a temperature in the range of about 100°C to about 180°C, or a temperature in the range of about 100°C to about 170°C, or a temperature in the range of about 100°C to about 150°C, or a temperature in the range of about 110°C to about 120°C. The heat treatment process of operation 220 can be carried out for a time period of 60 minutes or less, e.g., a temperature in the range of about 30 seconds to about 30 minutes, or a temperature in the range of about 30 seconds to about 5 minutes, or a temperature in the range of about 1 minute to about 3 minutes. In one example, the heat treatment process is carried out at a temperature in the range of about 110°C to about 120°C for about 3 minutes.

[0029] 3C illustrates a cross-sectional view of a portion of structure 300 at an intermediate stage of fabrication corresponding to operation 230, according to some embodiments. During operation 230, an adhesion layer 310 is formed by an electroless deposition process. The adhesion layer 310 improves adhesion of a subsequently deposited copper seed layer to the polymer surface 108f. The adhesion layer 310 can also function as a barrier layer by reducing diffusion of subsequently deposited copper into underlying layers, such as into the insulating material 108. The adhesion layer 310 may be formed on the polymer surface 108f, as shown in FIG. 3C. In at least one embodiment, the adhesion layer 310 includes a binary or ternary alloy, such as a binary or ternary cobalt or nickel alloy. Examples of ternary or binary cobalt or nickel alloys include cobalt boride (CoB), cobalt phosphide (CoP), nickel boride (NiB), nickel phosphide (NiP), cobalt tungsten phosphide (CoWP), cobalt tungsten boride (CoWB), nickel tungsten phosphide (NiWP), nickel tungsten boride (NiWB), cobalt molybdenum phosphide (CoMoP), cobalt molybdenum boride (CoMoB), nickel molybdenum phosphide (NiMoB), nickel molybdenum phosphide (NiMoP), nickel rhenium phosphide (NiReP), nickel rhenium boride (NiReB), cobalt rhenium boride (CoReB), cobalt rhenium phosphide (CoReP), derivatives thereof, or combinations thereof. In at least one specific embodiment, adhesion layer 310 comprises NiP, NiWP, CoP, or CoWP. In at least one embodiment, adhesive layer 310 has a thickness "T1" in the range of about 50 nanometers to about 500 nanometers, or in the range of about 100 nanometers to about 400 nanometers, or in the range of about 100 nanometers to about 300 nanometers, or in the range of about 240 nanometers to about 280 nanometers.

[0030] In at least one embodiment, the structure 300 is subjected to one of two techniques to form an adhesion layer 310 on the polymer surface 108f of the insulating material 108. The structure 300 may be immersed in a wet bath containing the electroless deposition solution, or the structure 300 may be placed on a rotating chuck where the electroless deposition solution is poured onto a rotating wafer (spin or shower deposition technique). The electroless deposition solution may be heated to a temperature in the range of about 70°C to about 100°C, or in the range of about 80°C to about 90°C, or in the range of about 80°C to about 85°C.

[0031] In at least one embodiment in which adhesion layer 310 is NiP, the electroless deposition solution includes a nickel sulfate solution, a sodium hypophosphite solution, and DI water. In one example, the electroless deposition solution is formed by adding 5 ml of nickel sulfate solution and 10 ml of sodium hypophosphite solution to 85 ml of DI water.

[0032] After deposition of adhesion layer 310 in operation 230, adhesion layer 310 may be exposed to a heat treatment process in operation 235. The heat treatment process of operation 235 may be performed similarly to the heat treatment process of operation 220. The heat treatment process of operation 235 is believed to improve the adhesion between adhesion layer 310 and polymer surface 108f.

[0033] FIG. 3D shows a cross-sectional view of a portion of structure 300 at an intermediate stage of fabrication corresponding to operation 240, according to some embodiments. During operation 240, a copper seed layer 320, e.g., an immersion copper seed layer, is formed by an immersion plating process. The immersion plating process deposits a copper coating on adhesion layer 310 from a copper-containing solution. One metal in adhesion layer 310 is replaced by copper ions, which have a lower oxidation potential than the replaced metal ions. In at least one embodiment, copper seed layer 320 replaces a portion of adhesion layer 310, e.g., 10% to 30% of T1 is replaced by copper seed layer 320 having a thickness "T2," reducing the thickness of adhesion layer 310 from T1 to "T3." In at least one embodiment, copper seed layer 320 has a thickness "T2" in the range of about 10 nanometers to about 100 nanometers, or in the range of about 10 nanometers to about 50 nanometers, or in the range of about 40 nanometers to about 80 nanometers. In one example, adhesion layer 310 has a thickness T3 in the range of about 130 nanometers to about 375 nanometers, and copper seed layer 320 has a thickness T2 in the range of about 40 nanometers to about 80 nanometers.

[0034] In at least one embodiment, structure 300 is subjected to one of two techniques for forming a copper seed layer 320 on the surface of adhesion layer 310. Structure 300 can be immersed in a wet bath containing a contact displacement deposition solution (immersion deposition technique), or structure 300 can be placed on a rotating chuck where the contact displacement solution is injected onto the rotating wafer (spin or shower deposition technique).

[0035] A variety of solutions acceptable for semiconductor applications can be used to deposit copper atoms forming the copper seed layer 320 onto the surface of the adhesion layer 310 by catalytic displacement. In at least one embodiment, an aqueous catalytic displacement solution is formed containing deionized (DI) water as the primary component of the solution. Various chemicals, as described below, can then be added to the DI water in the amounts described. The solution contains 0.001 to 2 moles / liter of Cu. +2The solution further includes copper sulfate (CuSO4) and sulfuric acid (H2SO4), which provide copper ions. In at least another embodiment, CuSO4·5H2O (1 g) and H2SO4 (2 ml to 5 ml) are added to 100 ml of DI water to form an aqueous contact displacement solution. In yet another embodiment, CuSO4·5H2O (1 g), H2SO4 (2 ml to 5 ml), and (NH4)2SO4 (5 g) are added to 100 ml of DI water to form an aqueous contact displacement solution. The aqueous contact displacement solution can further include ammonium sulfate, e.g., (NH4)2SO4 (5 g). The exposed adhesive layer 310 is exposed to this solution at a temperature in the range of approximately 50 to 100°C, or in the range of about 80 to about 90°C, or in the range of about 85 to about 86°C, for approximately 1 to 600 seconds, e.g., 10 to 20 seconds. Although the parameters can be varied, it is desirable to ultimately form a copper seed layer 320 having at least a monolayer of copper atoms to cover the surface of the adhesion layer 310. The structure 300 can then be removed from the contact replacement solution and rinsed with DI water.

[0036] It will be appreciated that by utilizing the above contact replacement process, a copper seed layer 320 is formed on the surface of adhesion layer 310 such that, when structure 300 is placed in a copper electroplating or copper electroless deposition solution, autocatalytic deposition of electrolessly deposited or electroplated copper can occur on the surface of adhesion layer 310. It should be noted that although the contact replacement technique is described with reference to the use of a cobalt- or nickel-containing adhesion layer, the same contact replacement technique can be used with other adhesion layer materials to activate the surface of the adhesion layer for copper deposition.

[0037] After deposition of the copper seed layer 320 in operation 240, the copper seed layer 320 may optionally be exposed to a heat treatment process in operation 245. The heat treatment process of operation 245 may be performed similarly to the heat treatment process of operation 220. The heat treatment process of operation 245 is believed to improve adhesion between the copper seed layer 320, the adhesion layer 310, and the polymer surface 108f.

[0038] FIG. 4 illustrates an exemplary flowchart of a method 400 for forming a 3-D MCM structure according to one or more embodiments of the present disclosure. FIGS. 5A-5I illustrate cross-sectional views of various stages of forming a 3-D MCM structure according to one or more embodiments of the present disclosure. With reference to FIGS. 5A-5I, cross-sectional views of some embodiments of a 3-D MCM structure at various stages of fabrication are provided to illustrate the method of FIG. 4. While FIGS. 5A-5I are described in conjunction with method 400, it will be understood that the structures disclosed in FIGS. 5A-5I are not limited to method 400 and, instead, may exist independently as structures independent of method 400. Similarly, while method 400 is described in conjunction with FIGS. 5A-5I, it will be understood that method 400 is not limited to the structures disclosed in FIGS. 5A-5I and, instead, may exist independently as structures independent of method 400.

[0039] FIG. 5A shows a cross-sectional view of a portion of a packaging structure 500 at an intermediate stage of fabrication corresponding to operation 410, according to some embodiments. The packaging structure 500 can form a portion of the 3-D MCM structures 100a, 100b. During operation 410, a substrate, such as the substrate 106 shown in FIG. 4A, is provided. The substrate 106 has an insulating material 108 formed thereon. The insulating material 108 may be formed on the entire surface of the substrate 106 so as to surround the substrate 106. The insulating material 108 includes sidewalls 511s, a major surface 120 (also referred to as a top surface), and a major surface 118 (also referred to as a bottom surface). The packaging structure 500 includes one or more through-hole vias 510a-c extending through the entire thickness of the substrate 106 and the insulating material 108. In one example, three through-hole vias 510a-c are depicted as depicted in FIG. 5A. The through-hole vias 510a-c are utilized to receive the interconnects 110. The through-hole vias 510a-c may be formed via any suitable patterning process. In at least one embodiment, the through-hole vias 510a-c are formed via a laser ablation process. In some embodiments, the substrate 106 is not present and the method 400 is performed on the insulating material 108.

[0040] Through-hole vias 510a-c have a depth equal to the thickness of substrate 106 and the thickness of insulating material 108, and thus are formed in opposing surfaces of substrate 106 and insulating material 108. For example, through-hole vias 510a-c formed in substrate 106 can have a depth of about 10 μm to about 1 mm, depending on the thickness of substrate 106.

[0041] FIG. 5B shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 420, according to some embodiments. During operation 420, adhesion layer 310 is formed. Adhesion layer 310 may be formed on the entire surface of substrate 106 to surround substrate 106. For example, as shown in FIG. 5B , adhesion layer 310 is formed on sidewalls 511s and major surfaces 118 and 120 defined by insulating material 108. Adhesion layer 310 includes sidewalls 521s, a top surface 521t, and a bottom surface 521b. Sidewalls 521s and top surface 521t and bottom surface 521b of adhesion layer 310 may be parallel or substantially parallel to sidewalls 511s and major surface 120 (also referred to as the top surface) and major surface 118 of insulating material 108, respectively. As described, adhesion layer 310 is formed by an electroless deposition process, such as the techniques described in method 200.

[0042] 5C shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 430, according to some embodiments. During operation 430, a copper seed layer 320 is formed. The copper seed layer 320 may be formed over the entire surface of substrate 106 so as to surround the substrate 106. For example, as shown in FIG. 5C , the copper seed layer 320 is formed on sidewalls 521s, a bottom surface 521b, and a top surface 521t defined by adhesion layer 310. The copper seed layer 320 includes sidewalls 531s, a top surface 531t, and a bottom surface 531b. The sidewalls 531s, the top surface 531t, and the bottom surface 531b of the copper seed layer 320 may be parallel or substantially parallel to the sidewalls 521s, the top surface 521t, and the bottom surface 521b of adhesion layer 310, respectively. As described, copper seed layer 320 is formed by an immersion (displacement) plating process, such as the technique of method 200 .

[0043] 5D shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 440, according to some embodiments. During operation 440, a photoresist layer 540, such as a dry film photoresist, is formed. Photoresist layer 540 is formed on top surface 531t and bottom surface 531b of copper seed layer 320. Photoresist layer 540 may be formed on copper seed layer 320 using, for example, a lamination process or a spin-coating process. Photoresist layer 540 can be formed to a thickness ranging from about 0.5 microns to about 10 microns, or from about 0.5 microns to about 1 micron.

[0044] 5E shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 450, according to some embodiments. During operation 450, photoresist layer 540 is patterned and exposed to form a pattern of exposed portions 550a-c. The pattern of exposed portions 550a-c of photoresist layer 540 corresponds to through-hole vias 510a-c. Photoresist layer 540 can be patterned by exposing photoresist layer 540 to an energy source, e.g., a patterned light source such as an ultraviolet (UV) light source, to induce a chemical reaction, and thus a physical change, and selectively remove either the exposed portions of photoresist layer 540 or the unexposed portions of photoresist layer 540, depending on the desired pattern.

[0045] 5F shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 460, according to some embodiments. During operation 460, a developer is applied to exposed portions 550a-c of photoresist layer 540 to remove exposed portions 550a-c and form openings 560a-c. Openings 560a-c in photoresist layer 540 expose sidewalls 531s of copper seed layer 320 formed in through-hole vias 510a-c. Openings 560a-c in photoresist layer 540 may also expose portions 561t of top surfaces 531t of copper seed layer 320 and portions 561b of bottom surfaces 531b of copper seed layer 320.

[0046] FIG. 5G shows a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 470, according to some embodiments. During operation 470, one or more interconnects 110a-c are formed throughout the thickness of semiconductor package 102. The one or more interconnects include one or more conductive materials, such as copper-tungsten or other conductive metals, and may be formed by electroplating, electroless plating, or the like. In at least one embodiment, an electroplating process is used in which copper seed layer 320 and photoresist layer 540 are submerged or immersed in an electroplating solution. The surface of copper seed layer 320 is electrically connected to the negative side of an external DC power supply so that copper seed layer 320 functions as a cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve into the solution from which the cathode, e.g., copper seed layer 320, acquires the dissolved atoms, thus plating the exposed conductive areas of copper seed layer 320 within the openings in photoresist layer 540.

[0047] 5H shows a cross-sectional view of a portion of packaging structure 500 during an intermediate stage of fabrication corresponding to operation 480, according to some embodiments. During operation 480, photoresist layer 540 may be removed using a suitable removal process. In at least one embodiment, a plasma ashing process is used to remove photoresist layer 540, and the temperature of the photoresist may be elevated to a point where the photoresist can undergo thermal decomposition and be removed. However, any other suitable process, such as wet stripping, may alternatively be utilized to remove photoresist layer 540. Removal of the photoresist may expose underlying portions of copper seed layer 320, such as top surface 531t and bottom surface 531b of copper seed layer 320.

[0048] FIG. 5I illustrates a cross-sectional view of a portion of packaging structure 500 at an intermediate stage of fabrication corresponding to operation 490, according to some embodiments. During operation 490, removal of exposed portions of copper seed layer 320 and underlying adhesion layer 310 may occur. Removal of exposed portions of copper seed layer 320 and underlying adhesion layer 310 may expose major surfaces 118 and 120 of insulating material 108. In at least one embodiment, exposed portions of copper seed layer 320 and underlying adhesion layer 310, e.g., portions of copper seed layer 320 and underlying adhesion layer 310 not covered by one or more interconnects 110a-c, may be removed, for example, by a wet or dry etching process. For example, in a dry etching process, one or more interconnects 110a-c may be used as a mask to direct reactants toward copper seed layer 320 and underlying adhesion layer 310. In another embodiment, the copper seed layer 320 and the underlying adhesion layer 310 may be sprayed or otherwise contacted with an etchant solution to remove exposed portions of the copper seed layer 320 and the underlying adhesion layer 310.

[0049] In at least one embodiment, the etchant solution includes copper sulfate, sulfuric acid, and DI water. The etchant solution can include about 0.5M to about 1.5M CuSO4·5H2O and about 0.02M to 2M H2SO4. In one example, the etchant solution includes 5g of CuSO4·H2O, 2ml of H2SO4, and 100ml of water, and the copper seed layer 320 and adhesion layer 310 are exposed to the etchant solution for 12 to 14 minutes. The etchant solution removes the copper seed layer 320 and adhesion layer 310 at a faster rate than the copper of the interconnects 110a-c.

[0050] Reference is made to particular features (including method operations) of the present disclosure in the Summary of the Invention, the Detailed Description, and the Claims, as well as in the accompanying drawings. It is to be understood that the disclosure herein includes all possible combinations of such particular features. For example, if a particular feature is disclosed in a particular aspect, embodiment, or example of the present disclosure, or in the context of a particular claim, that feature can also be used, to the extent possible, in combination with and / or in the context of other particular aspects and embodiments of the present disclosure, and in the present disclosure generally.

[0051] The term "comprises" and its grammatical equivalents are used herein to mean the optional presence of other elements, ingredients, operations, etc. For example, an article "comprising" (or "which comprises") elements A, B, and C can consist of (i.e., include only) elements A, B, and C, or it can include not only elements A, B, and C, but also one or more other elements. Furthermore, whenever a composition, element, or group of elements is preceded by the transitional phrase "comprising," or its grammatical equivalent, it is understood that the same composition or group of elements can also be preceded by the transitional phrase "consisting essentially of," "consisting of," "selected from the group of consisting of," or "is," and vice versa, and vice versa.

[0052] When reference is made herein to a method including two or more defined operations, the defined operations may be performed in any order or simultaneously (unless the context excludes this possibility), and the method may include one or more other actions performed before any of the defined operations, between two of the defined operations, or after all of the defined operations (unless the context excludes this possibility).

[0053] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.

[0054] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. depositing an adhesion layer on a polymer surface by an electroless deposition process, the polymer surface defining a sidewall of a through-hole via, the adhesion layer comprising a cobalt alloy or a nickel alloy; depositing a copper seed layer on the adhesion layer by an immersion plating process, the copper seed layer replacing a portion of the adhesion layer; filling the through-hole via with a copper-containing layer; A method for manufacturing a semiconductor device, comprising:

2. 10. The method of claim 1, further comprising exposing the polymer surface to a heat treatment process prior to depositing the adhesion layer, wherein the heat treatment process comprises exposing the polymer surface to heat at a temperature in the range of about 100°C to about 150°C.

3. exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride; exposing the polymer surface to a catalytic bath comprising hydrochloric acid, tin chloride, and palladium chloride; exposing the polymer surface to fluoroboric acid; 3. The method of claim 2, further comprising exposing the polymer surface to an activation process prior to the heat treatment process, comprising:

4. The method of claim 1 , wherein the electroless deposition process comprises exposing the polymer surface to an electroless deposition solution comprising a nickel sulfate solution, a sodium hypophosphite solution, and water.

5. The method of claim 4, wherein the electroless deposition solution is heated to a temperature in the range of about 80°C to about 90°C.

6. 2. The method of claim 1, wherein the portion of the adhesion layer replaced by the copper seed layer is about 10 to about 30% of the original thickness of the adhesion layer.

7. The method of claim 1 , wherein the adhesion layer comprises NiP, NiWP, CoP, or CoWP.

8. 8. The method of claim 7, wherein the polymer surface comprises polybenzoxazole (PBO), polyimide, polyimide derivatives, epoxy resin, prepreg (PP) material, or a combination thereof.

9. providing a substrate including an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole via coupling the first major surface and the second major surface; depositing an adhesion layer on the insulating material by an electroless deposition process, the insulating material defining a sidewall of the through-hole via, the adhesion layer comprising a cobalt alloy or a nickel alloy; depositing a copper seed layer on the adhesion layer by an immersion plating process, the copper seed layer replacing a portion of the adhesion layer; forming a photoresist layer on the copper seed layer formed on at least the first major surface; patterning the photoresist to form an opening through the photoresist layer, the opening exposing the copper seed layer formed along the sidewall of the through-hole via; filling the through-hole via and the opening with a copper-containing layer to form an interconnect structure; A method for manufacturing a semiconductor device, comprising:

10. 10. The method of claim 9, further comprising removing the photoresist to expose the adhesion layer and the copper seed layer formed on at least the first major surface.

11. 11. The method of claim 10, further comprising removing the adhesion layer and the copper seed layer from the first major surface by an etching process, wherein the etching process removes the copper seed layer and the adhesion layer at a faster rate than the copper of the interconnect structure.

12. The method of claim 11 , wherein the etching process comprises exposing the adhesion layer and the copper seed layer to an etchant solution comprising copper sulfate and sulfuric acid.

13. The etching process comprises etching the adhesion layer and the copper seed layer with about 0.5M to about 1.5M CuSO 4 ・5H 2 O and about 0.02M to 2M H 2 SO 4 The method of claim 11 , comprising exposing the surface of the substrate to an etchant solution comprising:

14. 10. The method of claim 9, further comprising exposing the polymer surface to a heat treatment process prior to depositing the adhesion layer, wherein the heat treatment process comprises exposing the polymer surface to heat at a temperature in the range of about 100°C to about 150°C.

15. exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride; exposing the polymer surface to a catalytic bath comprising hydrochloric acid, tin chloride, and palladium chloride; exposing the polymer surface to fluoroboric acid; 15. The method of claim 14, further comprising exposing the polymer surface to an activation process prior to the heat treatment process, comprising:

16. a substrate comprising an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole via coupling the first major surface and the second major surface; an adhesion layer formed on the insulating material defining a sidewall of the through-hole via, the adhesion layer comprising a cobalt alloy or a nickel alloy; a copper seed layer formed on the adhesion layer; a copper interconnect extending through the entire thickness of the substrate, filling the through-hole via and extending beyond both the first major surface and the second major surface; A semiconductor device comprising:

17. 17. The semiconductor device of claim 16, wherein the adhesion layer comprises NiP, NiWP, CoP, or CoWP.

18. 20. The semiconductor device of claim 17, wherein the polymer surface comprises polybenzoxazole (PBO), polyimide, polyimide derivatives, epoxy resin, prepreg (PP) material, or a combination thereof.

19. 20. The semiconductor device of claim 18, wherein the substrate further comprises a semiconductor die encapsulated by the insulating material.

20. 20. The semiconductor device of claim 19, wherein the substrate is part of a three-dimensional multi-chip module.

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