LDMOS devices

Abstract

The present disclosure provides an LDMOS device. [Solution] The LDMOS device includes a substrate structure, a drift region located vertically within the substrate structure, a field plate structure located vertically above the substrate structure, a portion of the field plate structure, the projection of which on the substrate structure covers a portion of the drift region, and a drain region located vertically within the substrate structure, wherein electric field lines of at least a portion of the drain region connected to a high voltage converge toward the field plate structure and terminate at the field plate structure.

Description

[Technical Field]

[0001] This disclosure claims priority to a patent application filed on December 28, 2022, bearing application number 202211698844.9 and entitled "LDMOS terminal structure and method for manufacturing LDMOS terminal structure," and a patent application filed on December 28, 2022, bearing application number 202211697140.X and entitled "Sic-LDMOS device," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor power devices, and in particular to LDMOS devices. [Background technology]

[0003] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is currently widely used in infrastructure that supports social development and daily life, such as industrial equipment, scientific instruments, and medical equipment. For high-voltage LDMOS devices, a rational terminal design is important for achieving high device breakdown voltage and improving device robustness. Summary of the Invention [Problem to be solved by the invention]

[0004] In the plan view of a conventional SiC-LDMOS device, as shown in Figure 1, the intrinsic region is to the left of the dashed line and the termination region is to the right of the dashed line. The source region forms the intrinsic region, and the gate electrode surrounds the edge of the source region. The drain region surrounds the edge of the gate electrode in the termination region. The electric field lines in the drain region of the termination region are concentrated inward, i.e., the electric field lines are concentrated inward at the gate electrode. This results in a higher electric field strength in the termination region than in the intrinsic region. This results in the actual breakdown voltage of the SiC-LDMOS device being much lower than that of the intrinsic region. Furthermore, the termination region of the SiC-LDMOS device breaks down earlier than the intrinsic region, resulting in a lower actual breakdown voltage (BV) of the SiC-LDMOS device. The electric field strength of SiC-LDMOS devices is much higher than that of silicon-doped LDMOS devices. Therefore, a solution is needed to address the technical issue of the termination region of conventional SiC-LDMOS devices breaking down earlier than the intrinsic region.

[0005] There are three main layouts for high-voltage LDMOS devices: circular, racetrack, and interdigitated. While circular and racetrack layouts are primarily used for high-voltage devices with low pass currents, LDMOS devices that require high currents generally use interdigitated layouts due to their long overall gate length. This results in the drain wrapping around the source at the interdigitated termination. When a high voltage is applied to the drain, the wrapping around the source causes the electric field to converge toward the source, resulting in early breakdown in this area and a low breakdown voltage for the LDMOS device. As a result, the overall breakdown voltage of the LDMOS device does not reach its ideal design value. Therefore, for high-voltage LDMOS devices, especially those requiring high-current operation using an interdigitated layout, how to ensure a high breakdown voltage for the LDMOS device, improve the breakdown voltage in this area, and ultimately ensure good robustness for the high-voltage LDMOS device, is another urgent issue in the LDMOS device field. [Means for solving the problem]

[0006] The main objective of the present disclosure is to provide an LDMOS device to solve the above technical problems.

[0007] According to one aspect of an embodiment of the present disclosure, there is provided an LDMOS device including: a substrate structure; a drift region located within the substrate structure in a vertical direction; a field plate structure located above the substrate structure in the vertical direction, a portion of the field plate structure, a projection of which on the substrate structure covers a portion of the drift region; and a drain region located within the substrate structure in the vertical direction, wherein electric field lines of at least a portion of the drain region connected to a high voltage converge toward the field plate structure and terminate at the field plate structure.

[0008] Optionally, the field plate structure is used to prevent degradation of the breakdown voltage effect of the epitaxial layer lateral breakdown voltage region.

[0009] Optionally, the drain region is formed laterally outside the drift region, and the LDMOS device further includes: a gate electrode located above the substrate structure in the vertical direction and spanning an intrinsic region and an termination region of the LDMOS device in the lateral direction; and a dielectric layer that is an insulating dielectric filled between the gate electrode and the drain region, the drift region being formed outside an outer edge of the gate electrode in the lateral direction and spanning the intrinsic region and the termination region, and the field plate structure is connected above and spanning the gate electrode and the drift region, respectively, in the vertical direction, surrounding the outer edge of the gate electrode in the lateral direction and spanning the intrinsic region and the termination region.

[0010] Optionally, the substrate structure includes a substrate and an epitaxial layer overlying the substrate, the drift region formed in the epitaxial layer, the epitaxial layer having a distance between the drift region and an outer edge of the gate electrode exposing an epitaxial layer lateral breakdown voltage region, the epitaxial layer lateral breakdown voltage region being a portion of the epitaxial layer located between the gate electrode and the drift region, and the LDMOS device further includes a source region extending in the vertical direction. a source region formed in the epitaxial layer in a direction perpendicular to the source line, the source region including a first end portion of the source region being a boundary between the intrinsic region and the termination region, wherein a distance is provided between the epitaxial layer lateral breakdown voltage region and an outer edge of the source region such that the epitaxial layer lateral breakdown voltage region does not extend into the intrinsic region and is located only in the termination region, the side of the epitaxial layer lateral breakdown voltage region remote from the source region is located below the field plate structure, and the drift region and the drain region are formed in the epitaxial layer.

[0011] Optionally, the gate electrode is a racetrack gate electrode, the shape of the epitaxial layer lateral breakdown voltage region is a portion of a racetrack and surrounds an outer edge of the gate electrode located in the termination region, and the drift region surrounds outer edges of the gate electrode and the epitaxial layer lateral breakdown voltage region.

[0012] Optionally, the field plate structure includes a Z-shaped first field plate, an upper lateral arm of the first field plate spaced apart from an upper surface of the gate electrode, a vertical arm of the first field plate spaced apart from the gate electrode, and a lower lateral arm of the first field plate spaced apart from an upper surface of the drift region.

[0013] Optionally, the field plate structure further includes a Z-shaped second field plate, the upper lateral arms of the second field plate being spaced above the upper lateral arms of the first field plate in a partially stacked manner.

[0014] Optionally, the LDMOS device further includes a first-layer body region and a second-layer body region formed from top to bottom, wherein the doping concentrations of the first-layer body region and the second-layer body region increase sequentially from top to bottom, and a body region contact region, wherein the body region contact region, the source region, and the first-layer body region are provided in the same layer in the lateral direction, and the second-layer body region is formed below the body region contact region, the source region, and the first-layer body region in the vertical direction.

[0015] Optionally, the LDMOS device further comprises a drift buffer region located within the drift region in the vertical direction and surrounding the drain region.

[0016] Optionally, the LDMOS device further includes a backside metal formed on a bottom surface of the substrate; two first metal layers, one first metal layer overlying the source region and one first metal layer overlying the drain region; a first through hole and metal filled in the first through hole, connecting the source region and the body region contact region with the first metal layer over the source region; a second through hole and metal filled in the second through hole, connecting the drain region with the first metal layer over the drain region; and a third through hole and metal filled in the third through hole, connecting the backside metal, the substrate, the epitaxial layer, and the second layer body region with the first metal layer over the source region.

[0017] Optionally, the LDMOS device further includes a fourth through hole and metal filled in the fourth through hole, the fourth through hole connecting the first metal layer above the source region to an upper lateral arm of the first field plate, wherein the upper lateral arm of the first field plate is spaced apart from an upper surface of the gate electrode, the vertical arm of the first field plate is spaced apart from the gate electrode, and the lower lateral arm of the first field plate is spaced apart from an upper surface of the drift region.

[0018] Optionally, the gate electrode, the source region and the drain region are coplanar.

[0019] Optionally, the substrate structure includes a substrate and an epitaxial layer located on a surface of the substrate, and the LDMOS device further includes a third layer body region, the third layer body region being spaced apart from the drift region in the epitaxial layer, the epitaxial layer and the third layer body region having the same doping type, the drift region and the epitaxial layer having a different doping type, and the drift region having a doping concentration greater than that of the epitaxial layer, and the field plate structure includes a field plate body and a field plate region located on one side of the field plate body. and an arcuate field plate having a third layer body region, the field plate body being in contact with the arcuate field plate; the field plate structure having a fifth through hole located between the field plate body and the arcuate field plate; a projection of the arcuate field plate in the epitaxial layer covering a portion of the drift region; a projection of the field plate body in the epitaxial layer covering a portion of the third layer body region; and a projection of the epitaxial layer between the third layer body region and the drift region in the field plate structure located within the fifth through hole.

[0020] Optionally, the drain region is located in the drift region, a surface of the drain region facing away from the substrate being flush with a surface of the drift region facing away from the substrate, and the drain region has the same doping type as the drift region, and the LDMOS device further includes a source region, the source region is located in the body region, a surface of the source region facing away from the substrate being flush with a surface of the epitaxial layer facing away from the substrate, and the source region has a different doping type than the body region; a source electrode, the source electrode being located on a portion of the surface of the source region facing away from the substrate; and a drain electrode, the drain electrode being located on a portion of the surface of the drain region facing away from the substrate.

[0021] Optionally, the LDMOS device further includes: a gate oxide layer located on a surface of a portion of the epitaxial layer, the gate oxide layer covering a portion of the body region and a portion of the epitaxial layer, and the gate oxide layer not in contact with the source region; a gate electrode located on a surface of the gate oxide layer remote from the epitaxial layer, and projections of the gate oxide layer and the gate electrode on the field plate structure located in the fifth through hole; and a dielectric layer covering the gate oxide layer, the gate electrode, and the surface of the epitaxial layer remote from the substrate, the surface of the dielectric layer remote from the epitaxial layer being planar, the source electrode and the drain electrode passing through the dielectric layer, and the field plate structure located on the surface of the dielectric layer remote from the substrate.

[0022] Optionally, the epitaxial layer is located on a surface of a portion of the substrate, and the LDMOS device further includes a second metal layer located on a surface of another portion of the substrate, the surface of the second metal layer facing away from the substrate being flush with the surface of the dielectric layer facing away from the substrate, the second metal layer being used to electrically connect the source region and the substrate, and the field plate structure being in contact with the second metal layer.

[0023] Optionally, the LDMOS device further includes a third metal layer located on a surface of a portion of the dielectric layer remote from the substrate, the third metal layer in contact with the drain electrode, the third metal layer spaced apart from the field plate structure, and the third metal layer and the field plate structure exposing a portion of the dielectric layer.

[0024] Optionally, the doping type of the epitaxial layer is P-type and the doping type of the drift region is N-type.

[0025] The technical solution of the present disclosure can achieve the following technical effects: 1) The field plate structure is installed not only in the intrinsic region but also in the termination region, and the field plate structure is connected vertically above the gate electrode and the drift region. In this way, the electric field lines of the drain region, which is connected to a high voltage, converge toward the field plate structure and terminate at the field plate structure in both the termination region and the intrinsic region. This reduces the drop in the electric field lines in the termination region and the risk of breakdown of the first oxide layer. At the same time, the difference in the drop in the electric field lines between the termination region and the intrinsic region is reduced, thereby reducing the difference in the electric field strength between the termination region and the intrinsic region. This reduces the difference between the actual breakdown voltage of the SiC-LDMOS device in the termination region and the actual breakdown voltage of the intrinsic region. This prevents early breakdown of the SiC-LDMOS device in the termination region and increases the actual breakdown voltage BV of the SiC-LDMOS device. 2) The substrate includes the substrate, the epitaxial layer, the body region, and the drift region, and the LDMOS device further includes the field plate structure, the field plate structure including the field plate main body and the arc-shaped field plate, the projection of the arc-shaped field plate on the substrate covers a portion of the drift region, and the field plate structure optimizes the electric field distribution in the drift region. Furthermore, the projection of the field plate structure on the epitaxial layer between the body region and the drift region is located within the first through-hole, i.e., the field plate structure skeletonizes a portion of the epitaxial layer, reducing the effect of the field plate structure on the electric field in the epitaxial layer, thereby optimizing the electric field distribution of the LDMOS device, thereby ensuring a high breakdown voltage of the LDMOS device and good performance of the semiconductor device. [Brief explanation of the drawings]

[0026] The drawings in the specification, which form a part of the present disclosure, are used to have a further understanding of the present disclosure, and the exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and are not intended to constitute an undue limitation of the present disclosure. [Figure 1] FIG. 1 is a plan view showing a conventional SiC-LDMOS device. [Figure 2] FIG. 1 is a plan view illustrating a SiC-LDMOS device according to an embodiment of the present disclosure. [Figure 3] 13 shows a cross-sectional view taken along line AA in FIG. 12. [Figure 4] FIG. 10 is a schematic diagram illustrating a structure after forming a preliminary gate electrode according to one embodiment of the present disclosure. [Figure 5] FIG. 2 is a schematic diagram illustrating a structure after forming a gate oxide layer and a gate electrode according to one embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram illustrating a structure after forming a substrate by implantation according to one embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram illustrating a structure after forming a pre-dielectric layer according to one embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram illustrating a structure after forming a second through hole, a third through hole, and a fourth through hole according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram illustrating a structure after forming a source, drain, and first metal layer according to one embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram illustrating a structure after forming a preliminary field plate structure according to one embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic diagram illustrating the structure of an LDMOS device according to one embodiment of the present disclosure. [Figure 12] FIG. 1 is a schematic plan view illustrating a structure of an LDMOS device according to an embodiment of the present disclosure. [Figure 13] FIG. 1 is a schematic diagram of a flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] The features in the examples and embodiments of the present disclosure may be combined with each other unless they conflict.The present disclosure will now be described in detail in connection with the examples with reference to the accompanying drawings.

[0028] In order to allow those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, but it is clear that the described embodiments are only some embodiments of the present disclosure, and are not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present disclosure without any creative efforts shall fall within the protection scope of the present disclosure.

[0029] The terms "first," "second," etc. in the specification and claims of this disclosure, as well as in the above-described drawings, are used to distinguish between similar objects without necessarily being used to describe a particular order or priority. It should be understood that the terms used in this manner can be interchanged where appropriate to describe the embodiments of the present disclosure. Furthermore, the terms "comprise" and "have" may refer to, for example, processes, methods, systems, products, or apparatuses that include a series of steps or units, and may include other steps or units inherent in those processes, methods, products, or apparatuses, rather than those explicitly recited.

[0030] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, it is understood that the element can be directly on the other element, or there can be intermediate elements present. Furthermore, in this specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or it can be "connected" to the other element by a third element.

[0031] To solve the technical problems described in the background, exemplary embodiments of the present disclosure provide an LDMOS device.

[0032] As shown in FIGS. 2 and 3, the SiC-LDMOS device according to the embodiment of the present disclosure has A substrate; a gate electrode 218 positioned vertically above the substrate and laterally spanning the intrinsic and termination regions of the LDMOS device, with the intrinsic region being to the left of the dashed line in FIG. 2 and the termination region being to the right of the dashed line; a drift region 26 located vertically within the substrate and laterally outside the outer edges of the gate electrode 218, spanning the intrinsic and termination regions; a drain region 23 formed vertically within the substrate and laterally outside the drift region 26; a dielectric layer, the dielectric layer being an insulating dielectric between all semiconductors and metals filled between the gate electrode 218 and the drain region 23; a field plate structure connected to and spanning above the gate electrode 218 and the drift region 26 in the vertical direction, surrounding the outer edge of the gate electrode 218 in the lateral direction, and spanning the intrinsic region and the termination region; Here, the electric field lines of the drain region connected to a high voltage converge towards the field plate structure and terminate at the field plate structure.

[0033] In the SiC-LDMOS device according to the embodiment of the present disclosure, a field plate structure is provided not only in the intrinsic region but also in the termination region, and the field plate structure extends vertically above the gate electrode 218 and the drift region 26. In this way, the electric field lines of the drain region connected to a high voltage are concentrated in the field plate structure and terminate at the field plate structure in both the termination region and the intrinsic region. This reduces the distance the electric field lines fall in the termination region, thereby reducing the risk of breakdown of the dielectric layer. Furthermore, this reduces the difference in the distance the electric field lines fall between the termination region and the intrinsic region, thereby reducing the difference in the electric field strength between the termination region and the intrinsic region. Consequently, the difference between the actual breakdown voltage of the SiC-LDMOS device's termination region and the actual breakdown voltage of the intrinsic region is reduced, preventing early breakdown of the SiC-LDMOS device's termination region and increasing the actual breakdown voltage BV of the SiC-LDMOS device.

[0034] Specifically, the vertical direction is the thickness direction of the SiC-LDMOS device, and corresponds to the up-and-down direction in Figure 3. The horizontal direction is the direction of a plane perpendicular to the vertical direction, and corresponds to the direction perpendicular to the paper surface in Figure 3.

[0035] Specifically, the substrate is a silicon carbide (chemical formula: SiC) substrate, and the gate electrode 218 is a polycrystalline silicon gate electrode.

[0036] Specifically, as shown in FIG. 3, a gate oxide layer 21 is formed under the gate electrode 218. The gate oxide layer 21 is a silicon dioxide gate oxide layer 21, and the gate oxide layer 21 is an insulating dielectric between the semiconductor as the source region 22 and the metal as the gate electrode 218. The gate oxide layer 21 is part of the dielectric layer. The field plate structure is also a metal structure, and an insulating dielectric is also formed around the field plate structure. The dielectric layer also includes an insulating dielectric filled between the drain region 23 and the first metal layer 210. That is, the dielectric layer is filled between all semiconductors and metals between the gate electrode 218 and the drain region 23.

[0037] In the embodiment, the gate electrode 218, the source region 22, and the drain region 23 are located in the same plane. That is, the SiC-LDMOS device according to the embodiment of the present disclosure is a SiC-LDMOS device with a planar structure, and is particularly suitable for a high-voltage SiC-LDMOS device with a planar structure.

[0038] 2 and 3, a first doping type substrate 216 is formed below the substrate, and a first doping type epitaxial layer 215 is formed above the substrate. The drift region 26 is formed within the epitaxial layer, and the drift region 26 is spaced apart from the outer edge of the gate electrode 218 to expose an epitaxial layer lateral breakdown voltage region 215-1. The epitaxial layer lateral breakdown voltage region 215-1 is a portion of the epitaxial layer between the gate electrode 218 and the drift region 26.

[0039] The SiC-LDMOS device further a source region (22) formed vertically within the epitaxial layer, the source region (22) having a first end that defines a boundary between the intrinsic region and the termination region; Here, the epitaxial layer lateral breakdown voltage region 215-1 is spaced apart from the outer edge of the source region, the epitaxial layer lateral breakdown voltage region 215-1 is located only in the termination region and does not extend into the intrinsic region, the epitaxial layer lateral breakdown voltage region 215-1 is located below the field plate structure toward the drift region, and the drift region and the drain region are formed within the epitaxial layer.

[0040] The epitaxial layer lateral breakdown voltage region is located only in the termination region and does not extend into the intrinsic region. The reason why the left side of the epitaxial layer lateral breakdown voltage region 215-1 does not extend into the intrinsic region, as shown in Figure 2, is that extending the epitaxial layer lateral breakdown voltage region into the intrinsic region would improve the on-resistance of the SiC-LDMOS device. We propose that the source region does not extend into the termination region annulus. If the source region did extend into the termination region annulus, the termination region would also be conductive during operation of the SiC-LDMOS device. On the other hand, the termination region is required to be non-conductive and only provide breakdown voltage.

[0041] The side of the epitaxial lateral breakdown region away from the source region is located below the field plate structure, i.e., the field plate structure covers the epitaxial lateral breakdown region at its edge toward the drain region. This method further increases the breakdown voltage of the SiC-LDMOS device termination region. The principle is to utilize the strong junction field of the PN junction formed by the epitaxial lateral breakdown region and the drift region to increase the electric field strength in the region near this PN junction, thereby further improving the breakdown capability of the SiC-LDMOS device termination region.

[0042] The field plate structure is used to prevent a decrease in the breakdown voltage effect of the epitaxial layer lateral breakdown voltage region.

[0043] The drift region does not completely surround the outer edge of the gate electrode. Instead, it does not form a drift region at the epitaxial layer lateral breakdown region, but instead exposes part of the epitaxial layer. This means that the drift region has a specific shape in the termination region. The epitaxial layer lateral breakdown region acts as an additional termination breakdown region, carrying more voltage and forming a lateral PP-NN junction. The formation of the body contact region / epitaxial layer lateral breakdown region / drift buffer / drain region helps to relax the electric field distribution, thereby solving the problem of BV reduction due to the electric field concentration effect in the termination region. The principle is that the junction electric field of the abrupt PN junction is strong, which can cause SiC-LDMOS devices to be preferentially destroyed at the junction interface. The reason why the epitaxial layer lateral breakdown voltage region must not extend beyond the edge of the field plate structure in the direction of the drain region is that if it does extend outside the field plate structure, the PN junction electric field in this case will be concentrated at the edge perpendicular to the drift region because the field plate structure does not distribute the electric field lines, which can cause a strong electric field concentration at the edge, potentially leading to early device destruction. On the other hand, by locating the lateral breakdown voltage region within the edge of the field plate structure, the electric field strength at the PN junction interface will not be much higher than at the edge of the field plate structure.

[0044] In an embodiment, as shown in FIG. 2, the portion of the gate electrode 218 located in the termination region is semi-annular.

[0045] The epitaxial layer lateral breakdown withstanding region 215-1 has a semi-annular shape and surrounds the outer edge of the gate electrode 218 located in the termination region.

[0046] The drift region 26 surrounds the outer edges of the gate electrode 218 and the epitaxial layer lateral breakdown breaking region 215-1.

[0047] The portion of the gate electrode 218 located in the termination region is semicircular, and the epitaxial layer lateral breakdown region 215-1 is also semicircular. This semicircular structure effectively mitigates the electric field concentration effect at the edge of the gate electrode in the termination region. The principle is similar to tip discharge: the sharper the structure, the more likely it is that charge concentration induced by an external high potential will occur, and the resulting high electric field may destroy the dielectric in this area. The semicircular structure effectively mitigates the tip charge concentration phenomenon, making it more difficult for dielectric breakdown and semiconductor avalanche breakdown to occur in the termination region.

[0048] As shown in FIGS. 2 and 3, the field plate structure includes: a Z-shaped first field plate 28, an upper lateral arm of the first field plate spaced apart from the upper surface of the gate electrode 218, a vertical arm of the first field plate spaced apart from the gate electrode, and a lower lateral arm of the first field plate 28 spaced apart from the upper surface of the drift region 26;

[0049] The first field plate disperses the high electric field strength at the edge of the gate electrode, reducing the risk of breakdown of the dielectric layer and improving the reliability of the dielectric layer.

[0050] In an embodiment, the field plate structure comprises: and a Z-shaped second field plate, the upper lateral arm of the second field plate being spaced above the upper lateral arm of the first field plate so as to be partially stacked.

[0051] The first and second field plates, in this multi-layer field plate installation method, disperse the high electric field strength at the edges of the gate electrode, reducing the risk of dielectric layer breakdown and improving the reliability of the dielectric layer.

[0052] In an embodiment, the SiC-LDMOS device further comprises: a first layer body region 24 and a second layer body region 214 formed from top to bottom, the doping concentrations of the first layer body region 24 and the second layer body region 214 increasing from top to bottom; and a body region contact region 25, wherein the body region contact region 25, the source region, and the first-layer body region are provided in the same layer in the lateral direction, and the second-layer body region 214 is formed below the body region contact region 25, the source region, and the first-layer body region in the vertical direction.

[0053] The channel is located between the source and drain regions and below the gate electrode. The first and second body regions 24 and 214 are formed at the channel from top to bottom. The doping concentrations of the first and second body regions 24 and 214 increase from top to bottom, i.e., the first body region 24 has a low doping concentration and the second body region 214 has a high doping concentration. The low doping concentration of the first body region 24 allows the threshold voltage VT to be adjusted within a reasonable range. The low doping concentration of the first body region 24 prevents further reduction in mobility due to carrier scattering caused by channel doping, thereby improving channel mobility. The high doping concentration of the second layer body region 214 reduces the electric field strength of the PN junction (the PN junction formed by the source region and the structure between the source region and the drain region) at the edge of the channel at high voltage, preventing the depletion region from excessively extending into the source region of the second doping type, suppressing the expansion of the depletion region, and preventing the short channel from being penetrated at high voltage, thereby increasing the breakdown voltage BV.

[0054] In an embodiment, as shown in FIG. 3, the SiC-LDMOS device further comprises: A drift buffer 27 is included, the drift buffer 27 being located vertically within the drift region 26 and surrounding the drain region 23 .

[0055] In an embodiment, as shown in FIG. 3, the SiC-LDMOS device further comprises: a backside metal 217 formed on the underside of the first doping type substrate 216; two first metal layers 210, one first metal layer 210 located above the source region and one first metal layer 210 located above the drain region; a first through hole 211 and a metal filled in the first through hole, the metal connecting the source region and the body region contact region with a first metal layer above the source region; a second through hole 212 and a metal filled in the second through hole, the second through hole connecting the drain region to a first metal layer above the drain region; a third through hole 213 and a metal filled in the third through hole, the third through hole 213 and the metal filled in the third through hole connecting the backside metal 217, the first doping type substrate 216, the epitaxial layer 215 and the second layer body region 214 with a first metal layer above the source region.

[0056] In an embodiment, as shown in FIG. 3, the SiC-LDMOS device further comprises: a fourth through-hole (29) and a metal filled in the fourth through-hole, wherein an upper lateral arm of the first field plate (28) is spaced apart from an upper surface of the gate electrode, a vertical arm of the first field plate (28) is spaced apart from the gate electrode, and a lower lateral arm of the first field plate (28) is spaced apart from an upper surface of the drift region;

[0057] In an embodiment, the gate electrode 218, the source region 22 and the drain region 23 are located in the same plane, as shown in Figure 3. The source region is grounded and the drain region is connected to an operating voltage, and applying different voltages to the gate electrode controls the switching of the device.

[0058] According to one aspect of the present disclosure, an LDMOS device is provided, and as shown in Figures 11 and 12, the LDMOS device includes a substrate 10 and a field plate structure 20. Here, the substrate 10 includes a substrate 101, an epitaxial layer 102, a third-layer body region 103, and a drift region 104, the epitaxial layer 102 is located on a surface of the substrate 101, the third-layer body region 103 is spaced apart from the drift region 104 in the epitaxial layer 102, the epitaxial layer 102 and the third-layer body region 103 have the same doping type, and the drift region 104 and the epitaxial layer 102 have the same doping type. The doping type of the drift region 104 is different from that of the epitaxial layer 102, and the doping concentration of the drift region 104 is greater than that of the epitaxial layer 102. The field plate structure 20 is located on a side of the epitaxial layer 102 away from the substrate 101, and the field plate structure 20 includes a field plate body 201 and an arc-shaped field plate 202 located on one side of the field plate body 201. The field plate body 201 is arranged in contact with the arc-shaped field plate 202, and the field plate structure 20 has a fifth through hole 203, which is located between the field plate body 201 and the arc-shaped field plate 202, a projection of the arc-shaped field plate 202 in the epitaxial layer covers a portion of the drift region 104, a projection of the field plate body 201 in the epitaxial layer 102 covers a portion of the third-layer body region 103, and a projection of the epitaxial layer 102 between the third-layer body region 103 and the drift region 104 in the field plate structure 20 is located within the fifth through hole 203.

[0059] The LDMOS device includes a substrate and a field plate structure, wherein the substrate includes a substrate, an epitaxial layer, a third-layer body region, and a drift region, the epitaxial layer is stacked with the substrate, the third-layer body region is spaced apart from the drift region in the epitaxial layer, the epitaxial layer and the third-layer body region have the same doping type, the drift region and the epitaxial layer have different doping types, and the drift region has a higher doping concentration than the epitaxial layer, the field plate structure is located on a side of the epitaxial layer away from the substrate, and the field plate structure includes a field plate body and an arc-shaped field plate located on the field plate body side, and the field plate body is located in contact with the arc-shaped field plate. The field plate structure also has a fifth through hole, the fifth through hole being formed by surrounding the field plate body and the arc-shaped field plate, the projection of the arc-shaped field plate in the epitaxial layer covering a portion of the drift region, the projection of the field plate body in the epitaxial layer covering a portion of the third-layer body region, and the projection of the epitaxial layer between the third-layer body region and the drift region in the field plate structure being located within the fifth through hole. In response to the problem of poor device performance due to low breakdown voltage in prior art devices, the LDMOS device of the present disclosure provides a substrate including the substrate, the epitaxial layer, the third-layer body region, and the drift region, and further includes the field plate structure, the field plate structure including the field plate body and the arc-shaped field plate. The projection of the arc-shaped field plate in the epitaxial layer covers a portion of the drift region, so that the field plate structure can optimize the electric field distribution in the drift region.Furthermore, the projection of the field plate structure of the epitaxial layer between the third-layer body region and the drift region is located within the fifth through-hole, i.e., the field plate structure skeletonizes a portion of the epitaxial layer, reducing the effect of the field plate structure on the electric field of the epitaxial layer. This in turn optimizes the electric field distribution of the LDMOS device, ensuring a high breakdown voltage for the LDMOS device and good performance for the semiconductor device.

[0060] Furthermore, since the third-layer body region is spaced apart from the drift region and the doping concentration of the drift region is greater than that of the epitaxial layer, the epitaxial layer with a lower concentration is present between the third-layer body region and the drift region, and the epitaxial layer and the drift region have different doping types, forming a reverse PN junction between the epitaxial layer and the drift region. This reverse PN junction allows the semiconductor device to withstand voltage, thereby ensuring good electric field distribution and, ultimately, a high breakdown voltage for the semiconductor device, further ensuring good performance of the semiconductor device.

[0061] Specifically, the principle of modulation of the breakdown voltage and the surface electric field of the drift region by the field plate is as follows. As shown in Figure 11, when the doping type of the epitaxial layer 102, the third-layer body region 103, and the source region 105 is P-type, and the doping type of the drift region 104 and the drain region 106 is N-type, and the entire device bears the external breakdown voltage, a positive voltage is applied to the electrode corresponding to the drain 108, and the electrode corresponding to the source 107 and the second metal layer 60 are shorted to ground. In this case, when a positive voltage is applied to the drain 108, electrons in the N region are converged toward the high-potential region of the drain region 106. Similarly, holes in the P region are converged toward the low-potential region of the source region 105. The depletion region at the junction interface between the epitaxial layer 102 and the drift region 104 expands until the spatial integral of the electric field due to fixed charges in the depletion region becomes equal to the externally applied voltage. At this time, the PN junction reaches a reverse-bias equilibrium state at a certain voltage. It should be understood that the strongest point in the overall electric field strength of the reverse-bias junction should appear at the junction interface. In an ideal case where doping is uniform, the electric field strength should decrease linearly from the junction interface to the boundary of the depletion region. The electric field strength on both sides of the junction interface forms a triangle (the dashed triangle in FIG. 11 ), and the area (integral) of the triangle is the reverse-bias voltage that the reverse-bias junction can withstand. Specifically, FIG. 11 is a schematic diagram showing the electric field strength distribution in the N-type region of the drift region 104 and the P-type region of the epitaxial layer 102 along the vertical junction interface. After the ground field plate (the field plate body 201 and the arc-shaped field plate 202) is introduced, it can be assumed that the field plate gradually approaches the drain pole as a low-potential point, which can further concentrate electrons in the drain region 106, i.e., assist in the depletion of the non-depleted region near the drain region 106. Correspondingly, the vertex of the triangular electric field in the drift region 104 is shifted to the right to increase the triangular area, thereby ensuring an increase in the breakdown voltage of the LDMOS device.At the same time, adjusting the height of the field plate, i.e., the distance it is brought closer to the N region, can improve the electric field strength at the position corresponding to the N region, i.e., the side of the triangular electric field near the drain region 106 is raised, similarly increasing the voltage carried by the device. However, as the field plate extends from the drain region 106 across the PN junction interface above the N region, it covers the P region, which reduces the breakdown voltage of the P region. However, the LDMOS device of the present disclosure uses a skeletonized field plate to suppress the effect of the field plate on the reduction in the electric field in the P region. This ensures that the electric field in the P region is not excessively reduced when the electric field in the N region is increased, ensuring a high reverse bias PN junction breakdown voltage for the device equipped with a skeletonized field plate.

[0062] 11 and 12 , the substrate 10 further includes a source region 105, a drain region 106, a source electrode 107, and a drain electrode 108. The source region 105 is located in the third-layer body region 103, and a surface of the source region 105 away from the substrate 101 is flush with a surface of the epitaxial layer 102 away from the substrate 101. The source region 105 and the third-layer body region 103 have different doping types. The drain region 106 is located in the drift region 104, and a surface of the drain region 106 away from the substrate 101 is flush with a surface of the drift region 104 away from the substrate 101. The drain region 106 and the drift region 104 have the same doping type. The source region 107 is located on a portion of the surface of the source region 105 away from the substrate 101. The drain electrode 108 is located on a portion of the surface of the drain region 106 that is away from the substrate 101. Because the substrate further includes the source region, the drain region, the source electrode, and the drain electrode, the source electrode can be led out through the source region, and the drain electrode can be led out through the drain region, ensuring the performance of the LDMOS device, and thus ensuring good performance of the LDMOS device.

[0063] According to another specific embodiment of the present disclosure, as shown in FIGS. 11 and 12 , the LDMOS device further includes a gate oxide layer 30, a gate electrode 40, and a dielectric layer 50. Here, the gate oxide layer 30 is located on a surface of a portion of the epitaxial layer 102. The gate oxide layer 30 covers a portion of the third-layer body region 103 and a portion of the epitaxial layer 102, and the gate oxide layer 30 does not contact the source region 105. The gate electrode 40 is located on a surface of the gate oxide layer 30 away from the epitaxial layer 102. Projections of the gate oxide layer 30 and the gate electrode 40 on the field plate structure 20 are located in the fifth through-hole 203. The dielectric layer 50 covers the surfaces of the gate oxide layer 30, the gate electrode 40, and the epitaxial layer 102 away from the substrate 101, and the surface of the dielectric layer 50 away from the epitaxial layer 102 is flat. The source electrode 107 and the drain electrode 108 penetrate the dielectric layer 50, and the field plate structure 20 is located on the surface of the dielectric layer 50 away from the substrate 101. Since the LDMOS device further includes the gate oxide layer, the gate electrode, and the dielectric layer, the performance of the LDMOS device can be realized by the gate electrode, which in turn ensures good performance of the LDMOS device.

[0064] 11, the surface area of ​​the gate electrode 40 close to the substrate 10 is smaller than the surface area of ​​the gate electrode 40 away from the substrate 10. That is, the corner of the gate electrode close to the substrate is not a right angle, and the gate electrode plays an optimizing role for the electric field of the substrate, which in turn ensures that the breakdown voltage of the semiconductor device is high and further ensures that the performance of the semiconductor device is good.

[0065] To further ensure the performance of the LDMOS device, according to another specific embodiment of the present disclosure, the epitaxial layer is located on a predetermined surface of a portion of the substrate. As shown in Figures 11 and 12, the LDMOS device further includes a second metal layer 60, which is located on a predetermined surface of another portion of the substrate 101, and the surface of the second metal layer 60 away from the substrate 101 is flush with the surface of the dielectric layer 50 away from the substrate 101. The second metal layer 60 is used to electrically connect the source region 105 to the substrate 101. The field plate structure 20 and the second metal layer 60 are in contact with each other. The epitaxial layer is located on the predetermined surface of the portion of the substrate, and the second metal layer is located on the predetermined surface of the other portion of the substrate, i.e., the epitaxial layer is in contact with the second metal layer, and both are located on the substrate. In addition, the second metal layer is used to electrically connect the source region to the substrate, so that the source region can be connected to the substrate through the second metal layer, i.e., can be grounded, and the quality of the LDMOS device can be ensured.

[0066] Specifically, the predetermined surface is a surface of the substrate near the epitaxial layer, the epitaxial layer is located on a surface of one portion of the substrate, the second metal layer is in contact with the epitaxial layer, and the second metal layer is located on the predetermined surface of another portion of the substrate.

[0067] 11 and 12 , the LDMOS device further includes a third metal layer 70. The third metal layer 70 is located on a portion of the surface of the dielectric layer 50 that is away from the substrate 10. The third metal layer 70 contacts the drain electrode 108, the third metal layer 70 is spaced apart from the field plate 20 structure, and the third metal layer 70 and the field plate structure 20 expose a portion of the dielectric layer 50. Because the LDMOS device further includes the third metal layer and the third metal layer contacts the drain electrode, the drain region can be led out through the third metal layer and the drain electrode, i.e., the drain electrode and the drain region can be connected through the third metal layer, thereby ensuring good performance of the LDMOS device.

[0068] According to another embodiment of the present disclosure, the material of the field plate structure includes aluminum. Of course, the field plate structure is not limited to aluminum, and other materials such as tungsten and copper may be selected, and are not limited here.

[0069] To further ensure good performance of the LDMOS device, in yet another embodiment of the present disclosure, the doping type of the epitaxial layer is P-type and the doping type of the drift region is N-type. By forming a reverse PN junction between the P-type epitaxial layer and the N-type drift region, the reverse PN junction can withstand voltage, optimizing the electric field distribution of the LDMOS termination device, ensuring a high breakdown voltage of the LDMOS, and further ensuring good performance of the LDMOS device.

[0070] Specifically, the termination breakdown voltage structure of current LDMOS devices typically involves a reverse PN junction between a heavily P-doped region in the source and an N-type drift region. The main design concept of this drain-wrapped source termination structure is to add a lightly P-doped region between the heavily P-doped region in the source and the N-type drift region in the drain, thereby softening the breakdown voltage of the entire termination. Considering process implementation, this lightly P-doped region is typically implemented in the P-type epitaxial layer itself. However, due to the difference in implantation concentration between the P-type epitaxial layer and the N-type drift region, the electric field strength drops rapidly within the N-type drift region, limiting the improvement of the breakdown voltage of LDMOS devices. The breakdown voltage can be increased by optimizing the surface electric field in the N-type region using a field plate for the reverse PN junction. However, if the field plate is designed to extend into the N-type region, the P-type region is covered. The low potential of the field plate clamps potential lines such as voltage, which in turn reduces the electric field strength in the P-type region and the breakdown voltage capability of the terminal. In the LDMOS device of the present disclosure, by designing the field plate structure including the field plate body and the arc-shaped field plate, the breakdown voltage is supported by the reverse PN junction formed between the P-type epitaxial layer and the N-type drift region, thereby optimizing the termination electric field distribution. On the other hand, the arc-shaped field plate above the N-type drift region optimizes the electric field distribution in the drift region.Furthermore, the projection of the epitaxial layer between the third-layer body region and the drift region onto the field plate structure is located within the fifth through hole, i.e., the portion of the P-type epitaxial layer corresponding to the field plate structure is skeletonized. This reduces the effect of the field plate structure on the electric field of the P-type epitaxial layer, optimizes the electric field in the P-type epitaxial layer region, and further ensures a high breakdown voltage and good performance of the LDMOS device.

[0071] In one specific example, actual potential distribution tests were performed on an LDMOS device formed with a non-skeletonized field plate according to the prior art and an LDMOS device including a skeletonized field plate according to the present disclosure. While the field plate of the prior art LDMOS device can enhance the surface electric field of the NLDD (N-type lightly doped drain region), the equipotential lines are pinned by the zero-potential field plate, resulting in a reduced breakdown voltage in the P-type epitaxial region and preventing the full utilization of the breakdown voltage capability. Actual tests showed that the maximum breakdown voltage of the prior art LDMOS device was 50 V. However, the LDMOS device according to the present disclosure has a skeletonized field plate structure that partially releases the potential lines at the drain end, improving the breakdown voltage of the epitaxial layer without significantly reducing the enhancement of the surface electric field of the NLDD due to the field plate structure (i.e., the skeletonized field plate). Furthermore, actual tests were performed on the electric field distribution maps of the LDMOS device according to the present disclosure and the conventional LDMOS device. Testing has shown that the termination breakdown voltage of the skeletonized field plate structure of the LDMOS device is 59 V. Therefore, compared to conventional non-skeletonized field plate designs, the LDMOS device breakdown voltage of the present disclosure is effectively improved.

[0072] According to an embodiment of the present disclosure, there is further provided a method for fabricating an LDMOS device.

[0073] 13 is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of the present disclosure. As shown in FIG. 13, the method includes the following steps:

[0074] In step S101, as shown in FIG. 6, a substrate 10 is provided, the substrate 10 including a substrate 101, an epitaxial layer 102, a third-layer body region 103, and a drift region 104, the epitaxial layer 102 is located on the surface of the substrate 101, the third-layer body region 103 is spaced apart from the drift region 104 in the epitaxial layer 102, the epitaxial layer 102 and the third-layer body region 103 have the same doping type, the drift region 104 and the epitaxial layer 102 have a different doping type, and the doping concentration of the drift region 104 is greater than the doping concentration of the epitaxial layer 102.

[0075] Step S102, as shown in FIGS. 11 and 12, forms a field plate structure 20 on a side of the epitaxial layer 102 away from the substrate 101, the field plate structure 20 including a field plate body 201 and an arc-shaped field plate 202 located on one side of the field plate body 201, the field plate body 201 being in contact with the arc-shaped field plate 202, the field plate structure 20 including a fifth through hole 203, the fifth through hole 203 being The field plate structure 20 is located between the field plate body 201 and the arc-shaped field plate 202, the projection of the arc-shaped field plate 202 in the epitaxial layer 102 covering a portion of the drift region 104, the projection of the field plate body 201 in the epitaxial layer 102 covering a portion of the third-layer body region 103, and the projection of the epitaxial layer 102 between the third-layer body region 103 and the drift region 104 in the field plate structure 20 is located within the fifth through-hole 203.

[0076] In the method for manufacturing the LDMOS device, first, a substrate is provided, the substrate including a substrate, an epitaxial layer, a third-layer body region, and a drift region, the epitaxial layer is located on a surface of the substrate, the third-layer body region and the drift region are spaced apart in the epitaxial layer, the epitaxial layer and the third-layer body region have the same doping type, the drift region and the epitaxial layer have different doping types, and the doping concentration of the drift region is greater than the doping concentration of the epitaxial layer. a field plate structure is formed on a side of the epitaxial layer away from the substrate, the field plate structure including a field plate body and an arcuate field plate located on one side of the field plate body, the field plate body being in contact with the arcuate field plate; the field plate structure having a fifth through hole located between the field plate body and the arcuate field plate; a projection of the arcuate field plate in the epitaxial layer covering a portion of the drift region; a projection of the field plate body in the epitaxial layer covering a portion of the third layer body region; and a projection of the epitaxial layer between the third layer body region and the drift region in the field plate structure located at the fifth through hole. The method for manufacturing the LDMOS device of the present disclosure provides the substrate including the substrate, the epitaxial layer, the third-layer body region, and the drift region, and also forms the field plate structure on a side of the epitaxial layer away from the substrate, the field plate structure including the main field plate portion and the arc-shaped field plate, such that a projection of the arc-shaped field plate on the epitaxial layer covers a portion of the drift region, thereby optimizing the electric field distribution in the drift region by the field plate structure.Furthermore, the projection of the field plate structure of the epitaxial layer between the third-layer body region and the drift region is located at the fifth through-hole, i.e., the field plate structure skeletonizes a portion of the epitaxial layer, thereby minimizing the effect of the field plate structure on the electric field in the epitaxial layer, thereby optimizing the electric field distribution of the LDMOS device, ensuring a high breakdown voltage of the LDMOS device, and further ensuring good performance of the semiconductor device.

[0077] Specifically, compared with the prior art, the process of forming the substrate and the field plate structure does not require additional design or additional process steps, and only requires the field plate structure to be skeletonized during the manufacturing process of the LDMOS device, ensuring high and simple process integration of the LDMOS device.

[0078] In one specific embodiment, the breakdown voltage of the LDMOS device can be increased by adjusting the position of the field plate structure and / or the width of the fifth through hole according to actual needs.

[0079] One specific embodiment of the present disclosure provides a substrate, and as shown in FIG. 4, provides a laminated substrate 101 and an epitaxial layer 102; as shown in FIG. 5, forms a gate oxide layer 30 on a surface of the epitaxial layer 102 away from the substrate 101; and forms a gate electrode 40 on a surface of the gate oxide layer 30 away from the substrate 101; and as shown in FIG. 6, performs ion implantation into the epitaxial layer 102 on both sides of the gate oxide layer 30 and the gate electrode 40 to form the third layer body region 103, the drift region 104, the source region 105, and the drain region 106, wherein the gate oxide layer 30 covers a portion of the third layer body region 103 and a portion of the epitaxial layer 102, and the gate oxide layer 30 does not contact the source region 105. , projections of the gate oxide layer 30 and the gate electrode 40 in the field plate structure 20 are located in the fifth through hole 203; the source region 105 is located in the third-layer body region 103, and a surface of the source region 105 away from the substrate 101 is flush with a surface of the epitaxial layer 102 away from the substrate 101, and the source region 105 and the third-layer body region 103 have different doping types; the drain region 106 is located in the drift region 104, and a surface of the drain region 106 away from the substrate 101 is flush with a surface of the drift region 104 away from the substrate 101, and the doping type of the drain region 106 is the same as the doping type of the drift region 104. By providing the stacked substrate and epitaxial layer, forming the gate oxide layer on a part of the surface of the epitaxial layer away from the substrate, further forming the gate electrode on the surface of the gate oxide layer away from the epitaxial layer, and finally performing ion implantation into the epitaxial layer, the third layer body region, the drift region, the source region, and the drain region are obtained, so that the substrate can be obtained through a relatively simple process, and the manufacturing process of the LDMOS device is ensured to be relatively simple.

[0080] Furthermore, since the third-layer body region is spaced apart from the drift region and the doping concentration of the drift region is greater than that of the epitaxial layer, the epitaxial layer with a lower concentration is present between the third-layer body region and the drift region, and the epitaxial layer and the drift region have different doping types, so a reverse PN junction is formed between the epitaxial layer and the drift region, and the reverse PN junction can withstand voltage, ensuring good electric field distribution in the semiconductor device, which in turn ensures a high breakdown voltage of the semiconductor device and good performance of the semiconductor device.

[0081] To further ensure a simpler manufacturing process for the LDMOS device, according to another specific embodiment of the present disclosure, a gate oxide layer is formed on a portion of the surface of the epitaxial layer remote from the substrate, and a gate electrode is formed on the surface of the gate oxide layer remote from the epitaxial layer, including a preliminary gate oxide layer 80 and a preliminary gate electrode 90 stacked on the surface of the epitaxial layer 102 remote from the substrate 101, as shown in Figure 4, and a portion of the preliminary gate oxide layer 80 and a portion of the preliminary gate electrode 90 are removed, as shown in Figure 5, with the remaining preliminary gate oxide layer 80 forming the gate oxide layer 30 and the remaining preliminary gate electrode 90 forming the gate electrode 40. By forming the preliminary gate oxide layer and the preliminary gate electrode stacked on the surface of the epitaxial layer remote from the substrate, and then removing the portion of the preliminary gate oxide layer and the portion of the preliminary gate electrode, the gate oxide layer and the gate electrode can be obtained through a relatively simple process, thereby ensuring a simple manufacturing process for the LDMOS device.

[0082] According to yet another specific embodiment of the present disclosure, before forming a field plate structure on the side of the epitaxial layer away from the substrate, the method includes forming a preliminary dielectric layer 100 on the exposed surface of the epitaxial layer 102, where the surface of the preliminary dielectric layer 100 away from the epitaxial layer 102 is planar, and the field plate structure 20 is located on the surface of the preliminary dielectric layer 100 away from the substrate 10, as shown in FIG. 7 ; removing portions of the preliminary dielectric layer 100 to form sixth through holes 110 and seventh through holes 120, as shown in FIGS. 7 and 8 , where the sixth through holes 110 and the seventh through holes 120 expose portions of the source region 105 and the drain region 106, respectively; As shown in FIG. 8 , a portion of the preliminary dielectric layer 100, a portion of the source region 105, a portion of the third-layer body region 103, and a portion of the epitaxial layer 102 are removed to form an eighth through hole 130, which exposes a portion of the substrate 101, and the remaining preliminary dielectric layer 100 forms a dielectric layer 50. As shown in FIG. 9 , metal materials are formed in the sixth through hole 110, the seventh through hole 120, and the eighth through hole 130 to form a source 107, a drain 108, and a second metal layer 60, respectively. The second metal layer 60 is used to electrically connect the source region 105 and the substrate 101, and the field plate structure 20 contacts the second metal layer 60.The sixth through-hole and the seventh through-hole are obtained by forming the pre-dielectric layer on the exposed surface of the epitaxial layer, and a portion of the pre-dielectric layer is removed to obtain the sixth through-hole and the seventh through-hole. The eighth through-hole is obtained by removing a portion of the pre-dielectric layer, a portion of the source region, a portion of the third-layer body region, and a portion of the epitaxial layer. The sixth through-hole, the seventh through-hole, and the eighth through-hole expose the source region, the drain region, and the substrate, respectively. The sixth through-hole, the seventh through-hole, and the eighth through-hole are formed by depositing the metal material into the sixth through-hole, the seventh through-hole, and the eighth through-hole to obtain the source electrode, the drain electrode, and the second metal layer, respectively. The source region can be connected via the source electrode, and the drain region can be connected via the drain electrode. The second metal layer electrically connects the source region and the substrate, thereby realizing grounding of the source region and ensuring good performance of the LDMOS device.

[0083] Specifically, the epitaxial layer is located on a predetermined surface of one portion of the substrate, and the second metal layer is located on the predetermined surface of another portion of the substrate.

[0084] According to one embodiment of the present disclosure, a field plate structure is formed on the side of the epitaxial layer away from the substrate. As shown in FIG. 10 , a preliminary field plate structure 140 is formed on a surface of the dielectric layer 50 away from the substrate 10. As shown in FIG. 11 , a portion of the preliminary field plate structure 140 is removed to expose a portion of the dielectric layer 50, and the remaining preliminary field plate structure 140 forms the spaced-apart field plate structure 20 and a third metal layer 70, which contacts the drain 108. The preliminary field plate structure is formed on the surface of the dielectric layer away from the substrate, and a portion of the preliminary field plate structure is removed to form the field plate structure and the third metal layer. The field plate structure includes the field plate body and the arc-shaped field plate located on one side of the field plate body. The projection of the arc-shaped field plate on the epitaxial layer covers a portion of the drift region, thereby optimizing the electric field distribution in the drift region by the field plate structure. Furthermore, the projection of the field plate structure of the epitaxial layer between the third-layer body region and the drift region is located within the fifth through-hole. That is, by skeletonizing a portion of the epitaxial layer using the field plate structure, the influence of the field plate structure on the electric field of the epitaxial layer can be reduced, which in turn optimizes the electric field distribution of the LDMOS device, further ensuring a high breakdown voltage of the LDMOS device and good performance of the semiconductor device.

[0085] Furthermore, by forming the third metal layer and having the third metal layer in contact with the drain electrode, the drain region can be extracted through the third metal layer and the drain electrode, i.e., the drain electrode and the drain region can be connected through the third metal layer, which further ensures good performance of the LDMOS device.

[0086] Specifically, the metal material includes tungsten, but the metal material is not limited to tungsten, and other metal materials such as copper may be selected, and is not limited here.

[0087] In the above-mentioned embodiments of the present disclosure, emphasis is placed on the description of each embodiment, and some embodiments do not have details, and reference can be made to the description of other embodiments.

[0088] In describing the present disclosure and its embodiments, the orientations or positional relationships indicated by the terms "top," "bottom," "height," etc. are based on the orientations or positional relationships shown in the drawings. They are merely used to facilitate and simplify the description of the present disclosure, and are not intended to indicate or imply that the referred devices or elements must have a particular orientation, be constructed, or operate in a particular orientation, and therefore should not be construed as a limitation of the present disclosure.

[0089] In the present disclosure and its embodiments, unless otherwise clearly specified or limited, the terms "set," "mounted," "connected," "connected," "fixed," etc. should be understood in a broad sense, and may refer to, for example, a mechanical connection, an electrical connection, or communication. They may be directly connected, indirectly connected via an intermediate medium, or an internal connection between two elements or an interactive relationship between two devices. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to specific circumstances.

[0090] In this disclosure and its embodiments, unless otherwise expressly specified or limited, a first feature may be "above" or "below" a second feature, which may include direct contact between the first and second features, or may include contact between the first and second features via another feature rather than direct contact. Furthermore, the terms "above," "above," and "on the top surface" of a first feature refer to whether the first feature is directly above or diagonally above the second feature, or simply whether the horizontal height of the first feature is higher than that of the second feature. The terms "below," "below," and "on the bottom surface" of a first feature refer to whether the first feature is directly above or diagonally above the second feature, or simply whether the horizontal height of the first feature is lower than that of the second feature.

[0091] The above disclosure has many different embodiments, or examples, for realizing different structures of the present disclosure. To simplify the disclosure, specific example components and configurations have been described above. Of course, these are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and / or alphabets in different examples for the purposes of brevity and clarity, without indicating the relationship between the various embodiments and / or configurations being discussed. Furthermore, while the present disclosure has examples of various specific processes and materials, those skilled in the art may recognize the use of other processes and / or the use of other materials.

[0092] Although the preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, it is intended that the appended claims be interpreted to include the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0093] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent techniques, the present disclosure also intends to include these modifications and variations. [Explanation of symbols]

[0094] 10 Substrate 20 Field plate structure 30 Gate oxide layer 40 gate electrode 50 dielectric layer 60 Second metal layer 70 Third metal layer 80 Pre-gate oxide layer 90 spare gate electrode 100 spare dielectric layer 101 Substrate 102 Epitaxial layer 103 Third layer body region 104 Drift Region 105 Source Area 106 Drain region 107 Source 108 Drain 110 6th through hole 120 7th through hole 130 8th through hole 140 spare field plate structure 201 Field Plate Body 202 Arc-shaped field plate 203 5th through hole 21 Gate oxide layer 22 Source Area 23 Drain region 24 First layer body area 25 Body area contact area 26 Drift Region 27 Drift Buffer 28 First Field Plate 29 4th through hole 210 First metal layer 211 First through hole 212 Second through hole 213 3rd through hole 214 Second layer body region 215 Epitaxial Layer 215-1 Epitaxial layer lateral breakdown region 216 First doping type substrate 217 Back metal 218 gate electrode

Claims

1. 1. An LDMOS device comprising: a substrate structure; a drift region located vertically within the substrate structure; a field plate structure located above the substrate structure in the vertical direction, the projection of a portion of the field plate structure on the substrate structure covering a portion of the drift region; a drain region located within the substrate structure in the vertical direction; wherein at least some of the electric field lines in the drain region connected to a high voltage are concentrated toward the field plate structure and terminate at the field plate structure.

1. An LDMOS device comprising:

2. The field plate structure is used to prevent a decrease in the breakdown voltage effect of the epitaxial layer lateral breakdown voltage region.

10. The LDMOS device of claim 1.

3. the drain region is formed laterally outside the drift region, The LDMOS device further comprises: a gate electrode positioned above the substrate structure in the vertical direction and spanning an intrinsic region and an edge termination region of an LDMOS device in the lateral direction; a dielectric layer, the dielectric layer being an insulating dielectric filled between the gate electrode and the drain region; the drift region is formed outside an outer edge of the gate electrode in the lateral direction and extends across the intrinsic region and the termination region; the field plate structure is connected to and straddles above the gate electrode and the drift region in the vertical direction, surrounds an outer edge of the gate electrode in the lateral direction, and straddles the intrinsic region and the termination region; 10. The LDMOS device of claim 1.

4. The substrate structure comprises: A substrate; an epitaxial layer overlying the substrate, the drift region being formed within the epitaxial layer, the epitaxial layer lateral breakdown voltage region being exposed at a distance between the drift region and an outer edge of the gate electrode, the epitaxial layer lateral breakdown voltage region being a portion of the epitaxial layer located between the gate electrode and the drift region; The LDMOS device further comprises: a source region formed in the epitaxial layer in the vertical direction, a first end of the source region defining a boundary between the intrinsic region and the termination region; wherein a distance is provided between the epitaxial layer lateral breakdown voltage region and an outer edge of the source region such that the epitaxial layer lateral breakdown voltage region does not extend into the intrinsic region but is located only in the termination region, a side of the epitaxial layer lateral breakdown voltage region remote from the source region is located below the field plate structure, and the drift region and the drain region are formed within the epitaxial layer.

10. The LDMOS device of claim 1.

5. the gate electrode is a racetrack gate electrode; the epitaxial layer lateral breakdown voltage region has a shape that is a portion of a racetrack and surrounds an outer edge of the gate electrode located in the termination region; the drift region surrounds the outer edges of the gate electrode and the epitaxial layer lateral breakdown withstanding region; 5. The LDMOS device of claim 4.

6. The field plate structure includes: a Z-shaped first field plate, an upper lateral arm of the first field plate being spaced apart from an upper surface of the gate electrode, a vertical arm of the first field plate being spaced apart from the gate electrode, and a lower lateral arm of the first field plate being spaced apart from an upper surface of the drift region; 5. The LDMOS device of claim 4.

7. The field plate structure further comprises: a Z-shaped second field plate, the upper lateral arms of the second field plate being spaced above the upper lateral arms of the first field plate so as to be partially stacked; 7. The LDMOS device of claim 6.

8. The LDMOS device further comprises: a first layer body region and a second layer body region formed from top to bottom, the doping concentrations of the first layer body region and the second layer body region increasing from top to bottom; a body region contact region, wherein the body region contact region, the source region, and the first-layer body region are provided in the same layer in the lateral direction, and the second-layer body region is formed below the body region contact region, the source region, and the first-layer body region in the vertical direction; 8. An LDMOS device according to claim 6 or 7.

9. The LDMOS device further comprises: a drift buffer region located within the drift region in the vertical direction and surrounding the drain region; 9. The LDMOS device of claim 8.

10. The LDMOS device further comprises: a backside metal formed on a lower surface of the substrate; two first metal layers, one first metal layer overlying the source region and one first metal layer overlying the drain region; a first through hole and a metal filled in the first through hole, the metal connecting the source region and the body region contact region with the first metal layer above the source region; a second through hole and a metal filled in the second through hole, the metal connecting the drain region to the first metal layer above the drain region; a third through hole and metal filled in the third through hole, the third through hole connecting the backside metal, the substrate, the epitaxial layer, and the second layer body region with the first metal layer above the source region; 9. The LDMOS device of claim 8.

11. The LDMOS device further comprises: a fourth through hole and metal filled in the fourth through hole, the fourth through hole connecting the first metal layer over the source region with an upper lateral arm of the first field plate; wherein an upper lateral arm of the first field plate is spaced apart from an upper surface of the gate electrode, a vertical arm of the first field plate is spaced apart from the gate electrode, and a lower lateral arm of the first field plate is spaced apart from an upper surface of the drift region.

11. The LDMOS device of claim 10.

12. the gate electrode, the source region, and the drain region are located in the same plane; 12. The LDMOS device of claim 11.

13. the substrate structure includes a substrate and an epitaxial layer located on a surface of the substrate; The LDMOS device further comprises: a third-layer body region, the third-layer body region being spaced apart from the drift region in the epitaxial layer, the epitaxial layer and the third-layer body region having the same doping type, the drift region and the epitaxial layer having different doping types, and the doping concentration of the drift region being greater than the doping concentration of the epitaxial layer; the field plate structure includes a field plate body and an arcuate field plate located on one side of the field plate body, the field plate body being in contact with the arcuate field plate; the field plate structure has a fifth through hole located between the field plate body and the arcuate field plate; a projection of the arcuate field plate in the epitaxial layer covers a portion of the drift region; a projection of the field plate body in the epitaxial layer covers a portion of the third layer body region; and a projection of the epitaxial layer between the third layer body region and the drift region in the field plate structure is located within the fifth through hole.

10. The LDMOS device of claim 1.

14. the drain region is located within the drift region, a surface of the drain region facing away from the substrate is flush with a surface of the drift region facing away from the substrate, and a doping type of the drain region is the same as a doping type of the drift region; The LDMOS device further comprises: a source region located within the third-layer body region, the surface of the source region facing away from the substrate being flush with the surface of the epitaxial layer facing away from the substrate, the source region having a doping type different from that of the third-layer body region; a source electrode located on a surface of the source region that is remote from the substrate; a drain electrode located on a surface of the drain region that is remote from the substrate; 14. The LDMOS device of claim 13.

15. The LDMOS device further comprises: a gate oxide layer located on a surface of a portion of the epitaxial layer, the gate oxide layer covering a portion of the third-layer body region and a portion of the epitaxial layer, and the gate oxide layer not contacting the source region; a gate electrode located on a surface of the gate oxide layer remote from the epitaxial layer, the projection of the gate oxide layer and the gate electrode on the field plate structure being located within the fifth through hole; a dielectric layer covering the gate oxide layer, the gate electrode, and a surface of the epitaxial layer remote from the substrate, the surface of the dielectric layer remote from the epitaxial layer being planar, the source electrode and the drain electrode passing through the dielectric layer, and the field plate structure being located on the surface of the dielectric layer remote from the substrate; 15. The LDMOS device of claim 14.

16. the epitaxial layer is located on a surface of a portion of the substrate; The LDMOS device further comprises: a second metal layer located on a surface of another portion of the substrate, the surface of the second metal layer facing away from the substrate being flush with the surface of the dielectric layer facing away from the substrate, the second metal layer being used to electrically connect the source region and the substrate, and the field plate structure contacting the second metal layer; 16. The LDMOS device of claim 15.

17. The LDMOS device further comprises: a third metal layer located on a surface of a portion of the dielectric layer remote from the substrate, the third metal layer contacting the drain electrode, the third metal layer being spaced apart from the field plate structure, and the third metal layer and the field plate structure exposing a portion of the dielectric layer; 16. The LDMOS device of claim 15.

18. the doping type of the epitaxial layer is P-type, and the doping type of the drift region is N-type; LDMOS device according to any one of claims 13 to 17.

Images