Semiconductor devices and related manufacturing methods

Abstract

A semiconductor device and related fabrication method are disclosed. Specifically, a multilayer structure 26 of the semiconductor device is formed on a surface 30 of a substrate 32 and is surrounded by dicing streets 28. The multilayer structure can be formed to include an interlayer dielectric (ILD) layer 38 that functions as an etch stop. A spacer dielectric layer 42 is then deposited over the multilayer structure and the surrounding dicing streets. The spacer dielectric layer is then etched back to expose the surrounding dicing streets while leaving sidewalls intact between the multilayer structure and the surrounding dicing streets. The use of the ILD layer to provide an etch stop, combined with depositing the spacer dielectric layer before etching and leaving the sidewalls intact after etching, allows the multilayer structure to be protected without compromising its integrity and performance.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 152,130, filed January 9, 2023, the entire contents of which are incorporated herein by reference as if set forth in their entirety.

[0002] TECHNICAL FIELD The techniques of this disclosure relate generally to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0003] Semiconductor devices such as transistors and diodes are found in nearly all electronic devices. Fabrication of these devices often requires numerous meticulous processing steps, including deposition, photoresist coating, lithography, etching, ionization, and packaging. For example, etching is a process that removes process material to expose open areas of a three-dimensional (3D) pattern on a semiconductor die. The etching step must be precise and must not affect the overall integrity and stability of the entire semiconductor device.

[0004] Typically, semiconductor dies are formed on a single wafer during manufacturing. Figure 1A is a schematic diagram of an exemplary top view of multiple dies 10 formed on a wafer 12. As shown in Figure 1A, each of the dies 10 is surrounded by multiple dicing streets 14, which are cut-out areas on the wafer 12 to separate the dies 10 from one another.

[0005] Figure 1B is a schematic diagram providing an exemplary side view of one of the dies 10 of Figure 1A along section line 18. Elements common between Figures 1A and 1B are indicated with common element numbers and will not be described again herein.

[0006] Here, the die 10 is formed on the surface 18 of the wafer 12 and sealed to the respective edges 16 of the peripheral dicing streets 14 to protect one or more internal layers 20 within the die 10. In a non-limiting example, the dicing streets 14 may be covered by a metal layer (ML) during fabrication. Therefore, to remove the metal layer and expose the dicing streets 14, a dry ML etch is typically performed on the dicing streets 14. Notably, ML etching is physical in nature and can have a significant etch rate. As a result, ML etching can create depressions 22 (e.g., 100-500 nanometers) below the surface 18. This can result in portions of the wafer 12 being accidentally exposed and etched, potentially leading to reliability issues for the die 10. Therefore, it is desirable to avoid or at least reduce the extent of depressions 22 during fabrication of the die 10. Summary of the Invention

[0007] Embodiments disclosed in the detailed description include semiconductor devices and related manufacturing methods. Specifically, a multilayer structure of the semiconductor device is formed on a surface of a substrate and surrounded by dicing streets. The multilayer structure can be formed to include an inter-layer dielectric (ILD) layer that functions as an etch stop. A spacer dielectric layer is then deposited over the multilayer structure and the surrounding dicing streets. The spacer dielectric layer is then etched back to expose the surrounding dicing streets while leaving sidewalls intact between the multilayer structure and the surrounding dicing streets. The use of the ILD layer to provide an etch stop, combined with depositing the spacer dielectric layer before etching and leaving the sidewalls intact after etching, allows the multilayer structure to be protected without compromising its integrity and performance.

[0008] In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device also includes a multi-layer structure disposed on the surface. The semiconductor device also includes a spacer dielectric layer disposed on the multi-layer structure and on the surface to form sidewalls.

[0009] In another aspect, a semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device also includes a multi-layer structure disposed on the surface. The semiconductor device also includes a spacer dielectric layer comprised of a selected dielectric material disposed on and over the multi-layer structure to form a sidewall to an outer edge of the sidewall.

[0010] In another aspect, a semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device also includes a multi-layer structure disposed on the surface. The semiconductor device also includes a spacer dielectric layer disposed over the multi-layer structure to form sidewalls at an original outer edge of the multi-layer structure.

[0011] In another aspect, a semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device also includes a multilayer structure disposed on the surface. The semiconductor device also includes a spacer dielectric layer disposed over and on the multilayer structure to form a sidewall. The sidewall includes an inner edge that coincides with an original outer edge of the multilayer structure. The sidewall also includes an outer edge that extends the original outer edge of the multilayer structure to form an extended outer edge of the multilayer structure.

[0012] In another aspect, a method for manufacturing a semiconductor device is provided. The method includes depositing an interlayer dielectric (ILD) metal layer (ML), i.e., a multilayer structure, on a surface of a substrate. The multilayer structure includes an ILD layer that functions as an etch stop during the ML etch and / or a final passivation etch. The method also includes depositing a spacer dielectric layer over the multilayer structure to form sidewalls at an original outer edge of the multilayer structure and extend the original outer edge of the multilayer structure to an extended outer edge of the multilayer structure.

[0013] In another aspect, any of the foregoing aspects and / or any of the various separate aspects and features as described herein can be combined, individually or together, for additional advantage. Any of the various features and elements as disclosed herein can be combined with one or more other disclosed features and elements, unless otherwise stated herein.

[0014] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in connection with the accompanying drawing figures.

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0016] [Figure 1A] FIG. 1 is a schematic diagram of an exemplary top view of multiple dies formed on a wafer. [Figure 1B] FIG. 1B is a schematic diagram providing an exemplary side view of one of the dies of FIG. 1A. [Figure 2] FIG. 1 is a schematic diagram of an exemplary side view of a semiconductor device fabricated in accordance with an embodiment of the present disclosure to protect the multi-layer structure of the semiconductor device and prevent over-etching into the dicing streets surrounding the semiconductor device. [Figure 3] 3 is a flow diagram of an exemplary process for manufacturing the semiconductor device of FIG. 2. [Figure 4A] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4B] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4C] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4D] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4E] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4F] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4G] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 4H] FIG. 4 is a schematic diagram providing an exemplary illustration of the processing steps involved in the process of FIG. 3. [Figure 5] FIG. 10 is a schematic diagram of an exemplary side view of a semiconductor device fabricated according to an embodiment of the present disclosure to protect a multi-layer structure of the semiconductor device and prevent over-etching into dicing streets surrounding the semiconductor device, according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] The examples described below represent the necessary information to enable one skilled in the art to practice the examples and illustrate the best mode of practicing the examples. Upon reading the following description in light of the accompanying drawings, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically addressed herein. It is understood that these concepts and applications are included within the scope of this disclosure and the appended claims.

[0018] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Additionally, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "below" or "upper" or "top" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms, and those described above, are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and related art, and will be further understood not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0023] Examples are described herein with reference to schematic diagrams of embodiments of the present disclosure. Accordingly, actual dimensions of layers and elements may vary, and variations from the shapes of the figures are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, regions shown or described as square or rectangular may have rounded or curved features, and regions shown as straight may have some irregularities. Accordingly, regions shown in the figures are schematic, and their shapes are not intended to represent the exact shape of a region of a device, nor are they intended to limit the scope of the present disclosure. Furthermore, the size of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes, and thus are provided to illustrate the general structure of the present subject matter, and may or may not be drawn to scale. Elements common between figures may be designated herein with common element numbers and may not be subsequently described again.

[0024] Embodiments disclosed in the detailed description include semiconductor devices and related fabrication methods. Specifically, a multilayer structure of a semiconductor device is formed on a surface of a substrate and surrounded by dicing streets. The multilayer structure can be formed to include an interlayer dielectric (ILD) layer that functions as an etch stop. A spacer dielectric layer is then deposited over the multilayer structure and the surrounding dicing streets. The spacer dielectric layer is then etched back to expose the surrounding dicing streets while leaving sidewalls intact between the multilayer structure and the surrounding dicing streets. The use of the ILD layer to provide an etch stop, combined with depositing the spacer dielectric layer before etching and leaving the sidewalls intact after etching, allows the multilayer structure to be protected without compromising its integrity and performance.

[0025] FIG. 2 is a schematic diagram of an exemplary side view of a semiconductor device 24 fabricated in accordance with an embodiment of the present disclosure to protect a multi-layer structure 26 of the semiconductor device 24 and prevent over-etching of dicing streets 28 surrounding the semiconductor device 24. Here, the multi-layer structure 26 is disposed on a surface 30 (e.g., a flat surface) of a substrate 32 (e.g., a semiconductor wafer). The substrate 32 may be bulk-grown silicon carbide (SiC) and / or a SiC epitaxial layer. Because the dicing streets 28 are part of the surface 30 of the substrate 32, the dicing streets 28 can be said to occupy a portion of the surface 30. In a non-limiting example, the multi-layer structure 26 includes a gate oxide layer 34, a field oxide layer 36, an interlayer dielectric (ILD) layer 38, and a final passivation layer 40.

[0026] In one embodiment, a gate oxide layer 34 and a field oxide layer 36 are both grown or deposited on the surface 30 and are adjacent to each other. An ILD layer 38, which may be, by way of example, silicon dioxide (SiO), silicon nitride (SiN), or a combination thereof, is deposited over the gate oxide layer 34 and the field oxide layer 36. A final passivation layer 40 is deposited over the ILD layer 38.

[0027] The semiconductor device 24 also includes a spacer dielectric layer 42 deposited over the multilayer structure 26 and the dicing streets 28. In one embodiment, the spacer dielectric layer 42 can include one or more types of dielectric materials, such as SiN, silicon dioxide (SiO), silicon (Si), silicon oxynitride (SiON), a SiN liner with an oxide spacer, or a SiN liner with an SiON spacer. The spacer dielectric layer etch can substantially reduce the rate of silicon carbide (SiC) etching compared to the metal layer (ML) etch, thereby reducing the likelihood of over-etching the dicing streets 28. As a result, the recess 22 in FIG. 1B can be made smaller, for example, during a dry etching process.

[0028] In another embodiment, the spacer dielectric layer 42 can create sidewalls 44 (also known as protective sidewalls) to completely encapsulate the multilayer structure 26. For example, the sidewalls 44 can be formed to have an inner edge 46 that surrounds the multilayer structure 26 and an outer edge 48 that contacts the dicing street 28. The inner edge 46 of the sidewalls 44 coincides with the original outer edge of the multilayer structure 26, and the outer edge 48 of the sidewalls 44 extends the original outer edge of the multilayer structure 26 to form an extended outer edge of the multilayer structure 26. In other words, the inner edge 46 of the sidewalls 44 is the same as the original outer edge of the multilayer structure 26, and the outer edge 48 of the sidewalls 44 defines a new outer edge of the multilayer structure 26. The inner edge 46 and the outer edge 48 together form a thickness d of the sidewalls 44. SW (d SW >0). Depositing a spacer dielectric layer 42 before etching and creating sidewalls 44 after etching allows for protection of the multi-layer structure 26 without compromising its integrity and performance.

[0029] After performing a spacer etch process (e.g., dry etching) on ​​the spacer dielectric layer 42 to create the sidewalls 44 and expose the dicing streets 28, an encapsulation layer 50 (e.g., polyimide) can be deposited over the spacer dielectric layer 42. As shown in FIG. 2 , the encapsulation layer 50 not only completely encapsulates the outer edges 48 of the sidewalls 44, but also covers some (but not all) of the dicing streets 28 on the surface 30.

[0030] The semiconductor device 24 can be fabricated based on the process. In this regard, Figure 3 is a flow diagram of an exemplary process 100 for fabricating the semiconductor device 24 of Figure 2. Elements of Figure 2 are referenced in the process 100 and will not be described again herein.

[0031] According to process 100, multi-layer structure 26 is first deposited (step 102) on surface 30 of substrate 32. Notably, multi-layer structure 26 includes an ILD layer 38 that can provide an etch stop during an OM etch and / or a final passivation etch.

[0032] The steps for depositing the multi-layer structure 26 are further illustrated in Figures 4A-4E. First, a field oxide layer 36 and a gate oxide layer 34 are provided on the surface 30 of the substrate 32.

[0033] Next, in process 100, an ILD layer 38 is deposited over the field oxide layer 36 and the gate oxide layer 34, as shown in Figure 4A.

[0034] Next, process 100 deposits ML 52 over ILD layer 38 during metal deposition, as shown in Figure 4B.

[0035] Next, in process 100, as shown in FIG. 4C, an ML etch (e.g., a dry etch) is performed to remove ML 52 and expose dicing streets 28. Because ILD layer 38 is deposited to cover the entire dicing streets 28 before the ML etch, ILD layer 38 acts as an etch stop during the ML etch. As a result, by preventing over-etching of dicing streets 28, recess 22 in FIG. 1B can be substantially reduced.

[0036] Next, in process 100, a final passivation layer 40 is deposited on substrate 32, as shown in Figure 4D. Notably, final passivation layer 40 completely covers ILD layer 38 and dicing streets 28.

[0037] Next, in process 100, a final passivation etch is performed to expose the portions of the surface occupied by the dicing streets 28, as shown in FIG. 4E. The ILD layer 38 remaining after the ML etch can also function as an etch stop during the final passivation etch. Here, the final passivation etch not only removes the bond pads but also exposes the dicing streets 28 by removing the ILD layer 38 and the final passivation layer 40 previously deposited on top of the dicing streets 28. The remaining gate oxide layer 34, field oxide layer 36, ILD layer 38, and final passivation layer 40 together form the multilayer structure 26. Notably, the field oxide layer 36, ILD layer 38, and final passivation layer 40 all terminate at the original outer edge 46 of the multilayer structure 26.

[0038] After depositing multi-layer structure 26, a spacer dielectric layer 42 is deposited over multi-layer structure 26 to form sidewalls 44 at an original outer edge 46 of multi-layer structure 26 and extend the original outer edge 46 of multi-layer structure 26 to an extended outer edge 48 of multi-layer structure 26 (Step 104). The step of depositing spacer dielectric layer 42 is further illustrated in Figures 4F-4H.

[0039] Next, in process 100, a spacer dielectric layer 42 is deposited over the final passivation layer 40 and the portion of the surface 30 occupied by the dicing streets 28, as shown in Figure 4F. SW Each film thickness d is proportional to FM In a non-limiting example, the spacer dielectric layer 42 is deposited to a thickness d FM is the thickness d SW It can be set to half (1 / 2) to five times (5x) of (0.5d SW ≦d FM ≦5d SW ).

[0040] Next, in process 100, a spacer etch is performed to etch back spacer dielectric layer 42, forming sidewalls 44 at the original outer edge 48 of multi-layer structure 26 and exposing the portion of surface 30 occupied by dicing street 28 beyond the extended outer edge 48 of multi-layer structure 26, as shown in FIG. 4G. Inside sidewall 44, gate oxide layer 34, ILD layer 38, and final passivation layer 40 each terminate at an inner edge 46 of sidewall 44. Outside sidewall 44, dicing street 28 contacts outer edge 48 of sidewall 44. While the etch performed on spacer dielectric layer 42 may result in a slight recess compared to recess 22 of FIG. 1B, the thickness d of sidewall 44 remains. SW This allows the multi-layer structure 26 to be completely sealed from any depressions on the dicing streets 28. In certain embodiments, the resulting depressions may be less than 50 nanometers, less than 25 nanometers, or even less than 15 nanometers, which is a significant improvement over the 100-500 nanometer (or greater) deep depressions of the prior art.

[0041] Next, process 100 deposits encapsulation layer 50 to completely encapsulate (also known as seal) outer edges 48 of sidewalls 44, thereby finally sealing multi-layer structure 26, as shown in FIG. 4H.

[0042] Referring to Figure 5, an alternative embodiment is shown. In this embodiment, the gate oxide 34 provided in Figure 2 has been removed. Therefore, the field oxide 36 extends all the way to the inner edge 46. An ILD layer 38 resides on the field oxide 36 and also extends to the inner edge 46. A final passivation layer 40 resides on the ILD layer 38. A spacer dielectric layer 42 resides on the final passivation layer 40 and extends down the sides of the final passivation layer 40, the ILD layer 38, and the field oxide layer 36 to the substrate 32. The outside of the spacer dielectric layer 42 defines an outer edge 48 and provides sidewalls 44.

[0043] It is contemplated that any of the foregoing aspects, and / or any of the various separate aspects and features described herein, may be combined to further advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments, unless otherwise noted herein.

[0044] Additionally, those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. a substrate having a surface; a multilayer structure provided on the surface; a spacer dielectric layer disposed on and at the surface of the multi-layer structure to form sidewalls; A semiconductor device comprising:

2. The spacer dielectric layer may be made of silicon nitride (SiN), silicon dioxide (SiO ２ 10. The semiconductor device of claim 1, comprising at least one of: silicon (Si), silicon oxynitride (SiON), a SiN liner with an oxide spacer, and a SiN liner with a SiON spacer.

3. The semiconductor device of claim 1 , wherein the substrate comprises at least one of bulk-grown silicon carbide (SiC) and a SiC epitaxial layer.

4. The multilayer structure is a gate oxide layer disposed on the surface; a field oxide layer disposed on the surface and adjacent to the gate oxide layer; an interlevel dielectric (ILD) layer disposed over the gate oxide layer and the field oxide layer; a final passivation layer disposed over the ILD layer; Equipped with the gate oxide layer, the ILD layer, and the final passivation layer each terminate at an inner edge of the sidewall; 4. The semiconductor device according to claim 1.

5. The side wall is an inner edge that coincides with the original outer edge of the multilayer structure; an outer edge extending the original outer edge of the multi-layer structure to form an extended outer edge of the multi-layer structure; 5. The semiconductor device according to claim 1, comprising:

6. 6. The semiconductor device of claim 5, further comprising an encapsulation layer disposed over the spacer dielectric layer and a portion of a dicing street surrounding the outer edge of the sidewall.

7. a substrate having a surface; a multilayer structure provided on the surface; a spacer dielectric layer comprising a selected dielectric material disposed on and on the multilayer structure to form a sidewall around the multilayer structure, thereby completely sealing the multilayer structure up to the outer edge of the sidewall; A semiconductor device comprising:

8. The selected dielectric material is silicon nitride (SiN), silicon dioxide (SiO ２ 8. The semiconductor device of claim 7, wherein the silicon oxynitride is at least one of silicon (Si), silicon oxynitride (SiON), a SiN liner with an oxide spacer, and a SiN liner with a SiON spacer.

9. 8. The semiconductor device of claim 7, wherein the substrate comprises at least one of bulk-grown silicon carbide (SiC) and a SiC epitaxial layer.

10. The multilayer structure is a gate oxide layer disposed on the surface; a field oxide layer disposed on the surface and adjacent to the gate oxide layer; an interlevel dielectric (ILD) layer disposed over the gate oxide layer and the field oxide layer; a final passivation layer disposed over the ILD layer; Equipped with the gate oxide layer, the ILD layer, and the final passivation layer each terminate at an inner edge of the sidewall; 10. The semiconductor device according to any one of claims 7 to 9.

11. 10. The semiconductor device of claim 7, further comprising an encapsulation layer disposed over the spacer dielectric layer and a portion of a dicing street surrounding the outer edge of the sidewall.

12. a substrate having a surface; a multilayer structure provided on the surface; a spacer dielectric layer disposed over the multi-layer structure to form sidewalls around the original outer edges of the multi-layer structure; A semiconductor device comprising:

13. 13. The semiconductor device of claim 12, wherein the substrate comprises at least one of bulk-grown silicon carbide (SiC) and a SiC epitaxial layer.

14. The multilayer structure is a gate oxide layer disposed on the surface; a field oxide layer disposed on the surface and adjacent to the gate oxide layer; an interlevel dielectric (ILD) layer disposed over the gate oxide layer and the field oxide layer; a final passivation layer disposed over the ILD layer; Equipped with the gate oxide layer, the ILD layer, and the final passivation layer each terminate at an inner edge of the sidewall; 14. The semiconductor device according to claim 12 or 13.

15. a substrate having a surface; a multilayer structure provided on the surface; a spacer dielectric layer disposed over the multi-layer structure to form sidewalls, the sidewalls comprising: an inner edge that coincides with the original outer edge of the multi-layer structure; and an outer edge extending the original outer edge of the multi-layer structure to a stretched outer edge of the multi-layer structure; A semiconductor device comprising:

16. providing a multi-layer structure including an interlayer dielectric (ILD) layer on a surface of a substrate; creating an etch stop layer by removing a portion of the ILD layer, the etch stop layer being a remaining portion of the ILD layer; providing a final passivation layer over the multi-layer structure and the etch stop layer; removing a portion of the final passivation layer and the etch stop layer to create access to the substrate; 1. A method for manufacturing a semiconductor device, comprising:

17. providing the multi-layer structure, depositing a field oxide layer and a gate oxide layer over the surface of the substrate; depositing the ILD layer over the field oxide layer and the gate oxide layer; depositing a metal layer (ML) on the ILD layer; performing a ML etch to remove the ML, the ILD layer providing an etch stop to protect a portion of the surface from over-etching; depositing the final passivation layer over the ILD layer; performing a final passivation etch to expose said portion of said surface; 17. The method of claim 16, comprising:

18. 18. The method of claim 16 or 17, further comprising depositing a spacer dielectric layer over the multilayer structure to form sidewalls at an original outer edge of the multilayer structure and extend the original outer edge of the multilayer structure to an extended outer edge of the multilayer structure.

19. depositing the spacer dielectric layer depositing the spacer dielectric layer over the final passivation layer and a portion of the surface of the substrate; performing a spacer etch to etch back the spacer dielectric layer, thereby forming sidewalls at the original outer edge of the multi-layer structure and exposing the surface beyond the extended outer edge of the multi-layer structure; depositing an encapsulation layer to seal the extended outer edge of the multi-layer structure; 20. The method of claim 18, comprising:

20. 20. The method of claim 18, wherein depositing the spacer dielectric layer comprises depositing the spacer dielectric layer to a thickness proportional to the thickness of the sidewalls.

21. The step of depositing the spacer dielectric layer may include depositing a dielectric layer of silicon nitride (SiN), silicon dioxide (SiO ２ 20. The method of claim 18, further comprising depositing the spacer dielectric layer comprised of a selected dielectric material that is one of: silicon (Si), silicon oxynitride (SiON), a SiN liner with an oxide spacer, and a SiN liner with a SiON spacer.

22. The multilayer structure is a field oxide layer disposed on said surface; an interlevel dielectric (ILD) layer disposed over the field oxide layer; a final passivation layer disposed over the ILD layer; Equipped with each of the field oxide layer, the ILD layer, and the final passivation layer terminates at an inner edge of the sidewall; The semiconductor device of claim 1 .

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