Integration of chips into cavities in a host wafer using lateral dielectric bonding

Abstract

The electronic assembly has a backside capping layer (370), and the backside (112) of the host wafer (110) is bonded to a top surface (372) of the backside capping layer (370) except for a wafer cavity (120) formed over an area of ​​the backside capping layer, the cavity (120) having a side surface (116) of the wafer. The backside (134) of the chiplet (130) is directly bonded to at least a portion of an area of ​​the top surface (372) of the backside capping layer (370). A lateral dielectric material (360) between the chiplet side surface (136) and the wafer side surface (116) mechanically and chemically bonds the chiplet (130) side surface (136) to the wafer (110).

Description

[Technical Field]

[0001] (Field)

[0002] This disclosure relates to a host wafer having circuitry and at least one chip (or chiplet) laterally bonded within a sidewall of at least one cavity in the wafer using a dielectric material, where, for example, the wafer and chip are separately fabricated. [Background technology]

[0003] Description of Related Art

[0004] An electronic assembly or hybrid circuit includes microelectronic circuits that are individually manufactured and assembled together to form a single component, which may itself be enclosed in an electronic circuit package. Assembling individually manufactured microelectronic circuits, for example, allows all microelectronic circuits to be individually tested before they are assembled, thereby improving the manufacturing yield of the final component. This capability is particularly significant when some of the individually manufactured microelectronic circuits are difficult and / or expensive to manufacture. Additionally, assembling individually manufactured microelectronic circuits allows microelectronic circuits that use different materials and different manufacturing processes to be combined into a single final component. This capability may result in higher circuit performance.

[0005] A need exists for electronic assemblies using host wafers having prefabricated interconnects and integrated circuits, e.g., passive components, connected with wafer-level microelectronic active chiplets (i.e., those having transistors) integrated within through-wafer cavities of the host wafer. This need may be, for example, for assemblies for microwave or other radio frequency (RF) integrated circuits that separate the fabrication of the active circuits (e.g., transistor fabrication) from the fabrication of the passive circuits (e.g., interconnect, resistor, and capacitor fabrication). Meeting this need would enable significantly faster fabrication of circuits at lower cost and the scaling up of active device technology for circuits without the cost and cycle time burden. [Brief explanation of the drawings]

[0006] [Figure 1A] FIG. 1 is a schematic top view illustrating a host wafer having cavities for in-substrate chiplet integration into wafer cavities of the host wafer using lateral dielectric material.

[0007] [Figure 1B] FIG. 1 is a schematic top view illustrating a chiplet for in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material.

[0008] [Figure 2] 1 is a schematic cross-sectional view illustrating a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material.

[0009] [Figure 3A] 1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material. [Figure 3B]1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material. [Figure 3C] 1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material. [Figure 3D] 1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material. [Figure 3E] 1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material. [Figure 3F] 1 is a flow diagram illustrating a process for fabrication of a device with in-substrate chiplet integration into a wafer cavity of a host wafer using lateral dielectric material.

[0010] [Figure 4] 4A-4C illustrate two processes for forming the device of FIG. 3C. DETAILED DESCRIPTION OF THE INVENTION

[0011] Throughout this description, components that appear in the drawings are assigned three or four digit reference numbers, where the last two digits are specific to the component and the first one or two digits may be the number of the drawing in which the component is first introduced or manufactured. A component not shown with a drawing may be considered to have the same features and function as an earlier or later described component having the same reference number.

[0012] (Device Description)

[0013] Described below are improved wafers, dies, chips, and fabrication techniques for electronic assemblies involving in-substrate chip (e.g., chiplets) integration into wafer cavities of a host wafer using lateral dielectric materials. The host wafer may have prefabricated interconnects and integrated circuits, e.g., passive components, connected to chiplet-level microelectronic transistor chips integrated into through-wafer cavities of the wafer. This may form an assembly for an integrated circuit device, where the chips contain active circuitry in at least one semiconductor technology and the wafer contains passive (or active) circuitry in another semiconductor technology (often a cheaper, larger-scale technology). The use of a low-cost, large-diameter integration platform for the chips with active devices allows for significantly faster fabrication of assembled circuits at larger scales and at lower cost.

[0014] An electronic assembly may integrate chiplets with one type of component onto a carrier wafer with a different type of component. An electronic assembly may integrate chiplets with high-performance integrated circuits, such as gallium nitride (GaN) radio frequency (RF) integrated circuits (ICs), onto a host wafer with other integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive, has high manufacturing yields, and short manufacturing cycles. A chip (or chiplet) of a high-performance RF IC may have III-V or other types of transistors and passives, and may be integrated onto a host wafer with resistors, inductors, capacitors, and matching networks, as well as active devices with another semiconductor technology. For example, an RF IC is one type of semiconductor technology, and it may be integrated with resistors, inductors, capacitors, matching networks, and active devices with another semiconductor technology that are part of the host wafer. A chiplet may be a chip including the circuits, materials, and / or devices described above in this paragraph. Additionally, a chiplet may be a chip or small chip having active microelectronic (i.e., transistor) devices, CMOS devices, microwave IC devices, and / or radio frequency (RF) IC devices. Additionally, a chiplet may be a chip or small chip having SAW, BAW, or other acoustic wave devices. The footprint or top surface area of ​​a chiplet may be half, one-third, one-fifth, or less than one-fifth that of a computer processor chip (e.g., 8086, P3, P4, etc.).

[0015] 1A is a schematic top view 100 of a host wafer 110 having cavities 120 for intra-substrate chiplet integration into the wafer cavities 120 of the host wafer 110 using lateral dielectric material. As shown in FIG. 2, the host wafer 110 has a backside 112 and a frontside 114. The host wafer 110 and / or each cavity 120 has side surfaces 116, such as vertical surfaces or sidewall surfaces between the backside 112 and the frontside 114. There may be three or more side surfaces 116. Typically, there are four side surfaces.

[0016] The wafer 110 may be or include (e.g., as a mixture of materials or layers of materials) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, diamond, silicon carbide, quartz, or alumina. When the wafer includes only interconnects and passive components, the wafer may be a dielectric, such as glass, quartz, alumina, or another ceramic. The host wafer 110 may have one or more layers of these materials in the form of oxide, crystalline, and polycrystalline materials, and / or amorphous materials. The wafer 110 may include at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers (e.g., signal traces or signal planes). The wafer 110 may include at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material.

[0017] The wafer 110 may include areas that are to be diced into integrated circuits, each having passive integrated components (e.g., signal traces, interconnects, and conductive vias, resistors, inductors, and / or capacitors), a single transistor, and / or multiple transistors. Silicon is an advantageous choice for the wafer 110 because it is less expensive than other materials and / or takes advantage of known microelectronics manufacturing processes and the potential for scalability and manufacturability.

[0018] 1B is a schematic top view 102 of a chiplet 130 for intra-substrate chiplet integration into a wafer cavity 120 of a host wafer 110 using a lateral dielectric material. As shown in FIG. 2, the chiplet 130 has a front side 132 (e.g., front surface) and a back side 134 (e.g., back surface). Each chiplet 130 has side surfaces 136, such as vertical or sidewall surfaces, between the front surface 132 and the back side 134. There may be three or more side surfaces 136. Sometimes there are four side surfaces. The number of side surfaces 136 of each chiplet 130 may be the same as the number of surfaces 116.

[0019] Each chiplet 130 may be or include (e.g., as a mixture of materials or layers of materials) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, quartz, alumina, gallium nitride, or silicon carbide. Chiplets 130 may have layers of one or more of these materials in the form of oxide, crystalline, and polycrystalline materials, and / or amorphous materials. There may be chiplets 130 of different electrical component types fabricated separately from one another. Chiplets 130 may include GaN, InP, or GaAs, or any other electrical component known in the industry, and may be fabricated on a substrate such as Si, SiGe, InP, GaAs, SiC, alumina, or diamond, or any other substrate known in the industry.

[0020] Chiplets 130 or types of chiplets 130 may include RF switches, transmit and / or receive circuits; power switches, amplifiers, and circuits using, for example, GaAs, InP, GaN, etc.; and / or transistors, for example, Si CMOS transistors. Chiplets 130 may have smaller and more expensive electrical components than those in wafer 110. A single wafer 110 may have hundreds, thousands, or hundreds of thousands of chiplets 130 embedded therein. Wafer 110 may have more passive components, lower-cost components, and routing (e.g., traces, conductive vias, and interconnects) than chiplets 130. Wafer 110 may be manufactured using a different microelectronic manufacturing technology or process than that used to manufacture chiplets 130.

[0021] Chiplets 130 and wafer 110 may be made of different materials. For example, wafer 110 may be a silicon wafer, while chiplets 130 may be type III-nitride material component chips. Each of chiplets 130 may be or include an integrated circuit having passive integrated components (e.g., signal traces, interconnects, and conductive vias, resistors, inductors, and / or capacitors), a single transistor, and / or multiple transistors.

[0022] Each of the chiplets 130 includes at least one of transistor circuitry and interconnects to contact pads on the front side 132 of the chiplet 130. The chiplets 130 may be high-end pre-fabricated active device chiplets integrated onto the wafer 110 by pick-and-place assembly onto a temporary wafer with an adhesive laminate or simply onto an adhesive laminate 340 (see FIG. 3B).

[0023] 2 is a schematic cross-sectional view of a device 200 having in-substrate chiplets 130 integrated into a wafer cavity 120 of a host wafer 110 using a lateral dielectric material 360. Device 200 may include the devices of FIGS. 1A and 1B.

[0024] Device 200 may be an electronic assembly having a backside capping layer 370 having a top surface 372 and a backside 374. Device 200 has a host wafer 110 having a backside 112 and a front side 114, with the backside 112 of the wafer bonded to the top surface 372 of the backside capping layer 370, except for a cavity 120 in the wafer 110 formed over a plurality of areas 376 of the top surface 372. The cavity may extend from the backside 112 through the wafer to the front side 114. The cavity has sides 116. The backside 112 of the wafer may be directly attached to and in contact with the top surface 372. The bond between the backside 112 and the top surface 372 may be a covalent bond, a chemical bond, or an atomic bond.

[0025] The chiplet 130 or chips have a backside 134 and a frontside 132, and the backside 134 of the chiplet 130 is directly bonded to at least portions 378 of multiple areas 376 of a top surface 372 of the backside capping layer. The portions 378 may be the footprint of the chiplet 130 on the top surface 372 within the cavity 120. The gap 350 between the side surfaces 116 and 136 may be the difference between the areas 376 and the portions 378. The backside 134 may be directly attached to and in contact with the top surface 372. The bond between the backside 134 and the top surface 372 may be a covalent bond, a chemical bond, or an atomic bond.

[0026] Cavities 120 may be through-substrate holes or through substrate holes etched into the wafer in areas 376. Chiplets 130 may be embedded in wafer 110 in the substrate holes or cavities 120.

[0027] The lateral dielectric material 360 extends between the side surface 136 of the chiplet 130 and the side surface 116 of the wafer or cavity. The lateral dielectric material 360 may mechano-chemically bond the side surface 136 of the chiplet 130 to the side surface 116 of the wafer. The lateral dielectric material 360 may form a mechanical and / or chemical bond to the side surface 136 and the side surface 116. In some cases, the lateral dielectric material 360 is a molding compound and the bond is a mechano-chemical bond.

[0028] Dielectric material 360 is not a metal and is an electrical insulator. Dielectric material 360 may be or include a material that is not conductive, not a semiconductor, not a plastic, not an alloy, or a biomaterial. Material 360 may be an epoxy. Material 360 may be an epoxy with silica particles. Material 360 may be an epoxy with SiO2 particles.

[0029] Material 360 may have dielectric characteristics such that charges do not flow through the material when placed in an electric field. Charges shift slightly from their average equilibrium position, creating dielectric polarization, where positive charges flow in the direction of the field and negative charges shift in the opposite direction of the field. This phenomenon results in an internal electric field, thereby reducing the overall electric field within the dielectric material.

[0030] In some cases, material 360 may not conduct current when a voltage is applied. However, certain changes occur at the atomic scale. When a voltage is applied to a dielectric object, it becomes polarized. Because atoms are made up of a positively charged nucleus and negatively charged electrons, the polarization effect causes the electrons to shift slightly toward the positive voltage. The electrons do not move far enough to cause a current to flow through the material. The shift is subtle, but has a very important effect. When the voltage source is removed from the material, the material either returns to its original, unpolarized state, or remains polarized if the molecular bonds within the material are weak. A dielectric material can be an insulator, but it is one that is easily polarized.

[0031] In some cases, the coefficient of thermal expansion of dielectric material 360 is between or equal to the coefficient of thermal expansion of wafer 110 and chiplet 130 .

[0032] Lateral dielectric material 360 is disposed in gap 350 between side surface 136 of each chiplet 130 and side surface 116 of the corresponding wafer cavity in which each chiplet 130 is disposed. The width gw of gap 350 is 1 / 5 (one-fifth) to 10 times the thickness tw of wafer 110 or chiplet 130.

[0033] The wafer thickness tw may be between 20 and 200 microns. It may be between 50 and 125 μm. It may be 75 μm. The thickness of one, many, or all of the chiplets may be the same as the wafer thickness.

[0034] The thickness te of the backside capping layer may be 3 to 300 microns. It may be 5 to 100 microns. It may be 10 to 50 microns. It may be 15 μm.

[0035] Each chiplet 130 has three to six sides. The chiplets 130 may have four sides. The sides may have a straight, curved, or wavy profile from a top perspective. The cavity 120 may have the same number of sides corresponding to the shape of the sides of the chiplets 130.

[0036] Backside capping layer 370 may be a high thermal conductivity backside metallization layer that improves heat transfer from chiplets 130 to wafer 110. Layer 370 may be a thermal plane that improves heat transfer from chiplets 130 by increasing thermal conduction from chiplets 130 to layer 370 and / or wafer 110. Layer 370 is a material that directly contacts chiplets 130 to increase thermal conduction between the material of chiplets 130 and the material of layer 370. In some cases, the thermal expansion coefficient of backside capping layer 370 is between or equal to the thermal expansion coefficients of wafer 110 and chiplets 130.

[0037] The interconnects 510 may be formed directly on the lateral dielectric material 360 to connect the electrical (e.g., power, ground, and / or signal) contacts 138 of the chiplets 130 with the contacts 118 of the wafer 110. The interconnects 510 may include direct interconnect routing or traces formed directly on the lateral dielectric material (e.g., without any dielectric / air gap) extending from the chiplets to the electrical routing of the wafer. The interconnect routing may include low-loss, high-performance DC, RF, and mmWave routing from the chiplets 130 directly on the lateral dielectric material to the wafer electrical routing. The interconnects 510 may reside directly on the lateral dielectric material 360 by being bonded and / or directly attached (e.g., contacting) to the top surface of the material 360.

[0038] In some cases, wafer 110 includes an electronic integrated circuit (not shown), at least one integrated circuit contact 118 (e.g., a contact pad) formed on the wafer front side 114, and at least one through-wafer cavity 120 having a side surface 116 joining the backside 112 to the front side 114. In some cases, chiplets 130 are held within through-wafer cavity 120 by a lateral dielectric material 360 that attaches at least one side surface 116 of through-wafer cavity 120 to at least one side surface 136 of chiplet 130. In some cases, lateral dielectric material 360 fills gaps 350 in the cavity, thereby attaching most of the side surface 136 of chiplet 130 to the side surface 116 of through-wafer cavity 120. However, material 360 does not attach backside 134 of chiplet 130 to top surface 372 of layer 370.

[0039] A passivation layer (not shown) may be disposed over most of the front surface 114 of the wafer 110. Conductive vias (e.g., TWVs) disposed through the passivation layer may connect active and / or passive circuitry of the wafer 110 to contacts 118 (e.g., contact pads) on the front surface 114. The wafer 110 may be a silicon wafer or substrate, allowing for utilization of known manufacturing processes and manufacturability for large wafer diameters.

[0040] It should be noted that wafer 110 may include any active or passive integrated circuits enabled by a selected fabrication process, such as a CMOS fabrication process. In some cases, the thickness of one or more integrated circuit layers may be, for example, a small fraction of the thickness t of wafer 110 (e.g., 1 / 10 to 1 / 1000 of the thickness of wafer 110; e.g., a 50 nm thickness for a 50 μm wafer thickness). In some cases, the thickness of wafer 110 may be reduced after fabrication of the integrated circuits on the wafer, such as before etching through-wafer cavities 120 or after filling gaps 350 with lateral dielectric material 360.

[0041] The chiplet 130 may include one or more transistors (not shown) having terminals connected to at least one integrated circuit contact 138 (e.g., contact pad), for example, by a conductive via (not shown). The chiplet 130 may include a substrate and an integrated circuit layer formed on top of the substrate, with the integrated circuit layer having a thickness that is, for example, a small fraction of the thickness of the substrate (e.g., 1 / 10 to 1 / 1000 of the thickness of the substrate). In some cases, the total thickness of the chiplet 130 is less than the total thickness of the host wafer 110. In some cases, the lateral dielectric material 360 contacts the side surface 136 of the chiplet 130 along most of its height (at least 50% of the height starting near the top surface of the chiplet 130). Preferably, the lateral dielectric material 360 contacts essentially all of the side surface 136 of the chiplet 130. Preferably, the lateral dielectric material 360 completely fills the gap 350, to a level that is essentially flush with the front surface 114 of the host wafer 110.

[0042] In some cases, the lateral dielectric material 360 holds the chiplet 130 so that the front side 132 of the chiplet is flush with the front side 114. "Flush" may be understood to mean that the two surfaces are in the same plane or have a small or negligible height difference relative to one another. The two surfaces may be made flush, such as by a process in which both the front side 132 and the front side 114 of the chiplet are temporarily attached to an adhesive laminate 340 while the chiplet 130 is permanently attached to the side surface 116 of the through-wafer cavity 120 by material 360 (see FIGS. 3A-3F), such as according to the processes illustrated herein. The front side 132 and the front side 114 may be made flush, such as by polishing or CMP of the surfaces after removing the temporary adhesive laminate 340.

[0043] In some cases, layer 370 has a flat, planar, continuous surface and a constant thickness te, where, for example, the backside 112 of the chiplets and the backside surface 134 of the wafer are all at the same vertical, planar level. In other cases, layer 370 has a non-flat surface and a non-constant thickness, where, for example, the height of the backside 112 of the chiplets and / or the backside surface 134 of the wafer varies and is not planar. In one case, thickness te of layer 370 varies from chiplet to chiplet and from wafer to wafer, by being a particular thickness for the wafer and having a different thickness for one or more chiplets. In other words, the wafer has a different thickness from some chiplets. In this case, some chiplets may have a different thickness from other chiplets.

[0044] It is contemplated that the host wafer 110 may be diced vertically at dicing lines (indicated by vertical bars in FIG. 2) along the perimeter 386 of the wafer around at least one chiplet to form chips having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0045] (Method description)

[0046] 3A-3F are flow diagrams illustrating process steps 301-306 for fabricating device 200 with in-substrate chiplet integration into a wafer cavity of a host wafer using a lateral dielectric material. This process may form device 200 using the devices of FIGS. 1A and 1B. This process begins with device 311 and ends with device 200. This process may be a method of forming or fabricating an electronic assembly or device. This process may be a lateral chiplet dielectric bonding process. The flow diagrams of FIGS. 3A-3F include only major process steps. Various conventional process steps (e.g., surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may occur before, between, after, and during the steps shown in FIGS. 3A-3F.

[0047] 3A shows step 301 for forming device 311, which includes a host wafer 110 bonded to an adhesive laminate 340. Step 301 may include forming a cavity 120 through the host wafer 110, which has a backside 112 and a frontside 114, the cavity having sides 116. Forming the cavity 120 may include etching a substrate through-hole in the backside 112 of the wafer.

[0048] Step 301 then involves bonding the front surface 114 of the wafer to the top surface 342 of an adhesive laminate 340, which has an upper surface 342 and a lower surface 344, thereby disposing the cavities 120 over a plurality of areas 376 of the top surface 342 of the adhesive laminate. The bonding in step 301 may include attaching the front surface 114 of the wafer directly to the top surface 342 such that the front surface 114, other than the cavities 120 or areas 376, is bonded to and in contact with the top surface 342. The bonding between the front surface 114 and the top surface 342 may be a covalent bond, a chemical bond, or an atomic bond. In some cases, the cavities 120 may be formed after bonding the wafer 110 and the laminate 340.

[0049] The laminate 340 may include at least one of an adhesive, an epoxy, a sacrificial layer on the wafer, a water-soluble adhesive, a solvent-dissolvable adhesive, a UV-releasable adhesive, or a heat-releasable adhesive.

[0050] Step 301 may include placing a host wafer 110 having through-substrate holes 120, such as by placing it on a laminate 340, or laminating the laminate 340 onto the surface of the wafer 110 to form a device 311. The holes 120 may have as few as one side (e.g., may be circular) or as many as an infinite number of sides, but preferably have four sides. The thickness of the wafer, tw, may be between 10 and 2,000 microns, but is preferably 75 μm.

[0051] 3B illustrates step 302 for forming device 312, which includes bonding chiplets 130 to a top surface 342 within cavity 120. Step 302 may include bonding front sides 132 of multiple chiplets 130, each having a back side 134 and a front side 132, to portions 378 of multiple areas 376 of the top surface 342 of adhesive laminate 340. The bonding in step 302 may include directly attaching the front sides 132 of the chiplets 130 to portions 378 of areas 376 such that the front sides 132 are bonded to and in contact with the top surface 342 within cavity 120. The bonding between the front sides 132 and the top surface 342 may be a covalent bond, a chemical bond, or an atomic bond.

[0052] Chiplets 130 typically have four sides, but may have between zero and an infinite number of sides, and are then aligned with and bonded (e.g., flip-chip bonded) face-down onto adhesive laminate material 340 therein in a substrate through-hole 120 of device 311. Chiplets 130 may be of thickness tw, the same as thickness tw of wafer 110, or of a thickness that is greater or less than that.

[0053] The bonding in step 302 may include pick-and-place assembly of high-end pre-fabricated chiplets 130 into cavities 120 on top surface 342 of adhesive laminate 340 .

[0054] Each chiplet 130 may include at least one of interconnects to active device circuitry and contact pads on the front side of the chiplet. Each chiplet 130 may be a pre-fabricated transistor chiplet.

[0055] 3C illustrates step 303 for forming device 313, which includes molding a lateral dielectric material 360 between chiplets 130 in cavity 120 and wafer 110. Step 303 may include molding lateral dielectric material 360 between side surfaces 236 of chiplets 130 in cavity 120 and side surfaces 116 of wafer 110. The lateral dielectric material 360 may mechano-chemically bond the side surfaces 136 of chiplets 130 to the side surfaces 116 of wafer 110. The lateral dielectric material 360 may fill gaps 150 between chiplets 130 and wafer 110. The lateral dielectric material 360 may completely fill the gap width gw and the gap thickness tw.

[0056] The molding in step 303 may include directly applying material 360 to side 136 of chiplet 130, top surface 342 of adhesive 340, and side 116 of wafer 110 such that material 360 contacts side 136, top surface 342, and side 116. The bond between material 360, side 136, top surface 342, and side 116 may be a covalent bond, a chemical bond, or an atomic bond. The bond may be an adhesive bond formed by pressing material 360 into gap 350.

[0057] Step 303 may involve a lateral chip bonding process that bonds chiplets 130 to wafer 110 of devices 312 (e.g., see Figures 4A-4C for details). The aspect ratio, defined by the ratio of wafer (or chip) thickness t w to gap 150 width g w (e.g., the shortest distance between the vertical side of chip 236 and the side of through-hole 116), may be on the order of 100:1, but will typically be 10:1. In some cases, thickness t w is 1000 μm and width g w is 10 μm.

[0058] Figures 4A and 4B are flow diagrams illustrating two processes for step 303 of forming device 313 of Figure 3C, which is also shown in Figure 4C. The process of Figures 4A and 4B may form device 313 by forming lateral dielectric material 360 in gap 350. The flow diagrams of Figures 4A-4C include only the major process steps. Various conventional process steps (e.g., surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may occur before, between, after, and during the steps shown in Figures 4A-4C.

[0059] 4A shows step 401 for forming device 411, which includes printing bumps 480 of lateral dielectric material 360 on the backside 134 of a chiplet or the backside 112 of a wafer. Step 401 may include using a printing process to print bumps 480 of lateral dielectric material 360 into gaps 350 between sides 136 of the chiplet and sides 116 of the wafer 110, for example using a permanent screen, such as using a wafer with cavities as the screen that is printed by a printer.

[0060] Step 401 may include a screen printing process, where 484 may be a squeegee that spreads balls 480 of bonding material onto surfaces 134 and 112 and into gaps 350 as shown in Figure 4C. Figure 4A is thus a step in the process prior to Figure 4C where bumps 480 of adhesive are no longer present.

[0061] Step 401 may include using a printer 482 having a print head 484 to print bumps 480 of material 360 on the backside and within gaps 350 .

[0062] 4B illustrates step 402 for forming device 412, which includes bumps 480 of lateral dielectric material 360 pressed onto backside 134 of device 411. Step 402 may include using a molding process using vacuum and pressure to mold bumps 480 of lateral dielectric material 360 into gaps 350 between side surfaces 136 of the chiplet and side surfaces 116 of wafer 110. This molding may be performed using a liquid compression molding technique, such as liquid composite molding (LCM).

[0063] The printing at 401 and / or molding at 402 may use a squeegee or squeegee process to print and / or mold the bumps 480 into the gaps 350 .

[0064] After either step 401 or 402, Figure 4C shows step 403 for forming device 313 of Figure 3C. Either step 401 or 402 may include mechano-chemically bonding bumps 480 between side surfaces 236 of chiplets 130 in cavity 120 and side surfaces 116 of wafer 110 to form lateral dielectric material 360. Step 403 may include heating and / or curing the molding of step 401 or 402.

[0065] After step 303, Figure 3D illustrates step 304 for forming device 314, which includes backside capping 370 encapsulating backside 134 of chiplet, backside 112 of wafer 110, and top surface of lateral dielectric material 360. Step 304 may include encapsulating backside 134, backside 112, and top surface of lateral dielectric material 360 with backside capping layer 370 having top surface 372 and backside 374, such that area of ​​cavity 120 is disposed above area 376 of top surface 372 of backside capping layer 370. As shown, portion 376 and area 378 may be vertically aligned with laminate 340 and layer 370.

[0066] The encapsulation in step 304 may include depositing a backside capping layer 370 directly onto the backside 134, the backside 112, and the top surface of the lateral dielectric material 360 such that the layer 370 contacts the backside 134, the backside 112, and the top surface of the material 360. The encapsulation in step 304 may include embedding the chiplets 130 in the wafer 110 in the holes or cavities 120.

[0067] The encapsulation in step 304 may include encapsulating the reconstructed wafer / panel device 313 with a metallized layer 370 acting as a thermal plane, preferably having a thickness te on the order of 5-25 microns thick, in direct contact with the backside face 134 and front face 114 of the chip 130 and wafer 110.

[0068] Backside capping layer 370 may be a high thermal conductivity backside metallization layer that improves heat transfer from the chiplets to, for example, a wafer. Backside capping layer 370 may form a "thermal plane" for conducting heat from the chiplets. The thermal conductivity coefficient of backside capping layer 370 may be greater than the thermal conductivity coefficients of the wafer and the chiplets. The thermal expansion coefficient of backside capping layer 370 may be between the thermal expansion coefficients of the wafer and the chiplets.

[0069] 3E shows step 305 for forming device 315, which does not include adhesive laminate 340, but does include layer 370 over chiplet 130, wafer 110, and lateral dielectric material 360. FIG. 3E shows device 314 inverted and without laminate 340. Step 305 may include using a bath, liquid, and / or heat to remove or separate adhesive laminate 340 from the surfaces of chiplet 130, wafer 110, and lateral dielectric material 360. Step 305 may also be the removal of adhesive laminate 340 from device 314.

[0070] Because the chiplets 130 are attached to the inside of the cavity 120 by the material 360 , the chiplets 130 are maintained within the cavity 120 in their positions relative to the wafer 110 when attached to the laminate 340 .

[0071] After laminate 340 is removed, the exposed undersides of chiplets 130 and the wafer may be polished, such as by chemical mechanical polishing (CMP). In other cases, the undersides are not polished. Exposed surface 132 may be a surface bearing electrical components, which are then interconnected with conductors 510, as added in FIG. 3F. In some cases, chiplets 130 may be arranged so that the fabricated surface is maintained parallel to the front surface of wafer 110. This possibility may be used to increase the number of component chiplets 130 embedded in wafer 110 and / or when the side of chiplet 130 maintained parallel to the front surface of wafer 110 has a specific function. This may be the case, for example, when chiplet 130 is a semiconductor laser chip and its side is the side that emits the laser.

[0072] 3F illustrates step 306 for forming device 316, including interconnects 510 connecting chiplet contacts 118 and wafer contacts 138. Step 306 may include forming interconnects 510 directly on lateral dielectric material 360 to connect the chiplet contacts and wafer contacts. Interconnects 510 may be formed by electroplating a pattern of interconnects 510 through photoresist and then dissolving the photoresist. Interconnects 510 may also be formed by depositing a mask over the pattern of interconnects 510 and etching away the unpatterned portions of a conductive material, such as a metal.

[0073] Beneficially, interconnects 510 can be formed without the cost, processing, or material height associated with using solder or contact bumps on chiplet 130 or wafer 110 contacts.

[0074] Forming in step 306 may include directly depositing interconnects 510 onto material 360 such that interconnects 510 contact a top surface of material 360. Forming in step 306 may include forming interconnect 510 routes or traces directly from contacts 138 of chiplets 130 onto lateral dielectric material 360 (e.g., bonded to, directly deposited on, in contact with, and / or with no air gap between the interconnect and the dielectric) directly to electrical routing or contacts 118 of the wafer.

[0075] It is contemplated that the host wafer 110 may be vertically diced at dicing lines (indicated by vertical bars in FIG. 3F) along the periphery 386 of the wafer around at least one chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0076] 2 and 3F may show how the interconnect structure 510 rests directly on top of the dielectric bonding material 360 between the chiplet 130 and the wafer 110.

[0077] Beneficially, the lateral mechano-chemical chiplet bonding of step 303 and / or the use of dielectric 360 are (1) low cost, such as by using a low-cost process and material such as dielectric 360 of step 303, and (2) volume-scalable, such as by allowing the size and number of chiplets 130 to be easily changed. Beneficially, the lateral mechano-chemical chiplet bonding of step 303 and / or the use of dielectric 360 mitigates the mismatch in thermal expansion coefficients between silicon wafer frame 110 and chiplets 130, such as by dielectric 360 having a thermal expansion coefficient that is close to or between one of the thermal expansion coefficients of wafer 110 and chiplets 130. Beneficially, the lateral mechano-chemical chiplet bonding of step 303 and / or the use of dielectric 360 enables (1) direct interconnect routing (e.g., without dielectric / air gaps) from chiplets 130 to wafer 110 electrical routing, and (2) low-loss, high-performance DC, RF, and mm-wave signal transmission between chiplets 130 and wafer 110 electrical routing, where (1) and (2) may use interconnect 510 between chiplet 130 and wafer 110 contacts, which may be formed on the surface of dielectric 360.

[0078] Beneficially, the lateral mechano-chemical chiplet bonding and / or use of dielectric 360 in step 303 reduces noise and frequency variations in the interconnect routing from the chiplets 130 to the wafer 110 electrical routing compared to using a semiconductor or conductor material in place of dielectric 360. Beneficially, the lateral mechano-chemical chiplet bonding and / or use of dielectric 360 in step 303 reduces capacitance for high frequency signals and lowers signal loss in the interconnect routing from the chiplets 130 to the wafer 110 electrical routing compared to using a semiconductor or conductor material in place of dielectric 360. Beneficially, the lateral mechano-chemical chiplet bonding and / or use of dielectric 360 in step 303 reduces material and processing costs for forming the lateral bonding material between the chiplets 130 and the wafer 110 compared to using a semiconductor or conductor material in place of dielectric 360.

[0079] In addition to these benefits, the lateral mechanical-chemical dielectric bonding process is augmented by the benefits of steps 304-304 and / or the use of a backside capping layer 370, which provides a high thermal conductivity backside metallization 370 on the reconstructed wafer 314 or 200, improving heat transfer from the chiplets 130 to the layer 370, which may be a "thermal plane" for the wafer 110 and device 200.

[0080] Processes 301-306 allow multiple electronic assemblies to be fabricated simultaneously, where multiple component chiplets 130 are provided and attached to multiple predetermined locations (e.g., areas 378) of laminate 340. Chiplets 130 may actually include multiple identical or different component chips, each of which may have its front side 132 temporarily attached to a predetermined location on top surface 342. In some cases, the various component chips may have different thicknesses, subject to the constraint that they may not be thicker than wafer 110.

[0081] Chiplets 130 are preferably pre-tested to verify their functionality. As a result, the yield of final devices 200 or diced devices is significantly improved over the assembly of component chips where the functionality of the component chips is not verified until after the assembly.

[0082] Embedding the chiplets 130 (including, for example, a single chip or multiple component chips) in the cavity 120 filled with the dielectric 360 allows for a desirable increase in the evacuation of any chip-generated heat from the chiplets during use into the wafer 110. This increased evacuation advantageously significantly limits any change in size of the chiplets due to temperature changes, allowing any mechanical strain due to such size changes to remain advantageously small. Another advantage is that the dielectric 360 may be elastic and flexible to better accommodate size changes. This heat evacuation is improved by connecting the bottom of the chiplets 130 with a metallic backside capping layer 370, such as a metal plate, formed on a portion of the underside of the wafer 110. As shown in FIG. 3 , a metallic (e.g., gold) backside capping layer 370 may be formed on the chiplets 130 and the bottom of the wafer 110. Doing so improves the thermal conductivity and interface between the chiplets 130, material 360, and wafer 110, further increasing the desired evacuation of any chip-generated heat from the chiplets to layer 370 during use of the chiplets.

[0083] Advantageously, by allowing different electrical components of the chiplets 130 to be manufactured separately from each other and from the wafer 110, all of the electronic components of the chiplets 130 and wafer 110 can be tested separately before assembling them. If a particular electrical component chiplet 130 or one component of the wafer 110 has an insufficient manufacturing yield, it is possible to separately spend time and money to improve the manufacturing yield of that electrical component and manufacture a finished product device 200 or die thereof that also includes the chiplet 130 within the cavity of the wafer 110. For example, if the electrical components of the chiplets 130 of a particular chiplet type have an insufficient manufacturing yield, it is possible to separately spend time and money to improve the manufacturing yield of that electrical component chiplet type and manufacture a finished product device 200 or die thereof that includes the chiplet 130 and wafer 110 without spending time and money to improve the manufacturing yield of other types of chiplets 130 or components of the wafer 110.

[0084] Furthermore, because embodiments allow different electrical component ones of chiplets 130 to be fabricated separately from each other and from wafer 110, it is not necessary to expose chiplets 130 and wafer 110 of all component types to fabrication steps for all different electrical component ones of chiplets 130, which could damage other ones of chiplets 130 or could damage wafer 110.

[0085] Thus, embodiments may reduce manufacturing costs by using small component chips in chiplets 130 made of exotic and expensive materials with specific characteristics and combining them with integrated circuits on other chiplets 130 and / or wafers 110 made of cheaper and more common materials with more common characteristics.

[0086] According to embodiments, chiplets 130 may include GaN, InP, or GaAs electrical components and may be fabricated on substrates such as Si, SiGe, InP, GaAs, alumina, or diamond. In some cases, the electrical components or integrated circuits of host wafer 110 may include metal routing and passive components fabricated on a wafer scale. In some cases, interconnects 510 may be fabricated using conductors fabricated in thin films, thick plated interconnects, multilayers, etc. The interconnects may also be fabricated using, for example, back-end steps of a manufacturing process. [Example]

[0087] (Example)

[0088] Examples of the technology herein include an electronic assembly including: a backside capping layer having a top surface and a backside; a wafer having a front surface and a backside, the backside of the wafer bonded to the top surface of the backside capping layer except for a cavity in the wafer formed over a plurality of areas of the top surface of the backside capping layer, the cavity having side surfaces; a plurality of chiplets having a backside and a front side, the backside of the chiplet bonded directly to at least a portion of the plurality of areas of the top surface of the backside capping layer; a lateral dielectric material between the side surfaces of the chiplets and the side surfaces of the cavity, the lateral dielectric material bonding the side surfaces of the chiplets to a side surface of the wafer; and direct interconnections of conductive material from the plurality of chiplets directly over the lateral dielectric material to wafer electrical routing of the wafer.

[0089] Examples include the backside of the wafer being directly attached to and in contact with the top surface of the backside capping layer except for the cavities, and the backside of the chiplet being directly attached to and in contact with multiple areas of the top surface of the backside capping layer.

[0090] Examples include the lateral dielectric material being disposed in a gap between a side of the chiplet and a side of the wafer; the width of the gap being 1 / 5 (one-fifth) to 10 times the thickness of the wafer or chiplet.

[0091] Examples include the backside capping layer being a high thermal conductivity backside metallization layer that improves heat transfer from the chiplet to the wafer.

[0092] Examples include the coefficient of thermal expansion of the lateral dielectric material layer being between the coefficients of thermal expansion of the wafer and the chiplets.

[0093] Examples include the lateral dielectric material being a molding compound and the bonding being a mechanical-chemical bond.

[0094] Examples include: the wafer includes at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers; the wafer includes at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material; each chiplet includes transistor circuitry and direct interconnects to contact pads on the front surface of the chiplet; and each chiplet is one of high-end pre-fabricated transistor chiplets or is integrated into a wafer using pick-and-place assembly on a temporary wafer.

[0095] An example includes direct interconnects connecting contacts on the chiplet to contacts on the wafer.

[0096] An embodiment includes dicing the wafer vertically along the periphery of the wafer around at least one chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0097] Examples include the backside capping layer being a single integral layer attached directly to the chiplets.

[0098] An embodiment includes that the direct interconnect includes a radio frequency (RF) interconnect connecting the plurality of chiplets for transmitting RF signals between the plurality of chiplets.

[0099] Examples of the technology herein include a method for assembling an electronic assembly, the method including the steps of: forming a cavity through a wafer having a front surface and a back surface, the cavity having a side surface of the wafer; bonding the front surface of the wafer to a top surface of an adhesive laminate having a top surface and a bottom surface so that the cavity is disposed over a plurality of areas of the top surface of the adhesive laminate; bonding front sides of a plurality of chiplets, having a back side and a front side, to portions of the plurality of areas of the top surface of the adhesive laminate; molding a lateral dielectric material between the side surfaces of the chiplets and sides of the cavity, the lateral dielectric material mechanically and chemically bonding the side surfaces of the chiplets and the sides of the cavity; encapsulating the back sides of the plurality of chiplets, the lateral dielectric material, and the back surface of the wafer on top of a backside capping layer having a top surface and a backside, the backside capping layer being a single, integral layer directly attached to the plurality of chiplets; and removing the adhesive laminate.

[0100] Examples include: bonding the front side of the wafer to the top surface of the adhesive laminate includes directly adhering the front side of the wafer excluding the cavities to the top surface of the adhesive laminate; bonding the front sides of the plurality of chiplets to portions of the plurality of areas includes directly adhering the front sides of the chiplets to the plurality of areas on the top surface of the adhesive laminate; and encapsulating the back sides of the chiplets, the lateral dielectric material, and the wafer backside of the wafer on the top surface of the backside capping layer includes directly adhering the back sides of the chiplets, the lateral dielectric material, and the wafer backside of the wafer to the top surface of the backside capping layer.

[0101] Examples include where forming the cavities includes etching through-substrate holes in the front or back side of the wafer, and encapsulating includes embedding the chiplets in the wafer in the through-substrate holes.

[0102] Examples include where molding the lateral dielectric material includes one of: using a permanent screen to print the lateral dielectric material in the gaps between the sides of the chiplet and the side of the wafer; or using vacuum and pressure to mold the lateral dielectric material in the gaps between the sides of the chiplet and the side of the wafer.

[0103] An embodiment includes bonding the front sides of the plurality of chiplets to portions of the plurality of areas includes pick-and-place assembling pre-fabricated transistor chiplets onto the top surface of the adhesive laminate.

[0104] Embodiments include further including forming a plurality of interconnects directly on the lateral dielectric material to connect contacts of the chiplets with contacts of the wafer.

[0105] An embodiment includes further including, after removing the adhesive laminate, forming direct interconnects from the chiplets directly onto the lateral dielectric material to the wafer electrical routing.

[0106] An embodiment includes further including vertically dicing the periphery of the wafer around the chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0107] Examples include the step of joining the front sides of the plurality of chiplets followed by the step of molding; the step of encapsulating followed by the step of molding; and the step of removing followed by the step of encapsulating.

[0108] Examples of the technology herein include a method of assembling an electronic assembly, the method including: bonding a front side of a wafer having a cavity with a front side, a back side, and a side of the wafer to a top side of an adhesive laminate having a top side and a bottom side, such that the cavity is disposed over a plurality of areas of the top side of the adhesive laminate; bonding front sides of a plurality of chiplets having a back side and a front side to portions of the plurality of areas of the top side of the adhesive laminate; molding a lateral dielectric material between the side sides of the chiplets and the side sides of the cavity, wherein the lateral dielectric material bonds the side sides of the chiplets and the side sides of the cavity; and forming direct interconnections of conductive material directly from the chiplets onto the lateral dielectric material to wafer electrical routing of the wafer.

[0109] An embodiment includes further including the steps of: encapsulating the backside of the chiplet, the lateral dielectric material, and the backside of the wafer on top of a backside capping layer having a top surface and a backside; and removing the adhesive laminate.

[0110] Examples include: bonding the front side of the wafer to the top surface of the adhesive laminate includes directly adhering the front side of the wafer excluding the cavities to the top surface of the adhesive laminate; bonding the front sides of the plurality of chiplets to portions of the plurality of areas includes directly adhering the front sides of the chiplets to the plurality of areas on the top surface of the adhesive laminate; and encapsulating the back sides of the chiplets, the lateral dielectric material, and the wafer backside of the wafer on the top surface of the backside capping layer includes directly adhering the back sides of the chiplets, the lateral dielectric material, and the wafer backside of the wafer to the top surface of the backside capping layer.

[0111] Examples include where molding the lateral dielectric material includes one of: using a permanent screen to print the lateral dielectric material in the gaps between the sides of the chiplet and the side of the wafer; or using vacuum and pressure to mold the lateral dielectric material in the gaps between the sides of the chiplet and the side of the wafer.

[0112] An embodiment includes bonding the front sides of the plurality of chiplets to portions of the plurality of areas includes pick-and-place assembling pre-fabricated transistor chiplets onto the top surface of the adhesive laminate.

[0113] An embodiment includes further including vertically dicing the periphery of the wafer around the chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0114] An embodiment includes that the direct interconnect includes a radio frequency (RF) interconnect connecting the plurality of chiplets for transmitting RF signals between the plurality of chiplets.

[0115] Examples include the step of joining the front sides of the plurality of chiplets followed by the step of molding; and the step of forming followed by the step of molding.

[0116] (Conclusion)

[0117] The embodiments and examples shown throughout this description should be considered exemplars, not limitations on the devices and procedures disclosed or claimed. While many of the examples presented herein include specific combinations of method operations or system components, it should be understood that those operations and those components may be combined in other ways to achieve the same purpose. With respect to flow diagrams, additional and fewer steps may be performed, and steps shown may be combined or further improved to achieve the methods described herein. Operations, components, and features discussed in connection with only one embodiment are not intended to be excluded from a similar role in other embodiments.

[0118] As used herein, "plurality" means two or more. As used herein, a "set" of an item may include one or more such items. As used herein, terms such as "comprising," "including," "carrying," "having," "containing," and "involving," as used in the written description or claims, should be understood to be open-ended, i.e., to mean including, but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of," respectively, are closed or semi-closed transitional phrases with respect to claims. The use of ordinal terms, such as "first," "second," and "third," in the claims to modify claim elements does not, by itself, imply any priority, precedence, or order of one claim element relative to another, nor does it imply a chronological order for performing the actions of a method, but is merely used as a label to distinguish one claim element having a certain name from another element having the same name (absent the use of ordinal terms). As used herein, "and / or" means that the listed items are alternatives, but that any combination of the listed items is also included in the alternatives.

Claims

1. a backside capping layer having a top surface and a back surface; a wafer having a front surface and a back surface, the back surface of the wafer being bonded to the top surface of the backside capping layer except for a cavity in the wafer formed over a plurality of areas of the top surface of the backside capping layer, the cavity having sides; a plurality of chiplets having a backside and a frontside, the backsides of the chiplets directly bonded to at least a portion of the plurality of areas of the top surface of the backside capping layer; a lateral dielectric material between a side surface of the chiplet and the side surface of the cavity, a lateral dielectric material, the lateral dielectric material joining the side of the chiplet and the side of the wafer; direct interconnection of conductive material from the plurality of chiplets directly onto the lateral dielectric material to wafer electrical routing of the wafer; 2. An electronic assembly comprising:

2. the backside of the wafer is directly attached to and in contact with the top surface of the backside capping layer except for the cavity; The electronic assembly of claim 1 , wherein the backside of the chiplet is directly attached to and in contact with the plurality of areas of the top surface of the backside capping layer.

3. 2. The electronic assembly of claim 1, wherein the lateral dielectric material is disposed in a gap between the side of the chiplet and the side of the wafer; and the width of the gap is 1 / 5 (one-fifth) to 10 times the thickness of the wafer or chiplet.

4. 10. The electronic assembly of claim 1, wherein the backside capping layer is a high thermal conductivity backside metallization layer that improves heat transfer from the chiplets to the wafer.

5. The electronic assembly of claim 1 , wherein the coefficient of thermal expansion of the lateral dielectric material layer is between the coefficients of thermal expansion of the wafer and the chiplets.

6. 2. The electronic assembly of claim 1, wherein said lateral dielectric material is a molding compound and said bonding is a mechanical-chemical bonding.

7. the wafer includes at least one of a resistor, a capacitor, an inductor, a through-substrate via, a dielectric layer, and a metal layer; the wafer comprises at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material; each chiplet including transistor circuitry and said direct interconnects to contact pads on the front surface of said chiplet; 10. The electronic assembly of claim 1, wherein each chiplet is one of high-end pre-fabricated transistor chiplets or is integrated onto a temporary wafer using pick-and-place assembly on the wafer.

8. The electronic assembly of claim 1 , wherein the direct interconnects connect contacts of the chiplets with contacts of the wafer.

9. 10. The electronic assembly of claim 1, wherein the wafer is diced vertically along a periphery of the wafer around at least one chiplet to form a chip having the at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

10. The electronic assembly of claim 1 , wherein the backside capping layer is a single, integral layer attached directly to the plurality of chiplets.

11. The method of claim 1 , wherein the direct interconnect comprises a radio frequency (RF) interconnect connecting the plurality of chiplets for transmitting RF signals between the plurality of chiplets.

12. 1. A method of assembling an electronic assembly, comprising: forming a cavity through a wafer having a front surface and a back surface, the cavity comprising a side surface of the wafer; bonding the front surface of the wafer to the top surface of the adhesive laminate, the adhesive laminate having the top and bottom surfaces, such that the cavities are disposed over a plurality of areas of the top surface of the adhesive laminate; bonding the front sides of a plurality of chiplets, each having a back side and a front side, to portions of the plurality of areas of the top surface of the adhesive laminate; molding a lateral dielectric material between a side surface of the chiplet and the side surface of the cavity, the lateral dielectric material mechanochemically bonding the side surface of the chiplet and the side surface of the cavity; encapsulating the backsides of the plurality of chiplets, the lateral dielectric material, and the backside of the wafer at the top surface of a backside capping layer having a top surface and a backside, the backside capping layer being a single, integral layer adhered directly to the plurality of chiplets; removing the adhesive laminate; A method comprising:

13. bonding the front surface of the wafer and the top surface of the adhesive laminate includes directly adhering the front surface of the wafer, excluding the cavity, to the top surface of the adhesive laminate; bonding the front sides of the plurality of chiplets to the portions of the plurality of sections includes directly adhering the front sides of the chiplets to the plurality of sections of the top surface of the adhesive laminate; 13. The method of claim 12, wherein encapsulating the backside of the chiplet, the lateral dielectric material, and the wafer backside of the wafer at the top surface of the backside capping layer comprises directly adhering the backside of the chiplet, the lateral dielectric material, and the wafer backside of the wafer to the top surface of the backside capping layer.

14. 13. The method of claim 12, wherein forming the cavity comprises etching through-substrate holes in the front or back side of the wafer, and encapsulating comprises embedding the chiplets in the wafer in the through-substrate holes.

15. shaping the lateral dielectric material; printing the lateral dielectric material in the gap between the side of the chiplet and the side of the wafer using a permanent screen; or molding the lateral dielectric material into the gap between the side of the chiplet and the side of the wafer using vacuum and pressure.

13. The method of claim 12, comprising one of:

16. 13. The method of claim 12, wherein bonding the front sides of the plurality of chiplets to the portions of the plurality of areas comprises pick-and-place assembling pre-fabricated transistor chiplets onto the top surface of the adhesive laminate.

17. 13. The method of claim 12, further comprising forming a plurality of interconnects directly on the lateral dielectric material to connect contacts of the chiplets with contacts of the wafer.

18. 13. The method of claim 12, further comprising forming direct interconnects from the chiplets directly onto the lateral dielectric material to wafer electrical routing after removing the adhesive laminate.

19. 13. The method of claim 12, further comprising vertically dicing the periphery of the wafer around the chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

20. a molding step occurs after the step of joining the front sides of the plurality of chiplets; The encapsulation step occurs after the molding step; 13. The method of claim 12, wherein the removing step occurs after the encapsulating step.

21. 1. A method of assembling an electronic assembly, comprising: bonding the front surface of the wafer having a cavity with a front surface, a back surface, and a side surface of the wafer to the top surface of an adhesive laminate having a top surface and a bottom surface such that the cavity is disposed over a plurality of areas of the top surface of the adhesive laminate; bonding the front sides of a plurality of chiplets, each having a back side and a front side, to portions of the plurality of areas of the top surface of the adhesive laminate; molding a lateral dielectric material between a side surface of the chiplet and the side surface of the cavity, the lateral dielectric material joining the side surface of the chiplet and the side surface of the cavity; forming direct interconnections of conductive material directly from the chiplets onto the lateral dielectric material to wafer electrical routing of the wafer; A method comprising:

22. encapsulating the backside of the chiplet, the lateral dielectric material, and the backside of the wafer at the top surface of a backside capping layer having a top surface and a backside; removing the adhesive laminate; 22. The method of claim 21 further comprising:

23. bonding the front surface of the wafer and the top surface of the adhesive laminate includes directly adhering the front surface of the wafer, excluding the cavity, to the top surface of the adhesive laminate; bonding the front sides of the plurality of chiplets to the portions of the plurality of sections includes directly adhering the front sides of the chiplets to the plurality of sections of the top surface of the adhesive laminate; 23. The method of claim 22, wherein encapsulating the backside of the chiplet, the lateral dielectric material, and the wafer backside of the wafer at the top surface of the backside capping layer comprises directly adhering the backside of the chiplet, the lateral dielectric material, and the wafer backside of the wafer to the top surface of the backside capping layer.

24. shaping the lateral dielectric material; printing the lateral dielectric material in the gap between the side of the chiplet and the side of the wafer using a permanent screen; or molding the lateral dielectric material into the gap between the side of the chiplet and the side of the wafer using vacuum and pressure.

22. The method of claim 21, comprising one of:

25. 22. The method of claim 21 , wherein bonding the front sides of the plurality of chiplets to the portions of the plurality of areas comprises pick-and-place assembling pre-fabricated transistor chiplets onto the top surface of the adhesive laminate.

26. 22. The method of claim 21, further comprising vertically dicing the periphery of the wafer around the chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

27. 22. The method of claim 21, wherein the direct interconnect comprises a radio frequency (RF) interconnect connecting the plurality of chiplets for transmitting RF signals between the plurality of chiplets.

28. a molding step occurs after the step of joining the front sides of the plurality of chiplets; 22. The method of claim 21, wherein the forming step occurs after the molding step.

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