Global shutter pixel with vertically integrated multiphase charge transfer

Abstract

The image sensor may include a plurality of pixels, each of which may include a photodiode having a charge storage region (“PD”), a floating diffusion region (“FD”), and a vertical charge transfer region between the PD and the FD. The vertical charge transfer region may include a first charge modulation region (“P1”), a second charge modulation region (“P2”), and a third charge modulation region (“P3”). The image sensor may operate in a global shutter mode, in which P2 may be used as an in-pixel charge memory region for temporarily storing charge during the transfer of charge from the PD to the FD via P1, P2, and P3.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to image sensors, and more particularly to image sensor pixels having vertically integrated multiphase charge transfer for image capture in global shutter mode. [Background technology]

[0002] Image capture devices such as cameras are widely used in various electronic devices, such as mobile devices (e.g., smartphones, tablets, laptops, etc.), robotic equipment, or security surveillance devices, among others. An image capture device may include an image sensor having a plurality of light-gathering pixels. Each pixel may include a photodiode. The image capture device can capture light from the environment and pass the light to the image sensor. When exposed to light, the photodiode of a pixel can accumulate an electric charge. During readout, the charge in the photodiode can be read out from the photodiode using one or more transistors to generate an analog image signal. The analog image signal can be converted to a digital signal and further processed to generate an image. [Brief explanation of the drawings]

[0003] [Figure 1] 1A-1C illustrate top and cross-sectional views of an exemplary pixel of an image sensor, according to some embodiments.

[0004] [Figure 2] 1 illustrates an exemplary implementation of a control gate of a pixel of an image sensor according to some embodiments.

[0005] [Figure 3] 1 illustrates an exemplary implementation of a vertical gate area of ​​a pixel of an image sensor according to some embodiments.

[0006] [Figure 4A]3A-3C show exemplary timing diagrams of control signals and potential profiles for pixels of an image sensor to illustrate charge transfer, according to some embodiments. [Figure 4B] 3A-3C show exemplary timing diagrams of control signals and potential profiles for pixels of an image sensor to illustrate charge transfer, according to some embodiments. [Figure 4C] 3A-3C show exemplary timing diagrams of control signals and potential profiles for pixels of an image sensor to illustrate charge transfer, according to some embodiments. [Figure 4D] 3A-3C show exemplary timing diagrams of control signals and potential profiles for pixels of an image sensor to illustrate charge transfer, according to some embodiments.

[0007] [Figure 5A] 1 illustrates a cross-sectional view of an exemplary pixel and a top view of an image sensor, according to some embodiments.

[0008] [Figure 5B] 1 illustrates exemplary control signals applied to different components of multiple pixels of an image sensor according to some embodiments.

[0009] [Figure 6] 1A-1C illustrate top and cross-sectional views of another exemplary pixel of an image sensor, according to some embodiments.

[0010] [Figure 7] 1 illustrates an exemplary isolation structure for a pixel of an image sensor, according to some embodiments.

[0011] [Figure 8] 1 illustrates an exemplary split pixel for autofocus applications, according to some embodiments.

[0012] [Figure 9] 1A-1C illustrate top and cross-sectional views of another exemplary pixel of an image sensor, according to some embodiments.

[0013] [Figure 10] 1A-1C illustrate top and cross-sectional views of another exemplary pixel of an image sensor, according to some embodiments.

[0014] [Figure 11] 1A-1C illustrate top and cross-sectional views of another exemplary pixel of an image sensor, according to some embodiments.

[0015] [Figure 12] FIG. 1 is a block diagram of an exemplary image capture device, according to some embodiments.

[0016] [Figure 13] 1 is a flowchart illustrating an exemplary method for using in-pixel charge memory regions to operate an image sensor in global shutter mode, according to some embodiments.

[0017] [Figure 14] FIG. 1 is a schematic diagram of an example device that may include an image capture device (e.g., a camera) having an image sensor that includes pixels with the disclosed in-pixel charge memory regions, according to some embodiments.

[0018] [Figure 15] FIG. 1 shows a schematic block diagram of an exemplary computing device, referred to as a computer system, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor that includes pixels with the disclosed intra-pixel charge memory regions, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0019] This specification includes references to "one embodiment" or "an embodiment." The phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0020] "Comprising." This term is open-ended. As used in the following claims, this term does not exclude additional structures or steps. Consider a claim that reads "an apparatus comprising one or more processor units...." Such a claim does not exclude the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

[0021] "Configured to." Various units, circuits, or other components may be described or claimed as being "configured to" perform a task or tasks. In this context, "configured" is used to connote structure by indicating that the unit / circuit / component includes structure (e.g., a circuit) that performs that task or tasks during operation. In that way, a unit / circuit / component can be said to be configured to perform a task even when the specified unit / circuit / component is not currently operational (e.g., not turned on). A unit / circuit / component used with the phrase "configured to" includes hardware, e.g., a circuit, memory that stores executable program instructions to perform an operation, etc. A statement that a unit / circuit / component is "configured to" perform one or more tasks expressly intends that 35 U.S.C. § 112(f) will not be invoked with respect to that unit / circuit / component. Additionally, "configured to" can include general-purpose structure (e.g., general-purpose circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the task(s) in question. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) adapted to perform or execute one or more tasks.

[0022] "first," "second," etc. As used herein, these terms are used as indicators of the nouns that follow and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing write operations on "first" and "second" values. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value.

[0023] "Based on." As used herein, this term is used to describe one or more factors that influence a decision. This term does not exclude additional factors that may influence the decision. That is, the decision may be based solely on those factors, or at least in part on those factors. Consider the phrase "determining A based on B." In this case, B is a factor that influences the decision on A, but such a phrase does not exclude that the decision on A is also based on C. In other examples, A may be determined solely on B.

[0024] In this specification, terms such as "first," "second," etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the intended scope. Although a first contact and a second contact are both contacts, they are not the same contact.

[0025] The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, as used herein, the term "and / or" should be understood to refer to and include any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] As used herein, the term "if" can be interpreted to mean "when," "upon," "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (a stated condition or event) is detected" can be interpreted to mean "upon determining," "in response to determining," "upon detecting (the stated condition or event)," or "in response to detecting (the stated condition or event)," depending on the context.

[0027] Various embodiments described herein relate to image sensors operating in a global shutter mode. In some embodiments, the image sensor may include a plurality of light-gathering pixels organized into a pixel array, for example, having one or more rows and one or more columns of pixels. In some embodiments, the image sensor may be a CMOS (complementary metal-oxide semiconductor) image sensor, a CCD (charge-coupled device) image sensor, or the like. In some embodiments, the image sensor may be part of an image capture device such as a camera, which may in turn be part of an electronic device such as a mobile device (e.g., a smartphone, tablet, laptop, etc.), a robotic device, or a security surveillance device, among others. In some embodiments, the pixels of the image sensor may each include at least one photodiode having a charge accumulation region (hereinafter "PD"), a floating diffusion region (hereinafter "FD"), and a charge transfer region perpendicular to the PD and the FD. When exposed to light, the PD may accumulate charge or photocarriers for each pixel. During readout, at least a portion of the charge can be transferred from the PD to the FD to generate an analog image signal (e.g., an analog voltage) at the FD, which can be further accessed at pixel output lines external to the pixel. In some embodiments, the analog image signal accessed via the pixel output lines can be further processed, for example, analog-to-digital converted using analog-to-digital converter(s), and digitally processed by an image signal processor (ISP), to generate one or more images.

[0028] Generally, a given image capture device can operate in either a rolling shutter mode or a global shutter mode. With a rolling shutter, different lines of a pixel array of an image sensor of the image capture device can be exposed to light at different times as a readout "wave" sweeps through the image sensor. For example, pixels of the pixel array can be exposed, and their image signals can be read out sequentially, row by row, from the top to the bottom of the pixel array. For example, pixels in the same row can be read out simultaneously, while pixels in the same column but different rows can be read out sequentially, one at a time. Thus, with a rolling shutter, the image sensor can record an image sequentially, row by row, rather than capturing the entire image at once. By comparison, with a global shutter, all pixels can have the same exposure time, meaning that each pixel in the image sensor can begin and end its exposure at the same time. This allows the entire image to be recorded at once. A rolling shutter can cause color and / or shade variations in the captured image because different "lines" of the image are recorded at different times. In some applications, e.g., in high-speed photography or recording, this can cause serious distractions and significantly affect the quality of the captured image. Therefore, in some embodiments, a global shutter may be preferred. However, in some embodiments, even if the pixels of an image sensor finish exposure at the same time, their image signals may still be read out sequentially, e.g., row by row, as in a rolling shutter. Thus, the image sensor may require a "memory" to temporarily store the pixel's (a) charge (e.g., in the charge domain) and / or (b) analog or digital image signal (e.g., in the voltage domain) at the end of exposure until the individual pixel is read out.

[0029] To solve this problem, in some embodiments, the pixels of the image sensors disclosed herein may each include an in-pixel charge memory area. At the end of exposure, charge may be transferred from the PD to the in-pixel charge memory area. The charge may be temporarily stored there until pixel readout. During readout, charge may be transferred from the in-pixel charge memory area to the FD, from which analog image information may be further accessed via a pixel output line. Those skilled in the art will appreciate that the disclosed image sensors can offer several advantages. First, each pixel may be provided with an in-pixel charge memory area to temporarily store pixel charge, thus enabling the image sensor to operate in a global shutter mode. Furthermore, "memory" may be integrated as part of the pixel to store charge within the pixel, thus eliminating or at least reducing other additional memory storage components (e.g., a memory chip on the image sensor). As a result, this may reduce the number of components for the image sensor, reduce the footprint of the image sensor, and / or increase the pixel density of the sensor.

[0030] FIG. 1 illustrates a top view and a cross-sectional view of an exemplary pixel of an image sensor, according to some embodiments. As shown, in some embodiments, pixel 100 may be formed on or in a substrate 130, e.g., a substrate made of silicon or other semiconductor material. In some embodiments, pixel 100 may be one of multiple pixels of an image sensor of an image capture device (e.g., a CMOS image sensor, a CCD image sensor, etc.). In some embodiments, pixel 100 may include one or more circuits (e.g., pixel readout circuitry) formed using one or more transistors to read out image signals from pixel 100 and generate one or more analog signals (e.g., analog voltages) at pixel output lines, and / or other signal conditioning or processing circuitry. For purposes of illustration, the circuits are not shown in FIG. 1 .

[0031] 1, in some embodiments, pixel 100 may include at least one photodiode comprising a charge storage region 102 (hereinafter, "PD"), a floating diffusion region 104 (hereinafter, "FD"), and at least one charge transfer region formed vertically between PD 102 and FD 104. As shown in FIG. 1, in some embodiments, PD 102 and FD 104 may be vertically arranged one relative to the other, for example, such that PD 102 is disposed below and at least partially overlaps FD 104, and FD 104 is disposed proximate a top surface of pixel 100. Additionally, in some embodiments, the at least one charge transfer region may include multiple charge modulation regions, for example, phase 1 charge modulation region 106 (hereinafter, "P1"), phase 2 charge modulation region 108 (hereinafter, "P2"), and phase 3 charge modulation region 110 (hereinafter, "P3"). 1 , in some embodiments, P1 106, P2 108, and P3 110 may be stacked vertically between the PD 102 and the FD 104. For example, P1 106 may be formed above the PD 102 and at least partially overlap it, P2 108 may be formed above the P1 106 and at least partially overlap it, and P3 110 may be (a) formed above the P2 108 and at least partially overlap it, or (b) formed below the FD 104 and at least partially overlap it. As a result, P1 106, P2 108, and P3 110 may be stacked together and collectively form a charge transfer region vertically between the PD 102 and the FD 104. In some embodiments, at least a portion of P3 110 may optionally be spaced apart from FD 104 by a physical gap. For example, in some embodiments, the physical gap may be located at an upper corner of P3 110 that interfaces with FD 104. The physical gap may provide a potential barrier (e.g., an electrostatic potential barrier) between P3 110 and FD 104, thereby preventing charge transfer from P3 110 to FD 104.

[0032] In some embodiments, P1 106, P2 108, and P3 110 may each be controlled by a control signal (e.g., a control voltage) applied to a respective control gate. Furthermore, each control gate may include a vertical gate area (hereinafter, "G") and an associated gate contact (hereinafter, "GC"). For example, the control gate of P1 106 may include a first vertical gate area 112 (hereinafter, "G1"), which may be further electrically connected to a first gate contact 122 (hereinafter, "GC1") disposed within the gate control area 120. Similarly, the control gate of P2 108 may include a second vertical gate area 114 (hereinafter, "G2") and a second gate contact 124 (hereinafter, "GC2") disposed within the gate control area 120. The control gate of P3 110 may include a third vertical gate area 116 (hereinafter referred to as "G3") and a third gate contact 126 (hereinafter referred to as "G3") disposed within the gate control area 120. In some embodiments, G1 112, G2 114, and G3 116 may be formed using a polysilicon material and embedded within the substrate 130. In some embodiments, G1 122, GC2 124, and GC3 126 may be formed using a metal or polysilicon material and may function as respective "electrodes" for receiving control signals (e.g., control voltages) applied to G1 112, G2 114, and G3 116. As shown in FIG. 1 , in some embodiments, the pixel 100 may include a region 132 in an outer layer surrounding the periphery of the pixel 100 that is separated from the substrate 130 by a dielectric material 150. In some embodiments, the region 132 may be formed using a polysilicon or metal material. In some embodiments, region 132 may attract holes from PD 102, thus promoting the accumulation of charge in PD 102 when PD 102 is exposed to light.

[0033] 1, in this example, G1 112, G2 114, and G3 116 may be positioned vertically on top of one another (thus only G3 116 is visible in top view) laterally adjacent to their corresponding modulation regions P1 106, P2 108, and P3 110. Furthermore, G1 112, G2 114, and G3 116 do not necessarily vertically overlap FD 104 as shown in FIG. 1. In this example, G1 112, G2 114, and G3 116 may be stacked vertically on top of one another. Additionally, G1 112, G2 114, and G3 116 each have a ring-shaped configuration and may therefore completely enclose their corresponding modulation regions P1 106, P2 108, and P3 110, and FD 102 (only laterally, as they do not overlap FD 102 vertically, as explained above). As a result, the potentials of P1 106, P2 108, and P3 110 may be separately modulated or controlled by respective control signals applied to G1 112, G2 114, and G3 116. For example, in some embodiments, the potential of P1 106 may be modulated by a control voltage signal applied to G1 112. For example, in some embodiments, P1 106 may be implanted with one or more p-type dopants. When a positive voltage is applied to G1 112, the positive voltage may repel holes in the layer of P1 106 interfacing with G1 112 away from G1 112, thus creating a channel in the interface layer. As a result, charge may migrate from PD 102 through the channel in P1 106. Similarly, in some embodiments, the potential of P2 108 may be modulated by a control voltage signal applied to G2 114, forming a channel in P2 102 for charge to further migrate through P2 108. Similarly, in some embodiments, the potential of P3 110 may be modulated by a voltage control signal applied to G3, forming a channel in P3 110 for charge to further migrate through P3 110. As described in more detail below, in some embodiments, P2 108 may function as an intra-pixel charge memory region for temporarily storing charge generated from PD 102.For example, at the end of exposure, charge may first be transferred from PD 102 to P2 108 via P1 106. The charge may be temporarily stored in P2 108 until readout of pixel 100. During readout, the charge may then be transferred from P2 108 to FD 104 via P3 110. Also, as shown in FIG. 1 , in this example, pixel 100 may be configured to receive backside illumination. However, alternatively, in some embodiments, frontside illumination may be implemented.

[0034] In some embodiments, the FD 104 may include a capacitance. Thus, transfer of charge to the FD 104 may generate an analog voltage between the FD 104 and ground. The analog voltage may represent an image signal captured by the pixel 100. The analog voltage of the FD 104 may be further accessed and read out from the FD 104 using, for example, a pixel readout circuit formed by one or more transistors to generate an analog voltage at a pixel output line external to the pixel 100. In some embodiments, the image sensor may include multiple pixel output lines for reading out FD voltages from pixels in different columns (e.g., one pixel output line for one corresponding column in a row-by-row readout). In some embodiments, the image sensor may also include one or more analog-to-digital circuits for converting the analog voltages on the pixel output lines into digital signals. In some embodiments, the image sensor may further include a transfer circuit for transmitting the digital signal to an external component, for example, an image signal processor (ISP), for further digital processing to generate an image.

[0035] 2 shows an example implementation of control gates for pixels of an image sensor, according to some embodiments. As shown on the left side of the figure, in some embodiments, vertical gate areas G1 112, G2 114, and G3 116 may each include an extension to the surface of substrate 130. For example, G1 112, G2 114, and G3 116 may each have an L-shape embedded within substrate 130 that extends to the surface of substrate 130. Furthermore, G1 122, GC2 124, and GC3 126 may be attached to G1 112, G2 114, and G3 116 at the surface of substrate 130. Alternatively, as shown on the right side of FIG. 2, in some embodiments, G1 112, G2 114, and G3 116 may each have a horizontal I-shape embedded within the substrate 130, while G1 122, GC2 124, and GC3 126 may extend within the substrate 130 to be electrically connected to G1 112, G2 114, and G3 116.

[0036] FIG. 3 illustrates an exemplary implementation of vertical gate areas of a pixel of an image sensor, according to some embodiments. Unlike the vertical gate areas of FIG. 1 , in some embodiments, as shown on the left side of FIG. 3 , the vertical gate areas G1, G2, and G3 of the pixel (e.g., the third vertical gate area G3 316 seen in top view) may individually have a C-shaped geometry and thus may only partially (rather than completely) enclose (laterally) the FD 304 and corresponding charge modulation region. Similarly, each vertical gate area G1, G2, and G3 may be electrically connected to an associated gate contact (e.g., GC1, GC2, and GC3) to receive a respective control signal. Alternatively, as shown in the center of FIG. 3 , in some embodiments, the vertical gate areas of the pixel (e.g., the third vertical gate area G3 356 seen in top view) may individually have an I-shape disposed proximate to the FD 344 and corresponding charge modulation region. The cross-sectional views on the right side of Figure 3 represent cross-sectional views of both the C-shaped pixel and the I-shaped pixel described above. As shown in the cross-sectional views, the PD 342 and the FD 304 (in the case of a C-shaped pixel) or 344 (in the case of an I-shaped pixel) can still be arranged perpendicular to one another. Similarly, the vertical charge transfer region between the PD and the FD can include multiple charge modulation regions, such as P1 346, P2 348, and P3 350, stacked vertically on one another. However, unlike Figure 1, P1, P2, P3, and the FD have smaller cross-sectional areas and therefore may only partially, rather than completely, overlap with the PD 342. In some embodiments, different doping concentrations in P1, P2, and P3 of the C-shaped and I-shaped pixels can be introduced by implantation or other methods to create sufficient capacitance and facilitate vertical charge transfer. Note that Figures 1-3 are provided for illustrative purposes only and as non-limiting examples. In some embodiments, the various regions of the pixel can be formed and arranged in various ways. For example, in some embodiments, different embodiments of Figures 1-3 may be used in combination for a given pixel, such that some of the vertical gate areas of the pixel may be formed in a ring shape, while others may be formed in a C shape.

[0037] 4A-4D show example timing diagrams of control signals and potential profiles of pixels of an image sensor to illustrate charge transfer, according to some embodiments. In FIG. 4A, the horizontal axis represents time, and the vertical axis represents voltage control signals 422, 424, and 426 applied to gate areas G1 412, G2 414, and G3 416 of the pixel. As shown in FIG. 4A, the operation of the pixel can include three periods 432, 434, and 436. During the first period 432, all pixels of the image sensor (including those shown in FIGS. 4A-4D) can be exposed to light. For example, all pixels can begin exposure to light simultaneously at time 442 and end exposure simultaneously at time 444. Due to the exposure, all pixels can generate and accumulate charge within their respective PD regions during period 432. FIG. 4B shows potential profiles of different regions of pixels of the image sensor corresponding to period 432. 4B, during period 432, active control voltages 422, 424, and 426 are not applied (or are applied with a negative voltage, if desired) to G1 412, G2 414, and G3 416. For example, G1 412, G2 414, and G3 416 may be biased with zero voltage (or a negative voltage, if desired). Thus, charge may accumulate within PD 402, indicating that P1 406, P2 408, and P3 410 may be turned off. In some embodiments, different regions of the pixel may have different doping types and / or doping concentrations. For example, in some embodiments, PD 402 may be an n-type region formed with one or more n-type dopants, P1 406, P2 408, and P3 410 may be p-type regions formed with one or more p-type dopants, and P1, P2, and P3 may also be n-type regions with different doping concentrations. FD 404 may be an n-type region formed with one or more n-type dopants. Thus, as shown in FIG. 4B , the potential profiles of PD 402, P1 406, P2 408, P3 410, and FD 404 may have a multi-step shape. Additionally, in this example, P1 406, P2 408, and P3 410 may have the same doping concentration.4B, at turn-off, P1 406, P2 408, and P3 410 may have the same potential. Alternatively, in some embodiments, P1 406, P2 408, and P3 410 may have different doping concentrations, which may cause different potentials between these regions (e.g., in a multi-step configuration).

[0038] During the second period 434, after exposure has been completed for all pixels of the image sensor, all pixels may simultaneously transfer charge from their PD regions to their in-pixel memory regions, such as their P2 regions, at the same time. For example, as shown in FIG. 4A, active control voltages 422 and 424 may be applied to G1 412 and G2 414, while active control voltage 426 may not be applied to G3 410. In other words, P1 406 and P2 408 may be turned on, while P3 410 may remain off. For example, as shown in FIG. 4A, a positive voltage may be applied to G1 412 and G2 414, while G3 416 may still be biased at zero voltage (or a negative voltage, if desired). As described above, in some embodiments, a positive voltage can repel holes in the interface layers of P1 406 and P2 408 from P1 406 and P2 408, thus causing at least a portion of the charge to be transferred from PD 402 to P1 406 and P2 408. Also, as described above, P1 406 and P2 408 may be at the same potential during turn-off. Therefore, in some embodiments, voltages of different values ​​may be applied to G1 412 and G2 414, thus causing a step-like potential profile between P1 406 and P2 408, as shown in FIG. 4C corresponding to period 434. As a result, charge can be transferred from PD 402 to P2 408 via P1 406, as shown in FIG. 4C. As described above, in some embodiments, P1 406 and P2 408 may have different doping concentrations and therefore may have different potentials during turn-off. Therefore, in that case, the same value of voltage can be applied to G1 412 and G2 414 to still maintain the stepped potential profile between P1 406 and P2 408 shown in FIG. 4C for charge transferred from PD 402 to P2 408 via P1 406.

[0039] As explained, once charge is transferred to P2 408, P2 408 can function as an in-pixel charge memory area for temporarily storing charge therein until pixel readout. Again, as described above, the pixels of the image sensor may be read out individually at different times. For example, in a row-by-row readout mode, pixels in the same row may be read out simultaneously, while pixels in the same column but different rows may be read out sequentially, one at a time. As shown in FIG. 4A , at time 446, a pixel may be selected for readout. During the third period 436, active control voltages 424 and 426 may be applied to G2 414 and G3 416, but active control voltage 422 may not be applied to G1 412. In other words, P2 408 and P3 410 may be turned on, but P1 406 may be turned off. 4A, positive voltages may be applied to G2 414 and G3 416, while G1 412 may be biased at zero voltage (or a negative voltage, if desired). Similar to what was described above, different voltage values ​​may be applied to G2 414 and G3 416, thus creating a stepped potential profile between P2 408 and P3 410 to transfer charge from P2 408 to FD 404 via P3 410, as shown in FIG. 4D corresponding to period 436. Alternatively, P2 408 and P3 410 may have different doping concentrations, and the same voltage value may be applied to G2 414 and G3 416 to still maintain a stepped potential profile between P2 408 and P3 410 and transfer charge from P2 408 to FD 404 via P3 410. 4A, in some embodiments, the active control voltage 424 may be continuously applied to G2 414 during periods 434 and 436. Alternatively, in some embodiments, the active control voltage 424 may be removed at the end of period 436 when charge has been transferred from PD 402 to P2 408, as indicated by the dashed line in FIG. 4A, and then reapplied at or near the beginning of period 436 to transfer charge from P2 408 to FD 404. Combining FIGS. 4A-4D, using appropriate control signals, the image sensor may be controlled to operate in a global shutter mode.All pixels of the image sensor may be exposed simultaneously during the same time interval and transfer accumulated charge from their PD regions to intra-pixel memory regions, e.g., their P2 regions. The pixels may then be read out individually, e.g., during their respective rolling readout intervals, during which charge may be transferred from the P2 regions of individual pixels to their FD regions.

[0040] FIG. 5A shows a cross-sectional view of an exemplary pixel and a block diagram of an image sensor including readout circuitry and image signal processing circuitry, according to some embodiments. As shown in FIG. 5A, pixel 500 can be one of multiple pixels of image sensor 550. Also, as described above, in some embodiments, multiple pixels may be organized as a pixel array having one or more rows and one or more columns of pixels. Similar to the pixels described above, pixel 500 can include at least one PD, an FD, and a vertical charge transfer region between the PD and the FD, the vertical charge transfer region including P1, P2, and P3. Additionally, for illustrative purposes, FIG. 5A shows at least some of the transistors that can be used to form a pixel readout circuit for reading out the image signal of pixel 500. For example, in some embodiments, the pixel readout circuit can include a reset transistor (“RG”) 542, a source follower transistor (“SF”) 544, and a readout select transistor (“RS”) 546. As shown in FIG. 5A, the FD can be coupled to a reset voltage VDD via RG 542. In some embodiments, RG 542 may be selectively turned on to reset the voltage of the FD to VDD. Furthermore, as shown in FIG. 5A , the FD may also be connected to SF 544 and one or more RS 546. In some embodiments, SF 544 and RS 546 may be turned on to couple the FD to a pixel output line, through which the voltage of the FD can be accessed and read out. In some embodiments, SF 544 may provide a voltage buffer for the voltage of the FD, while RS 546 may be selectively turned on to couple the FD to a pixel output line to read out the voltage of the FD. During readout, SF 544 and RS 546 may be first turned on to couple the FD to the pixel output line. Then, RG 542 may be turned on to reset the voltage of the FD to a reset voltage VDD. The voltage of the FD may be sampled using an amplifier and analog / digital circuit 554, for example, as a first sample of the voltage of the FD. Next, RG 542 may be turned off and the charge transfer region between the PD and FD may be turned on to transfer charge from the PD to the FD, as described above in FIGS. 1-4.As described above, the transfer of charge may generate an analog voltage across the capacitance C of the FD. The voltage of the FD may again be accessed and read out at the pixel output line via SF 544 and RS 546, as described above. The voltage of the FD may be sampled as a second sample of the voltage of the FD, for example, using amplifier and analog / digital circuitry 554. The difference between the first and second samples may be calculated to offset the reset voltage VDD, and the differential voltage may be determined as the final image signal from the pixel 500. The image signal may be further processed, for example, using digital processing circuit(s) 556. The image signal may be sent to an image signal processor (ISP), for example, using data transfer I / O circuitry 558, where it is processed to generate an image. Furthermore, as shown in FIG. 5A , the image sensor 550 may also include row logic and driver circuitry 552 and global logic and clock circuit(s) 560 to generate appropriate control signals for the multiple pixels of the image sensor 550.

[0041] FIG. 5B illustrates exemplary control signals applied to different components of multiple pixels of an image sensor 550, according to some embodiments. FIG. 5B illustrates similar information as described above with respect to FIGS. 4A-4D, but for multiple pixels instead of one individual pixel. For example, as shown in FIG. 5B, the illustrated control signals include control signals applied to pixels in different rows, e.g., row 0, row 1, row 2, ..., row n. In this example, the image sensor 550 may operate in a global shutter mode. For example, all pixels may be exposed to light during a first period, e.g., an exposure period (similar to period 432 in FIGS. 4A-4D). Additionally, all pixels may simultaneously transfer charge in their PD regions to their in-pixel memory regions, e.g., their P2 regions, during a second period, e.g., a global shutter period (similar to period 434). Furthermore, the pixels of the image sensor may be individually read out at respective times during a third period, e.g., a rolling readout period (similar to period 436). 4A-4B, as shown in FIG. 5B, during a first period, active control voltages may not be applied to the control gates of the pixels of image sensor 550, so that all gates are turned off, and the pixels may accumulate charge in their respective PD regions. Additionally, as shown in FIG. 5B, as described above in FIG. 4A and 4C, during a second period, active control voltages may be applied to the control gates G1 and G2 of the pixels of image sensor 550, so that all pixels may simultaneously transfer charge from their respective PD regions to the P2 regions via the P1 regions. Furthermore, as shown in FIG. 5B, as described above in FIG. 4A and 4D, during a third period, active control voltages may be applied to the control gates G2 and G3 of the pixels of image sensor 550 at each readout time, so that each pixel may transfer charge from their respective P2 regions to the FD regions via the P2 regions. Also, as described above in FIG. 5A, different control signals can be applied to the transistors (eg, the RST and RS transistors) of each pixel to select and read out each pixel, as shown in FIG. 5B.Also, as shown in FIG. 5B, these transistor control signals can be applied at different times to pixels in different rows to represent a rolling readout operation. For example, the control signals to RSG[0] and RS[0] for the pixels in row 0 can be applied before the control signals to RSG[1] and RS[1] for the pixels in row 1, meaning that the pixels in row 0 can be read out before the pixels in row 1. As described above, charge can be transferred from the PD region to the P2 region simultaneously globally for all pixels during the second period. However, pixels in different rows can be read out at different times. Thus, the P2 region can function as an in-pixel charge memory region for temporarily storing charge for each individual pixel.

[0042] FIG. 6 illustrates a top view and a cross-sectional view of another exemplary pixel of an image sensor, according to some embodiments. As shown in FIG. 6 , in some embodiments, the gate areas G1 612, G2 614, and G3 616 of pixel 600 may be arranged in a hexogen-shaped configuration. Additionally, G1 612, G2 614, and G3 616 may be electrically connected to gate contacts, e.g., G1 622, GC2 624, and GFC3 626, respectively. Also, unlike the pixels described above, in FIG. 6 , G1 622, GC2 624, and GFC3 626 do not necessarily overlap each other. Instead, they may be arranged around a hexogen-shaped configuration, and the gate area of ​​each charge modulation region may include a first portion of the gate area connected to a first portion of the gate contact and a second portion of the gate area connected to a second portion of the gate contact, with each pair located on one of two opposing sides of the corresponding charge modulation region. For example, as shown in the cross-sectional view along AA′, G1 612 of P1 606 may include a first G1 portion on the left side of P1 606 and a second G1 portion on the right side. The G1 portion on the left side may be electrically connected to the first GC portion 622, while the G1 portion on the right side may be electrically connected to the second GC portion 622, and the first and second GC portions may be electrically connected to each other. Additionally, as shown in FIG. 6 , in some embodiments, G1 612, G2 614, and G3 616 may be embedded within the substrate 630 at different depths. For example, G1 612 may be embedded at the deepest depth closer to PD 602, G3 616 may be embedded at the shallowest depth closer to the surface of the substrate 630, while G2 614 may be embedded in the center.

[0043] FIG. 7 illustrates an exemplary isolation structure for a pixel of an image sensor, according to some embodiments. The diagram on the left illustrates a partial deep trench isolation (DTI) for the pixel, according to some embodiments. As shown in the figure, in some embodiments, the DTI may include region 732 formed using polysilicon or metal material. In some embodiments, region 732 may be formed in a trench (filled with polysilicon or metal material) separated from a substrate 730 by a dielectric material 750, which may enclose the PD region of the pixel. In some embodiments, region 732 may be biased to create passivation for the trench surface to isolate the pixel from other neighboring pixels. Alternatively, in some embodiments, the trench may be filled with a high-k dielectric material. In this case, region 732 does not necessarily need to be biased. The diagram on the right illustrates an alternative isolation structure for the pixel: deep doped well isolation. As shown in this figure, the trench in region 752 may extend all the way to the surface of the pixel. The trench may be implanted with dopants to form electrical isolation between the pixels.

[0044] FIG. 8 illustrates an exemplary split pixel for autofocus applications, according to some embodiments. As shown in FIG. 8, pixel 800 may include at least two PDs: left PD 802 and right PD 862. In some embodiments, PD 802 and PD 862 may be isolated from each other using one or more isolation structures. For example, as shown in FIG. 8, in some embodiments, the two PDs may be separated by a partial deep trench insulation (DTI) region 832, as described above, located between PD 802 and PD 862. In some embodiments, each PD may be associated with an FD and vertical charge transfer regions, including P1, P2, and P3. 1 to 7, the left PD 802 may be associated with left P1 (L-P1), left P2 (L-P2), left P3 (L-P3), and left FD (L-FD), while the right PD 862 may be associated with right P1 (R-P1), right P2 (R-P2), right P3 (R-P3), and right FD (R-FD). Also, the L-FD and R-FD may be electrically connected, and image signals from the L-FD and R-FD may be read out to pixel output lines using the same pixel readout circuit. In operation, gate areas LG1 (for L-P1) and RG1 (for R-P1) may receive control signals simultaneously or nearly simultaneously, and LG2 (for L-P2) and RG2 (for R-P2) may receive control signals simultaneously or nearly simultaneously, so that charge can be transferred from PD 802 to L-FD simultaneously with charge transfer from PD 862 to R-FD. However, gate areas LG3 (for L-P3) and RG3 (for R-P3) may receive control signals at different times, so that charge can be transferred from L-P2 to L-FD and from R-P3 to R-FD at different times. That is, the image signals of L-PD 802 and R-PD 862 of pixel 800 may be read out sequentially. In some embodiments, pixel 800 may be used for autofocus of an image capture device. For example, when light is incident on pixel 800 at a certain angle, the amount of light captured by L-PD 802 and R-PD 862 may be different. As a result, the amount of charge stored in the two PDs may differ, resulting in different output voltages during readout.In some embodiments, the difference between the output voltage from the L-PD 802 and the output voltage from the R-PD 862 may be used to adjust and / or perform autofocus of the image capture device.

[0045] 9 shows a top view and a cross-sectional view of another exemplary pixel of an image sensor, according to some embodiments. As shown in FIG. 9, in some embodiments, the vertical gate and DTI isolation of the pixel may be formed within the same trench. For example, in some embodiments, gate areas G1 912, G2 914, and G3 916 of pixel 900 may be formed within the same trench 930 inside the substrate of pixel 900, as shown particularly in the cross-section of FIG. 9. G1 912, G2 914, and G3 916 may each receive a control signal (e.g., a control voltage) through an associated gate contact, e.g., GC1 922, GC2 924, and GC3 926, respectively. 1-8, pixel 900 may include a PD 902, an FD 904, and a vertical charge transfer region between PD 902 and FD 904, which may include multiple charge modulation regions P1 906, P2 908, and P3 910. In some embodiments, pixel 900 may be operated in a global shutter mode similar to the pixels described above, where P2 908 may function as an in-pixel charge memory region for pixel 900.

[0046] FIG. 10 shows a top view and a cross-sectional view of another exemplary pixel of an image sensor, according to some embodiments. As shown in FIG. 10, the structure of pixel 1000 may be similar to that of pixel 900. However, the P1, P2, P3, and FD regions of pixel 1000 may have smaller cross-sectional areas such that these regions only partially, rather than completely, overlap the PD below the PD region. In some embodiments, different doping concentrations in P1, P2, and P3 may be introduced by implantation or other methods to create sufficient capacitance and facilitate vertical charge transfer. As shown in FIG. 10, in some embodiments, there may be a set of gate areas for an adjacent pixel (not shown) to the right of pixel 1000, which are located within a trench adjacent to pixel 1000. Thus, in some embodiments, there may be an isolation region 1032 between the gate areas (G1, G2, and G3) of pixel 1000 and the gate areas of other pixels. In some embodiments, isolation region 1032 may be implanted with dopants to provide isolation.

[0047] FIG. 11 shows a top view and a cross-sectional view of another exemplary pixel of an image sensor, according to some embodiments. In this example, FD 1104, P1 1106, P2 1108, and P3 1110 may be moved to the corners of the pixel (e.g., for PD 1102), such as the right corner of the pixel, as shown in the cross-sectional view of FIG. 11. In some embodiments, one performance parameter of a global shutter image sensor is parasitic light sensitivity (PLS), which quantifies the sensor's sensitivity to light when the shutter is assumed to be closed. Thus, the image signal generated in this case can be considered background noise. Therefore, in some embodiments, it may be desirable to minimize or at least reduce the value of PLS. By moving P1 1106, P2 1108, and P3 1110 to the corners of the pixel, DTI region 1132 may be used as a shield for incident light to reduce the amount of light entering P2 1108 and thus improve PLS performance. Additionally, in some embodiments, the pixel may include doping region 1152 to provide a potential barrier to prevent charge from PD 1102 from being transferred to P1, P2, P3, and FD in the left corner of the pixel (because these regions are for the left pixel). Instead, charge in PD 1102 may be guided to be correctly transferred to FD 1104 via P1 1106, P2 1108, and P3 1110, because these regions correspond to PD 1102, as shown by the left arrow in FIG. 11. Similarly, for the right pixel (e.g., PD 1162), the pixel may also include doping region 1172 to prevent charge from PD 1162 from being erroneously transferred from PD 1162 to P1 1106, P2 1108, P3 1110, and FD 1104. Instead, the charge of PD 1162 can be transferred to FD via P1, P2, and P3 at the right corner of the right pixel, as indicated by the right arrow in Figure 11. In some embodiments, the doping type of doping regions 1152 and 1172 can be opposite to the doping type of PD 1102 and PD 1162.

[0048] FIG. 12 is a block diagram of an exemplary image capture device, according to some embodiments. As shown in FIG. 12 , in some embodiments, the image capture device 1200 may include one or more lenses 1202 and an image sensor 1204. In some embodiments, the image capture device 1200 can capture light from the environment, which can pass through the lens 1202 to reach the image sensor 1204. In some embodiments, the image sensor 1204 may include multiple pixels similar to those described above, each of which may include an in-pixel charge memory area for global shutter operation. Also, in some embodiments, the image capture device 1200 may include an infrared cutoff filter (IRCF) 1206 disposed between the lens 1202 and the image sensor 1204 to block infrared light from reaching the image sensor 1204. As shown in FIG. 12 , in this example, the image sensor 1204 and the IRCF 1206 may be mounted on a substrate 1208, and the image sensor 1204 may be positioned upside down to receive backside illumination. However, as noted above, in some embodiments, front illumination may alternatively be implemented on the image sensor 1204 having the pixels described above. In some embodiments, the image sensor 204 may be a CMOS image sensor.

[0049] FIG. 13 is a flowchart illustrating an exemplary method for using an in-pixel charge memory region to operate an image sensor in global shutter mode, according to some embodiments. As shown in FIG. 13 , in some embodiments, an image sensor including a plurality of pixels may be provided, as indicated by block 1302. In some embodiments, each pixel of the image sensor may include (a) a photodiode with a charge storage region (PD), (b) a floating diffusion region (FD), and (c) a gate transfer region vertically disposed between the PD and the FD. Also, in some embodiments, the vertical gate transfer region may further include (i) a plurality of charge modulation regions (P1, P2, P3) vertically disposed between the PD and the FD, and (ii) a control gate for each charge modulation region. As shown in FIG. 13 , in some embodiments, for a particular one of the pixels, the pixel may accumulate charge in its PD when exposed to light during a first period, as indicated by block 1304. As described above, in some embodiments, the image sensor may operate in global shutter mode, and therefore, all pixels, including the particular pixel, may begin and end exposure simultaneously during the first period. As shown in FIG. 13 , in some embodiments, for a particular pixel, at least a portion of the charge in PD may be transferred from PD to P2 via P1 during the second period, as indicated by block 1306. As described above, in some embodiments, the transfer of charge from PD to P2 may be a global operation for all pixels of the image sensor. In other words, all pixels, including the particular pixel, may simultaneously transfer their charge from PD to P2 during the second period. In addition, as described above, in some embodiments, P2 may function as an intra-pixel charge memory area for the particular pixel. Thus, once charge is transferred to P2, it may be temporarily stored there until readout of the particular pixel. As shown in FIG. 13 , in some embodiments, the charge transferred to P2 may be further transferred from P2 to FD via P1 during the third period, as indicated by block 1308. As described above, even in the global shutter mode, each pixel of the image sensor is not necessarily read out simultaneously.Alternatively, the pixels may be read out line by line sequentially, so the third period for transferring charge from P2 to FD for a particular pixel may or may not be the same as the readout period for another pixel.

[0050] 14 is a schematic diagram of an example device 1400 that may include an image capture device (e.g., a camera) having an image sensor including pixels with the in-pixel charge memory regions described above, according to some embodiments. In some embodiments, device 1400 may be a mobile device and / or a multifunction device. In various embodiments, device 1400 may be any of a variety of types of device, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, or router, or generally any type of computing or electronic device.

[0051] In some embodiments, device 1400 may include a display system 1402 (e.g., including a display and / or a touch-sensitive surface) and / or one or more cameras 1404. In some non-limiting embodiments, display system 1402 and / or one or more front-facing cameras 1404a may be provided on the front side of device 1400, for example, as shown in FIG. 14 . Additionally or alternatively, one or more rear-facing cameras 1404b may be provided on the rear side of device 1400. In some embodiments comprising multiple cameras 1404, some or all of the cameras may be the same or similar to one another. Additionally or alternatively, some or all of the cameras may be different from one another. In various embodiments, the location(s) and / or configuration(s) of camera(s) 1404 may differ from that shown in FIG. 14 .

[0052] Among other things, device 1400 may include memory 1406 (e.g., comprising an operating system 1408 and / or application(s) / program instructions 1410), one or more processors and / or controllers 1412 (e.g., comprising CPU(s), memory controller(s), display controller(s), and / or camera controller(s), etc.), and / or one or more sensors 1416 (e.g., orientation sensor(s), proximity sensor(s), and / or position sensor(s), etc.). In some embodiments, device 1400 can communicate with one or more other devices and / or services, such as computing device(s) 1418, cloud services 1420, etc., via one or more network(s) 1422. For example, device 1400 may include a network interface (e.g., network interface 810) that enables device 1400 to transmit data to and receive data from network(s) 1422. Additionally or alternatively, device 1400 may be capable of communicating with other devices via wireless communications using any of a variety of communication standards, protocols, and / or technologies.

[0053] 15 shows a schematic block diagram of an exemplary computing device, referred to as computer system 1500, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor including pixels with the in-pixel charge memory regions described above, according to some embodiments. Additionally, computer system 1500 may implement methods for controlling the operation of the camera and / or for performing image processing of images captured using the camera. In some embodiments, device 1400 (described herein with reference to FIG. 14) may additionally or alternatively include some or all of the functional components of computer system 1500 described herein.

[0054] Computer system 1500 can be configured to perform any or all of the above-described embodiments. In different embodiments, computer system 1500 can be any of a variety of types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, or router, or generally any type of computing or electronic device.

[0055] In the illustrated embodiment, computer system 1500 includes one or more processors 1502 coupled to system memory 1504 via an input / output (I / O) interface 1506. Computer system 1500 further includes one or more cameras 1508 coupled to I / O interface 1506. Computer system 1500 further includes a network interface 1510 coupled to I / O interface 1506, and one or more input / output devices 1512, such as a cursor control device 1514, a keyboard 1516, and a display(s) 1518. While in some cases, an embodiment may be implemented using a single instance of computer system 1500, it is contemplated that in other embodiments, multiple such systems, or multiple nodes comprising computer system 1500, may be configured to host different portions or instances of an embodiment. For example, in one embodiment, some elements may be implemented via one or more nodes of computer system 1500 that are different from the nodes implementing other elements.

[0056] In various embodiments, computer system 1500 may be a uniprocessor system including one processor 1502, or a multiprocessor system including multiple processors 1502 (e.g., two, four, eight, or another suitable number). Processor 1502 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 1502 may be a general-purpose or embedded processor implementing any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. Also, in some embodiments, one or more of processors 1502 may include additional types of processors, such as a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. In a multiprocessor system, each of processors 1502 may generally, but not necessarily, implement the same ISA. In some embodiments, computer system 1500 may be implemented as a system-on-a-chip (SoC). For example, in some embodiments, the processor 1502, memory 1504, I / O interface 1506 (e.g., fabric), etc. may be implemented in a single SoC with multiple components integrated on a single chip. For example, the SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, a cache, one or more memories, etc. integrated on a single chip. In some embodiments, the SoC implementation may implement a reduced instruction set computing (RISC) architecture, or any other suitable architecture.

[0057] The system memory 1504 may be configured to store program instructions 1520 accessible by the processor 1502. In various embodiments, the system memory 1504 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash-type memory, or any other type of memory. Additionally, existing camera control data 1522 in the memory 1504 may include any of the information or data structures for implementing the techniques described above. In some embodiments, the program instructions 1520 and / or data 1522 may be received, sent, or stored on different types of computer-accessible media, or on similar media separate from the system memory 1504 or the computer system 1500. In various embodiments, some or all of the functionality described herein may be performed via such a computer system 1500.

[0058] In one embodiment, I / O interface 1506 may be configured to coordinate I / O traffic between processor 1502, system memory 1504, and any peripheral devices within the device, including other peripheral interfaces such as network interface 1510 or input / output devices 1512. In some embodiments, I / O interface 1506 may perform any necessary protocol, timing, or other data conversions to convert data signals from one component (e.g., system memory 1504) into a format suitable for use by another component (e.g., processor 1502). In some embodiments, I / O interface 1506 may include support for devices attached via various types of peripheral buses, such as, for example, variants of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of I / O interface 1506 may be split between two or more separate components, such as, for example, a northbridge and a southbridge. Additionally, in some embodiments, some or all of the functionality of I / O interface 1506 , such as an interface to system memory 1504 , may be incorporated directly into processor 1502 .

[0059] Network interface 1510 may be configured to allow data to be exchanged between computer system 1500 and other devices (e.g., carrier or agent devices) attached to network 1524, or between nodes of computer system 1500. Network 1524, in various embodiments, may include one or more networks, including, but not limited to, a local area network (LAN) (e.g., an Ethernet or enterprise network), a wide area network (WAN) (e.g., the Internet), a wireless data network, some other electronic data network, or some combination thereof. In various embodiments, network interface 1510 may support communication over a wired or wireless general-purpose data network, such as, for example, any suitable type of Ethernet network. It may also support communication over a telecommunications / telephone network, such as an analog voice network or a digital fiber communications network, a storage area network, such as a Fibre Channel SAN, or any other suitable type of network and / or protocol.

[0060] The input / output devices 1512, in some embodiments, may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for inputting or accessing data by one or more computer systems 1500. Multiple input / output devices 1512 may be present within computer system 1500 or may be distributed on various nodes of computer system 1500. In some embodiments, similar input / output devices may be separate from computer system 1500 and may interact with one or more nodes of computer system 1500 through wired or wireless connections, such as via network interface 1510.

[0061] Those skilled in the art will appreciate that computer system 1500 is merely exemplary and is not intended to limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the depicted functions, including computers, network devices, Internet appliances, PDAs, wireless telephones, pagers, etc. Computer system 1500 may also be connected to other devices not shown, or alternatively, may operate as a stand-alone system. Additionally, functionality provided by the illustrated components may, in some embodiments, be combined in fewer components or distributed among additional components. Similarly, in some embodiments, the functionality of some of the illustrated components may not be provided, and / or other additional functionality may be available.

[0062] Those skilled in the art will also understand that while various items are shown as being stored in memory or on storage during use, these items, or portions thereof, may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments, some or all of the software components may execute in memory on another device and communicate with the illustrated computer system via computer-to-computer communications. Some or all of the system components or data structures may also be stored (e.g., as instructions or structured data) on a computer-accessible medium or portable item to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system 1500 may be transmitted to computer system 1500 via a transmission medium or signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communications medium, such as a network and / or a wireless link. Various embodiments may further include receiving, sending, or storing instructions and / or data to be executed on a computer-accessible medium in accordance with the preceding description. Generally speaking, a computer-accessible medium may include a non-transitory computer-readable storage medium or memory medium, such as a magnetic medium or an optical medium, e.g., a disk or DVD / CD-ROM, a RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), a volatile or non-volatile medium, such as a ROM, etc. In some embodiments, a computer-accessible medium may include a transmission medium or a signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communication medium, such as a network and / or a wireless link.

[0063] The methods described herein may, in different embodiments, be implemented in the form of software, hardware, or a combination thereof. In addition, the order of method blocks may be changed, and various elements may be added, reordered, combined, omitted, modified, etc. Various modifications and variations may be made as would be apparent to one of ordinary skill in the art having the benefit of this disclosure. The various embodiments described herein are illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Thus, components described herein as singular may be provided in plural. Boundaries between various components, operations, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific exemplary configurations. Other allocations of functionality are contemplated and may be included within the scope of the following claims. Finally, structures and functions presented as separate components in exemplary configurations may be implemented as combined structures or components. These and other variations, modifications, additions, and improvements may be included within the scope of the embodiments, as defined by the following claims.

Claims

1. 1. An image sensor, comprising: a plurality of pixels, each of the pixels comprising: at least one photodiode including a charge storage region; at least one floating diffusion region; at least one charge transfer region formed vertically between the charge storage region and the floating diffusion region, the charge transfer region comprises at least one charge transfer region including a first charge modulation region, a second charge modulation region, and a third charge modulation region; The pixel is accumulating charge in the charge accumulation region based on exposure to light; transferring at least a portion of the charge from the charge storage region to the second charge modulation region through the first charge modulation region; and controlling the transfer of at least a portion of the charge from the second charge modulation region to the floating diffusion region via the third charge modulation region.

2. the first charge modulation region is formed above and at least partially overlaps the charge storage region of the photodiode; the second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; the third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; the floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region; The image sensor of claim 1 .

3. the first charge modulation region and the second charge modulation region are turned on to transfer the at least some of the charge from the charge storage region to the second charge modulation region through the first charge modulation region; the second charge modulation region and the third charge modulation region are turned on to transfer at least a portion of the charge from the second charge modulation region to the floating diffusion region through the third charge modulation region; The image sensor of claim 1 .

4. the first charge modulation region, the second charge modulation region, and the third charge modulation region are turned on in response to respective positive voltages applied to gate control areas of the first charge modulation region, the second charge modulation region, and the third charge modulation region; the first charge modulation region, the second charge modulation region, and the third charge modulation region are turned off in response to removal of the respective positive voltages from the gate-controlled areas of the first charge modulation region, the second charge modulation region, and the third charge modulation region, respectively; The image sensor of claim 3 .

5. the first charge modulation region, the second charge modulation region, and the third charge modulation region have the same concentration of dopant, whereby applying respective positive voltages of different values ​​to the respective gate controlled areas of the first charge modulation region and the second charge modulation region to create a stepped potential profile between the first charge modulation region and the second charge modulation region to transfer the at least some of the charges from the charge storage region to the second charge modulation region through the first charge modulation region; applying respective positive voltages of different values ​​to the respective gate controlled areas of the second charge modulation region and the third charge modulation region to create a stepped potential profile between the second charge modulation region and the third charge modulation region to transfer the at least some of the charges from the second charge modulation region to the floating diffusion region through the third charge modulation region; The image sensor of claim 4 .

6. the first charge modulation region, the second charge modulation region, and the third charge modulation region have different concentrations of dopants to create a stepped potential profile between the first charge modulation region, the second charge modulation region, and the third charge modulation region, thereby applying respective positive voltages of the same value to the respective gate controlled areas of the first charge modulation region and the second charge modulation region to maintain the stepped potential profile between the first charge modulation region and the second charge modulation region to transfer the at least some of the charges from the charge storage region to the second charge modulation region through the first charge modulation region; applying respective positive voltages of the same value to the respective gate controlled areas of the second charge modulation region and the third charge modulation region to maintain the stepped potential profile between the second charge modulation region and the third charge modulation region to transfer the at least some of the charges from the second charge modulation region to the floating diffusion region through the third charge modulation region; The image sensor of claim 4 .

7. 5. The image sensor of claim 4, wherein the gate control areas of the first charge modulation region, the second charge modulation region, and the third charge modulation region are formed in a shape that at least partially surrounds a lateral periphery of the floating diffusion region.

8. the plurality of pixels are organized as a pixel array to divide the pixels into a plurality of rows and a plurality of columns; The plurality of pixels are controlled to operate in a global shutter mode, whereby: the plurality of rows and the plurality of columns of pixels simultaneously accumulate charge in their respective charge accumulation regions based on exposure to light; the plurality of rows and plurality of columns of pixels simultaneously transfer at least a portion of the charge from their respective charge storage regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer said at least some charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; pixels in different rows sequentially transfer said at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in said row order; The image sensor of claim 1 .

9. 2. The image sensor of claim 1, wherein the charge storage region is an n-type region, the first charge modulation region, the second charge modulation region, and the third charge modulation region are p-type regions, and the floating diffusion region is an n-type region.

10. 10. The image sensor of claim 1, wherein the pixel further comprises pixel readout circuitry including at least one of a reset switch for resetting a voltage on the floating diffusion region to a reset voltage, a source follower switch for buffering the voltage on the floating diffusion region, or a pixel select switch for selectively coupling the floating diffusion region to a pixel output line for reading out the voltage on the floating diffusion region.

11. 1. A system comprising: one or more lenses; 1. An image sensor, comprising: a plurality of pixels configured to receive light through the lens, each of the pixels comprising: at least one photodiode including a charge storage region; at least one floating diffusion region; at least one charge transfer region formed vertically between the charge storage region and the floating diffusion region, the charge transfer region comprises at least one charge transfer region including a first charge modulation region, a second charge modulation region, and a third charge modulation region; The pixel is accumulating charge in the charge accumulation region based on exposure to light; transferring at least a portion of the charge from the charge storage region to the second charge modulation region through the first charge modulation region; a plurality of pixels controlled to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region to generate an image signal in the floating diffusion region; a circuit for reading out image signals from the plurality of pixels; an image sensor comprising: A system comprising:

12. the first charge modulation region is formed above and at least partially overlaps the charge storage region of the photodiode; the second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; the third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; the floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region; The system of claim 11.

13. the first charge modulation region and the second charge modulation region are turned on to transfer the at least some of the charge from the charge storage region to the second charge modulation region through the first charge modulation region; the second charge modulation region and the third charge modulation region are turned on to transfer at least a portion of the charge from the second charge modulation region to the floating diffusion region through the third charge modulation region; The system of claim 11.

14. the first charge modulation region, the second charge modulation region, and the third charge modulation region are turned on in response to respective positive voltages applied to gate control areas of the first charge modulation region, the second charge modulation region, and the third charge modulation region; the first charge modulation region, the second charge modulation region, and the third charge modulation region are turned off in response to removal of the respective positive voltages from the gate-controlled areas of the first charge modulation region, the second charge modulation region, and the third charge modulation region, respectively; The system of claim 13.

15. the first charge modulation region, the second charge modulation region, and the third charge modulation region have the same concentration of dopant, whereby applying respective positive voltages of different values ​​to the respective gate controlled areas of the first charge modulation region and the second charge modulation region to create a stepped potential profile between the first charge modulation region and the second charge modulation region to transfer the at least some of the charges from the charge storage region to the second charge modulation region through the first charge modulation region; applying respective positive voltages of different values ​​to the respective gate controlled areas of the second charge modulation region and the third charge modulation region to create a stepped potential profile between the second charge modulation region and the third charge modulation region to transfer the at least some of the charges from the second charge modulation region to the floating diffusion region through the third charge modulation region; The system of claim 14.

16. the first charge modulation region, the second charge modulation region, and the third charge modulation region have different concentrations of dopants to create a stepped potential profile between the first charge modulation region, the second charge modulation region, and the third charge modulation region, thereby applying respective positive voltages of the same value to the respective gate controlled areas of the first charge modulation region and the second charge modulation region to maintain the stepped potential profile between the first charge modulation region and the second charge modulation region to transfer the at least some of the charges from the charge storage region to the second charge modulation region through the first charge modulation region; applying respective positive voltages of the same value to the respective gate controlled areas of the second charge modulation region and the third charge modulation region to maintain the stepped potential profile between the second charge modulation region and the third charge modulation region to transfer the at least some of the charges from the second charge modulation region to the floating diffusion region through the third charge modulation region; The system of claim 14.

17. the plurality of pixels are organized as a pixel array to divide the pixels into a plurality of rows and a plurality of columns; The plurality of pixels are controlled to operate in a global shutter mode, whereby: the plurality of rows and the plurality of columns of pixels simultaneously accumulate charge in their respective charge accumulation regions based on exposure to light; the plurality of rows and plurality of columns of pixels simultaneously transfer at least a portion of the charge from their respective charge storage regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer said at least some charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; pixels in different rows sequentially transfer said at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in said row order; The system of claim 11.

18. A device, 1. An image capture device, comprising: one or more lenses; 1. An image sensor, comprising: a plurality of pixels configured to receive light through the lens, each of the pixels comprising: at least one photodiode including a charge storage region; at least one floating diffusion region; at least one charge transfer region formed vertically between the charge storage region and the floating diffusion region, the charge transfer region comprises at least one charge transfer region including a first charge modulation region, a second charge modulation region, and a third charge modulation region; The pixel is accumulating charge in the charge accumulation region based on exposure to light; transferring at least a portion of the charge from the charge storage region to the second charge modulation region through the first charge modulation region; a plurality of pixels controlled to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region to generate an image signal in the floating diffusion region; an image capture device comprising an image sensor comprising a circuit for reading out image signals from the plurality of pixels; an image signal processor configured to process the image signals to generate one or more images.

19. the first charge modulation region is formed above and at least partially overlaps the charge storage region of the photodiode; the second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; the third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; the floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region; 20. The device of claim 18.

20. the plurality of pixels are organized as a pixel array to divide the pixels into a plurality of rows and a plurality of columns; The plurality of pixels are controlled to operate in a global shutter mode, whereby: the plurality of rows and the plurality of columns of pixels simultaneously accumulate charge in their respective charge accumulation regions based on exposure to light; the plurality of rows and plurality of columns of pixels simultaneously transfer at least a portion of the charge from their respective charge storage regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer said at least some charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; pixels in different rows sequentially transfer said at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in said row order; 20. The device of claim 18.

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