System and method for calculating correlation in a navigation receiver

Abstract

A correlator module (320) is configured to perform a correlation between a first batch of received signal samples and a second batch of code samples of a local replica of a spreading code. The correlator module includes a carrier phase generator circuit (324), a code generator circuit (326), a correlation calculation circuit (328), and an accumulator circuit (323). A signal correlator system includes a system bus, a central processing module connected to the system bus, and the correlator module. The first batch is provided as a word (310) to the correlator module via the system bus. The correlator module is configured to trigger a correlation operation of the correlation calculation circuit each time one of the words is provided by the system bus. A method for performing the above operations is described.

Description

[Technical Field]

[0001] The present disclosure relates to digital circuits, computer systems, and related methods for calculating the correlation of baseband samples from a satellite navigation receiver with a local replica of a particular satellite's code sequence. [Background technology]

[0002] Global Navigation Satellite Systems (GNSS) are widely used to provide position, velocity, and time to any user on or near the Earth's surface. GNSS includes, among other things, a constellation of multiple navigation satellites (GNSS satellites) that transmit dedicated navigation signals, also known as "ranging signals." The best-known is the Global Positioning System (GPS), developed by the United States. Other systems include the European Galileo system, the Russian GLONASS, and the Chinese BeiDou system.

[0003] Satellites in satellite-based positioning systems transmit signals in several frequency bands. The carriers are modulated by pseudorandom (PRN) spreading codes unique to each satellite. For example, the latest generation of GPS satellites transmit on L1, L2, and L5 carriers at 1575.42 MHz, 1227.6 MHz, and 1176.45 MHz, respectively. Each carrier may be modulated by several PRN codes. For example, for GPS satellites, the L1 carrier is modulated by the L1C / A code, the L1P(Y) code, and the L1C code. The PRN codes consist of a long sequence of "0" or "1" chips, which are multiplied by 1 and -1 on the carrier, respectively, using a modulation scheme known as binary phase-shift keying (BPSK). For example, the GPS L1C / A code is a sequence of 1023 chips unique to each satellite. Some signals, such as GPS-L2CM, are time-multiplexed with other signals. The PRN codes of these signals are blanked during the intervals in which other signals are transmitted. This blanking can be interpreted as multiplying the carrier by zero.

[0004] The PRN codes of most civilian signals are periodic. For added security, military and some next-generation signals use aperiodic sequences generated by cryptographic encryption algorithms. Other next-generation signals override selected chips of the default periodic sequence with an encrypted signature sequence that is known to the user only after some time (a few seconds to a few minutes) and requires signal memorization and post-processing to verify the signal's authenticity. For example, GPS L1C signals use a 10230-chip repeating PRN code, selected chips of which may be modified according to a cryptographically generated aperiodic sequence. This so-called watermark code is used to verify the signal's authenticity (GPS Chimera). The applicable key to the cryptographic algorithm for reconstructing the watermark is only made available long after the signal is transmitted.

[0005] In a GNSS receiver, different frequency bands are first amplified, filtered, and downconverted to an intermediate frequency (IF) in front-end circuits. In a multi-band receiver, each band is downconverted in a dedicated front-end. The front-end may also include means to mitigate RF signal damage such as interference. In a digital receiver, each front-end outputs a stream of digital samples at a rate that depends on the Nyquist frequency of the front-end filter. Depending on the receiver's frequency plan, the IF sample rate Fs may vary from a few MHz to tens of MHz.

[0006] The IF samples contain signals from all satellites transmitting in the corresponding frequency band, and the GNSS receiver identifies an individual satellite by correlating the IF samples with a local replica of that satellite's PRN code sequence, after removing any residual carrier.

[0007] In a hardware-defined GNSS receiver (HDR), the correlation operation is performed in a dedicated hardware channel. HDR includes multiple hardware channels, each of which calculates the correlation for a single GNSS signal. Since all operations are hard-coded in hardware, the main advantage of the HDR architecture is processing speed at the expense of hardware complexity and flexibility.

[0008] In so-called software-defined GNSS receivers (SDRs), correlation operations are performed in software running on one or more central processing unit (CPU) cores. The SDR approach is very flexible because the correlation algorithms are coded in software, but places a heavy burden on the CPU, especially when the number of signals being tracked is large. For each tracked signal, the operations performed in software generally include: - Reading IF samples from RAM - Updating the carrier phase and the local code phase - Rotating the IF sample - Correlating the IF samples with the local PRN code - Accumulating correlations

[0009] Therefore, SDR receivers are primarily used in post-processing mode, where batches of IF samples are first stored in RAM and then correlations are calculated without strict real-time constraints.

[0010] T. Humphreys et al., "Exploiting Multicore Technology in Software-Defined GNSS Receivers," ION GNSS 2009 conference, demonstrated the benefits of leveraging the multicore architecture of some processors to optimize for real-time operation.

[0011] Petovello et al., "Architecture and Benefits of an Advanced GNSS Software Receiver," Journal of Global Positioning Systems (2008) Vol. 7, No. 2, pp. 156-168, uses the massively parallel processing power of graphics processing units (GPUs) to optimize the throughput of the SDR.

[0012] D. Miralles and D. M. Akos, "A SIMD intrinsic correlator library for GNSS software receivers," GPS Solutions (2019) 23:72 propose to exploit the single instruction multiple data (SIMD) of modern processors to perform operations on multiple IF samples in a single instruction.

[0013] These techniques rely on advanced CPU / GPU hardware, which is power-hungry, expensive, and unsuitable for most GNSS applications.

[0014] Tran et al., "Programmable custom multi-core architectures for multi-constellation GNSS receivers," IGNSS Symposium 2015, describe two architectures. The first architecture is a software-defined radio designed to process a single satellite signal, built around a proprietary microcontroller core that collects local data and words with vectored IF sample data. The local code and carrier are generated by a dedicated peripheral on the local system bus. This process is strictly timed by processor interrupts at a rate equal to the sampling rate times the number of samples in the vector. The correlation process is performed in software. This is very resource-intensive, requiring a microcontroller with dedicated instruction and data memory for each signal and a large proprietary code generation circuit with associated code memory that holds one or more complete PRN sequences.

[0015] In the second architecture, a custom core is combined with a dedicated programmable correlator that can be dynamically reconfigured by the core controller to process different GNSS signals. The correlator is a pipelined channel that operates at a clock rate that is an integer multiple of the sampling rate. The pipelines are used in a time-interleaved fashion to process multiple signals on the same hardware resource. IF samples are sourced via a dedicated data path (as in a classical correlator) rather than via the CPU system and enter the pipeline in a non-vectored, strictly timed manner. Data is vectorized at the correlator level to take advantage of parallel correlation techniques. The microcontroller accesses multiple pipelines via the system bus to configure the numerically controlled oscillators (NCOs), download the respective spreading codes to internal memory, and collect correlation and timing data in a shared RAM block. The signal to be correlated enters the correlator channel in a tapped-delay fashion until the in-phase and quadrature buffers are filled and the correlation is performed. The time-interleaving and parallel correlation dramatically reduce hardware resource requirements, yet from a system perspective, it closely resembles the matrix architecture of a classical GNSS correlator. Time interleaving and parallel correlation do not offer the level of flexibility of software-defined radio because their design is tailored to specific GNSS sampling rates and code lengths. Time interleaving and parallel correlation are not suitable for handling signals that rely on post-processing, such as aperiodic PRN codes or watermark codes.

[0016] U.S. Patent Application Publication No. 2011 / 0261805 discloses a multi-channel receiver architecture in which high-speed correlation is performed in dedicated hardware channels, with one channel assigned to each signal to be processed. All channels are connected to all digitized IF signals generated by the RF front end. The hardware channels operate on a 60 MHz system clock, which is also used to sample the digitized IF signals generated by the RF front end. A master clock module generates a global 1 ms interrupt pulse that triggers a transaction to collect accumulated data from the hardware channels via the system bus into the positioning engine. Thus, the hardware channels operate at the same rate as the samples are being supplied by the front end, enabling real-time processing.

[0017] U.S. Patent Application Publication No. 2010 / 0074308 discloses a GNSS receiver including a sampling stage that records carrier-stripped pre-correlation samples in a buffer. The sampling stage is clocked by a code-numerically controlled oscillator whose rate is controlled according to the Doppler shift of the satellites intended for acquisition, and the recorded pre-correlation samples are therefore sampled chip-by-chip. The dynamic range of the pre-correlation samples is compressed to conserve memory size. This results in a reduced rate, enabling multiple correlations to be performed quickly in the same hardware correlator using a time-multiplexing scheme. Each correlator therefore operates on data provided by several independent channels. The correlators provide sets of correlation data that are fed to a processor that calculates absolute correlation values ​​and accumulates the results. The correlation process in this GNSS receiver is entirely hardware-controlled, with timing set by the physical chip rate, thereby enabling only real-time operation. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0261805 [Patent Document 2] U.S. Patent Application Publication No. 2010 / 0074308 [Non-patent literature]

[0019] [Non-Patent Document 1] T. Humphreysら、「Exploiting Multicore Technology in Software-Defined GNSS Receivers」、ION GNSS 2009 conference [Non-patent document 2] Petovello et al., "Architecture and Benefits of an Advanced GNSS Software Receiver," Journal of Global Positioning Systems (2008) Vol. 7, No. 2, 156-168 [Non-patent document 3] D. Miralles and D. M. Akos, "A SIMD intrinsic correlator library for GNSS software receivers," GPS Solutions (2019) 23:72 [Non-patent document 4] Tranら、「Programmable custom multi-core architectures for multi-constellation GNSS receiver」、IGNSS Symposium 2015 Summary of the Invention [Problem to be solved by the invention]

[0020] There is a need in the art to combine the flexibility of software-defined radio with the efficiency of dedicated hardware to reduce the complexity, power consumption, and CPU overhead of navigation receivers. There is a need in the art to provide a navigation receiver that is capable of performing correlation calculations more efficiently and / or more flexibly, for example, with optimized CPU involvement and reduced system requirements, in both real-time and post-processing modes. [Means for solving the problem]

[0021] Therefore, according to a first aspect of the present disclosure, there is provided a signal correlator system, a correlator module for use in the signal correlator system, and a navigation receiver including the signal correlator system, as set forth in the accompanying claims.

[0022] A correlator module according to an aspect of the present disclosure is configured to perform a correlation between a first batch of received signal samples and a second batch of code samples of a local replica of a spreading code. The correlator module includes a carrier phase generator circuit, a code generator circuit, a correlation calculation circuit, and an accumulator circuit. The carrier phase generator circuit is configured to determine a carrier phase corresponding to each of the received signal samples of the first batch. The code generator circuit is configured to determine each of the second batch of code samples. The correlation calculation circuit is configured to correlate one received signal sample of the first batch with a respective code sample of the second batch. These correlation operations may include or consist of rotating the received signal sample by a respective carrier phase provided by the carrier phase generator circuit to obtain a rotated sample, and multiplying the respective code sample of the local replica provided by the code generator circuit to obtain a correlation output for each received signal sample. The accumulator circuit is configured to accumulate correlation outputs of the correlation calculation circuit for a plurality of the first batches. The correlator module is configured to be connected to a system (data) bus of the computer system. The computer system is advantageously implemented with executable program code configured to provide the first batch as words to the correlator module via the system bus. The words each consist of a predetermined number of received signal samples, i.e., the number of received signal samples is the same for each word. The correlator module is configured to trigger an operation configured to obtain a correlation output for each received signal sample of the word each time one of the words is provided by the system bus. These operations may include one or more of a correlation operation of a correlation calculation circuit and a state update of a code generator circuit and / or a carrier phase generator circuit. The correlation calculation circuit is advantageously configured to perform the correlation operation on all received signal samples of the word in parallel.It will be appreciated that the received signal samples advantageously represent complex values, such as those comprising or consisting of in-phase and quadrature components.

[0023] A signal correlator system according to an aspect of the present disclosure, which may refer to the computer system described above, includes a system (data) bus and a central processing module (CPU) connected to the system bus. The signal correlator system further includes at least one of the correlator modules described above connected to the system bus. The signal correlator system is configured to provide the first batch as words to the correlator module via the system bus. To this end, the signal correlator system may be implemented with corresponding executable program code executable by the CPU or other suitable device of the signal correlator system, such as a direct memory access device. The words provided to the correlator module may be retrieved from a memory module of the signal correlator system or from any local or remote data storage system, such as, for example, from a remote (data) network via a wired or wireless data communication channel.

[0024] Thus, in the above-described correlator module and signal correlator system, the correlation calculation operation (of the correlation calculation circuit of the correlator module) for a received signal sample of a word is triggered or initiated by providing / writing that same word to the correlator module. One advantage of doing so is that, in contrast to the prior art (e.g., Tran et al., cited above), the operation of the correlator module is fully asynchronous and therefore completely decoupled from the rate of the physical signal. The rate at which the correlator module performs correlations depends entirely on the rate at which words are written to the correlator module by the system bus, which does not need to be a fixed rate such as a clock rate. Rather, if a higher-priority task needs to be performed by the computer system, the provision of new words may be interrupted. This is not necessarily a problem; correlation can simply resume upon the next write access. The result is a highly flexible correlator module and signal correlator system suitable for both real-time and post-processing operations. In real-time processing mode, the correlation calculation operation for a received signal sample is advantageously configured to be performed within a predetermined time delay, for example, from the reception of each received signal sample by the front-end circuitry. In post-processing mode, there are typically no constraints on such time delays, and the time between receiving the received signal samples and performing the correlation calculation operation may be variable.

[0025] Advantageously, the signal correlator system includes a data storage device connected to the system bus. The data storage device is configured to store words of signal samples. The signal correlator system is configured to read the words from the data storage device, such as continuously, and write the words, preferably sequentially, to a data structure of the correlator module through transactions on the system bus. To this end, the signal correlator system may be implemented with corresponding executable program code executable by a CPU or other suitable device of the signal correlator system, such as a direct memory access device, to perform the above-mentioned read and write transactions over the system bus.

[0026] Advantageously, the correlator module is configured to trigger an update of the state of the carrier phase generator circuit and / or the state of the code generator circuit each time one of the words is supplied by the system bus. The state update of the carrier phase generator circuit and / or the code generator circuit can be performed before or, more advantageously, after the execution of a correlation operation of the correlation calculation circuit on one of the words. In this way, the supply of a word to the correlator module triggers a complete repetition of the state of the correlator module, so that the correlator module is ready for the next word.

[0027] Advantageously, the correlator module includes an input data structure configured to receive words from a system bus and coupled to the correlation calculation circuit. The input data structure, such as an input register having a size equal to the bit size of one word, is advantageously configured to store a single word at a time. Advantageously, such a method of operation overcomes the need for a large data storage structure within the correlator module.

[0028] Advantageously, the system bus has a width which is an integer multiple of the bit size of each of the words. Even more advantageously, the system bus has a width which is equal to the bit size of each of the words.

[0029] Advantageously, the correlator module includes a set of memory data structures, such as registers, configured to store values ​​defining the state of the carrier phase generator circuit and / or the code generator circuit. Initial values ​​defining the initial state of the carrier phase generator circuit and / or the code generator circuit are advantageously configured to be written to the memory data structures via the system bus. The initial values ​​advantageously refer to values ​​for the first word of a received signal sample processed by the correlator module. The correlator module is further advantageously configured to update the state of the carrier phase generator circuit and / or the code generator circuit for successive words of a batch of words processed consecutively by the correlator module autonomously, without intervention from a CPU or other device, and particularly without requiring an external write operation.

[0030] Advantageously, the correlator module includes an output data structure, such as a register, configured to be readable by the system bus. The correlator module is configured to write the output data structure with the accumulated correlation output of the accumulator circuit. The accumulated correlation output is further advantageously configured to be retrieved (read) from the output data structure by the system bus. As a result, the correlator module can be connected for data communication to (other devices of) the computer system solely via the system bus, providing complete flexibility of use and allowing for real-time or post-processing (batch) operation, depending on the rate at which samples are provided to the correlator via the system bus.

[0031] Optionally, the correlator module is configured to write the final (or current) states of the carrier phase generator circuit and / or the code generator circuit to an output data structure. Alternatively, the final (current) states of either or both generator circuits can be accessible via the system bus in a memory data structure, which can be, for example, a read / write register. These final states of the carrier phase generator circuit and / or the code generator circuit can advantageously be utilized to calculate the correlation of the next batch (word) of received signal samples. This reduces CPU load, for example, when correlation is performed in batches associated with multiple navigation signals (e.g., multiple satellites), because the CPU does not need to calculate the initial states of the next batch of received signal samples.

[0032] The provision of words to the correlator module via the system bus may be controlled / monitored by a CPU. Alternatively, the signal correlator system may include a direct memory access control module operably coupled to the system bus and, in some cases, a system memory module coupled to the system bus. The direct memory access control module is advantageously configured to be implemented with executable program code configured to execute a sequence of word transfers from a local or remote data storage device, such as the system memory module, to the correlator module. Advantageously, the executable program code is configured to write initial values ​​defining the initial state of the carrier phase generator circuit and / or the code generator circuit to a memory data structure before each sequence of transfers, and / or the executable program code is configured to retrieve accumulated correlation outputs from the output data structure after the sequence of transfers. Delegating read / write tasks to the direct memory access control module reduces CPU overhead, further improving system flexibility and efficiency.

[0033] Advantageously, the system is configured to maintain a circular queue of buffers of received signal samples in a data storage device, such as a system memory module, via, for example, a direct memory access control module. The signal correlator system is implemented with executable program code advantageously configured to execute a sequence of instructions configured to transfer received signal samples as words from one or more buffers of the circular queue to the correlator module and push new ones of the received signal samples into other ones of the buffers in the circular queue, e.g., thereby replacing previously transferred received signal samples. The circular queue is efficient in real-time processing mode, as it reduces the amount of data storage required. The buffers advantageously have equal sizes, which are advantageously equal to or an integer multiple of the bit size of a word.

[0034] A navigation receiver according to an aspect of the present disclosure includes the above-described signal correlator system and further includes an input device, preferably a radio frequency antenna, configured to capture a radio frequency signal, and a front-end circuit coupled to the input device and configured to convert the radio frequency signal into a stream of received signal samples. Advantageously, the navigation receiver includes a formatter circuit configured to pack the stream of received signal samples into a first batch. The formatter circuit may be coupled to a system bus.

[0035] According to a second aspect of the present disclosure, there is provided a method for correlating received signal samples with code samples, as set forth in the accompanying claims. A method for correlating received signal samples, which may be navigation signal samples such as GNSS navigation signal samples, with code samples of a spreading code replica according to this aspect of the disclosure includes packing a first batch of received signal samples into words, each word consisting of the same predetermined number of received signal samples, and providing the words to a signal correlator circuit, such as the correlator module described above, via a system bus. For the received signal samples of each word, a respective carrier phase value and a respective code sample of the spreading code replica are determined. Correlations of the received signal samples of each word with the respective code samples are calculated by the signal correlator circuit to obtain correlation outputs. The step of calculating the correlations may include rotating the received signal samples by their respective carrier phases and multiplying the rotated samples by the respective code samples of the spreading code replica. The correlation outputs calculated for multiple words are accumulated to obtain an accumulated output, which is advantageously retrieved via a transaction on the system bus. Providing each word to the signal correlator circuit triggers calculating by the signal correlator circuit a correlation of the received signal samples of the respective word. Advantageously, the system bus provides the words to the signal correlator circuit one word at a time, e.g., a single word per system bus transaction.

[0036] Advantageously, each time one of the words is provided to the signal correlator circuit, the carrier phase values ​​and the code samples of the spreading code replica are updated, such as before, during or advantageously after calculating the correlation of the received signal samples of the respective word. In the latter case, advantageously, the step of calculating the correlation of the received signal samples of the respective word by the signal correlator circuit triggers the step of updating the carrier phase values ​​and the code samples of the spreading code replica for the subsequent one of the words. As a result, the signal correlator circuit is prepared for the next word to be provided to the signal correlator circuit.

[0037] Advantageously, the above method may be performed recursively on received signal samples for spreading code replicas for different navigation signals, either sequentially on the same signal correlation circuit or in parallel on multiple signal correlation circuits.

[0038] The above methods may be implemented in the above-mentioned correlator module, signal correlator system, and navigation receiver. According to aspects of the present disclosure, a correlator module and executable program code are provided. The executable program code, when implemented on a computer system such as a signal correlator system, is configured to perform any of the methods according to the present disclosure.

[0039] According to a further aspect of the present disclosure, there is provided a method of operating a direct memory access control module to control data transfers to and from a correlation calculation circuit via a system bus, wherein a correlation calculation circuit, such as the correlator module described above, is configured to calculate correlations of received signal samples with code samples of a spreading code replica, for example, as described in the method described above. The direct memory access control module executes first instructions to write initial values ​​defining an initial state of the correlation calculation circuit to an internal data structure of the correlation calculation circuit. The initial state may include an initial state of a carrier phase and / or an initial state of a code phase. The first instructions may include writing at least a portion of the spreading code replica to a data memory structure of the correlation calculation circuit. The direct memory access control module executes second instructions to sequentially supply (a predetermined number of) words to the correlation calculation circuit, each consisting of a predetermined number of received signal samples, the predetermined number being the same for each word. The direct memory access control module can retrieve the words from a buffer that stores the received signal samples, for example, in a local or remote data storage device. The words may be retrieved starting from a predetermined word index in the buffer, which may depend on the spreading code replica to be correlated. The direct memory access control module executes third instructions to retrieve the correlation output from the output data structure of the correlation calculation circuit, and possibly to retrieve an end state of the correlation calculation circuit. Advantageously, the first, second, and third instructions are executed as a sequential chain of operations. Advantageously, the first, second, and third instructions are executed recursively, for example, for multiple spreading codes for different navigation signals. The method of operating the direct memory access control module, and in particular the first, second, and third instructions, may be implemented as executable program code, such as for execution in the signal correlator system described above.

[0040] Aspects of the present invention will now be described in more detail with reference to the accompanying drawings, in which like reference numerals indicate like features. [Brief explanation of the drawings]

[0041] [Figure 1] FIG. 1 is a block diagram of a GNSS navigation receiver. [Figure 2] FIG. 1 is a block diagram of a correlator module of a GNSS receiver. [Figure 3] FIG. 1 is a block diagram of a GNSS receiver according to an aspect of the present disclosure. [Figure 4] FIG. 1 is a graphical representation of 4-bit complex-valued intermediate frequency samples packed into a 32-bit word. [Figure 5] 1 is a flowchart of a method performed by a correlation device according to an aspect of the present disclosure. [Figure 6] 4 is a block diagram of a correlation device according to an aspect of the present disclosure for use in the GNSS receiver of FIG. 3. [Figure 7] 7 is a block diagram of a carrier phase generator for use in the correlation device of FIG. 6. [Figure 8] 7 is a block diagram of a code phase generator for use in the correlation device of FIG. 6. [Figure 9] 7 is a flow diagram of a control sequence for the correlation device of FIG. 6. [Figure 10] FIG. 10 illustrates how IF sample words can be read from a buffer using an offset to calculate correlations for different satellites. [Figure 11] 1 is a flow diagram of a DMA chain for calculating correlation values ​​of different satellites. [Figure 12] FIG. 1 is a diagram of memory blocks involved in controlling interrelated devices through a DMA chain. [Figure 13] 1 is a diagram of a circular queue of multiple sample buffers in RAM that are successively filled by DMA transactions. [Figure 14] FIG. 10 illustrates the timing of correlation in a triple IF buffer. [Figure 15] 1 is a flow diagram of a DMA chain for calculating correlation values ​​for different satellites, including iterations of a tracking loop. [Figure 16] 1 is a diagram of DMA operation in continuous real-time mode using a triple-buffer architecture. [Figure 17] FIG. 1 is a block diagram of a GNSS receiver according to an aspect of the disclosure, including a multi-layer bus structure. DETAILED DESCRIPTION OF THE INVENTION

[0042] Referring to FIG. 1, a GNSS receiver 10 includes a radio frequency (RF) antenna 14 configured to receive at least one RF signal within one or more GNSS frequency bands. This RF signal includes signals from all satellites transmitting in the corresponding frequency band. The RF signal is processed in a front-end module 11, which includes a downconverter 111 for converting the RF signal to an intermediate frequency (IF) signal and an analog-to-digital converter (ADC) 112 for converting the IF signal into a stream of digital IF samples. The IF samples, including signals from all satellites transmitting within the corresponding frequency band, modulated by, for example, code division multiple access (CDMA), are forwarded to a correlator module 12. The correlator module 12 identifies individual satellites by correlating the IF samples with a local replica of that satellite's PRN code sequence, after removing any residual carrier. The correlator module 12 can recursively perform correlation operations to identify signals from multiple satellites emanating within a specified frequency band. The output of the correlator module 12 is fed to a processing module 13 where it is processed for signal tracking and possibly position, velocity and / or time determination.

[0043] 2, the correlator module 12 performs a correlation process to evaluate IF samples obtained from the RF signal with respect to one or more specific GNSS signals. The IF samples 110 are typically presented in the form of complex I+jQ values, with the in-phase I and quadrature Q components coded with a small number of bits. For example, if the I and Q components are coded with two bits each, then each complex sample is four bits wide. Carrier Phase Replica

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[0044] The correlation amplitude is greatest when the phases of the carrier and code replicas are aligned with the carrier and code phases of the satellite signal of interest in the IF samples. The correlation values ​​127 can be used as input to carrier and code tracking loops (not shown), which periodically adjust the carrier and code NCO frequencies, for example, via configuration signals 128, to keep their phases synchronized with the arriving signal of interest. This process is known as signal tracking. This process is well known in the art and will not be further documented herein.

[0045] Referring to FIG. 3, a GNSS receiver architecture 30 according to the present disclosure includes a central processing unit (CPU) 33 including one or more cores; a system memory (RAM) module 36; a DMA controller module 34 including one or more direct memory access (DMA) controllers configured to control direct read and / or write access to the RAM module 36; and a peripheral interface controller module 35 including one or more control devices for controlling peripheral interfaces such as a universal serial bus (USB) or universal asynchronous receiver-transmitter (UART). All of the above modules are configured to communicate with each other through a system bus structure. The system bus 31 allows devices within the computer system of the receiver 30 to access other devices within the system, transfers system data words (e.g., 32- or 64-bit) and uses an addressing system (e.g., 32-bit addresses). The system bus 31 may include a data bus 311, an address bus 312, and a control bus 313, as known in the art. In some systems, the system bus 31 handles a single access at a time. The system bus 31 may be multi-tiered, in which case multiple transactions may be performed / processed in parallel, provided that the endpoints of these transactions are disjoint. Examples of suitable system bus architectures are the Advanced Microcontroller Bus Architecture (AMBA®) and Wishbone, which include several sub-protocols suited to specific purposes: Advanced High-performance Bus (AHB), Advanced eXtensible Interface (AXI), Advanced Peripheral Bus (APB).

[0046] The GNSS receiver 30 further includes a front-end module 11 including F front ends, where F is the number of supported frequency bands. F may be equal to 1 for a single-band L1-only receiver or 3 for a three-band L1-L2-L5 receiver, for example. Each front end outputs I and Q digital IF samples at a respective IF sampling rate Fs. The formatter module 37 includes a formatter circuit for each front end, which packs the IF sample output stream from each front end into words that fit the word size of the system memory. The words output by the formatter module 37 are written to a buffer in the RAM module 36. For example, if the front ends generate 4-bit IF samples (e.g., 2 bits I and 2 bits Q) and the RAM word size is 32 bits, the formatter groups eight consecutive IF samples into a 32-bit word. Thus, RAM module 36 contains a succession of 32-bit IF sample words, each containing eight IF samples. The format of such an IF sample word 310 is shown in Figure 4, where I(n) and Q(n) are the real and imaginary components of the nth IF sample 110.

[0047] The GNSS receiver 30 further includes a correlation module 32. Unlike prior art software-defined receivers in which correlation is calculated in software running on the CPU 33, in the receiver of the present disclosure, a separate, dedicated device—the correlation module 32—performs the correlation calculations on the IF samples 110 and is connected to the system bus 31 to offload the CPU. It will be understood that in the architecture of the GNSS receiver 30, GNSS signal tracking operations are generally performed through software running on the CPU 33, as is known in the art. The same applies to position, velocity, and time calculations.

[0048] The correlation module 32 may include one or more correlation devices 320, for example, one for each frequency band or front-end circuit. Referring to Figure 5, each correlation device 320 is configured to perform an operation 50 on all IF samples of a word input to the correlation device, which operation 50 advantageously conforms to the operations described in connection with Figure 2. In operation 51, a complete word 310 (the length of which depends on the architecture of the computer / bus system) of Ns IF samples is read from an address in the RAM module 36 by a transaction on the system bus 31 and written to a data structure, such as a register, of the correlation device 320. Advantageously, the word is input to the correlation device by a single bus transaction, and for example, the word 310 has a length equal to the width of the system bus 31, such as 16 bits or 32 bits.

[0049] According to aspects of the present disclosure, writing a new word to the data structure of correlation device 320 initiates a new set of correlation operations 52-55. In operation 52, the carrier phase replica

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[0050] 6, correlation device 320 includes a set of data structures such as buffers or registers 330 that interface with system bus 31 of GNSS receiver 30, i.e., system bus 31 is configured to access registers 330 for read and / or write operations, as the case may be. Advantageously, correlation device 320 is configured to operate solely from write access to registers 330 (i.e., perform a chain of operations 50) to generate accumulated results that are written to an output data structure, such as output register 332, that can be accessed (read) through system bus 31.

[0051] The set of data structures includes an input data structure, such as input register 331 (IFIN[]), configured to receive a complete word 310 of Ns IF samples. Thus, the length of input register 331 is equal to Ns times the number of bits in one IF sample. In some examples, word 310 is 32 bits and one IF sample is 4 bits, so Ns equals 8. System bus 31 writes to input register 331 one word at a time, for example, from an address in RAM module 36.

[0052] Advantageously, the correlation device 320 is configured to initiate (trigger) an operation (e.g., operation 50) by writing a new IF sample word 310 to the input register 331. Each new IF sample word 310 written to the input register 331 is processed by the correlation calculation module 328. In particular, for each new IF sample word 310 written to the input register 331, the correlation device 320 is configured to apply a carrier rotation (ROT) to the Ns IF samples to obtain Ns baseband samples. The correlation device is configured to multiply the baseband sample with one or more code replicas (e.g., an early code replica, an on-time code replica, and a late code replica) to obtain a multiplication result. The multiplication result is added to the current value of the respective accumulator 323. Advantageously, the correlation device 320 is configured to apply a carrier rotation and / or multiply the baseband samples in parallel for all Ns IF samples of the word 310, although it may be capable of sequential operation. To this end, the correlation device 320 may include an appropriate rotation module 321, a multiplication module 322, and an accumulator module 323.

[0053] Local Carrier Phase

number

[0054] The correlation device 320 may include a local memory 326 that fully or partially stores the PRN code replica. The correlation device may be configured to generate the PRN code replica internally or to receive the PRN code replica from an external device, such as the RAM module 36, and store it in the local memory 326.

[0055] The set of registers 330 may include one or more of the following registers: CARFREQ, CARPHASE: These registers are used by the carrier phase generator 324 to determine the carrier phase value for each IF sample of the word 310 at the moment being processed by the correlation device 320, and the values ​​in these registers may be updated from time to time, for example by a signal tracking loop, to take into account variations in carrier frequency due to Doppler shifts. CODEFREQ, CODEPHASE: These registers are used by the code generator 325 to determine the code phase of each IF sample of the current word 310 being processed by the correlation device 320. CODEMEM[]: A set of registers 337 for loading PRN code chips into the local PRN code memory 326. Advantageously, the values ​​written to the above registers 330 enable the carrier phase generator and code phase generator to determine the carrier phase and code phase of each of the IF samples of a sequence of words that are successively processed (written) by the correlation device 320. In particular, they represent the initial phase of the first IF sample and the phase shift over one word. Advantageously, these registers are configured to be written once by the system bus 31 at the beginning of each processing of a sequence of words, and may be updated from time to time to adjust the values ​​to compensate for small shifts or variations detected by signal tracking.

[0056] To correlate over time T, T*Fs IF samples must be processed, i.e., the correlation device must run T*Fs / Ns times. In other words, Nw=T*Fs / Ns words must be successively written to input register 331 to generate a multiplication result that is accumulated in accumulator module 323. The current accumulated value of the accumulator module is advantageously available in output register 332 accessible via system bus 31. Thus, output register 332 can be the working register of accumulator module 323, which advantageously allows the correlation output to be read at any time. Output register 332 may include separate registers for the on-time code replica and each of the offset code replicas (e.g., early, on-time, and late). Alternatively, output register 332 may be an independent register. Accumulator module 323 may be configured to write the current accumulated value to output register 332 at predetermined time intervals, for example, after processing Nw words.

[0057] Carrier phase generator 324 may be implemented as in Figure 7. A CARPHASE register 334 stores the phase rotation to be applied to the first IF sample of word 310.

number

[0058]

number

number

[0059] In one alternative implementation, the CARFREQ register 333 may contain a value representing the carrier phase shift over one IF sample. The carrier phase may then be determined by cumulatively adding this value to all IF samples of the word, starting with the CARPHASE value of the first IF sample. Because there are a fixed number of IF samples in one word 310, the CARPHASE register may be simply updated by incrementing its value by Ns*CARFREQ to prepare for the next word.

[0060] Advantageously, a value representing the initial carrier phase to be applied to the first IF sample of the first word 310 written to the input register 331 is written to the CARPHASE register before writing the first IF sample word to the input register 331. This allows the correlation device 320 to begin performing the correlation operation immediately upon writing the IF sample word to the input register 331. Furthermore, the system bus need only write the CARPHASE and CARFREQ values ​​to the corresponding registers once for the entire sequence of words, except to compensate for, for example, variations in the carrier frequency as detected by the signal tracking control loop. The output of the carrier phase generator 324 is coupled to the rotation block 321 of the correlation calculation module 328.

[0061] The code phase generator 325 may be implemented as shown in Figure 8. The CODEPHASE register 336 can be a fixed-point representation of the code phase. For example, the CODEPHASE register may be 48 bits wide, with the 16 most significant bits (MSBs) containing the integer part of the code phase (chip number) and the 32 least significant bits (LSBs) containing the fractional part (phase in chips).

[0062] The CODEPHASE register 336 can represent the code phase of the code replica at the epoch of the first IF sample of the word written to the input register 331, which can be an on-time code replica, or alternatively, an early replica cp as shown in FIG. E It may be a time-offset code replica such as (n). E (n+i) is the code phase corresponding to the early code replica of the i-th IF sample of the word in the input register, and cp E (n)+i*CODEFREQ / Ns. Thus, the value of CODEFREQ register 335 represents a code phase shift across one word 310 (i.e., across Ns IF samples). Any other time-offset code phases, e.g., on-time code phase and late code phase, can be calculated by adding or subtracting a respective offset to (from) the code phase represented in CODEPHASE register 336. In FIG. 8, the on-time code phase is calculated by adding a determined offset d to the calculated early code phase value of each IF sample, and the late code phase is calculated by adding a determined offset d to the on-time code phase value of each IF sample. Additional phase shifts may be implemented as desired. To process the next IF sample word written to input register 331, e.g., after updating the accumulator, the value of CODEPHASE register 336 is advantageously updated, e.g., by adding the value of CODEFREQ register 335. By doing so, the code phase generator is prepared to determine the code phase for the next batch of Ns samples (next word 310).

[0063] In one alternative implementation, the CODEFREQ register 335 may contain a value representing the phase shift over one IF sample. The code phase may then be determined by cumulatively adding this value to all IF samples of the word, starting with the CODEPHASE value of the first IF sample. Because there are a fixed number of IF samples in one word 310, the CODEPHASE register may be simply updated by incrementing its value by Ns*CODEFREQ to prepare for the next word.

[0064] Advantageously, a value representing the initial code phase to be applied to the first IF sample of the first word 310 of the sequence of words written to the input register 331 is written to the CODEPHASE register before writing the first word 310 to the input register 331. This allows the correlation device 320 to begin performing the correlation operation immediately upon writing the IF sample word to the input register 331. Furthermore, the system bus need only write the CODEPHASE and CODEFREQ values ​​to the corresponding registers once for the entire sequence of words, except to compensate for variations in code frequency as detected, for example, by a signal tracking control loop.

[0065] The code phase generator is advantageously coupled to the local PRN code memory block 326 to generate the correct code sample at the output of the memory block 326. The integer part (chip number) of the code phase in the CODEPHASE register 336 is advantageously used as an index in the local PRN code memory block 326. Updating the CODEPHASE register 336 after processing one word automatically updates the index from which the memory block 326 should be read. The output of the memory block 326 is coupled to the multiplier block 322 of the correlation calculation module 328.

[0066] 9, a control sequence 60 for operating the correlation device 320 may include the following chain of operations: In operation 61, data structures of the correlation device are initialized. This may include, for example, writing initial values ​​that enable carrier phase and code phase to be generated by the carrier phase generator 324 and the code phase generator 325 for the Ns IF samples of the first word to be processed. In some examples, operation 61 includes writing an initial carrier phase and an initial code phase to the CARPHASE register 334 and the CODEPHASE register 336, respectively, and writing carrier phase and code phase shift values ​​to the CARFREQ register 333 and the CODEFREQ register 335, respectively, where the carrier phase and code phase shift values ​​may represent respective phase shifts over one or more, e.g., Ns IF samples. Operation 61 is advantageously performed by the system bus writing the initial values ​​to the respective data structures of the correlation device.

[0067] In operation 62, the applicable PRN code segments are determined. In some examples, the code segments are written to the CODEMEM[] register 337, for example, by one or more transactions on the system bus. The applicable code segments may be retrieved, for example, from the RAM module 36 or from a remote network, such as a cloud network. Alternatively, the PRN code segments are generated locally by internal circuitry of the correlation device 320.

[0068] In operation 63, one or more, in particular, Nw=T*Fs / Ns words, each containing Ns IF samples, are successively written to an input data structure, e.g., input register 331, where T is the desired correlation duration and Fs is the IF sampling frequency. The words can be retrieved from any local or remote data storage system, e.g., RAM module 36, and can be stored in a contiguous address range. In some examples, multiple Nw words are written to the input data structure by a chain of consecutive system bus transactions. Advantageously, intermediate local storage of words within correlation device 320 is avoided, and input register 331 is configured to store just one word. In operation 64, for each IF sample word written to input register 331, the correlation device 320 performs the rotate, multiply, and accumulate operations as described in connection with the chain of operation 50. Advantageously, writing the IF sample word 310 to the input register 331 triggers operation 64, which includes operation of the correlation calculation module 328. Advantageously, the correlation calculation module 328 is configured to perform its operation on complete words at a rate at least equal to, and possibly higher than, the rate at which the system bus 31 is writing new words to the input data structure. Operation 64 advantageously includes, for each of the N words, cumulatively updating initial values ​​that enable the carrier phase and code phase to be generated for the next word, for example, by the carrier phase generator 324 and the code phase generator 325. In operation 65, the output register 332 (CORROUT[]) is read, for example, by the system bus, to retrieve the correlation value. Optionally, the CARPHASE register 334 and the CODEPHASE register 336 are read to retrieve the end values ​​of the carrier phase and the code phase, respectively, so that the end values ​​of the carrier phase and the code phase may be available for successive batches of IF samples (words) without having to recalculate them.

[0069] Advantageously, the chain of operations 61 to 65 is repeated for another signal, for example from another satellite of the GNSS constellation. The control sequence 60 is advantageously controlled by the DMA controller 34.

[0070] Uploading the IF sample words (operation 63) is typically the dominant operation in control sequence 60. Loading the PRN code segments (operation 62) can be shorter because there are typically 2 to 20 IF samples per PRN chip, and PRN codes are typically coded with fewer bits than IF samples.

[0071] It will be appreciated that local code memory block 326 does not necessarily have to hold the entire period of the PRN sequence. Local code memory block 326 can be a buffer that is loaded during control sequence 60, for example, in operation 61, to support correlation processing. CODEPHASE register 336 can be interpreted as a chip count, and thus an index into code memory block 326, and can be offset relative to the absolute chip number of the satellite's PRN code.

[0072] By doing so, the correlation device 320 is extremely flexible compared to implementations that embed signal design parameters in a hardware implementation. The uploaded code segments can even correspond to aperiodic encryption codes. Next to flexibility, a smaller code memory also offers area and power consumption advantages. For example, a 1024-chip code memory can be used to process a 10230-chip correlation (e.g., for a GPS L5 signal). The correlation would simply be subdivided into 10 sub-correlations of 1023 chips, uploading the right segment to the code memory 326 each time. Although the CPU must sum the 10 sub-correlations generated by the correlation device 320 and configure the initial code phase and initial carrier phase for each segment, the associated overhead remains small.

[0073] The code memory block 326 can use single-bit chips that represent multiplication with 1 or -1. Alternatively, the code memory block 326 can contain ternary chips (-1, 0, 1) encoded on two bits, or even higher value chips. This inserts blanks in inapplicable time slots to allow correlation with time-multiplexed codes and watermark codes.

[0074] Some GNSS signals use so-called binary offset carriers (BOC). For these signals, the PRN code chips are modulated by a fixed pattern. For example, for BOC(1,1) (e.g., in GPS L1C), a logical 1 is replaced by 10 and a logical 0 is replaced by 01. This pattern should be reflected in the local signal to support direct correlation. There are several ways to do this known to those skilled in the art. A trivial way is to write the entire permuted pattern to the local code memory 326 as if it were an actual PRN code. For BOC(1,1), the code 1 0 1 1 would be replaced by 1 0 0 1 1 0 1 0 in this case. Alternatively, a pattern can be generated as a function of the fractional part of the code phase, e.g., via a lookup table. The output of this function is then used to modulate the corresponding PRN chips (e.g., by an XOR operation). This function can be configured via an additional configuration register, e.g., in the first step of the correlation sequence. The latter method reduces data traffic and storage space for PRN code templates in system memory, but adds some complexity to the design.

[0075] Handling navigation symbols The correlation values ​​obtained by the above methods and devices correspond to the correlation between the segments of PRN codes stored in the correlation device's local memory 326 (initialized in the CODEMEM[] register 337) and the IF samples dumped into the input register 331.

[0076] In GNSS satellites, the PRN code may be further modulated at a lower rate (e.g., 1 kHz) by a navigation symbol or a secondary-code symbol. If the symbol is "0", the PRN code is transmitted as is. If the symbol is "1", the signs of all PRN code chips are inverted. To avoid correlation loss caused by sign changes in the received PRN code, it is advantageous to synchronize the correlation with the symbol transitions.

[0077] There are several ways to do this. For example, the first IF sample provided to the correlation device can be aligned with a symbol transition. If the symbol transition occurs at sample index i1 for satellite 1, sample index i2 for satellite 2, etc., then correlations for different satellites are performed over different IF sample windows, as shown in FIG. 10. FIG. 10 illustrates a 1 kHz symbol rate, where correlations are calculated over 1 ms intervals aligned with the received symbols. This means that the IF sample words dumped into the input register 331 for different satellites are taken from different starting addresses within the RAM module 36. The first word dumped for satellite N is the word containing sample index iN. It will be understood that the sample at index iN is not necessarily the first sample of that first word. Similarly, the last sample in the correlation window may not be the last sample of the last of the N words. The extra samples at the beginning of the first word and the end of the last word cause a small loss of correlation that is acceptable in most cases. This can be avoided by extending the local code with a short prefix and / or suffix and encoding states that nullify correlations with code samples outside the correlation window. Suitable encodings include ternary PRN codes (-1, 0, 1), such as time-multiplexed codes, that insert nulls in inapplicable time slots.

[0078] Another possibility is to memorize and reset the correlation device every time the code phase is a multiple of the symbol duration. For example, if the symbol rate is 1 kHz, the correlation device would be reset every time the code phase is a multiple of 1 millisecond.

[0079] DMA Chain Referring again to FIG. 3, the DMA controller 34 is used to transfer large amounts of data between system memory ranges and / or interface controller buffers. The DMA controller 34 reduces the load on the CPU core because CPU time does not need to be spent copying data from one location to another. The DMA controller may be configured, for example, by the CPU 33 by writing one or more descriptors of the desired transaction. These transactions copy data to or from incrementing addresses if memory ranges are involved, and keep the transaction address fixed if data is to be dumped or collected from the interface controller. Interaction with the interface controller is often managed with handshake signals that notify the DMA controller whether the interface has new data available or is ready to receive new data. The DMA controller then collects or provides the interface data and provides an acknowledgement signal indicating that the data request has been addressed. In some cases, the handshake signals can be disabled, a process known as "autobauding." In this case, the DMA controller transfers data to or from the destination address as fast as the bus arbitration system and its internal arbitration allow. Transactions between memory ranges, on the other hand, do not use handshaking signals and transfer data directly to and from incrementing addresses. DMA controllers usually have multiple channels to handle several streams simultaneously, with internal arbitration. DMA controllers often also support chaining, sometimes called scatter-gather, which allows multiple transaction sequences to be concatenated according to descriptors stored in memory.

[0080] 9 for controlling the correlation device includes only transfers from the system RAM memory 36 to the correlation device 320 and vice versa. This can be performed by the CPU 33, or advantageously by the DMA control module 34 without CPU involvement.

[0081] Advantageously, the operation and sequencing of the correlation devices is driven by a chain of DMA transactions 70, as depicted in Figure 11. In an initialization operation 71, CPU 33 prepares DMA transfer chain 70. This includes one or more of the following: - Preparing a memory block in RAM module 36 containing values ​​to be sent to the CARFREQ, CARPHASE, CODEFREQ, CODEPHASE, and CODEMEM[] registers for all desired satellites or signals. - reserving a memory area in the RAM module 36 for receiving the correlation value from the CORROUT[] register 332 and, optionally, reserving a memory area in the RAM module 36 for receiving the end value of the CODEPHASE register 336 and / or the CARPHASE register 334, respectively. - Preparing DMA descriptors for defining the DMA chain 70. In particular, for each satellite or signal, the descriptor contains an offset or mark indicating which IF sample word to start from (the word containing i1, i2, ... iK). The different memory blocks that are prepared are shown in FIG.

[0082] Referring again to FIG. 11, once the initialization operation 71 is performed, the DMA chain 70 can begin as soon as a buffer of IF samples is ready in the RAM module 36 .

[0083] The following operations are performed sequentially by the DMA control module 34 for each of the K satellites. In operation 72, the DMA control module 34 copies the CARFREQ, CARPHASE, CODEFREQ, and CODEPHASE registers from RAM to the corresponding registers 333-336 of the correlation device 320. The DMA control module 34 also copies (a segment of) the PRN code from RAM 36 to the CODEMEM[] register 337. In operation 73, the DMA control module 34 copies a total of Nw IF sample words from the RAM module 36 to the input data structure (input registers 331) of the correlation device, advantageously starting from a word index included in the DMA descriptor. The Nw IF sample words can be written sequentially to the input data structure in multiple (Nw) bus transactions, or may be written in a single data stream over the system bus. In the present disclosure, a transaction may be defined as the process of transferring one word from RAM 36 to the input data structure of the correlation device. In one aspect of the present disclosure, the correlation device processes each IF sample word as soon as it is provided by the system bus, i.e., as soon as the word arrives in the input register 331. Therefore, advantageously, writing an IF sample word 310 to the input register 331 triggers the operation of the correlation calculation module 328 of the correlation device 320. One advantage of doing so is that the progress of the correlation operation is determined entirely by the rate at which IF sample words are provided to the input data structure. In contrast to prior art, such as Tran et al., the correlation device is not clocked at a fixed rate. Instead, the correlation is updated each time a new word is pushed. This makes it highly flexible to operate in both real-time or post-processing modes. The CPU module 33 or DMA module 34 do not need to provide new IF words at a fixed rate. Writing new words to the input data structure can be interrupted if other higher-priority tasks need to be performed.This is not a problem and the correlation can simply be restarted on the next write access.

[0084] In operation 74, for example, once all N words have been processed by the correlation device 320, the DMA control module 34 controls the system bus 31 to copy the CORROUT[] register 332 of the correlation device 320 to the RAM module 36. At the end of the chain 70, all correlation values ​​are available in the RAM module 36 and accessible for further processing.

[0085] To allow for DMA transfers in which Nw IF samples are written to incrementing addresses, the input register may be mapped to a series of addresses rather than a single address. In particular, some DMA modules may be configured to write IF sample words to consecutive addresses (A1, A2 = A1 + 1, A3 = A2 + 1, etc.). In that case, the trigger for the correlation operation is linked to writing not only to A1, but also to A1, or A2, or A3, etc.

[0086] Real-time operation One advantage of the correlation device and DMA chain 70 described above is that they are suitable for both post-processing and real-time operation. In post-processing (e.g., in the case of watermarking), the IF sample buffer 360 in the RAM module 36 can be processed by the DMA chain without strict real-time constraints. This mode requires only a single IF sample buffer in RAM. Once all relevant information (e.g., encryption keys) is available, the DMA chain can be started, and correlations become available shortly thereafter, which may be used to adjust subsequent correlations, progressing gradually through the IF sample buffer.

[0087] 13, for continuous real-time operation, instead of a single buffer, it is advantageous to maintain a circular queue 361 of multiple IF sample buffers 360 in RAM. At any time, one of the IF sample buffers in queue 361 is being filled while at least one of the other IF sample buffers is being processed by one or more correlation devices 320. In the example using queue 361 of three IF sample buffers 360 as shown in FIG. 13, the three IF sample buffers are advantageously filled sequentially by DMA control module 34 transactions with minimal CPU involvement.

[0088] FIG. 14 shows an example in which the three circular IF sample buffers 360 of FIG. 13 each cover 1 ms, and three successive correlation values ​​can be calculated for satellites 1...K. In cycle A, the DMA chain 70 starts when buffer #2 is ready. The DMA chain 70 calculates correlations for sat 1...K for IF samples partially stored in buffer #1 and buffer #2 over a 1 ms time span. One millisecond later, in cycle B, the DMA chain restarts, this time calculating correlations for IF samples partially stored in buffer #2 and buffer #3 over a 1 ms time span. In cycle C, correlations are calculated for IF samples partially stored in buffer #3 and buffer #1 over a 1 ms time span. This process can continue indefinitely. The number of satellites in the chain, K, is advantageously selected so that the chain completes within the time required to fill a buffer, i.e., so that a "chain end" event occurs before the next buffer is filled. It will be appreciated that in each buffer, an appropriate starting index may be utilized for each satellite i1, i2, ..., 1K. In each cycle, for each satellite, the correlation operation begins with the IF sample where the previous cycle ended.

[0089] 15, the flow of FIG. 11 is modified in that after DMA chain 70 is completed for all navigation signals (satellites), a tracking loop 75 is executed before the next run of the DMA chain with new IF samples. Tracking loop 75 may include operation 751 in which the CPU processes correlation values ​​read from correlation module 32 by DMA operation 74 and written to RAM module 36. Tracking loop 75 may include operation 752 in which carrier and / or code tracking loops may be repeated, for example, to adjust the carrier frequency and code frequency, respectively. Tracking loop 75 may include operation 753 in which the carrier frequency and / or code frequency in RAM module 36 are updated with the values ​​obtained in operation 752. This may include updating registers in RAM module 36 that are written to CARFREQ register 333 and CODEFREQ register 335 of the correlation device to prepare for the next run of the chain. It will be appreciated that DMA operation 74 may include reading the ending values ​​of CARPHASE register 334 and CODEPHASE register 336 (i.e., those used for the last word in the execution of the DMA chain) and updating the corresponding registers in RAM module 36 to prepare for the next execution of the DMA chain. Note that operation 71 to "prepare DMA chain in RAM" needs to be performed only once. This sequence of operations is typical for continuous real-time operation.

[0090] Figure 16 provides a complete overview of the above-described DMA data flow corresponding to the circular triple-buffer architecture.

[0091] The correlation module 32 may be used equally well for post-processing of aperiodic or watermark codes for real-time operation. Post-processing mode and continuous real-time mode may be combined on a single correlation device, with the correlation device being fed with data from a static IF buffer containing data to be post-processed after real-time processing is complete. Switching between these different modes of operation may be fully controllable through DMA, without CPU overhead.

[0092] The maximum throughput that a correlation device must support depends on the capabilities and requirements of the system. In some systems, bus transactions may take several clock cycles, and / or the DMA controller may first have to fetch data from memory in a separate transaction before it can be pushed toward the correlation device, one word at a time, in one transaction. In these cases, the time between successive transactions toward the correlation device may be several clock cycles, allowing for a partially sequential implementation. For example, if an access requires two clock cycles, the correlation (and local signature) can be calculated in two stages, each of which considers an IF sample word half the system bus width. This situation can also be created by inserting bus wait states when silicon area is more important than throughput.

[0093] In other systems, the DMA controller may be able to provide data in burst transactions with a throughput of one system word per clock cycle. Standard digital design techniques, such as introducing pipeline registers during some operations, can be exploited to maximize throughput. For example, in a 400 MHz system with a correlation device with Ns = 8 input registers and a DMA controller that uses one clock cycle to fetch a word from RAM and another to push that word to the correlation device, a theoretical throughput rate of 400 * 8 / 2 = 1600 Msps could be achieved. Given a 20 MHz IF sampling rate, this is theoretically sufficient to process 80 GNSS signals in real time. In practice, the throughput will be slightly lower because the DMA controller is typically also handling other transactions, and some of the bus bandwidth (especially to memory) is required for the CPU. Uploading PRN code segments also consumes bus bandwidth, but this is typically much less than the IF sample data traffic described above.

[0094] Throughput can be increased by a DMA controller with two or more interfaces to a multi-layered bus structure. For example, Figure 17 shows a GNSS receiver system 80 in which a multi-layered bus 81 supports N parallel streams to the system RAM module 36 and M parallel streams to the DMA control module 34. Such an architecture allows, for example, fetching data from memory while simultaneously pushing previously fetched data to the correlation module 320.

[0095] In some examples, the CPU module 33 does not have direct access to the correlation device. The correlation module can be designed to be CPU core independent, without requiring any custom adaptation of the core. In the initial phase, the CPU can prepare the DMA chain in RAM. During tracking, the CPU only needs to periodically update the code and carrier phase and frequency, as it does for the parallel channels, except that the new values ​​are stored in RAM. Advantageously, the DMA chain takes care of all communication to and from the correlation device. This allows for a reduction in the complexity of the GNSS receiver without affecting the CPU load.

[0096] In the foregoing description, aspects of the present disclosure have been illustrated with respect to GNSS signals, but it will be appreciated that the present disclosure may be equally applied to other types of navigation signals, such as terrestrial navigation signals or low-Earth orbit navigation signals, and more broadly, to any positioning, velocity and timing (PVT) signal. [Explanation of symbols]

[0097] 1 satellite 2 satellites 10 GNSS receivers 11 Front-end module 12 Correlator Module 13 Processing Module 14 Radio Frequency (RF) Antenna 30 GNSS receiver architecture, GNSS receiver 31 System Bus 32 Correlation Module 33 Central Processing Unit (CPU), CPU module 34 Direct Memory Access (DMA) Controller Module, DMA Control Module, DMA Controller 34, DMA Module 35 Peripheral Interface Controller Module 36 System Memory (RAM) Modules, RAM Modules, System RAM Memory 37 Formatter Module 50 operations 51 Operation 52~55 Correlation operation 60 Control Sequences 61~65 operation 70 DMA transaction chains, DMA transfer chains 71 Initialization operation 72 operation 73 operation 74 DMA operations 75 Tracking Loop 80 GNSS receiver systems 81 Multi-level bus 110 IF samples 111 Down Converter 112 Analog-to-Digital Converter (ADC) 121 Numerically Controlled Oscillator (NCO) 122 Rotor Block 123 Code generator 124 Code NCO 125 Multiplier Blocks 126 Accumulator 127 Correlation, correlation value 128 configuration signals 310 IF Sample Word, Complete Word, Moment Word 311 Data Bus 312 address bus 313 Control Bus 320 Correlation Devices 321 Rotating module, rotating block 322 Multiplication Module, Multiplier Module 323 Accumulator, Accumulator Module 324 Carrier Phase Generator 325 code phase generator 326 local memory, local PRN code memory, memory block, local PRN code memory block 328 Correlation Calculation Module 330 Buffers or Registers 331 Input Registers 332 Output register, CORROUT[] register 333 CARFREQ Register 334 CARPHASE register 335 CODEFREQ Register 336 CODEPHASE register 337 CODEMEM[] register 360 IF sample buffer, circular IF sample buffer 361 Circular Queue 751 operation 752 operation 753 operation

Claims

1. A signal correlator system (30), comprising: A system bus (31), a central processing module (33) connected to the system bus; a correlator module (320) connected to the system bus and configured to perform a correlation between a first batch of received signal samples (110) and a second batch of code samples of a local replica of the spreading code; a carrier phase generator circuit (324) configured to determine a carrier phase corresponding to each of the received signal samples of the first batch; a code generator circuit (326, 325) configured to determine each of the second batches of code samples; a correlation calculation circuit (328) configured to correlate the received signal samples of one of the first batches with the code samples of a respective second batch of the second batches, thereby obtaining a correlation output; an accumulator circuit (323) configured to accumulate correlation outputs for a plurality of said first batches; a correlator module (320) including: Including, a signal correlator system configured to provide the first batch to the correlator module via the system bus as words (310), each of the words consisting of a predetermined number of the received signal samples (110); the correlator module is configured to trigger an operation configured to obtain the correlation output each time one of the words is provided by the system bus; A signal correlator system (30).

2. 2. The signal correlator system of claim 1, wherein the system bus (31) has a width that is an integer multiple of the bit size of each of the words, and preferably the system bus has a width equal to the bit size of each of the words.

3. 3. The signal correlator system of claim 1, further comprising a data storage device (36) connected to the system bus (31) and configured to store the words, wherein the signal correlator system is configured to read at least one of the words (310) from the data storage device and write the at least one of the words to a data structure of the correlator module through transactions on the system bus, preferably configured to write one word at a time to the data structure of the correlator module.

4. 4. The signal correlator system of claim 1, wherein the correlator module (320) includes an input data structure (331) configured to receive the words from the system bus, the input data structure being coupled to the correlation calculation circuit (328).

5. 5. The signal correlator system of claim 1, wherein the correlator module includes an output data structure (332) readable by the system bus, and wherein the output of the accumulator circuit (323) is configured to be written to the output data structure.

6. 6. The signal correlator system of claim 1, wherein the correlator module (320) is configured to trigger an update of the state of the carrier phase generator circuit (324) and / or the state of the code generator circuit (325, 326) each time one of the words is provided by the system bus, and preferably wherein the correlator module is configured to trigger the update of the state of the carrier phase generator circuit (324) and / or the state of the code generator circuit (325, 326) after the correlation calculation circuit has completed a correlation operation on one of the words.

7. the code generator circuit a data memory structure (326) configured to contain at least a portion of the local replica of the spreading code; a first code register (336) configured to contain a value representing a code phase index that enables a first code phase to be determined for a given one of the code samples; a second code register (335) configured to contain a value representing a code phase shift over a predetermined number of said code samples; Including, and for each successive one of the words provided to the correlator module via the system bus, the code generator circuit is configured to increment the value of the first code register by an amount representing a code phase shift across the word of the received signal samples based on the value of the second code register. A signal correlator system according to any one of claims 1 to 6.

8. The carrier phase generator circuit (324) a first carrier register (334) configured to contain a value representing a carrier phase index that enables a first carrier phase to be determined for a given one of the received signal samples; a second carrier register (333) configured to contain a value representing a carrier phase shift over a predetermined number of said received signal samples; Including, and for each successive one of the words provided to the correlator module via the system bus, the carrier phase generator circuit is configured to increment the value of the first carrier register by an amount representing a carrier phase shift across the word of the received signal samples based on the value of the second carrier register. A signal correlator system according to any one of claims 1 to 7.

9. 9. The signal correlator system of claim 1, further comprising a direct memory access control module (34) operatively coupled to the system bus and the central processing module, the direct memory access control module being configured to be implemented with executable program code configured to execute sequences of transfers of the words from the data storage device (36) to the correlator module, preferably the executable program code being configured to write initial values ​​defining initial states of the carrier phase generator circuit and the code generator circuit to memory data structures (333-337) of the correlator module before each sequence of transfers.

10. 10. The signal correlator system of claim 1, configured to maintain a circular queue of buffers of the received signal samples in the data storage device, and configured to execute a sequence of instructions configured to transfer the received signal samples as words from one or more buffers of the circular queue to the correlator module and to push new ones of the received signal samples into another one of the buffers in the circular queue.

11. 11. A signal correlator system according to any one of claims 1 to 10, configured to selectively operate the correlator module in a real-time processing mode and a post-processing mode.

12. A navigation receiver including the signal correlator system of any one of claims 1 to 11, an input device configured to capture radio frequency signals, preferably a radio frequency antenna (14); a front-end circuit (11) coupled to the input device and configured to convert the radio frequency signal into the stream of received signal samples; a navigation receiver further comprising:

13. a formatter circuit (37) coupled to the system bus (31) and configured to pack the stream of received signal samples into the words; a data storage device (36) configured to store the words, preferably in a contiguous address range, the data storage device (36) coupled to the system bus, the signal correlator system configured to read at least one of the words (310) from the data storage device and write the at least one of the words to a data structure of the correlator module through transactions on the system bus; 13. The navigation receiver of claim 12, further comprising:

14. A correlator module (320) configured to be connected to a system bus of a computer system, the correlator module (320) being as described in any one of claims 1 to 11.

15. A method (50, 60) for correlating received signal samples (110) with code samples of a spreading code replica, comprising: packing the first batch of received signal samples into words, each of the words consisting of a predetermined number of the received signal samples; providing said words to a signal correlator circuit via a system bus, preferably said system bus having a width which is an integer multiple of the bit size of each of said words, preferably said system bus having a width equal to the bit size of each of said words; determining, for the received signal samples of each word, a respective carrier phase value and a respective code sample of the spreading code replica, and calculating, by the signal correlator circuit, a correlation of the received signal samples of each word with the respective code sample to obtain a correlation output; accumulating the correlation outputs calculated for a plurality of the words to obtain an accumulated output; Including, providing each word to the signal correlator circuit triggers calculating the correlation of the received signal samples with each word by the signal correlator circuit; Preferably, each time one of said words is provided to said signal correlator circuit, said carrier phase values ​​and said code samples of said spreading code replica are updated, and preferably the step of calculating the correlation of said received signal samples of said respective word by said signal correlator circuit triggers a step of updating said carrier phase values ​​and said code samples of said spreading code replica for a subsequent one of said words. Method (50, 60).

16. 16. The method of claim 15, further comprising retrieving the accumulated output by the system bus.

17. 17. The method of claim 15 or 16, wherein determining the respective code samples of the spreading code replica comprises determining a respective code phase value based on a code index value representing a code phase for a given one of the code samples and a code phase shift value representing a code phase shift over a given number of the code samples, and wherein determining the code sample for a subsequent one of the words comprises incrementing the code index value by applying a phase shift determined based on the code phase shift value.

18. 18. The method of claim 15, wherein the respective carrier phase value is determined based on a carrier index value representing a carrier phase for a predetermined one of the received signal samples and a carrier phase shift value representing a carrier phase shift over a predetermined number of the received signal samples, and wherein determining the carrier phase value for a subsequent one of the words comprises incrementing the carrier index value by applying a phase shift determined based on the carrier phase shift value.

19. capturing a radio frequency signal and down-converting the captured radio frequency signal to an intermediate frequency signal; digitizing the intermediate frequency signal to obtain the received signal samples (110); 19. The method of any one of claims 15 to 18, further comprising:

20. 20. A method according to any one of claims 15 to 19, wherein the received signal samples comprise one or more navigation signals, preferably one or more Global Navigation Satellite System signals.

21. 21. The method of claim 20, wherein the received signal samples are sequentially correlated with code samples of spreading code replicas for a plurality of navigation signals, and preferably, for each of the plurality of navigation signals, the words are stored in a data storage device and supplied from the data storage device to the signal correlator circuit starting from different sample indexes within the data storage device.

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