Quantum processing devices and methods

Abstract

A quantum processing device comprising at least one bilinear array of quantum dots, each array configured to hold a plurality of spin qubits, the device further comprising a controller configured to control the coherent transport of one or more of the plurality of qubits in each array to implement a quantum error correction code (QECC), the QECC encoding the collective state of the spin qubits of the respective array as a corresponding first level (L1) logic qubit.

Description

[Technical Field]

[0001] This application claims priority to Australian Provisional Patent Application No. 2022904005, filed on 23 December 2022, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to quantum processing devices and methods for operating quantum processing devices to achieve fault-tolerant computation via quantum error correction that is scalable and feasible in current quantum technology. [Background technology]

[0003] The realization of large-scale quantum computers capable of executing basis-breaking algorithms remains a challenging endeavor because their building blocks (qubits) are susceptible to errors arising from effects such as decoherence and noise. Quantum error correction is used in quantum computing to protect quantum information from errors and is considered essential for achieving fault-tolerant quantum computing.

[0004] Quantum error correction operates by representing quantum information associated with a high-quality logical qubit as an entangled state of multiple physical qubits. Thus, the state of the physical qubit can be encoded into the logical qubit state. The state of the logical qubit can be protected from errors in one or more of the physical qubits if the logical qubit is encoded according to a quantum error correcting code (QECC).

[0005] Like classical error correction, QECCs do not always correctly decode logical qubits, but their use reduces the effects of noise, thereby improving the utility of quantum processing devices. The number of high-fidelity qubits required for error correction has long remained beyond experimental reach. As we enter the era of quantum computing, characterized by control over noisy qubits, implementations of quantum error correction are becoming practically feasible. Therefore, there is a need for error correction techniques that utilize small numbers of qubits and also respect the constraints of realistic and manufacturable architectures.

[0006] Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention and is not to be construed as an admission that any or all of such matter forms part of the prior art or was common general knowledge in the art relevant to the present invention prior to the priority date of each claim in this application.

[0007] It will be understood that throughout this specification the word "comprise" or variations such as "comprises" or "comprising" imply the inclusion of a stated element, element, or step, or group of elements, elements, or steps, but not the exclusion of any other element, element, or step, or group of elements, elements, or steps. Summary of the Invention

[0008] A quantum processing device is provided that includes at least one bilinear array of quantum dots, each array configured to hold a plurality of spin qubits, and a controller configured to control coherent transport of one or more of the plurality of qubits in each array to implement a quantum error correction code (QECC), where the QECC encodes the collective state of the spin qubits of the respective array as a corresponding first level (L1) logic qubit.

[0009] In some embodiments, each bilinear array comprises a first line of N quantum dots configured to hold up to N spin qubits, and a second line of N quantum dots configured to allow entanglement operations to be performed between the respective qubits via coherent transport.

[0010] In some embodiments, the spin qubits are held in a first line of the array according to an arrangement selected to facilitate coherent transport of one or more of the plurality of spin qubits to perform error correction according to QECC.

[0011] In some embodiments, the device is configured to perform an error correction cycle for any one L1 logical qubit in at least one bilinear array by: (i) initializing one or more ancillary qubits of a QECC in the array according to the configuration; (ii) executing one or more two-qubit entanglement gates, each gate entangling one or more pairs of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

[0012] In some embodiments, the entangled qubits of the QECC include a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

[0013] In some embodiments, the system is configured to entangle two spin qubits in the array by coherently transporting a selected spin qubit of a pair of spin qubits from a first line of the array through a second line of the array, aligning the selected spin qubit with the other spin qubit, performing a two-qubit gate, and then coherently transporting at least the selected spin qubit back to the first line of the array.

[0014] In some embodiments, the device is configured to entangle two spin qubits in the array by inducing a direct local interaction between the qubits when the qubit to be entangled is already present in an adjacent dot.

[0015] In some embodiments, the one or more two-qubit entanglement gates are scheduled according to the QECC and the geometry of the bilinear array.

[0016] In some embodiments, the placement of the qubits in the first line of the array is determined to minimize the depth of the syndrome extraction circuitry.

[0017] In some embodiments, each bilinear array is constructed from silicon metal oxide semiconductor (SiMOS) quantum dots.

[0018] In some embodiments, the QECC is a surface code.

[0019] Also provided is a method for enabling quantum error correction on a quantum processing device, the method including: (i) arranging a plurality of spin qubits in a bilinear array of quantum dots of the quantum processing device according to a quantum error correction code (QECC), wherein the collective state of a subset of the spin qubits forms a first level (L1) logical qubit protected by the QECC; (ii) determining a sequence of one or more entanglement operations for each pair of the plurality of spin qubits; and (iii) executing a syndrome extraction circuit to determine a syndrome of the QECC for performing cycles of error correction by performing the sequence of entanglement operations, wherein performing the sequence of entanglement operations involves coherently transporting one or more of the plurality of spin qubits in the array.

[0020] In some embodiments, the arrangement of the plurality of spin qubits in the first line is selected to facilitate coherent transport of one or more of the plurality of spin qubits to perform error correction in accordance with the QECC.

[0021] In some embodiments, executing the syndrome extraction circuit includes (i) initializing one or more ancillary qubits of the QECC in the array according to the configuration; (ii) performing the determined sequence of entanglement operations, each entanglement operation entangling a pair of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

[0022] In some embodiments, each pair of entangled qubits includes a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

[0023] In some embodiments, entangling a pair of spin qubits of a QECC includes coherently transporting a selected spin qubit of the pair of spin qubits from a first line of the array through a second line of the array, aligning the selected spin qubit with the other spin qubit of the pair, performing a two-qubit gate, and then coherently transporting at least the selected spin qubit back to the first line of the array.

[0024] In some embodiments, entangling a pair of spin qubits involves inducing a direct local interaction between the qubits when the qubits to be entangled are already present in adjacent dots, without coherently transporting either of the qubits.

[0025] In some embodiments, the sequence of entanglement operations of the syndrome extraction circuit is determined according to the QECC and the geometry of the bilinear array.

[0026] In some embodiments, the placement of the qubits in the first line of the array is determined to minimize the depth of the syndrome extraction circuitry.

[0027] In some embodiments, the method for enabling quantum error correction on a quantum processing device further includes (iv) decoding the syndrome to obtain an output recovery operator, and (v) applying the recovery operator to the QECC of the array.

[0028] In some embodiments, steps (iv) and (v) are performed by the classical processing device in response to transmission of the syndromes from the quantum processing device to the classical processing device.

[0029] In some embodiments, the device comprises a plurality of bilinear arrays of quantum dots, and the controller is further configured to selectively couple a first L1 logical qubit of a first bilinear array to a second L1 logical qubit of a second bilinear array via a coherent coupling mechanism, the coupling occurring by long-range interaction-based transport of information encoded by the first L1 qubit to the second L1 qubit, and to perform one or more fault-tolerant quantum processing operations on the L1 logical qubits of the plurality of bilinear arrays.

[0030] In some embodiments, the coherent coupling mechanism includes a quantum transport structure configured to connect multiple bilinear arrays, enabling the controller to selectively couple the first and second L1 logical qubits by coherent transport of one or more spin qubits between a first bilinear array and a second bilinear array connected to the first array.

[0031] In some embodiments, the quantum transport structure includes one or more shuttling arrays of quantum dots, each shuttling array disposed between a connected pair of bilinear arrays.

[0032] In some embodiments, the controller is further configured to couple the first and second L1 logical qubits by transferring spin qubits from one array of the pair to the other array of the pair and performing one or more entanglement operations between the transferred spin qubits, thereby creating an entanglement operation between one or more of the spin qubits in each array of the pair.

[0033] In some embodiments, the controller is further configured to perform a fault-tolerant CNOT gate between a control array of the plurality of bilinear arrays and a target array of the plurality of bilinear arrays by coherently transporting spin qubits from the control array to the target array via the quantum transport structure, performing a nearest-neighbor CNOT gate between one or more pairs of data qubits of the QECC, coherently transporting the spin qubits from the target array back to the control array, and performing a cycle of error correction for each of the control array and the target array.

[0034] In some embodiments, the controller is further configured to apply a second-level QECC to encode the collective state of the set of L1 logical qubits as a corresponding second-level (L2) logical qubit.

[0035] In some embodiments, the distance of the second level QECC is arbitrarily scalable with the number M>1 of bilinear arrays of devices.

[0036] Also, a quantum processing device includes a plurality of bilinear arrays of quantum dots, each array configured to hold a plurality of up to N spin qubits; and a controller, wherein the controller implements a first level of QECC to control the coherent transport of one or more of the plurality of qubits in each array to encode the collective state of the spin qubits of the array as a corresponding first-level (L1) logic qubit, and selectively couples one or more pairs of the L1 logic qubits of the plurality of bilinear arrays via a coherent combining mechanism to encode the collective state of the spin qubits of the array as a corresponding first-level (L1) logic qubit. A quantum processing device is provided that is configured to implement a second level QECC for encoding collective states of M>1 sets of bits as corresponding second level (L2) logical quantum bits, wherein the coupling is performed, for each pair, by long-range interaction-based transport of information encoded by the first L1 quantum bit of the pair to the second L1 quantum bit of the pair, wherein the first level QECC reduces the error rate of the spin quantum bits to a lower error rate of the L1 logical quantum bit, and the second level QECC further reduces the lower error rate of the L1 logical quantum bit to an even lower error rate of the L2 logical quantum bit.

[0037] In some embodiments, the coherent coupling mechanism includes a quantum transport structure configured to connect multiple bilinear arrays, enabling the controller to selectively couple one or more pairs of L1 logical qubits by coherently transporting, for each pair, one or more spin qubits between a first array of the pair and a second array of the pair connected to the first array.

[0038] In some embodiments, the controller is further configured to perform a set of fault-tolerant quantum processing operations using one or more L2 logical qubits of the device.

[0039] Also provided is a method for performing a fault-tolerant quantum processing operation, the method being performed by a quantum processing device described herein, the method including: determining at least two coupled bilinear arrays for performing the quantum processing operation; selecting one or more pairs of the determined coupled bilinear arrays; and for each selected pair comprising a first array and a second array, (i) coherently transporting at least a subset of the spin qubits from the first array to the second array; (ii) performing individual entanglement operations between the spin qubits in the second array; (iii) reversing the coherent transport of step (i); and (iv) performing error correction cycles for each of the first and second arrays, the error correction cycles being enabled by any of the methods described herein.

[0040] Some embodiments of the present invention will now be described with reference to the accompanying drawings. [Brief explanation of the drawings]

[0041] [Figure 1A] FIG. 1 is a schematic diagram of a quantum processor according to some embodiments. [Figure 1B] 1B is a schematic diagram of a bilinear array of quantum dots of the first quantum processor of FIG. 1A. [Figure 1C] FIG. 1 is a schematic diagram of a portion of a quantum processor having multiple bilinear arrays coupled via a coherent combining mechanism, according to some embodiments. [Figure 1D] FIG. 1D is a diagram of an example layout of the quantum processor of FIG. 1C. [Figure 1E] FIG. 1D is a diagram of a qubit control means for controlling the bilinear array of the quantum processor of FIG. 1C. [Figure 1F] FIG. 1D is a diagram of a means of coherent transport of qubits between pairs of bilinear arrays of the quantum processor of FIG. 1C. [Figure 2A] FIG. 1 is a cross-sectional view of a qubit device circuit schematic for achieving shuttling of spin qubits. [Figure 2B] FIG. 10: Stability diagram of charge transfer for shuttling a spin qubit. [Figure 3A] FIG. 1 is a flow diagram of a method for enabling quantum error correction on a quantum processing device, according to some embodiments. [Figure 3B] FIG. 1 is a flow diagram of a method for performing an execution of a syndrome extraction circuit, according to some embodiments. [Figure 4A] FIG. 1D is a schematic diagram of an implementation of the Surafce-17 code on a bilinear array of processors of FIGS. 1A-1D. [Figure 4B] FIG. 1B is a schematic diagram of a stabilizer for the Surface-17 code implemented on the bilinear array of processors of FIGS. 1A-1D. [Figure 5] FIG. 1 is a circuit diagram of a syndrome extraction circuit for Surface-17 code, according to some embodiments. [Figure 6] FIG. 1 is a schematic diagram of a round of quantum error correction for one cycle of the Surface-17 code, according to some embodiments. [Figure 7A] FIG. 1 is a flow diagram of a simulation model used to evaluate the performance of quantum error correction in a 2×N array of quantum dots, according to some embodiments. [Figure 7B] FIG. 1 is a circuit diagram illustrating an implementation of a CNOT gate based on a combination of a CZ gate and two Hadamard gates. [Figure 7C] FIG. 1 is a circuit diagram illustrating the propagation of Pauli error in a CNOT gate according to an exemplary configuration of the gate. [Figure 8] 7B is a graph illustrating the logic failure rate of a quantum error correcting code for an L1 logic qubit encoded in a 2×N module according to the error model for shuttling of FIG. 7A. [Figure 9A] FIG. 10 is a circuit diagram illustrating a logic |0>L and logic |+>L fault-tolerant logic encoding circuit for initializing each state of the Surface-17 code. [Figure 9B]FIG. 10 is a circuit diagram illustrating a logic |0>L and logic |+>L fault-tolerant logic encoding circuit for initializing each state of the Surface-17 code. [Figure 10A] 1A-1C are circuit diagrams of a logical CNOT gate between two L1 qubits of a coupled 2×N module at the logical and physical levels, respectively, in accordance with some embodiments. [Figure 10B] 1A-1C are circuit diagrams of a logical CNOT gate between two L1 qubits of a coupled 2×N module at the logical and physical levels, respectively, in accordance with some embodiments. [Figure 11] FIG. 1 is a flow diagram of a method for combining (entangling) two logical qubits encoded in two separate 2×N arrays, according to some embodiments. [Figure 12] FIG. 12 is a schematic diagram of the coherent transport of the underlying spin qubit in the formation of a CNOT gate on a pair of L1 logic qubits, according to the method shown in FIG. 11 . [Figure 13] 10 is a graph of the failure rate of logic |Φ+> preparation in the evaluation of transversal-based two-qubit gates. DETAILED DESCRIPTION OF THE INVENTION

[0042] Previous approaches to the design of quantum processing architectures and corresponding devices have typically utilized lattice-based structures to create and manipulate qubits. Quantum error correction can be achieved by forming logical qubits using QECC applied to portions of a lattice, such as square sections of predetermined dimensions. Practical realizations of fault-tolerant quantum computing architectures aim to achieve error rates for processing qubits (i.e., qubits on which quantum operations are performed) of around 10 -15 (See Delfosse [1]).

[0043] To reduce the error rate, it is necessary to use a code with more qubits (i.e., increase the code distance). However, the difficulty of implementing quantum error correction increases (often nonlinearly) with the distance between a given qubit and the edge of the structure. Practical limits on logical qubit error rates often arise from the interconnect costs and layout difficulties of conventional architectures. As a result, it is difficult to design conventional lattice-based architectures that are suitable for long-distance QECC (such as those required to achieve sufficiently low logical qubit error rates) and that are practically feasible using currently available fabrication techniques.

[0044] Furthermore, the applicable structures for achieving practical fault-tolerant quantum computing architectures depend on the device's physical platform. In previous studies, neutral atom-based qubits have been transported across spatial structures (see Bluvstein [2]). However, neutral atom qubits differ significantly from qubits formed in other platforms, such as those that utilize the spin of charge carriers (i.e., electrons or holes) within a solid-state host (known as "spin qubits"). Therefore, the transfer operations performed on qubits in each platform are fundamentally different. For example, neutral atoms are trapped and shuffled by lasers using optical tweezers, whereas spin qubit transport relies on electric field control. Laser-based tweezers control of neutral atoms can experience scalability challenges related to resolution and optical aberrations. In contrast, gate-based electrical control of spin qubits has strong scalability that is practically achievable based on the manufacturing capabilities of the metal-oxide semiconductor (MOS) device industry.

[0045] In other approaches, error correction is performed on a 2D qubit lattice, a one-dimensional structure in which electrons are moved to symmetric points of a nanomagnet array to perform, for example, exchange-interaction-based qubit operations (see Mohiyaddin [3]). It would be desirable to devise a technique that ameliorates these, or one or more other, shortcomings of the prior art, or at least provides a useful alternative.

[0046] overview Disclosed herein are devices and methods for fault-tolerant quantum processing in which high-quality logical qubits are encoded by applying quantum error correction to bilinear arrays of quantum dots. In one aspect, the proposed architecture is based on qubit modules including bilinear arrays configured to hold multiple physical spin qubits. A controller is configured to control the coherent transport (referred to as "shuttling") of one or more spin qubits within each array. Quantum information stored within the spin qubits of the arrays collectively form first-level (L1) logical qubits, and shuttling of the qubits enables the implementation of QECCs, such as surface codes, to protect the L1 logical qubits in the presence of errors in the spin qubits.

[0047] The proposed architecture advantageously enables the formation of logical qubits for quantum processing devices by arranging physical qubits according to a linear structure. The architecture offers scalability in that computations can be performed with physical arrangements of qubits that are easier to control with practically achievable fanouts compared to the denser arrangements in conventional surface-code architectures, such as those using a square lattice of qubits. Furthermore, the proposed architecture is naturally suited to the use of silicon-based spin qubits, realized by electrons in respective silicon-metal-oxide-semiconductor (SiMOS) quantum dots. In this way, the design and fabrication of quantum devices can be achieved with practical processes using modern transistor foundries.

[0048] In some embodiments, the bilinear array is organized into two lines of N quantum dots each (referred to as a "2xN array"), and the 2xN array is configured to hold up to N qubits. For example, this disclosure describes a 2xN array composed of SiMOS quantum dots, where a qubit is the spin of each of the electrons held in the dot.

[0049] The relative placement of spin qubits within the 2×N array is selectively configured to facilitate shuttling of qubits (i.e., electrons) for operations that implement the QECC of the L1 logical qubit. The spin qubits are held according to their placement in a first line of the array, enabling initialization, quantum computation, and readout of the QECC qubits. A second line of the array (also referred to as the "shuttle line" of the array) allows entanglement operations to be performed between any of the spin qubits via shuttling.

[0050] In this disclosure, the L1 logical qubits are encoded by QECC in the form of a low-distance (“small”) surface code, such as Surface-17. The placement of qubits in the first line of a 2×N array minimizes the depth of the code's corresponding syndrome extraction circuit as it is scheduled for the array. Optimization techniques are applied to determine placements that facilitate shuttling of one or more of the multiple spin qubits in the array (e.g., by minimizing the errors associated with shuttling). For example, one or more numerical tools based on simulated annealing and the Metropolis algorithm can be applied to determine the placements. Simulation results demonstrate that a full cycle of the Surface-17 code can be scheduled for a 2×N array using a total of eight steps (a circuit depth of eight), which is just two rounds more than the optimal depth of six when qubits are laid out on a square lattice.

[0051] In a further aspect, the proposed architecture includes multiple bilinear arrays. A controller is configured to control the shuttling of multiple qubits in each array (i.e., implement a QECC that encodes L1 logical qubits) and selectively couple each pair of first L1 logical qubits in a first bilinear array to a second L1 logical qubit in a second bilinear array. L1 logical qubit coupling operations can also be enabled by other coupling mechanisms based on long-range interaction-based transport of information encoded by the first L1 qubit to the second L1 qubit. Thus, second-level (L2) logical qubits can be constructed by controlling and coupling L1 logical qubits.

[0052] An exemplary coupling mechanism includes a quantum transport structure connecting the arrays, such that coupling of the L1 logical qubit occurs through coherent transport of one or more spin qubits between each interconnected array of the plurality. In one example, each array in the architecture is connected to at least one other array through a separate shuttling array of quantum dots. In this way, shuttling of the underlying spin qubit is possible between pairs of interconnected 2×N arrays. In other examples, the coupling mechanism may include quantum transport arrays in alternative physical configurations, such as patches or buses of quantum dots, and / or one or more other coupling devices (e.g., superconducting couplers).

[0053] The controller performs fault-tolerant quantum processing operations on sets of the L1 logical qubits in the multiple bilinear arrays. The ability to perform any universal set of quantum operations on the L1 logical qubits allows these logical qubits to be used as underlying qubits to which further error correction methods can be applied.

[0054] In one implementation, a first QECC is applied to each 2×N array to reduce the error rate of the spin qubits (e.g., about 10 -4) to a lower error rate for the corresponding L1 logical qubit. For example, evaluations using logical CNOT gates have shown that the error rate for an L1 logical qubit is approximately 10 -5 We demonstrate the ability to achieve an error rate of 10. A second QECC is then applied to encode the collective state of the set of L1 logical qubits as corresponding L2 logical qubits. The L2 logical qubits have a further reduced error rate (e.g., 10) compared to the lower error rate of the L1 logical qubits. -15 approaching the desired value of

[0055] For example, by choosing the number of L1 logic qubits in the set M > 1, the distance of the second level code can be extended to achieve arbitrarily well-protected (L2 logic) qubits. Thus, the formation of L2 logic qubits according to the proposed architecture provides a solution to the lack of scalability of a single 2 × N array for achieving improved quantum error correction. The total number of qubits utilized for error correction can be increased by increasing the number of L1 qubits M while maintaining a fixed size N of the underlying bilinear array.

[0056] In at least this way, the proposed architecture advantageously facilitates implementing fault-tolerant quantum processing by enabling a scalable, practical, and universal approach to error correction across two levels of logical qubits.

[0057] quantum processor 1A illustrates a quantum processor 100 including at least one bilinear array, such as multiple arrays 102a, 102b. Qubits 101 (filled) are spin qubits realized within corresponding quantum dots 103 (filled and unfilled circles) of arrays 102a, 102b. The qubits of processor 100 are digital qubits in that each represents information in digital form, such as electron or nuclear spin, or superconducting qubits using Josephson junctions. The digital qubits of each array 102a, 102b may have a specific functional role, such as a data qubit or an auxiliary qubit in the QECC implemented by processor 100.

[0058] Quantum processor 100 also includes a controller 110 configured to control the coherent transport (referred to as "shuttling") of one or more of the qubits held in each of arrays 102a, 102b. Shuttling is controlled by controller 110 to implement a QECC in at least one of arrays 102a, 102b that encodes the collective state of the spin qubits of the respective array as a corresponding first-level (L1) logical qubit. In this sense, controller 110 applies a first error correction method, which is the formation of a QECC on each of arrays 102a, 102b and the generation of L1 qubits. In some embodiments, the QECC is a surface code that reduces the error rate of the physical spin qubits to a relatively low error rate for each L1 logical qubit of the respective array 102a, 102b.

[0059] Each array 102a, 102b is configured to hold multiple qubits within a corresponding quantum dot 103. That is, each quantum dot 103 may or may not hold a qubit at any given time. The "holding" of each qubit by the array refers to the localization of a physical qubit (e.g., an electron) at a location (or "address") of the array. For example, a qubit 101 may be realized as the spin state of an electron held by a quantum dot 103.

[0060] FIG. 1B illustrates an exemplary bilinear array 102 implemented as arrays 102a, 102b in the exemplary processor 100 of FIG. 1A. In other examples, the processor 100 may be configured with a single array or with any positive real number of arrays. The arrays 102 are configured as two lines of N quantum dots each, collectively referred to as a "2×N" array. Each single 2×N array 102 is configured with a first (bottom) line 105 for holding up to N spin qubits 101 and a second (top) line 107 for enabling shuttling of the spin qubits 101 within the array 102. That is, in such an embodiment, shuttling of the spin qubits occurs between the first and second lines of the bilinear array 102. In other embodiments, the shuttling line may be implemented as the first (bottom) line, with the qubits held on the second (top) line. Quantum dots 103 containing spin qubits 103b are depicted in the figure as shaded rounded squares, while empty quantum dots 103a are depicted as unfilled rounded squares.

[0061] In the described embodiment, the 2×N array 102 includes a set of SiMOS quantum dots. In one implementation, the electron spin of each SiMOS quantum dot is confined to the interface between silicon and SiO2 within the quantum dot. SiMOS quantum dots offer advantages for quantum computing, including long coherence times, the ability to be controlled to perform quantum logic operations, and are scalable. SiMOS quantum dots also have long-range qubit interactions via qubit shuttling, as discussed below.

[0062] 1A and 1B illustrate the geometry of the 2×N array 102 in terms of abstraction in two dimensions (i.e., as a simple double line). It will be apparent that in an actual implementation of the processor 100, the array will be fabricated with a particular fanout according to a three-dimensional layout. For example, in one implementation, the gates may be densely packed along an arrangement of one-dimensional channels that support the electrostatic quantum dots, but may be contacted by a three-dimensional metal layer with a predetermined pitch between the interconnects. Furthermore, the controller 110 may be configured according to any one or more possible layouts for multiple arrays, including a layout in which the controller 110 is physically separated into two or more sub-controllers or portions of readout and / or control electronics, each controlling a predetermined group of arrays from the multiple arrays (but collectively operating as a single logical controller for the processor).

[0063] Coherent transport of spin qubits High-fidelity coherent transport of electron spin qubits between quantum dots (termed "shuttle" of the spin qubit) has been demonstrated in isotopically enriched silicon (see Yoneda [4]). In a double quantum dot system, a single electron spin can be coherently transported between a pair of metal-oxide semiconductor (MOS) quantum dots.

[0064] Figure 2A illustrates a cross-sectional schematic diagram of a qubit device circuit 200 of Yoneda [4] configured to achieve coherent spin transfer between corresponding quantum dot sites. A single electron is loaded into quantum dot site A and manipulated by gate voltage pulses applied to aluminum metal gates A and B. The single electron is transferred between site A and site B by biasing the voltage applied to the surface gate electrode.

[0065] The gate voltage is swept along the detuning axis ε to vary the energy difference between states localized at individual sites. Figure 2B illustrates the stability diagram 210 of charge transfer from Yoneda [4]. The charge configuration within the dot array is mapped through the SET current, and within the plotted area there are two and one charge transition lines for sites A and B, respectively. The arrow defines the gate voltage axis used for qubit transport ε. As ε increases, the site where the electron resides changes from A to B. The inter-dot transition (ε = 0) is marked by a circle. Spin initialization and readout are performed in diamond using spin-selective tunneling from site A to the reservoir in combination with charge detection.

[0066] Spin polarization can be transported between sites with high fidelity. Spin-flip tunneling from site A to site B (e.g., due to spin-orbit fields generated by electron transfer or small site differences in spin quantization) is avoided by increasing the tunnel coupling above the Zeeman energy (approximately 28 GHz). Large tunnel coupling also suppresses state leakage due to nonadiabatic tunneling.

[0067] Evaluation results in Yoneda [4] indicate that the transfer process can be viewed as a unitary phase rotation gate with an average gate fidelity of (99.36 ± 0.05)%. The physical mechanisms expected to limit transfer fidelity in longer chains reside primarily in the evaluated double-dot system. Extrapolating the observed coherence loss p of about 2% for transfer between adjacent sites corresponds to spin transfer across about 50 sites, or a distance of about 2 μm (assuming a 40 nm site spacing), before phase coherence decays to 1 / e. For example, if only spin polarization is required for qubit readout, electrons can be transported across 2500 sites (or about 100 μm) before the polarization decays to 1 / e in the spin-up case.

[0068] Furthermore, the results illustrate that the qubit frequency is best matched with the small spin dependence in the inter-dot tunnel coupling due to spin-orbit interaction. Furthermore, a detuning spot occurs approximately near ε = −7 mV, where the qubit frequency is first-order insensitive to detuning variations due to charge noise as a result of competition between the Stark shift and tunneling hybridization. Further techniques for coherent transport of spin qubits are described in International Patent Publication No. PCT / AU2021 / 050869, the contents of which are incorporated herein by reference. Despite this, qubit shuttling can be completed within nanoseconds, which is several orders of magnitude faster than the qubit dephasing time. This offers advantages for facilitating coherent electron shuttling in fault-tolerant quantum computing architectures utilizing 2 × N arrays such as those described herein.

[0069] Quantum error correction in a 2×N array Quantum processing architectures based on linear arrays of electron spin qubits, such as those formed by silicon metal oxide semiconductor (SiMOS) quantum dots, advantageously have long coherence times and can therefore be controlled to perform desired quantum logic operations. Linear structures also facilitate the ability to exploit long-range qubit interactions for qubit shuttling (i.e., coherent transport of spin qubits through the array), which can be achieved using densely packed gate layout configurations.

[0070] However, implementing quantum error correction for these linear architectures is challenging due to the constraints imposed on qubit geometry. This disclosure provides techniques for correcting errors in quantum processing by applying coherent qubit transport operations, as discussed above, with the aim of converting QECCs to the constrained geometry of 2×N arrays.

[0071] Error correction using first-level logic qubits 3A illustrates a method 300 for enabling quantum error correction on a quantum processing device, such as a quantum processor, according to the architecture described herein. In step 302, a QECC is determined to apply to each of one or more bilinear arrays of quantum dots in the device, each array configured to hold a plurality of spin qubits. Each array is configured as a 2×N array with N spin qubits. The QECC is a surface code with a distance d, such as Surface-17 (see Tomita [5]).

[0072] In step 304, the spin qubits in each 2×N array of the device are arranged according to the QECC such that the collective state of a subset of the spin qubits forms a first-level (L1) logical qubit protected by the QECC. In step 306, a sequence of one or more entanglement operations is determined for each pair of the plurality of spin qubits in each 2×N array. The qubit arrangement and entanglement sequence determination (also referred to as "scheduling") enables the execution of a syndrome extraction circuit in the geometry of the 2×N array (or "module"), as performed in step 308. The sequence of entanglement operations involves the coherent transport of one or more of the plurality of spin qubits in each 2×N array.

[0073] In step 310, the syndromes resulting from execution of the extraction circuit are passed through a decoder that outputs a recovery operator. This operator is then applied to the code, restoring the code to code space (i.e., step 312). In some embodiments, the steps of method 300 are performed entirely by a quantum processing device. In other embodiments, at least the decoding step 310 and the recovery step 312 are performed by a classical processing device. For example, the classical processing device may be configured to instruct the quantum processing device to generate the syndromes and to perform the decoding and recovery in response to transmission of the generated syndromes from the quantum computing device to the classical processing device.

[0074] Various embodiments of quantum processor 100 that implement method 300 for quantum error correction using L1 logical qubits are described below.

[0075] Surface Code A surface code is a type of topological QECC implemented on a 2D planar qubit layout with nearest-neighbor interactions. The surface code encodes a single logical qubit into several physical qubits as determined by the code distance d and the desired layout. A first-level QECC is applied to encode the collective state of the spin qubits 101 of the 2×N array 102 as a corresponding first-level (L1) logical qubit. In one example, the QECC determined in step 302 is a surface code such as the Surface-17 code. Surface-17 is a distance d=3 QECC requiring N=17 physical qubits, as shown in FIGS. 1A and 1B.

[0076] FIG. 4A illustrates a 2D abstraction of an array 102 in which the Surface-17 code is implemented, with nine data qubits (labeled 0 through 8) storing the logical information of the code and eight auxiliary qubits (labeled 9 through 16) performing the projection measurements required for error correction.

[0077] Surface-17 stores one logical qubit that can control the logical X(Z) operator at the physical level by performing the X(Z) Pauli operation on a Pauli X column (Pauli Z row) operation. For example, the operation

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[0078] The code state of the QECC is defined as the +1 eigenstate of the stabilizer group.

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[0079] Information about the parity of the error that occurred can be obtained by measuring the eigenvalues ​​of the stabilizer: an eigenvalue of -1 indicates the presence of odd parity of the error acting on the support of the stabilizer, i.e., on the qubit on which the stabilizer acts non-trivially (e.g.,

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[0080] To illustrate this, let ε=Z0 (phase inversion on qubit 0, identity operation on the remaining qubits). Qubit 0 is

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[0081] Performing quantum error correction of method 300 involves measuring the stabilizer of the QECC to obtain the syndrome. However, the data qubits cannot be measured directly on the stabilizer support because this would decoherence the stored quantum information. Instead, the measurements are projected onto the ancillary qubits, which then undergo readout. The sequence of operations required to extract the code's stabilizer information via the ancillary qubits is known as the syndrome extraction circuit (SEC).

[0082] Gate scheduling and qubit placement To perform SEC, the operations of a surface code, such as Surface-17, are mapped to a 2×N array. Initially, the qubits of the QECC are formed in the first line 107 of the array, such as the arrangement shown in FIG. 4A. The qubits of Surface-17 are laid out in the first line 107 of the array 102, and the second line 105 is left empty to be used to shuttling qubits and to perform any nonlocal two-qubit gates. Scheduling refers to determining the sequence of gates to execute to couple the spin qubits through each shuttling operation of the array 102.

[0083] The ancillary qubits 108 are initialized by tunneling electrons from reservoirs located around the array 102, close to the quantum dots. If desired, nearest-neighbor and shuttling two-qubit gates can be performed one at a time by using a second line 105 for shuttling.

[0084] Due to the geometrically constrained architecture of a 2 × N array, few operations can be performed in parallel. For example, the shuttling paths required to implement the first two CNOT gates of a SEC (e.g., CNOT|0〉|10〉 and CNOT|11〉|1〉 for the exemplary SEC 500 of FIG. 5 ) intersect within the array and therefore must be executed in separate rounds, one at a time. The total number of separate rounds required to execute a circuit is known as the circuit depth. The longer the circuit takes to execute, the longer the spin qubits are left idle and exposed to undesirable decoherence effects in the environment.

[0085] This leads to an accumulation of errors that impairs the error correction capabilities of the scheme. In the standard layout of Surface-17 qubits (2D arrangement 400 shown in Figure 4B), the circuit depth is 6. In the naive arrangement of Figure 4A, the circuit depth is 26, which is the worst possible depth of the circuit (i.e., all operations are performed serially).

[0086] In method 300, qubits are instead selectively arranged to facilitate shuttling one or more of the plurality of spin qubits to perform error correction in accordance with QECC. That is, in the illustrated example, rearrangement of qubits in first line 107 of array 102 from their initial arrangement is performed in a manner that allows multiple two-qubit gates to be implemented simultaneously (i.e., such that at least some of the entanglement gate operations can be performed in parallel during SEC) without crossing shuttling paths.

[0087] In the described embodiment, the placement of qubits in the first line 107 of array 102 is determined to minimize the depth of the SEC, or to provide an approximation to this minimum depth. Qubit placements that minimize circuit depth can be approximated using techniques from simulated annealing and Metropolis sampling algorithms.

[0088] Let σ represent a particular qubit placement in the first line 107 of array 102, and define E(σ) as the objective (energy) function to be minimized. In this case, this is the circuit depth E(σ) = Circuit Depth(σ). Pseudocode for an algorithm for placing qubits to approximate this minimum depth is provided below. [Table 1]

[0089] At each step of the algorithm (line 3), two adjacent qubits

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[0090] The algorithm first calculates the temperature T = T high We start sampling at . This means that initially there is a reasonable chance of accepting a suboptimal solution (i.e., a higher-energy qubit configuration). This prevents the algorithm from getting stuck in a local minimum metastable state. Slowly, the temperature decreases, and the probability of accepting a worse configuration also decreases. Eventually, the temperature tends toward 0, and the algorithm settles on a near-optimal configuration that minimizes the energy function.

[0091] There may be more than one possible qubit configuration that minimizes the depth of the circuit. In some implementations, step 304 involves selecting a qubit configuration for performing syndrome extraction as the configuration with the smallest number of shuttling two-qubit gates, since these are expected to be the worst-performing gates of the circuit. That is, once the desired configuration is determined in step 304, a sequence of two-gate entanglement operations is determined in step 306.

[0092] The desired qubit placement for Surface-17, as obtained by minimizing over the depth and then over the total number of shuttled two-qubit gates, is shown in Figure 6. In some embodiments, the desired (i.e., optimal or near-optimal) placement is already known to processor 100, so that step 304 involves laying out the qubits according to the desired placement. In some embodiments, the sequence of (two-gate or other) entanglement operations is determined prior to or concurrently with the determination of the desired placement (i.e., by performing step 306 before or in conjunction with step 304).

[0093] Placement Optimization For the Surface-17 code, simulated annealing is performed starting from the naive qubit configuration shown in Figure 4A. The minimum circuit depth reached is 8, which is two rounds away from the optimal depth. As we discuss below, this depth is sufficient to achieve adequate error correction performance with a 2 × N module.

[0094] Among all possible qubit configurations that minimize the circuit depth, the configurations with the minimum number of shuttling two-qubit gates are selected, as these are expected to be the worst-performing gates in the circuit. The optimal qubit placement for Surface-17 is obtained by minimizing the depth and then minimizing the total number of shuttled two-qubit gates, as shown in Figure 5.

[0095] Syndrome Extraction The syndrome of the code is determined by running SEC in step 308. FIG. 5 illustrates an exemplary syndrome extraction circuit 500 for the Surface-17 QECC. Quantum error correction is achieved over a series of one or more cycles, the total number of cycles being given by the circuit depth of the constellation. To complete one full quantum error correction cycle, the syndrome is extracted and then decoded to form an output recovery operator for projecting the qubit into code space.

[0096] In the illustrated example, device 100 is configured to perform cycles of error correction on a 2×N array of L1 logical qubits (represented by QECCs), (i) initializing one or more ancillary qubits of the QECCs in the array according to the arrangement determined in step 304, (ii) executing one or more two-qubit entanglement gates, as determined in step 306, each gate entangling one or more pairs of spin qubits of the QECCs, and (iii) measuring the ancillary qubits.

[0097] Figure 6 illustrates one cycle of error correction rounds of the Surface-17 code using the desired arrangement of qubits, with each circuit operation explicitly shown on a 2xN array. The total number of rounds, i.e., the circuit depth, is 8 (2 away from the optimum achieved in an unconstrained 2D architecture). The initial and final rounds involve preparation and measurement of an auxiliary qubit, respectively.

[0098] In the first round, ancillary qubits 9-16 are initialized in the basis of each of the stabilizers they are measuring. For example, auxiliary qubit 11 is initialized in the basis of the X-type stabilizer

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[0099] Intermediate rounds (2-7) involve entanglement operations between ancillary qubits and data qubits. That is, an entangled qubit includes a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC. Horizontal double arrows represent nearest-neighbor two-qubit gates, and arrows through empty holes in the top row of the array represent shuttled two-qubit gates. Referring to Figure 3B, the lines indicate pairs of entangled qubits. That is, ancillary qubit 11 is entangled with data qubits 0, 1, 3, and 4.

[0100] The final round of the circuit (8) consists of reading out the state of the ancillary qubit in the appropriate basis. For ancillary qubit 11, this is a measurement in the X basis. The observed readings of the ancillary qubits (±1) are assumed to correspond to the measurements of the corresponding stabilizers.

[0101] Figure 3B shows the SEC of a particular QECC, C. 2×N 3 illustrates a generalized process for performing step 308 to achieve the implementation of (C), where the scheduling of constituent operations is optimized in a 2×N array using the method of steps 304 and 306. For example, SEC for Surface-17 2×N (C) is shown in Figure 6 as discussed above. In step 322, a pair of qubits to entangle is selected, the entangled pair of qubits including a data qubit associated with a stabilizer of the QECC and a corresponding ancillary qubit of the QECC. The pair of qubits is selected according to the gate scheduling and placement of steps 306 and 304.

[0102] The entanglement operation depends on the relative locality of the qubits within array 102. In step 323, a check is performed to determine whether the qubits are neighboring qubits. If so, the qubits to be entangled are already in neighboring dots, and entangling the qubits involves causing a direct local interaction between the qubits without shuttling either of the qubits. Otherwise, in step 324, entangling the pair of spin qubits involves shuttling a selected spin qubit of the pair of spin qubits from a first line of the array through a second line of the array, aligning the selected spin qubit with the other spin qubit, performing a two-qubit gate, and then shuttling at least the selected spin qubit back to the first line of the array.

[0103] The entanglement operation is completed, forming a two-qubit gate between the selected pair of spin qubits, in step 328. Repeating the process for at least one non-adjacent pair of spin qubits provides coherent transport of spin qubits within the array as a means by which quantum information is relayed between remotely located locations within the array.

[0104] Decryption and Recovery Referring to FIG. 3A, following the syndrome extraction process in step 308, decoding is performed in step 310 to obtain the code SEC 2×N The syndrome in (C) is mapped to the recovery operator D:S→R. The recovery operator is the code

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[0105] Syndrome SEC 2×N The recovery operator determined for (C) may vary depending on the decoding process.

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[0106] The decoder implementation is related to the number of stabilizer generators in the QECC. For example, the Surface-17 has four X-type stabilizers,

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[0107] In one example, due to the small number of stabilizers in the code, decoding is performed via a decoder map that explicitly specifies D:S → R. That is, the decoder map associates a recovery operator with each possible observed X syndrome (top) and Z syndrome (bottom), as determined individually by finding the optimal correction operator for each observed syndrome. This is known as exact maximum likelihood decoding. For example, the observed syndromes

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[0108] In step 312, a recovery operator ZX is applied to the code, restoring it to code space. In some embodiments, the syndrome decoding operation is performed by a classical computing processor device (e.g., using the binary data as +1 or −1) and using a classical algorithm. The classical processor may be configured to receive information (e.g., syndrome values) from quantum processor 100 via electrical connections (e.g., hardwiring). In such embodiments, the classical processor acts as a decoding device that communicates with quantum processor 100 and associated components. This is advantageous in that decoding can be performed off-chip relative to quantum processor 100 while still achieving computations that are fast enough to avoid decoherence of spin qubits. The table-based decoder described above runs in constant time O(1) and is therefore practical to implement using current classical technology.

[0109] Fault-tolerant circuit extraction The error correction of a code with distance d is such that a single error on any component of the circuit causes at most 100 qubits of the code to be corrected.

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[0110] For the example code described here with distance d=3, fault tolerance is such that a single error event in SEC results in at most one output error.

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[0111] An example of an error that damages a stored logical qubit is ε′=Z0Z1. This error is

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[0112] Fault tolerance is achieved by ordering two-qubit entanglement gates in a specific way. In the case of Surface-17, the two-qubit gates of SEC500 are ordered to propagate a single-qubit error to a two-qubit error, as depicted in Figure 5. This is an unavoidable property of two-qubit gates, but only one of the two propagated errors is aligned along the direction of the logical operator. Therefore, the effective number of directionally aligned errors that can cause a logical failure is one, satisfying fault tolerance. Because optimization of operations in a 2×N array schedules operations in different rounds without changing their relative order, fault tolerance is preserved for one-qubit and two-qubit gate errors when running SEC on a 2×N array.

[0113] Fault tolerance against measurement errors requires the ability to detect if one of the ancillary qubits has been read incorrectly; for example, if the qubit reads -1 instead of the correct +1. The measurement error, if it is of sufficiently low magnitude, can be tolerated by repeating the stabilizer measurement. This iteration of the circuit execution ensures that the first SEC produces a trivial syndrome (i.e., all stabilizers give a +1 reading,

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[0114] The final output of SEC for a code, after considering fault tolerance, is the syndrome of the code, i.e., the list of stabilizers that return a measurement result of -1,

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[0115] Other quantum error-correcting codes In other embodiments, quantum error correction is performed using a QECC other than the Surface-17 code. For example, the processor 100 may apply a QECC such as a Shor code (e.g., Shor6X2Z and Shor6Z2X, see Debroy [6]), a Bacon-Shor-13 code (see Bacon [7]), or a XZZX-17 surface code (see Bonilla Ataides [8]). All of these codes have a distance d=3 and require 20 or fewer physical qubits to implement. The characteristics of the syndrome extraction circuit for the above QECC, when implemented in a 2×N array, are given as follows: [Table 2]

[0116] "Qubits" is the total number of physical spin qubits required by each scheme, "Circuit Depth" is the depth of the syndrome extraction circuit when implemented in a bilinear array, "2-qubit Gates" is the number of 2-qubit gates used by the circuit, and "Shuttling" is the number of shuttled 2-qubit gates required by the circuit.

[0117] The SECs in these codes are fault-tolerant, requiring only the measurement of an ancillary qubit at the end of an error correction round. This reduces the demands on measurements using spin qubits, which are slow operations. In described embodiments, the error correction circuitry is predetermined and remains fixed throughout the entire quantum error correction cycle. In some embodiments, the execution of different parts of the circuitry is conditional on the result of the measurement of the flag qubit.

[0118] Error correction performance evaluation Monte Carlo simulations are performed to evaluate the failure rate of L1 logic qubits stored in a 2×N array of processor 100 according to the method 300 proposed above. FIG. 7A illustrates a simulation model 700 used to evaluate the performance of error correction in a 2×N array of SiMOS quantum dots. First, a QECC C is selected and its syndrome extraction circuit is decomposed to fit the 2×N array in an optimal way (using the method described above). Errors are modeled during every operation of the circuit according to an externally injected error model E.

[0119] Syndrome extraction circuit SEC 2×N (C) is repeated, providing that the measurement result of the ancillary qubit is nontrivial, to account for measurement error. The final output of the circuit is a syndrome S, which is passed through a decoder D to form a recovery operator R. The latter is applied to the code, and the recovered code state is checked to determine whether it registers a logic failure (i.e., a failure on the code's stored logic qubit). Various aspects of the evaluation are described below.

[0120] Error Modeling Error events are modeled during qubit initialization, single qubit gates, two qubit gates, shuttling, measurement, and idling. The native operations used in the syndrome extraction circuit and the associated errors modeled for each are listed below. [Table 3]

[0121] An "operation" is the native operation used in the extraction circuit. An "error rate" is the probability that an error occurs in that operation during any given round. These error rates are given as multiples of the two-qubit error rate p. A "structure" is the type of error that is modeled after each operation, provided that an error occurs first.

[0122] 1. Two-qubit gates: CNOT and CZ The CZ gate is native to the physical architecture and is implemented directly by altering the exchange interaction. Figure 7B illustrates a circuit diagram 710 representing an implementation of a CNOT gate based on a combination of a CZ gate and two Hadamard gates.

[0123] Error correction circuits primarily use CNOT gates, and occasionally CZ gates. The fidelity of CNOT and CZ gates is comparable because they can be related to each other by two Hadamard gates, which have an order of magnitude higher fidelity than two-qubit gates. Therefore, we define the typical two-qubit error rate as p 2q If we define it as follows:

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[0124] The dominant error traveling through the CZ gate is ZZ. The relevant error channel used in the simulation is: ε CZ (ρ)=(1-p)II+p(ZZρZZ)

[0125] The CZ gate is CZ The Hadamard gate can be executed in ~0.1 μs. H The time required to execute a CNOT gate is dominated by the time required to execute a Hadamard gate, which takes ~1 μs, t CNOT ~2μs.

[0126] 2. Single-qubit gates The discussion focuses on the Hadamard gate H because it is the primary single-qubit gate used in circuits. The fidelity of this gate is approximately 10 times greater than that of two-qubit gates.

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[0127] For single-qubit gates, a depolarized Pauli channel is used, and X, Y, and Z errors occur at the same rate.

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[0128] The time required to perform a single qubit gate is t 1q ~1μs.

[0129] 3. Initialization and measurement In the evaluation example, the fidelity of the initialization and measurement are comparable because they are linked processes, and each is approximately equal to the fidelity of a two-qubit gate. Let the error rates of the initialization and measurement be p i and p m Let's say. p i =p m =p(3)

[0130] Both initialization and measurement are modeled as errors in assignment. For example, for preparation of state |0〉 (or |+〉), probability p i Similarly, if the measurement result is expected to be +1 (or -1), the measurement result output will be generated with probability p m is -1 (or +1).

[0131] It is assumed that initialization involves moving qubits from reservoirs located on the left side of the array, and measurement involves moving qubits out of the array towards the right. Under this assumption, the effective time for initialization and measurement (i.e., how long other qubits are idle) is equal to the total time required to shuttling qubits in and out of the array. For a code requiring a total of N qubits, this time is: t i =t m -(N+1)t d ~2ns=0.002μs

[0132] For the evaluated code, N~20 is used, where t d ~0.1 ns is the time required to shuttling on one dot, and this assumes that the actual measurement of the auxiliary qubit, which takes much longer, can be performed separately and is not needed until the end of the circuit.

[0133] In other instances, knowledge of an auxiliary measurement result may be required before proceeding with the quantum error correction cycle (e.g., for flag-based error correction), in which case the initialization time remains the same, but the measurement time is

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[0134] 4. Shuttling This evaluation describes two possible models of shuttling across multiple dots. In the first model, the dominant error arises from the one-time cost required to move the spin, which is then largely independent of the number of dots traversed. In the second model, the error accumulates exponentially after each dot jump. d Let ∑ be the fidelity of shuttling across a single dot, then the error rates associated with moving across n dots in the exponential shuttling model and the one-time cost model are, respectively:

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[0135] In either shuttling model, the qubit being shuttled experiences primarily dephasing errors. The noise bias is quantified by the following coefficient:

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[0136] The shuttling time per dot is t d = 0.1 ns. The time for a shuttled two-qubit gate across n dots is equal to the shuttling time plus the time required to perform the two-qubit gate. Because shuttling is several orders of magnitude faster than the two-qubit gate, the time for a shuttled two-qubit gate is t 2q is given largely by

[0137] 5. Idling The fidelity of an idle qubit is modeled as an exponential decay with a lifetime constant given by the computation time T2. IdlDefine (t) as the probability of an error on an idle qubit over a period of t.

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[0138] T2 can be as long as 2 ms, achieved experimentally by continuously and resonantly driving a spin qubit with an external field (see Hansen [9]). Although T2 is expected to increase in the future, T2 = 2 ms is taken as a current estimate of what can be achieved with a spin qubit.

[0139] A typical error rate is assigned to idling as a multiple of the two-qubit error rate p. For a conservative estimate, the idling error rate during the longest round of the syndrome extraction circuit is used. This is the round in which the CNOT gate is implemented (the longest two-qubit gate used in the circuit), and the time is t CNOT First, shuttling is so fast (0.1 ns per dot) that it does not affect the two-qubit gate time, and shuttling hardly occurs over distances greater than 6 dots. Second, the time for the longest round is about 2 μs, whether the two-qubit gate is shut or not, and the associated idling error rate is p Idl (2μs)=1-e -2μs / 2000μs ∼p / 10. This general formula is used to model the idling error on all qubits that do not receive an operation during each round of the extraction circuit.

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[0140] The idling noise is also dominated by dephasing. The appropriate bias factor for our physical implementation of the spin qubit is η = 1000, the same error channel as in equation (6).

[0141] Circuit Noise Simulation The error model is used to simulate noise in all operations of the error correction circuit, including during idle time. 2×N (C) is performed using an error model according to the following steps: (i) Perform the circuit operations. (ii) Propagate the current error state through the operation (e.g., through a gate). (iii) Introduce new errors associated with the operation as specified by the error model and group them with the propagated errors.

[0142] The way in which Pauli errors propagate through the gates of a circuit depends on the explicit quantum operations the gates perform. Figure 7C illustrates the propagation of Pauli errors in a CNOT gate according to one exemplary configuration of gate 720. A Pauli Y error can be decomposed into a Pauli X error and a Pauli Z error, which can propagate separately.

[0143] Knowledge of how errors are introduced and propagated through the syndrome extraction circuit completes a full description of circuit noise simulation. These errors propagate through the qubits of the code, and it is the job of the decoder to find a suitable recovery operator based on the extracted syndrome (e.g., as described above for a look-up decoder). A check is performed to determine whether physical errors have accumulated and damaged the stored logical qubits in the code. An exemplary process for performing this type of logic state diagnosis is described below.

[0144] Logic Status Diagnostics The logic state of the QECC is restored

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[0145] The total number of data qubits in the code is n=9 for Surface-17. A recovery operator R is applied to the error state of the code, resulting in a recovered state. The recovery operator is

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[0146] Next, the following calculations are performed:

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[0147] For example, the code

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[0148] Performance evaluation The performance of error correction in a 2×N array is evaluated for the five QECCs described above, each applied to protect an L1 logical qubit stored in a 2×N module. The error model described above applies when all error sources are given as multiples of a single parameter p that quantifies the strength of the noise.

[0149] The simulation takes QECC and SEC as input. 2×N (C) and its associated syndrome extraction circuit in a 2 × N array, and produces as output a "1" if the stored logical qubit fails or a "0" if it remains intact. The logical failure rate P of a stored qubit is N m It is evaluated by running a simulation and observing F logic failures. As given by Monte Carlo estimation, there is uncertainty in the estimate (standard deviation) σP.

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[0150] Roughly speaking, the QECC in a 2×N module is the encoded logical qubits in the module.

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[0151] Therefore, p pth An error correction scheme with a pseudo-threshold of p pth We successfully protect a qubit (i.e., reduce the error rate of the qubit from its current value) only if the noise on the qubit is less than p pth Above , encoding qubits with QECC becomes harmful rather than beneficial, causing the qubits to fail at a higher rate than if they were left bare (unencoded). Effective error correction therefore typically exhibits a high spurious threshold, so that they can provide protection for a larger number of noisy qubits.

[0152] Figure 8 shows the performance (i.e., logical failure rate) of the QECC for an L1 logical qubit encoded in a 2xN module using five different QECCs and a single-off error model for shuttling. The pseudo-threshold is the ratio of the failure rate of the encoded qubit to that of the unencoded bare physical qubit.

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[0153] The intersections between the logic failure curves and the dashed lines for different codes are the pseudo thresholds p for each code. pth Characterize the physical error rate p <p pth If , the logical failure rate of a qubit encoded with that code is less than the logical failure rate of a bare physical qubit that is not encoded. The table below shows the exact values ​​of the pseudo-threshold for the different codes used and for each of the two shuttling error models evaluated (i.e., single-off and exponential accumulation of errors). [Table 4]

[0154] The observed linear trend and the parallelism of the lines in Figure 8 can be explained as follows: At low p-values, sampling is (p~10 -4 ~10 -3 ) (see the x-axis values ​​in Figure 5), and very few errors are introduced into the code per simulation run. Therefore, logic failures are actually due to the lowest weight error configurations that cannot be corrected by the underlying code. Since all codes are at distance d=3, all weights

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[0155] Therefore, the next most likely number of errors that can lead to failure is a double error event. When two errors occur in succession, a logical failure can occur. Therefore, the logical failure rate is dominated by errors of weight 2 at the low sampled p values. Since each error occurs with probability p, the logical failure rate caused by these double error events is given by:

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[0156] For a one-time shuttling error, the pseudo-threshold is p~O(10 -3 ) is as large as 4×10 -4 (Shor-6X2Z). The physical failure rate used in the error correction simulation is the 2-qubit gate error rate p=p (as shown above). 2q Therefore, p=10 -3 The pseudo-threshold of requires a two-qubit gate fidelity of 99.9% for error correction to be successful.

[0157] It is desirable to use QECC to significantly reduce the error rate of the stored logical qubits compared to unencoded qubits. -4 At this point, the error rate for most QECCs is approximately

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[0158] Another metric of interest is the ability of the code to preserve the noise bias at the logic level (the degree of "logic bias"). This ensures that the encoded L1 logic qubit can be used for further QEEC (discussed below). The tabulated results show the noise logic bias for each code, which is expressed as the rate of logical Z errors relative to the rate of logical X and Y errors:

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[0159] Based on these results, the technique proposed above provides a general framework for decomposing the error correction circuitry of any QECC so that it fits within the geometric constraints of a bilinear 2xN array of quantum dots. That is, if another code of interest arises in the future, it can be subjected to the methods presented above to analyze its error correction capabilities relative to other codes and evaluated according to the metrics in this section.

[0160] Fault-tolerant scalable quantum processing Scalable quantum error correction requires processing qubits with an error rate of about 10 to run useful quantum algorithms. -15 The approach described above protects multiple spin qubits as L1 logic qubits in a bilinear array. Fault tolerance is approximately 10 -3 This is achieved by performing an identity gate on the L1 logical qubits with a high pseudo-threshold of . However, achieving the desired error rate in first-level (L1) logical qubits is practically difficult because expanding the number of physical qubits N, as required to increase the distance of the QECC, increases the distance over which the qubits are shuttled, which reduces the protection provided by the error correction strategy.

[0161] It is desirable to utilize the encoding of L1 logical qubits in 2×N arrays performed according to the first-level QECC as described above as high-quality qubits in an architecture that provides fault tolerance while allowing scalability of error protection. The proposed technique provides scalable quantum error protection by connecting multiple 2×N arrays so that second-level qubit encoding can be implemented from any number M>1 of L1 logical qubits. The encoding applied to second-level (L2) logical qubits can be extended to achieve arbitrarily well-protected logical qubits. Described below is an approach to (i) combining multiple 2×N quantum dot arrays and (ii) using the combined array to implement a set of fault-tolerant quantum operations, thereby enabling the treatment of L1 qubits as “base qubits” to which further (second-level) error protection can be applied.

[0162] Combining multiple 2xN arrays 1C schematically illustrates a portion of quantum processor 100 having multiple bilinear arrays of quantum dots 102a, 102b, 102c, 102d arranged in a grid disposed between control circuitry portions 110a, 110b, 110c. Control circuitry portions 110a, 110b, 110c each include readout and control electronics that collectively constitute or form part of controller 110 of quantum processor 100. Controller 110 is configured to control operation of quantum processor 100 by selectively coupling at least a first L1 logic qubit of a first bilinear array to a second L1 logic qubit of a second bilinear array via a coherent coupling mechanism, where the coupling occurs by long-range interaction-based transport of information encoded by the first L1 qubit to the second L1 qubit. Based thereon, controller 110 is configured to perform one or more fault-tolerant quantum processing operations on the L1 logical qubits of the plurality of bilinear arrays 102a-102d.

[0163] In the illustrated embodiment, the coherent combining mechanism includes a quantum transport structure 150 configured to connect multiple bilinear arrays according to the architecture. Referring to FIG. 1c, multiple 2×N quantum dot arrays 102a, 102b, 102c, and 102d are connected by multiple shuttling arrays 150a-150j of the quantum transport structure 150. Each shuttling array 150a-150j includes one or more quantum dots arranged in a linear structure extending along a first dimension, either horizontally or vertically, relative to the orientation of the bilinear array. In the embodiment shown in FIG. 1c, horizontally oriented shuttling array sections 150a, 150b, 150c, 150d, 150g, 150h, 150i, and 150j connect directly to the ends of their respective bilinear arrays 102a, 102b, 102c, and 102d, while vertically oriented arrays 150e, 150e form intersections with the horizontal sections.

[0164] In the described embodiment, each of the shuttling arrays 150a-150j spans a single quantum dot in the second dimension, forming a 1×D array, as shown in FIG. 1C. That is, the first dimension D of the shuttling array section is scalable to connect the bilinear arrays 102a, 102b, 102c, 102d in a grid layout. In some embodiments, the shuttling arrays 150a-150j are configured with a second dimension greater than one (e.g., as a 2×D array, a 3×D array, etc.) to provide redundancy in the shuttling capability for transporting quantum bits between the respective bilinear arrays 102a, 102b, 102c, 102d.

[0165] Figure 1D illustrates an example layout of quantum processor 100 of Figure 1C, in which multiple bilinear arrays are organized according to the architecture depicted by Figure 1c. Bilinear arrays, such as array 102a, are connected in a grid by shuttling gate arrays vertically and horizontally. The sparse arrangement of the bilinear arrays allows for the scattering of readout and control electronics needed to implement integrated control of the arrays as L1 qubits.

[0166] The layout geometry depicted in Figure 1D is advantageous in that it allows the gates that store the quantum dots to have fan-out regions while also accommodating the placement of control and measurement electronics. For example, the gates can be densely packed along the one-dimensional channel defined by the shuttling array, yet remain in contact with the three-dimensional metal layer with a more relaxed pitch between interconnects.

[0167] As shown in FIG. 1D, each 2×17 bilinear array (e.g., 102a, 102b, etc.) is configured to implement a distance 17 surface code by coherently shuttling qubits across a shuttling line 107 to facilitate long-range two-qubit interactions. In the example of FIG. 1D, the qubits of each bilinear array are confined within an active silicon layer (nanowire) beneath multiple plunger gates. Multiple barrier gates are used to control the interactions between the qubits of the bilinear array as well as to assist the shuttling process. This allows each bilinear array to be operated as an L1 logical qubit as described herein.

[0168] The readout and control electronics are collectively configured to selectively couple a first L1 logical qubit and a second L1 logical qubit by coherently transporting one or more spin qubits between a first bilinear array (102a, 102b) and a second bilinear array (102c, 102d) connected to the first array. The selective coupling of the L1 logical qubits occurs by creating an entanglement operation between one or more of the spin qubits of each array of L1 logical qubits, as described below in the context of performing quantum processing operations on the L1 qubits.

[0169] Figures 1E and 1F illustrate means of qubit control and qubit coherent transport, respectively, for the quantum processor 100 of Figure 1D. Qubit control is achieved by applying an oscillating electromagnetic field 160 to rotate the qubit spin vector 161. Two-qubit coupling is achieved by applying pulses 162 to one or more barrier gates to bring the qubits into close proximity for exchange interaction. Referring to Figure 1F, the qubit array 102b of one L1 qubit can be shuttled to the shuttling line 107 of another L1 qubit 102a to execute a concatenated error-correcting code for the interacting logical L1 qubits and create an L2 logical qubit.

[0170] In other embodiments, quantum transport structure 150 can take different forms that can vary according to the layout of the bilinear array and / or other components of the quantum processor. For example, structure 150 can include one or more quantum buses or pipelines configured to physically connect one or more of the bilinear arrays of the processor. In some embodiments, structure 150 includes one or more coupling devices, such as superconducting couplers.

[0171] Fault-tolerant logic operations Utilizing the L1 logical qubits of each 2×N array as physical qubits requires the ability to universally manipulate the logical qubits. For example, for processor 100, this allows controller 110 to perform any quantum operation on each L1 logical qubit stored in arrays 102a, 102b, 102c, and 102d. The universal set of operations can be realized through a discrete set. g={P Z ,M Z ,H,T,CNOT} where P Z and M Z are preparation and measurement in the Z basis, H and T are single-qubit gates, and CNOT is a two-qubit entangled gate.

[0172] Described below is an approach for implementing these operations, which are similarly defined on physical spin qubits in silicon quantum dots on L1 logical qubits. The ability to achieve precise universal manipulation of L1 logical qubits allows processor 100 to treat L1 qubits as logical qubits, thereby enabling the implementation of second-level QECCs to encode collective states of M>1 sets of L1 logical qubits. In this way, approximately 10 of the L1 logical qubits can be manipulated. -4 ~10 -5 The lower error rate (for spin qubits) is about 10 of that of L2 logical qubits. -15This reduces the error rate to an even lower level of 0.5. This makes the L2 logical qubit a high-quality qubit with an error rate sufficient for practical quantum computing.

[0173] Certain quantum processing operations can be performed in a similar way across different QECCs and are called transversal operations: operations on logical qubits that can be realized as tensor products of operations on individual physical qubits in different codes.

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[0174] Initialization and measurement Encoding a logical state using a stabilizer code can be performed by initializing all data qubits to the appropriate basis and performing an entanglement operation prescribed by the code's stabilizer. However, instead of entangling the data onto ancillary qubits, with respect to the syndrome extraction circuit, the data is entangled onto the data qubits, thereby changing the state of the code to the required entangled logical state (within the +1 eigenspace of the stabilizer).

[0175] 9A and 9B respectively show the logic |0> for initializing each state of the Surface-17 QECC. L and logic |+> L Illustrated are fault-tolerant logic encoding circuits 900 and 910. Note that the entanglement operations in both circuits are performed between data qubits of code, since it is these qubits that encode the logical states used in quantum computation.

[0176] This type of initialization is general to all stabilizer codes. Z and preparation (initialization) P in the X basis X Note the similarity between | and |. The main difference is the initial preparation of the data qubits in either the |0> or |+> state. For any stabilizer code, measuring the state of the L1 logical qubit can be done transversally by measuring the state of each data qubit. Classical error correction can then be performed to identify the logical state with high probability. The logical measurement in the Z(X) basis, M Z (M X ) requires transversal measurements of data qubits in the Z(X) basis.

[0177] Single qubit gates: H and T The H (Hadamard) gate is transversal for some codes, such as the Stein code, but not for many others. To implement the H gate with other stabilizer codes, code transformation techniques such as braiding around lattice defects (see Fowler

[10] ) or lattice surgery (see Litinski

[11] ) can be applied. Such techniques are applicable to logical qubits formed by 2 × N arrays, using the methods discussed above to break down the circuit when necessary.

[0178] For Surface-17, the H gate is approximately a transversal. Applying the H gate to all physical qubits results in the correct logic state (the X and Z logical operators are swapped), but the code boundaries are switched. In some examples, processor 100 implements the gate by performing a shuttling procedure to rearrange the qubits in a 2×N array so that the boundary qubits restore their natural positions. Alternatively, controller 110 can be configured to track the switched boundaries for all ongoing operations.

[0179] One of the most common uses of H gates is to rotate between the X and Z bases (e.g., to prepare a |+> state, a |0> state may be prepared, followed by an H gate). If this is the intended use of H for a particular circuit performing the algorithm of interest, then a logical H gate is not required, as the logical states in each of the X and Z bases can be initialized and measured directly. In such an example, all that is needed is initialization and measurement in both bases, and an H gate at the physical level (see Figures 9A and 9B), which can be achieved with high fidelity using physical spin qubits.

[0180] For surface codes, logical T-gates can be achieved using magic state distillation, which involves using multiple faulty T-gates to produce a single high-quality "distilled" T-gate (see Gidney

[12] ). These distillation protocols require a large number of physical qubits to produce a single high-quality logical T-gate.

[0181] It will be appreciated that single-qubit gates at the logic level of code can be one of the most resource-intensive operations to implement in terms of the number of extra qubits they may require. However, single-qubit gates do not necessarily require the qubits to be of high quality. In fact, the noisiest operations, which set a limit (i.e., a pseudo-threshold) for qubit quality below which QECC can be successfully applied, are generally CNOT gates.

[0182] Two-qubit gate: logical CNOT The proposed architecture can implement logical CNOT gates (i.e., between pairs of L1 logical qubits) while maintaining a high pseudothreshold. The CNOT gate implementation is transversal to all codes whose X and Z stabilizers consist exclusively of X and Z operators, respectively (termed "CSS codes"), including Surface-17 codes.

[0183] 10A and 10B are a pair of circuit diagrams of a logical CNOT gate between two L1 qubits of coupled 2×N modules at the logical level 1000 and the physical level 1050, respectively. The logical qubit state encoded in one of the 2×N modules (the control) is

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[0184] Controller 110 is configured to combine first and second L1 logical qubits encoded in two separate 2×N arrays (e.g., 102a and 102c, or 102b and 102d). Combining a pair of L1 qubits involves performing an entanglement operation between the spin qubits in each array by transferring a spin qubit from one array of the pair to the other array of the pair and performing one or more entanglement operations between the transferred spin qubits.

[0185] FIG. 11 illustrates a method 1100 performed by controller 110 to combine (entangle) two logical qubits encoded in two separate 2×N arrays, such as to achieve a fault-tolerant CNOT gate between a control array of a plurality of bilinear arrays and a target array of a plurality of bilinear arrays.

[0186] In step 1102, qubits from the control array are shuttled via the shuttling array to a second line of empty dots in the target array. In step 1104, nearest-neighbor CNOT gates are performed between the data qubits in each array. This generates logic CNOT gates between the L1 logic qubits encoded in each array. In step 1106, the shuttling process is reversed so that qubits from the second line are shuttled back to the first line of their original array. In step 1108, a cycle of error correction is performed on each of the control and target arrays. This corrects any single error events that may have occurred during the entire entanglement process.

[0187] 12 shows a schematic diagram 1200 illustrating the coherent transport of the underlying spin qubits in the formation of a CNOT gate across a pair of L1 logic qubits according to method 1100. i >, |Q i >) are entangled because they carry encoded logical information, and the ancillary qubits (|a i >, |A i Note that the sigma (labeled >) is used for the syndrome extraction circuitry.

[0188] Evaluation of two-qubit logic gates The fidelity of the transversal two-qubit gate in generating entangled logical Bell states using Surface-17 is evaluated via simulation. The simulation uses the encoding circuit of Figure 9 to generate the logical |0〉 L (|+〉 L ) state. The two logical qubits are entangled using a CNOT gate, as modeled in Figure 10. That is, according to the experiment, the logical CNOT gate is executed, preceded and advanced by a round of error correction. Land |0> as the target L The action of the logic CNOT gate with is checked to see if it produces the following logic Bell state:

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[0189] Therefore, the logic of the final generated state

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[0190] Circuit noise simulations are performed as presented in the evaluation of the L1 logical qubit error rate (discussed above), however, in this simulation, errors are modeled at every point in the error correction, including during each encoding operation, the error correction rounds performed, and the shuttling of qubits between different modules.

[0191] Figure 13 shows the logic |Φ + >Failure rate of preparation

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[0192] The results demonstrate the preservation of the strong error-correction capability of the QECC when performing one of the noisiest operations on L1 logical qubits, i.e., logical CNOTs, stored in a 2 × N array. This verifies that the proposed technique is useful for providing protection to idle L1 logical qubits and for performing computations with stored L1 logical qubits while maintaining protection.

[0193] Scalable quantum error correction using second-level logic qubits Referring to Figure 13, approximately 10 -4 Achieving an error rate of about 10 for the encoded L1 qubits -5 Because universal manipulation of L1 logic qubits stored in a 2×N array is possible, the L1 logic qubits provide a reduced error rate of approximately 10, which can implement subsequent error correction. -5 can be treated as a high-quality quantum bit with an error rate of

[0194] An architecture for quantum processing is proposed, the quantum processor 100 having multiple bilinear arrays of quantum dots, each of up to N spin qubits, and a controller configured to (i) control the coherent transport of one or more of the multiple qubits in each array to implement a first-level QECC to encode the collective state of the spin qubits of the array as a corresponding first-level (L1) logical qubit, and (ii) selectively couple one or more pairs of the L1 logical qubits of the multiple bilinear arrays via a coherent combining mechanism to implement a second-level QECC to encode the collective state of an M>1 set of L1 logical qubits as a corresponding second-level (L2) logical qubit. The combining is performed for pairs of arrays by long-range interaction-based transport of information encoded by the first L1 qubit of the pair to the second L1 qubit of the pair (e.g., via qubit shuttling across respective shuttling arrays, as described in the examples discussed herein).

[0195] This approach advantageously performs two levels of quantum error correction by applying two separate QECCs, such that a first level QECC reduces the error rate of the (physical) spin qubits to the lower error rate of the L1 logical qubits, and a second level QECC further reduces the lower error rate of the L1 logical qubits to an even lower error rate of the L2 logical qubits.

[0196] A generalized implementation of the proposed two-level quantum error correction technique involves placing any number of sets of M>1 L1 qubits to allow for placement of larger surface codes across the L2 qubits. That is, to protect the L2 qubits, a surface code with a distance greater than d=3 is applied. A set of M L1 logical qubits is approximately 10 -5 , which is below the threshold for the surface code family (approximately 1%), surface codes large enough to reduce the failure rate of encoded L2 logic qubits to any desired target are available.

[0197] The proposed approach is advantageous in that it allows for selective trade-offs between resources (i.e., more qubits) for improved error protection. In particular, the availability of sufficiently large surface codes can reduce the error rate of the encoded L1 logical qubits to about 10, the value required to execute desired quantum algorithms. -15 This allows the reduction to

[0198] Furthermore, the proposed two-level approach to qubit error correction can be implemented, at least in part, using classical decoding machines that are practical with current technology. In one example, processor 100 includes a plurality of L2 logical qubits, each of which is generated from a total of M=10,000 high-quality (L1) qubits, each of which is composed of N=17 physical qubits.

[0199] Those skilled in the art will appreciate that numerous variations and / or modifications may be made to the above-described embodiments without departing from the broad general scope of the present disclosure, and the present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. References [1] Delfosse, Hierarchical decoding to reduce hardware requirements for quantum computing, 2020, arXiv:2001.11427 [2] Bluvstein, D.et al., “A quantum processor based on coherent transport of entangled atom arrays”, Nature, Vol.604, 21 April 2022, pp.451-456. [3] Mohiyaddin, F.A.et al., “Large-Scale 2D Spin-Based Quantum Processor with a Bi-Linear Architecture”, IEEE International Electron Devices Meeting, 11-15 December 2021, pp.27.5.1 - 27.5.4. [4] J.Yoneda, et al., Nature Communications 12, 10.1038 / s41467-021-24371-7(2021). [5] Y.Tomita and K.M.Svore, Physical Review A 90, 10.1103 / physreva.90.062320(2014) [6] D.M.Debroy, M.Li, S.Huang, and K.R.Brown, Logical performance of 9 qubit compass codes in ion traps with crosstalk errors(2020), arXiv:1910.08495. [7] D.Bacon, Physical Review A 73, 10.1103 / physreva.73.012340(2006). [8] J.P.Bonilla Ataides, D.K.Tuckett, S.D.Bartlett, S.T.Flammia, and B.J.Brown, Nature Communications 12, 10.1038 / s41467-021-22274-1(2021). [9] I.Hansen et al.Implementation of the smart protocol for global qubit control in silicon(2021), arXiv:2108.00836.

[10] A.G.Fowler et al., Physical Review A 86, 10.1103 / physreva.86.032324(2012).

[11] D.Litinski, Quantum 3, 128, arXiv:1808.02892v3,(2019).

[12] C.Gidney and A.G.Fowler, Quantum 3, 135, arXiv:1812.01238v3,(2019).

Claims

1. 1. A quantum processing device, comprising: at least one bilinear array of quantum dots, each array configured to hold a plurality of spin qubits; and a controller configured to control the coherent transport of one or more of the plurality of qubits in each array to implement a quantum error correction code (QECC), the QECC encoding a collective state of the spin qubits of each of the arrays as a corresponding first level (L1) logic qubit.

2. 10. The device of claim 1, wherein each bilinear array comprises a first line of N quantum dots configured to hold up to N spin qubits and a second line of N quantum dots configured to allow an entanglement operation to be performed between the respective qubits via the coherent transport.

3. 3. The device of claim 2, wherein the spin qubits are held in the first line of the array according to an arrangement selected to facilitate the coherent transport of the one or more of the plurality of spin qubits to perform error correction according to the QECC.

4. 4. The device of claim 3, wherein the device is configured to perform the error correction cycle for the L1 logical qubit of any one of the at least one bilinear arrays by: (i) initializing one or more ancillary qubits of the QECC in the array according to the arrangement; (ii) executing one or more two-qubit entanglement gates, each gate entangling one or more pairs of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

5. 5. The device of claim 4, wherein the entangled qubits of the QECC include a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

6. 6. The device of claim 4, wherein the device is configured to entangle two spin qubits in the array by coherently transporting a selected spin qubit of the pair of spin qubits from the first line of the array through the second line of the array, aligning the selected spin qubit with the other spin qubit, performing a two-qubit gate, and then coherently transporting at least the selected spin qubit back onto the first line of the array.

7. 6. The device of claim 4 or 5, wherein the device is configured to entangle two spin qubits in the array by inducing a direct local interaction between the qubits when the qubits to be entangled are already in adjacent dots.

8. The device of any one of claims 4 to 7, wherein the one or more two-qubit entanglement gates are scheduled according to the QECC and the geometry of the bilinear array.

9. A device according to any one of claims 3 to 8, wherein the arrangement of the qubits in the first line of the array is determined to minimize a depth of syndrome extraction circuitry.

10. A device according to any preceding claim, wherein each bilinear array is constructed from silicon metal oxide semiconductor (SiMOS) quantum dots.

11. The device according to any one of claims 1 to 10, wherein the QECC is a surface code.

12. 1. A method for enabling quantum error correction on a quantum processing device, the method comprising: (i) arranging a plurality of spin qubits in a bilinear array of quantum dots of the quantum processing device according to a quantum error correcting code (QECC), wherein the collective state of a subset of the spin qubits forms a first level (L1) logic qubit protected by the QECC; (ii) determining a sequence of one or more entanglement operations for each pair of the plurality of spin qubits; (iii) executing a syndrome extraction circuit to determine a syndrome of the QECC for performing a cycle of error correction by performing the sequence of entanglement operations; 20. The method of claim 19, wherein performing the sequence of entanglement operations involves coherently transporting one or more of the plurality of spin qubits in the array.

13. 13. The method of claim 12, wherein the bilinear array comprises a first line of N quantum dots configured to hold up to N spin qubits, and a second line of N quantum dots configured to allow an entanglement operation to be performed between the respective qubits via coherent transport.

14. 14. The method of claim 13, wherein the arrangement of the plurality of spin qubits in the first line is selected to facilitate the coherent transport of the one or more of the plurality of spin qubits to perform error correction in accordance with the QECC.

15. 15. The method of claim 13 or 14, wherein executing the syndrome extraction circuitry comprises: (i) initializing one or more ancillary qubits of the QECC in the array according to the arrangement; (ii) performing the determined sequence of entanglement operations, each entanglement operation entangling a pair of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

16. 16. The method of claim 15, wherein each pair of entangled qubits includes a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

17. 17. The method of claim 15 or 16, wherein entangling the pair of spin qubits of the QECC comprises coherently transporting a selected spin qubit of the pair of spin qubits from the first line of the array through the second line of the array, aligning the selected spin qubit with the other spin qubit of the pair, performing a two-qubit gate, and then coherently transporting at least the selected spin qubit back to the first line of the array.

18. 17. The method of claim 15 or 16, wherein entangling a pair of spin qubits comprises, if the qubits to be entangled are already in adjacent dots, inducing a direct local interaction between the qubits without coherently transporting either of the qubits.

19. The method of any one of claims 12 to 18, wherein the sequence of the entanglement operations of the syndrome extraction circuit is determined according to the QECC and the geometry of the bilinear array.

20. 20. The method of any one of claims 12 to 19, wherein the placement of the qubits in the first line of the array is determined to minimize a depth of the syndrome extraction circuitry.

21. (iv) decoding the syndrome to obtain an output recovery operator; The method of any one of claims 12 to 20, further comprising: (v) applying the recovery operator to the QECC of the array.

22. 22. The method of claim 21 , wherein steps (iv) and (v) are performed by a classical processing device in response to transmission of the syndromes from the quantum processing device to the classical processing device.

23. The device comprises a plurality of bilinear arrays of quantum dots, and the controller selectively coupling a first L1 logic qubit of a first bilinear array to a second L1 logic qubit of a second bilinear array via a coherent coupling mechanism, the coupling occurring by long-range interaction-based transport of the information encoded by the first L1 qubit to the second L1 qubit; 12. The device of claim 1, further configured to:

24. 24. The device of claim 23, wherein the coherent coupling mechanism includes a quantum transport structure configured to connect the plurality of bilinear arrays, enabling the controller to selectively couple the first and second L1 logical qubits by the coherent transport of one or more spin qubits between the first bilinear array and the second bilinear array connected to the first array.

25. 25. The device of claim 24, wherein the quantum transport structure includes one or more shuttling arrays of quantum dots, each shuttling array disposed between a connected pair of the bilinear arrays.

26. The controller controls an entanglement operation between one or more of the spin qubits of each array of the pair, transferring the spin qubits from one array of the pair to the other array of the pair; 26. The device of claim 24 or 25, further configured to couple the first and second L1 logical qubits by:

27. the controller is configured to: coherently transporting the spin qubits from the control array to the target array through the quantum transport structure; performing a nearest-neighbor CNOT gate between one or more pairs of the data qubits of the QECC; and coherently transporting the spin qubits from the target array back to the control array; 27. The device of claim 26, further configured to perform by: performing a cycle of error correction on each of the control array and the target array.

28. 28. The device of claim 27, wherein the controller is further configured to apply a second-level QECC to encode the collective state of the set of L1 logical qubits as a corresponding second-level (L2) logical qubit.

29. 30. The device of claim 28, wherein the distance of the second level QECC is arbitrarily scalable with the number M>1 of the bilinear arrays of the device.

30. 1. A quantum processing device, comprising: a plurality of bilinear arrays of quantum dots, each array configured to hold a plurality of up to N spin qubits; a controller, the controller comprising: implementing a first level QECC to control the coherent transport of one or more of the plurality of qubits in each array to encode the collective state of the spin qubits of the array as a corresponding first level (L1) logical qubit; configured to selectively combine one or more pairs of L1 logical qubits of the plurality of bilinear arrays via a coherent combining mechanism to implement a second-level QECC for encoding the collective states of M>1 sets of L1 logical qubits as corresponding second-level (L2) logical qubits; the coupling is performed, for each pair, by long-range interaction-based transport of the information encoded by a first L1 qubit of the pair to a second L1 qubit of the pair; a first level QECC that reduces the error rate of the spin qubit to a lower error rate of the L1 logical qubit, and a second level QECC that further reduces the lower error rate of the L1 logical qubit to an even lower error rate of the L2 logical qubit.

31. 31. The device of claim 30, wherein the coherent coupling mechanism includes a quantum transport structure configured to connect the plurality of bilinear arrays, enabling the controller to selectively couple the one or more pairs of L1 logical qubits by coherent transport of one or more spin qubits, for each pair, between a first array of the pair and a second array of the pair connected to the first array.

32. 32. The device of claim 30 or 31, wherein the controller is further configured to perform a set of fault-tolerant quantum processing operations using one or more L2 logical qubits of the device.

33. 33. A method for performing a fault-tolerant quantum processing operation, the method being performed by a quantum processing device according to claim 32, the method comprising: determining at least two coupled bilinear arrays for performing quantum processing operations; selecting one or more pairs of the determined combined bilinear arrays; and for each selected pair including a first array and a second array, (i) coherently transporting at least a subset of the spin qubits from the first array to the second array; (ii) performing individual entanglement operations between the spin qubits in the second array; and (iii) reversing the coherent transport of step (i); and (iv) performing a cycle of error correction on each of the first and second arrays, the cycle of error correction being enabled by a method according to any one of claims 12 to 22.

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