Directional selective filling for silicon gap filling processes.

Abstract

An exemplary processing method can include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The processing region can house a substrate. The substrate can define a feature therein. The method can include forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor. The method can include depositing a silicon- and carbon-containing material on the substrate. The method can include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor, and etching the silicon- and carbon-containing material from sidewalls of the feature in the substrate. The method can include providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the nitrogen-containing precursor, and doping the silicon- and carbon-containing material with nitrogen.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 18 / 095,279, entitled "DIRECTIONAL SELECTIVE FILL FOR SILICON GAP FILL PROCESSES," filed January 10, 2023, which is incorporated herein by reference in its entirety.

[0002] The present technology relates to semiconductor processing, and more particularly to the deposition and etching of materials to form densified seamless materials in gap-fill processes. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires methods to control the formation and removal of exposed material. As device sizes continue to shrink, material formation can affect subsequent operations. For example, gap-fill operations may involve forming or depositing material to fill trenches or other features formed on semiconductor substrates. These fill operations can be challenging because the features may be characterized by higher aspect ratios and reduced critical dimensions. For example, because deposition may occur at the top and along the sidewalls of the feature, continued deposition can cause the feature to pinch off, including between the sidewalls within the feature, creating voids within the feature. This can affect device performance and subsequent processing operations.

[0004] Therefore, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary processing method can include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The processing region can house a substrate. The substrate can define features within the substrate. The processing region can be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate rests. The method can include forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor. The method can include depositing silicon and carbon-containing materials on the substrate. The method can include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The method can include forming plasma effluents of the hydrogen-containing precursor. The method can include etching silicon and carbon-containing materials from sidewalls of features in the substrate using the plasma effluents of the hydrogen-containing precursor. The method can include providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber. The method can include forming plasma effluents of the nitrogen-containing precursor. The method can include doping the silicon and carbon-containing materials with nitrogen from the plasma effluents of the nitrogen-containing precursor.

[0006] In some embodiments, the feature in the substrate may be characterized by an aspect ratio of about 2:1 or greater. The feature may be characterized by a width across the feature of about 20 nm or less. Bias power may be applied to the substrate support from a bias power supply. The bias power supply may be operated in a pulsed mode at a pulse frequency of about 1 kHz or less during both deposition and etching. The bias power supply may be operated at a duty cycle of about 50% or less during both deposition and etching. The plasma power supply may be operated in a continuous wave mode, and the bias power supply may be operated in a pulsed mode during deposition and etching. Plasma effluents of the silicon-containing precursor and the carbon-containing precursor may be formed from the plasma power supply at a first power level. Plasma effluents of the hydrogen-containing precursor may be formed from the plasma power supply at a second power level lower than the first power level. The method may include densifying the remaining silicon- and carbon-containing material in the feature defined in the substrate using the plasma effluents of the hydrogen-containing precursor. The densifying step may include reducing the hydrogen content of the remaining silicon- and carbon-containing material to about 30 atomic % or less. The silicon-containing precursor may be provided at a flow ratio of about 1:1 or greater to the carbon-containing precursor. The method may be repeated as a second cycle. The thickness of the silicon and carbon-containing material may be about 5 nm or less. The pressure in the semiconductor processing chamber may be maintained at a pressure of about 10 Torr or less.

[0007] Some embodiments of the present technology include a semiconductor processing method. The method can include i) forming plasma effluents of a silicon-containing precursor and a carbon-containing precursor. The method can include ii) depositing a silicon- and carbon-containing material on a substrate. The substrate can define a feature within the substrate. The substrate may be mounted on a substrate support. The method can include iii) forming plasma effluents of a hydrogen-containing precursor. The method can include iv) etching silicon and carbon-containing material from sidewalls of the feature within the substrate using the plasma effluents of the hydrogen-containing precursor. The method can include v) forming plasma effluents of a nitrogen-containing precursor. The method can include vi) doping the silicon and carbon-containing material with nitrogen from the plasma effluents of the nitrogen-containing precursor. The method can include repeating operations i)-vi) to iteratively fill the feature.

[0008] In some embodiments, bias power can be applied to the substrate support from a bias power supply. The bias power supply can be operated in a pulsed mode at a frequency of about 1 kHz or less. The bias power supply can be operated at a duty cycle of about 25% or less. The bias power supply can be operated at a plasma power of about 750 W or less. The etching can completely remove silicon and carbon-containing material from the sidewalls of the feature above the base fill of the feature. The carbon-containing precursor can be or include a silicon and carbon-containing precursor. The temperature of the substrate can be maintained at a temperature of about 100° C. or greater.

[0009] Some embodiments of the present technology include a semiconductor processing method. The method can include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The processing region can house a substrate. The substrate can define a feature therein. The processing region can be at least partially defined between a faceplate and a substrate support on which the substrate rests. The method can include forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor. The plasma effluents of the silicon-containing precursor can be formed from a plasma power source at a first power level. The method can include depositing a silicon- and carbon-containing material on the substrate. The carbon content of the silicon- and carbon-containing material can be about 50 atomic % or less. The method can include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The method can include forming plasma effluents of the hydrogen-containing precursor. The plasma effluents of the hydrogen-containing precursor can be formed from a plasma power source at a second power level lower than the first power level. The method can include etching the silicon- and carbon-containing material from a sidewall of a feature in the substrate using the plasma effluents of the hydrogen-containing precursor. The etching can completely remove silicon- and carbon-containing material from the sidewalls of the feature above a base fill of the feature. The method can include providing a nitrogen-containing precursor to a processing region of the semiconductor processing chamber. The method can include forming a plasma effluent of the nitrogen-containing precursor. The method can include doping the silicon- and carbon-containing material with nitrogen from the plasma effluent of the nitrogen-containing precursor.

[0010] In some embodiments, depositing the silicon- and carbon-containing material on the substrate may be performed at a first spacing distance from the faceplate, and etching the silicon- and carbon-containing material from sidewalls of features in the substrate may be performed at a second spacing distance from the faceplate, the second spacing distance being less than the first spacing distance.

[0011] Such techniques can provide numerous benefits over conventional systems and techniques. For example, by performing sequential deposition and etching operations in accordance with embodiments of the present technology, sidewall coverage can be limited or controlled, thereby limiting the formation of seams or voids in small features. Additionally, processing operations following deposition and etching operations in accordance with embodiments of the present technology can provide doped silicon-containing materials for gapfill operations. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique; [Figure 2] 1A-1C illustrate exemplary operations in a processing method according to some embodiments of the present technology. [Figure 3A] 1A-1D are schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technique; [Figure 3B] 1A-1D are schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technique; [Figure 3C] 1A-1D are schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technique; [Figure 3D] 1A-1D are schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technique; [Figure 3E] 1A-1D are schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0014] Some of the drawings are included as schematic views. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Additionally, as schematic views, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0015] In the accompanying figures, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar components. If only a first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016] Amorphous silicon and carbon-containing materials may be used in many structures and processes in the manufacture of semiconductor devices, such as as trench fill or gap fill materials. In some gap fill operations, the process may utilize plasma-enhanced deposition under process conditions to increase the directionality of the deposition, which may allow the deposited material to better fill features on the substrate. In other gap fill operations, the process may utilize flowable films under process conditions to avoid the formation of seams and / or voids in the deposited material.

[0017] As feature sizes continue to shrink, plasma-enhanced deposition can be challenging for narrow features, which may further be characterized by high aspect ratios. For example, feature pinching may be more likely to occur due to deposition on the sidewalls of the feature, which may further restrict further flow and deposition into the feature when the feature size is small, potentially creating seams or voids in the deposited material. Prior art has attempted to address the formation of seams or voids by performing intermittent etching operations to remove material from the sidewalls of filled features. However, prior art etching operations required many cycles to limit the formation of seams or voids. Alternatively, prior art has attempted to use flowable films. However, flowable films can form porous materials that cannot withstand subsequent integration processes, such as etching or ashing operations. Additionally, flowable films tend to shrink during curing operations, which can damage the structure or create voids.

[0018] The present technique overcomes these limitations by performing intermittent etching of the deposited film. Etching can limit or prevent sidewall coverage during trench filling, allowing for improved filling operations. Additionally, the present technique can perform a nitrogen treatment to introduce nitrogen dopants into the deposited material.

[0019] After describing general aspects of chambers according to some embodiments of the present technology in which the plasma processing operations discussed below may be performed, specific methodologies can be described. It should be understood that the described technology may be used to improve several film formation processes and may be applicable to a variety of processing chambers and operations, and therefore the present technology is not intended to be limited to the particular films, chambers, or processes described.

[0020] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 in accordance with some embodiments of the present technology. The diagram may provide an overview of a system incorporating one or more aspects of the present technology and / or capable of performing one or more deposition or other processing operations in accordance with embodiments of the present technology. Further details of the chamber 100 or the method performed may be further described below. While the chamber 100 may be utilized to form a film layer in accordance with some embodiments of the present technology, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be placed on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 about which the shaft 144 of the substrate support 104 may lie, as indicated by arrow 145. Alternatively, the substrate support 104 may be elevated to rotate as needed during the deposition process.

[0021] A plasma profile modulator 111 can be positioned within the processing chamber 100 to control plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile modulator 111 can include a first electrode 108 positioned adjacent to the chamber body 102 and separating the chamber body 102 from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106 or can be a separate sidewall electrode. The first electrode 108 can be an annular or ring-shaped member or a ring electrode. The first electrode 108 can be a continuous loop around the periphery of the processing chamber 100 surrounding the processing volume 120, or can be discontinuous at selected locations as desired. The first electrode 108 can also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as a secondary gas distributor.

[0022] One or more isolators 110 a, 110 b, which may be a dielectric material such as ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from a gas distributor 112, also referred to as a faceplate, and from the chamber body 102. The gas distributor 112 may define apertures 118 for distributing process precursors into the process volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that may be coupled to a process chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0023] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142, as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0024] The first electrode 108 may be coupled to a first tuned circuit 128 capable of controlling the ground path of the processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuned circuit 128 may be or include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the processing volume 120 during processing. In some embodiments, as shown, the first tuned circuit 128 may include a first circuit section and a second circuit section coupled in parallel between ground and the first electronic sensor 130. The first circuit section may include a first inductor 132A. The second circuit section may include a second inductor 132B coupled in series with the first electronic controller 134. A second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit sections to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134, thereby providing some degree of closed-loop control of the plasma conditions within the process volume 120.

[0025] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146, such as a cable having a selected resistance, e.g., 50 ohms, disposed within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the process volume 120.

[0026] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0027] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 can provide real-time control of plasma conditions within the processing volume 120. A substrate 103 may be placed on the substrate support 104, and process gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may exit the processing chamber 100 through the outlet 152. Power may be coupled to the gas distributor 112 to establish a plasma within the processing volume 120. The substrate may be electrically biased using a third electrode 124 in some embodiments.

[0028] Upon exciting a plasma in the process volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. Electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to independently control the deposition rate and center-to-edge uniformity of the plasma density. In embodiments in which both electronic controllers may be variable capacitors, the electronic sensor may adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0029] Each tuning circuit 128, 136 can have a variable impedance that can be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and each variable capacitor may have a minimum value within its capacitance range. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape that minimizes spatial or lateral coverage on the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the spatial coverage of the plasma is maximized, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls, reducing spatial coverage of the substrate support. The second electronic controller 140 can have a similar effect; varying the capacitance of the second electronic controller 140 can increase or decrease the spatial coverage of the plasma on the substrate support.

[0030] Electronic sensors 130, 138 can be used to tune the respective circuits 128, 136 of the closed loop. Depending on the type of sensor used, a current or voltage set point may be installed in each sensor, and the sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the plasma shape can be selected and dynamically controlled during processing. While the preceding discussion is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component with adjustable characteristics can be used to provide the tuned circuits 128, 136 with adjustable impedance.

[0031] In some embodiments of the present technology, the processing chamber 100 may be utilized in processing methods that may include forming or etching materials for semiconductor structures. The described chamber should not be considered limiting, and it should be understood that any chamber that can be configured to perform the described operations can similarly be used. FIG. 2 illustrates exemplary operations in a processing method 200 in accordance with some embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above, and on one or more mainframes or tools. Method 200 can include many optional operations that may or may not be specifically associated with some embodiments of the method in accordance with the present technology. For example, many of the operations are not critical to the present technology but are described to provide a broader range of structure formations or may be performed by alternative methodologies as will be readily understood. Method 200 can describe operations shown schematically in FIGS. 3A-3E, which illustrations will be described in conjunction with the operations of method 200. It should be understood that the figures are only partial schematic views, and that the substrate can include any number of additional materials and features having various properties and aspects as shown in the figures.

[0032] Method 200 may include additional operations before the enumerated operations begin. For example, the additional processing operations may include forming structures on the substrate, which may include both forming and removing materials. For example, a transistor structure, a memory structure, or any other structure may be formed. Prior processing operations may be performed in a chamber in which method 200 can be performed, or processing may be performed in one or more other processing chambers before providing a substrate in a semiconductor processing chamber in which method 200 can be performed. In either case, method 200 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be placed on a substrate support, which may be a pedestal, such as substrate support 104, or may be present in the processing region of a chamber, such as processing volume 120 described above.

[0033] The substrate on which multiple operations have been performed may be substrate 305 of structure 300, which may represent a partial view of a substrate on which semiconductor processing can be performed. It should be understood that structure 300 may depict only some of the top layers of processing to illustrate aspects of the present technology. Substrate 305 may include a material on which one or more features 310 can be formed. Substrate 305 may be any number of materials used in semiconductor processing. The substrate material may be or include a dielectric material, including silicon, germanium, silicon oxide, or silicon nitride, a metallic material, or any combination of these materials, which may be formed within substrate 305 or structure 300. Feature 310 may be characterized by any shape or configuration according to the present technology. In some embodiments, the feature may be or include a trench structure or an opening formed in substrate 305.

[0034] While the feature 310 may be characterized by any shape or size, in some embodiments, the feature 310 may be characterized by a higher aspect ratio, i.e., the ratio of the depth of the feature to the width across the feature. For example, in some embodiments, the feature 310 may be characterized by an aspect ratio of about 2:1 or greater, or about 3:1 or greater, about 5:1 or greater, about 10:1 or greater, or even greater. Additionally, the feature may be characterized by a narrow width or diameter across the feature, including between two sidewalls, such as a dimension of about 20 nm or less, or a width across the feature of about 15 nm or less, about 12 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, or less.

[0035] In some embodiments, method 200 can include any processing operations, such as pre-treatment, that may be performed to prepare the surface of substrate 305 for deposition. Once prepared, method 200 can include, in operation 205, providing one or more precursors to a processing region of a semiconductor processing chamber that houses structure 300. The precursors can include one or more silicon-containing precursors and one or more carbon-containing precursors, as well as one or more diluents or carrier gases, such as an inert gas or other gas, that are supplied with the silicon-containing precursors and the carbon-containing precursors. Carrier gases can include, but are not limited to, helium, argon, xenon, and any other inert gas or other gas. Silicon-containing precursors that can be used during deposition of silicon- and carbon-containing material 315 include silane (SiH), disilane (SiH), trisilane (SiH), tetrasilane (SiH), and tetrasilane (SiH). 10 ), pentasilane (Si5H 12), or other organosilanes including cyclohexasilane, silicon tetrafluoride (SiF), silicon tetrachloride (SiCl), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursor that can be used in silicon- and carbon-containing film formation. Carbon-containing precursors that can be used during the deposition of silicon- and carbon-containing material 315 include, but are not limited to, dimethylsilane (C2H8Si), trimethylsilane (C3H 10 Si), tetramethylsilane (CH 12 The precursors may include, but are not limited to, silicon (Si), neopentasilane ((SiH)Si), tetraethyl orthosilicate (TEOS), and any other carbon-containing precursor that can be used in silicon and carbon-containing film formation.

[0036] In operation 210, deposition plasma effluents may be formed from deposition precursors, including a silicon-containing precursor and a carbon-containing precursor. The deposition plasma effluents may be formed within the processing region, which allows deposition material to be deposited on the substrate 305. For example, in some embodiments, a capacitively coupled plasma may be formed within the processing region by applying plasma power to a faceplate or substrate support, as described above.

[0037] The power applied during deposition may be a low-power plasma, which can suppress dissociation and maintain carbon incorporation in the deposited material. Thus, in some embodiments, the plasma power source can provide a plasma power of about 500 W or less to the faceplate or substrate support, and can provide a power of about 450 W or less, about 400 W or less, about 350 W or less, about 300 W or less, or less. Plasma power to the faceplate or substrate support exceeding 500 W, for example, can damage the substrate 305, including the sidewalls defining the feature 310.

[0038] During the deposition operation, as previously described, an additional power source, a bias power supply, can be activated and coupled to the substrate support to provide a bias to the plasma generated above the substrate 305. This can attract plasma effluents to the substrate 305, potentially increasing deposition at the bottom of the feature 310. The applied bias power can be relatively low to limit damage to the structure. Thus, in some embodiments, the plasma power source can provide a bias plasma power of about 1,000 W or less to the substrate support, and can provide a power of about 750 W or less, about 600 W or less, about 500 W or less, about 450 W or less, about 400 W or less, about 350 W or less, about 300 W or less, or less. Additionally, adjusting the applied source power and bias power can result in densification of the deposited silicon- and carbon-containing material 315 during the deposition operation.

[0039] In operation 215, a silicon- and carbon-containing material 315 may be deposited on a substrate from plasma effluents of a silicon-containing precursor and a carbon-containing precursor. The silicon- and carbon-containing material 315 may be or include an amorphous material. The deposited silicon- and carbon-containing material 315 may at least partially fill a feature 310 on the substrate 305 to provide bottom-up gap filling. As shown in FIG. 3A , the silicon- and carbon-containing material 315 may be deposited on the substrate 305 and may be deposited not only on the bottom of the feature 310, but also above and on the sidewalls of the feature 310 on the substrate 305. The amount of silicon- and carbon-containing material 315 deposited on the sidewalls may be relatively small or thin, but continued formation may cause the feature 310 to pinch off. Pinch-off may result in the formation of seams or voids in the silicon- and carbon-containing material 315 as gap filling continues. Thus, as further described below, a series of depositions, etches, and / or processes may be performed to deposit a seamless and void-free silicon and carbon-containing material 315 within the feature 310.

[0040] The carbon content of the silicon- and carbon-containing material 315 may be about 50 atomic % or less. A higher carbon content may result in incomplete etching of the silicon- and carbon-containing material 315 in subsequent etching operations. Thus, the carbon content of the silicon- and carbon-containing material 315 may be about 45 atomic % or less, or may be about 40 atomic % or less, about 35 atomic % or less, about 30 atomic % or less, about 25 atomic % or less, about 20 atomic % or less, about 15 atomic % or less, about 10 atomic % or less, or even less. To maintain the carbon content of the silicon- and carbon-containing material 315 at about 50 atomic % or less, the silicon-containing precursor may be provided at a higher flow rate than the carbon-containing precursor. For example, the silicon-containing precursor can be provided at a flow ratio of about 1:1 or greater relative to the carbon-containing precursor, and can be provided at a flow ratio of about 1.2:1 or greater, about 1.4:1 or greater, about 1.6:1 or greater, about 1.8:1 or greater, about 2:1 or greater, about 2.2:1 or greater, about 2.4:1 or greater, about 2.6:1 or greater, about 2.8:1 or greater, about 3:1 or greater, or greater. In embodiments, the flow rate of the silicon-containing precursor can be maintained at about 500 sccm or less, and can be maintained at about 450 sccm or less, about 400 sccm or less, about 350 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, or less. Higher flow rates can increase the deposition rate and cause the feature 310 to fill too quickly.

[0041] Following a predetermined amount of deposition, in some embodiments of the present technique, an etching or modification process configured to etch back the formed material may be performed. This process may be performed in the same chamber as the deposition or in a cyclical process to fill features. In some embodiments, the silicon-containing precursor and / or carbon-containing precursor flow may be stopped and the processing region may be purged. Following the purging, in operation 220, a hydrogen-containing precursor may be provided to the processing region of the semiconductor processing chamber. In operation 225, etching plasma effluents may be formed, which may also be capacitively coupled plasma formed in the processing region, although in some embodiments, inductively coupled plasma may be applied as well. The etching plasma effluents may be formed by applying plasma power to a faceplate or substrate support, and in some embodiments, no other power sources may be activated.

[0042] Similar to the deposition operation, during the etching operation, a bias power supply can be activated to provide a bias to the plasma generated above the substrate 305. This can attract plasma effluents to the substrate 305 and impact the silicon- and carbon-containing material 315, causing densification of the deposited silicon- and carbon-containing material 315. While any hydrogen-containing material can be used, in some embodiments, diatomic hydrogen can be used as a hydrogen-containing precursor along with one or more additional precursors to generate the etching plasma. In embodiments, hydrogen radicals and ions can easily penetrate the material formed within the feature 310 and release trapped hydrogen from the silicon- and carbon-containing material 315, causing densification. The applied bias power can be relatively low to reduce sputtering of the silicon- and carbon-containing material 315 and potential damage to underlying structures. The material supplied to form the plasma can also have a reduced amount of heavier material to reduce sputtering of the deposited film. Additionally, the etching operation can be performed by adjusting the applied source power and bias power, which can reduce sidewall coverage of the deposited material.

[0043] As previously mentioned, hydrogen or any other hydrogen-containing material may be utilized to generate a plasma in the processing region by supplying power from a plasma power source to the faceplate. In some embodiments, the source plasma power may be equal to or less than the plasma power used during deposition. For example, the supplied plasma power may be about 500 W or less, and power may be supplied at about 450 W or less, about 400 W or less, about 350 W or less, about 300 W or less, about 250 W or less, or less. Plasma power to the faceplate or substrate support exceeding, for example, 500 W may damage the substrate 305, including the sidewalls defining the features 310. In addition, aspects of the bias power may also be adjusted to further limit damage to underlying structures. For example, the bias power may be maintained at about 1,000 W or less, and may be about 750 W or less, about 600 W or less, about 500 W or less, about 400 W or less, or less. In some operations, the bias power may be higher than the plasma source power, while in other operations, the bias power may alternatively be lower than the plasma power.

[0044] Applying a larger bias may increase the directionality of the delivery in a direction perpendicular to the plane across the substrate. Therefore, reducing the applied bias power may decrease the amount of directionality and increase the interaction of the plasma effluents within the feature 310. Then, in operation 230, the plasma effluents may etch the silicon- and carbon-containing material 315 and remove it from the sidewalls of the feature 310. The plasma effluents may completely remove the silicon- and carbon-containing material 315 from the sidewalls of the feature 310 above a base fill of the silicon- and carbon-containing material 315. A base fill of the silicon- and carbon-containing material 315 may refer to silicon- and carbon-containing material 315 deposited at the bottom of the feature 310 or deposited on silicon- and carbon-containing material 315 previously deposited toward the bottom of the feature 310.

[0045] Simultaneously, or in addition, the more directionally delivered plasma effluents can penetrate into the remaining silicon- and carbon-containing material 315 formed on the bottom of the feature 310 and / or the substrate 305. As previously described, this penetration can reduce hydrogen incorporation and densify the film in optional operation 235. As shown in FIG. 3B , silicon- and carbon-containing material 315 may be removed from the sidewalls of the feature 310, from overhanging regions of the substrate 305, and / or from the top surface of the substrate 305. This removal may retain the deposited silicon- and carbon-containing material 315 on the bottom region of the feature 310 and / or the top surface of the substrate 305. This process can also reduce hydrogen incorporation in the remaining material, such as hydrogen incorporation of about 40 atomic % or less, and can reduce hydrogen incorporation to about 35 atomic % or less, about 30 atomic % or less, about 25 atomic % or less, about 20 atomic % or less, about 15 atomic % or less, about 10 atomic % or less, about 5 atomic % or less, or less.

[0046] Additional adjustments can be made to further increase etching of deposited material along the sidewalls of features by adjusting one or more characteristics of the supplied plasma power or bias power. For example, in some embodiments, both the plasma power source and the bias power source can be operated in a continuous wave mode. Additionally, one or both of the power sources can be operated in a pulsed mode. In some embodiments, the source power can be operated in a continuous wave mode or a pulsed mode, and the bias power can be operated in a pulsed mode. The pulse frequency of the bias power can be about 100 Hz or greater, about 200 Hz or greater, about 300 Hz or greater, about 500 Hz or greater, about 750 Hz or greater, about 1,000 Hz or greater, about 1,500 Hz or greater, about 2,000 Hz or greater, or even higher. Similarly, the pulse frequency of the bias power can be about 5,000 Hz or less, about 4,500 Hz or less, about 4,000 Hz or less, about 3,500 Hz or less, about 3,000 Hz or less, about 2,500 Hz or less, about 1,000 Hz or less, about 500 Hz or less, or less. The duty cycle of the bias power can be about 75% or less, and the bias power can be operated at a duty cycle of about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, about 5% or less, or less. Operating the bias power at a reduced duty cycle, such as about 50% on-time duty, can provide a longer time per cycle to provide a more isotropic etch within the feature, which can result in better material removal from the sidewalls.

[0047] Additional power configurations may also include synchronization of the source power and bias power in a master / slave relationship. For example, both power supplies can be operated in a pulsing orientation, with the source power activated with each pulse followed by the bias power synchronously. Interlevel pulsing may also be applied. For example, the source power can be operated at a first plasma power while the bias power is duty-on. During the remainder of the cycle when the bias power is off, the source power can be operated at a second plasma power, which may be greater than the first plasma power. This not only promotes isotropic etching by eliminating bias-induced directionality, but also improves the etching characteristics of the isotropic etch.

[0048] Following the predetermined amount of etching, in some embodiments of the present technique, a treatment or doping process configured to incorporate additional materials into the formed material may be performed. This process may be performed in the same chamber as the deposition and / or etching, or may be performed in a cyclical process to fill features. In some embodiments, the flow of the hydrogen-containing precursor may be stopped and the processing region may be purged. Following the purging, in operation 240, a processing precursor may be provided to the processing region of the semiconductor processing chamber. In operation 245, a processing plasma effluent may be formed, which may also be a capacitively coupled plasma formed in the processing region, although in some embodiments, an inductively coupled plasma may be applied as well. The processing plasma effluent may be formed by applying plasma power to a faceplate or substrate support, and in some embodiments, no other power sources may be activated.

[0049] Similar to the etching operation, during the processing operation, a bias power supply can be activated to provide a bias to the plasma generated above the substrate 305. This can attract plasma effluents to the substrate 305 and cause them to impinge on the silicon- and carbon-containing material 315, resulting in doping of the deposited silicon- and carbon-containing material 315. While any process precursor can be used to incorporate a dopant into the silicon- and carbon-containing material 315, in some embodiments, a nitrogen-containing precursor, such as diatomic nitrogen, can be used as the processing precursor along with one or more additional precursors. The additional precursors can include one or more diluents or carrier gases, such as an inert gas or other gas, supplied with the processing precursor. The carrier gas can include, but is not limited to, helium, argon, xenon, and any other inert gas or other gas. However, it is contemplated that other precursors can be used depending on the dopant to be introduced into the silicon- and carbon-containing material 315. In embodiments, nitrogen radicals and ions can easily penetrate the material formed in feature 310, for example, and combine with terminal silicon, hydrogen, or other materials in silicon- and carbon-containing material 315 to incorporate nitrogen into the material. The applied bias power may be relatively low to reduce sputtering of silicon- and carbon-containing material 315 and to reduce potential damage to underlying structures. The materials supplied to form the plasma may also have reduced amounts of heavier materials to reduce sputtering of the deposited film.

[0050] As previously mentioned, nitrogen or any other nitrogen-containing material may be utilized to generate a plasma in the processing region by supplying power from a plasma power source to the faceplate. In some embodiments, the source plasma power may be equal to or less than the plasma power used during deposition and / or etching. For example, the plasma power supplied may be about 400 W or less, and may be about 350 W or less, about 300 W or less, about 250 W or less, about 200 W or less, or less. Plasma power to the faceplate or substrate support exceeding, for example, 500 W may damage the substrate 305, including the sidewalls defining the feature 310.

[0051] Additionally, aspects of the bias power can also be adjusted to reduce damage to underlying structures. For example, the bias power can be maintained at about 1,000 W or less, and can be about 750 W or less, about 600 W or less, about 500 W or less, about 400 W or less, or less. In some operations, the bias power can be higher than the plasma source power, while in other operations, the bias power can alternatively be lower than the plasma power. Applying a larger bias can increase the directionality of the delivery in a direction perpendicular to the plane across the substrate. Thus, reducing the delivered bias power can reduce the amount of directionality and increase the interaction of the plasma effluents within the feature 310. As shown in FIG. 3C, the plasma effluents can then dope the material in operation 250 to form a doped silicon- and carbon-containing material 320.

[0052] As shown in FIG. 2 , in embodiments of the present technology, deposition, etching, and treatment operations can be repeated any number of times in cycles to fill a feature. As shown in FIGS. 3D-3E , deposition, etching, and treatment operations can fill a feature with a silicon- and carbon-containing material, such as amorphous silicon- and carbon-containing material. For example, the process may be repeated for a second cycle, a third cycle, a fourth cycle, a fifth cycle, a sixth cycle, a seventh cycle, or any number of cycles necessary to completely fill the feature 310 with the silicon- and carbon-containing material 315. During each cycle, the thickness of the deposited silicon- and carbon-containing material 315 may be maintained to allow subsequent processing to form a uniformly doped silicon- and carbon-containing material 320. Thus, the thickness of the silicon- and carbon-containing material 315 deposited in each cycle may be about 5 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, or less. The increased thickness may not allow complete penetration of the dopant in the processing operation, potentially resulting in a non-uniformly doped material.

[0053] Temperature and pressure can also affect the operation of the present technique. For example, the process may be performed at a temperature of about 450°C or less, about 400°C or less, about 350°C or less, about 300°C or less, about 250°C or less, about 200°C or less, about 150°C or less, or lower. The temperature may be maintained within any of these ranges throughout the method, including during deposition, etching, and / or processing, or may be adjusted during deposition, etching, and / or processing. Higher temperatures may result in the formation of crystallized silicon and carbon-containing materials instead of amorphous silicon and carbon-containing materials. Additionally, higher temperatures may decrease the efficiency of the etching operation, increasing throughput time.

[0054] The pressure in the semiconductor processing chamber may be kept relatively low for any of the processes, such as a chamber pressure of about 20 Torr or less, and the pressure may be maintained at about 18 Torr or less, about 16 Torr or less, about 14 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2.5 Torr or less, about 2 Torr or less, about 1.5 Torr or less, about 1 Torr or less, or less. However, lower pressures may result in slower feature fill rates. Furthermore, higher pressures may lead to reduced pattern loading and / or line bending. Therefore, the pressure in the semiconductor processing chamber during deposition operations may be maintained at about 1 Torr or greater, and the pressure may be maintained at about 2 Torr or greater, about 3 Torr or greater, about 4 Torr or greater, about 5 Torr or greater, or greater. Furthermore, higher pressures during etching operations may cause hydrogen to crystallize. Therefore, the pressure in the semiconductor processing chamber during etching operations may be maintained at about 3 Torr or less, about 2.5 Torr or less, about 2 Torr or less, about 1.5 Torr or less, or less. Finally, increasing the pressure during processing operations may increase directionality and result in non-uniform doping of the deposited material. Therefore, the pressure in the semiconductor processing chamber during processing operations may be maintained at about 2 Torr or less, about 1.5 Torr or less, about 1 Torr or less, or less. Performing processes according to some embodiments of the present technology may improve filling of narrow features utilizing silicon and carbon-containing materials.

[0055] The spacing between the faceplate and the substrate support can also affect the operation of the present technique. Increasing the spacing between the faceplate and the substrate support can increase the directionality of the generated plasma effluents due to increased residence time. Conversely, decreasing the spacing between the faceplate and the substrate support can increase the isotropy of the plasma effluents. Thus, the spacing between the faceplate and the substrate support during deposition operations can be about 300 mm or more, about 320 mm or more, about 340 mm or more, about 360 mm or more, about 380 mm or more, about 400 mm or more, about 450 mm or more, about 500 mm or more, about 550 mm or more, about 600 mm or more, or more. During etching operations, the spacing between the faceplate and the substrate support can be about 300 mm or less, about 280 mm or less, about 260 mm or less, about 240 mm or less, about 220 mm or less, about 200 mm or less, or less. The spacing between the faceplate and the substrate support during processing operations can be between the spacing during deposition operations and the spacing during etching operations. The spacing during processing operations can affect the depth of the dopant and can be adjusted based on the thickness of the material being deposited.

[0056] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0057] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. In addition, while a method or process may be described sequentially or stepwise, it should be understood that operations may be performed simultaneously or in a different order than listed.

[0058] Where a range of values ​​is provided, it is understood that each intervening value, to the smallest decimal point of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated or unstated intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may each independently be included or excluded, and each range in which either limit, neither limit, or both limits are included in the smaller range is also encompassed within the technology, subject to the specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0059] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a silicon-containing precursor" includes a plurality of such precursors, a reference to "the silicon-and-carbon-containing material" includes a reference to one or more such materials and equivalents thereof known to those skilled in the art, and so forth.

[0060] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, the substrate defining features therein, and the processing region is defined at least in part between a faceplate and a substrate support on which the substrate rests; forming a plasma effluent of the silicon-containing precursor and the carbon-containing precursor; depositing a silicon and carbon containing material on the substrate; providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the hydrogen-containing precursor; etching the silicon and carbon-containing material from sidewalls of the feature in the substrate with the plasma effluents of the hydrogen-containing precursor; providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the nitrogen-containing precursor; doping the silicon and carbon-containing material with nitrogen from the plasma effluent of the nitrogen-containing precursor; A semiconductor processing method comprising:

2. the features in the substrate are characterized by an aspect ratio of about 2:1 or greater; the feature is characterized by a width across the feature of about 20 nm or less; 10. The semiconductor processing method of claim 1.

3. bias power is applied to the substrate support from a bias power supply; the bias power supply is operated in a pulsed mode at a pulse frequency of about 1 kHz or less during both the deposition and the etching; 10. The semiconductor processing method of claim 1.

4. 4. The semiconductor processing method of claim 3, wherein said bias power supply operates at a duty cycle of about 50% or less during both said deposition and said etching.

5. 4. The semiconductor processing method of claim 3, wherein during said deposition and said etching, the plasma power supply operates in a continuous wave mode and said bias power supply operates in a pulsed mode.

6. the plasma effluents of the silicon-containing precursor and the carbon-containing precursor are formed from a plasma power source at a first power level; the plasma effluent of the hydrogen-containing precursor is formed from the plasma power source at a second power level lower than the first power level.

10. The semiconductor processing method of claim 1.

7. further comprising densifying the remaining silicon and carbon-containing material in the feature defined in the substrate using the plasma effluents of the hydrogen-containing precursor, the densifying comprising reducing the hydrogen content of the remaining silicon and carbon-containing material to about 30 atomic % or less.

10. The semiconductor processing method of claim 1.

8. 10. The semiconductor processing method of claim 1, wherein the silicon-containing precursor is provided at a flow ratio of about 1:1 or greater to the carbon-containing precursor.

9. The semiconductor processing method of claim 1 repeated for a second cycle.

10. 10. The semiconductor processing method of claim 1, wherein the silicon and carbon containing material has a thickness of about 5 nm or less.

11. 10. The semiconductor processing method of claim 1, wherein the pressure in the semiconductor processing chamber is maintained at a pressure of about 10 Torr or less.

12. i) forming a plasma effluent of a silicon-containing precursor and a carbon-containing precursor; ii) depositing a silicon and carbon containing material onto a substrate, the substrate defining features therein, the substrate being mounted on a substrate support; iii) forming a plasma effluent of a hydrogen-containing precursor; iv) etching the silicon and carbon-containing material from sidewalls of the feature in the substrate using the plasma effluents of the hydrogen-containing precursor; v) forming a plasma effluent of a nitrogen-containing precursor; vi) doping the silicon and carbon-containing material with nitrogen from the plasma effluent of the nitrogen-containing precursor; repeating operations i) to vi) to iteratively fill in said features; A semiconductor processing method comprising:

13. applying bias power to the substrate support from a bias power supply; the bias power supply operates in a pulsed mode at a frequency of about 1 kHz or less; 13. The semiconductor processing method of claim 12.

14. 14. The semiconductor processing method of claim 13, wherein the bias power supply operates at a duty cycle of about 25% or less.

15. 14. The semiconductor processing method of claim 13, wherein the bias power supply operates at a plasma power of about 750 W or less.

16. 13. The semiconductor processing method of claim 12, wherein said etching completely removes said silicon and carbon-containing material from said feature sidewalls above said feature base fill.

17. 13. The semiconductor processing method of claim 12, wherein the carbon-containing precursor comprises a silicon and carbon-containing precursor.

18. 13. The semiconductor processing method of claim 12, wherein the temperature of the substrate is maintained at a temperature of about 100°C or greater.

19. providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, the substrate defining features therein, and the processing region is defined at least in part between a faceplate and a substrate support on which the substrate rests; forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor, the plasma effluents of the silicon-containing precursor being formed from a plasma power source at a first power level; depositing a silicon and carbon containing material on the substrate, wherein the silicon and carbon containing material has a carbon content of about 50 atomic % or less; providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the hydrogen-containing precursor, the plasma effluent of the hydrogen-containing precursor being formed from the plasma power source at a second power level lower than the first power level; etching the silicon and carbon-containing material from sidewalls of the feature in the substrate using the plasma effluents of the hydrogen-containing precursor, wherein the etching completely removes the silicon and carbon-containing material from the sidewalls of the feature above a base fill of the feature; providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the nitrogen-containing precursor; doping the silicon and carbon-containing material with nitrogen from the plasma effluent of the nitrogen-containing precursor; A semiconductor processing method comprising:

20. depositing the silicon and carbon-containing material on the substrate is performed at a first spacing distance from the face plate; etching the silicon and carbon-containing material from the sidewalls of the features in the substrate is performed at a second spacing distance from the faceplate, the second spacing distance being less than the first spacing distance; 20. The semiconductor processing method of claim 19.

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