Dynamic Body Biasing for Radio Frequency (RF) Switches

Abstract

A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET) having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to U.S. patent application Ser. No. 18 / 104,409, entitled "DYNAMIC BODY BIASING FOR RADIO FREQUENCY (RF) SWITCH," filed on February 1, 2023, which is a continuation-in-part of U.S. patent application Ser. No. 17 / 892,800, entitled "DYNAMIC BODY BIASING FOR RADIO FREQUENCY (RF) SWITCH," filed on August 22, 2022, the disclosures of which are expressly incorporated by reference in their entireties into this specification.

[0002] This disclosure relates generally to integrated circuits (ICs). More particularly, this disclosure relates to dynamic body biasing for radio frequency (RF) switches. [Background technology]

[0003] The design complexity of mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is compounded by the addition of circuit functions to support enhanced communications. Designing a mobile RF transceiver can involve using semiconductor-on-insulator (SOI) technology. Semiconductor-on-insulator (SOI) technology replaces the traditional semiconductor (e.g., silicon) substrate with a layered semiconductor-insulator-semiconductor substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from traditional silicon devices because the silicon junction resides above an electrical insulator, typically a buried oxide (BOX) layer. However, a reduced-thickness BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of active devices on the SOI layer to the SOI substrate supporting the BOX layer.

[0004] For example, high-performance complementary metal oxide semiconductor (CMOS) radio frequency (RF) switch technology is currently fabricated using SOI substrates. While SOI substrates can provide some protection against out-of-band harmonics in RF transceivers, there is a need to improve device isolation and reduce RF losses. Furthermore, transistors fabricated using SOI technology can suffer from the floating body effect, in which the body of the transistor collects charge generated at the junctions of the transistor device. Summary of the Invention

[0005] A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET) having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

[0006] A method of constructing a radio frequency integrated circuit (RFIC) having a switch field effect transistor (FET) is described. The method includes coupling a gate region to a body region of the switch FET. The method also includes forming a dynamic bias control circuit between the gate region and the body region of the switch FET. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

[0007]

[0007] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the following Detailed Description may be better understood. Additional features and advantages of the present disclosure will be described below. Those skilled in the art will appreciate that the present disclosure may readily be utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood by considering the following description in conjunction with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended to define the limits of the present disclosure. [Brief explanation of the drawings]

[0008] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Figure 1]

[0009] 1 is a schematic diagram of a wireless device having a wireless local area network module and a radio frequency (RF) front-end module for a chipset. [Figure 2]

[0010] 1 illustrates a cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) including an RF silicon on insulator (SOI) device. [Figure 3]

[0011] FIG. 3A is a schematic diagram illustrating a switch field effect transistor (FET) that includes a body current bypass resistor for improved breakdown voltage and harmonic performance.

[0012] FIG. 3B is a schematic diagram illustrating a switch field effect transistor (FET) that includes a body current bypass resistor to further improve breakdown voltage and harmonic performance. [Figure 4]

[0013] FIG. 1 is a schematic diagram illustrating a switch stack including switch field effect transistors (FETs) with dynamic bias control circuitry according to aspects of the present disclosure. [Figure 5]

[0014] FIG. 1 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switch FET, in accordance with aspects of the present disclosure. [Figure 6]

[0015] FIG. 6 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switch FET, in accordance with aspects of the disclosure. [Figure 7]

[0016] FIG. 7 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switch FET, in accordance with aspects of the disclosure. [Figure 8]

[0017] FIG. 8 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switch FET, in accordance with aspects of the disclosure. [Figure 9]

[0018] FIG. 9 is a schematic diagram illustrating a radio frequency integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switch FET, in accordance with aspects of the disclosure. [Figure 10]

[0019] 10A and 10B are schematic diagrams illustrating radio frequency (RF) integrated circuits (RFICs) including switch field effect transistors (FETs) and dynamic bias control circuits for improving the performance of the switch FETs, according to aspects of the disclosure. [Figure 11]

[0020] FIG. 1 is a process flow diagram illustrating a method for constructing a radio frequency (RF) integrated circuit (RFIC) having dynamic bias control circuitry according to one aspect of the present disclosure. [Figure 12]

[0021] FIG. 1 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch field effect transistor (FET) and a dynamic bias control circuit for further improving the performance of the switch FET, in accordance with aspects of the present disclosure. [Figure 13]

[0022] FIG. 1 is a process flow diagram illustrating a method for constructing a radio frequency (RF) device having a dynamic bias control circuit according to aspects of the present disclosure. [Figure 14]

[0023] FIG. 1 is a block diagram illustrating an exemplary wireless communication system in which an aspect of the present disclosure may be advantageously employed. [Figure 15]

[0024] FIG. 1 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components, according to one configuration. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0025] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0026] As described herein, the use of the term "and / or" is intended to mean an "inclusive or," and the use of the term "or" is intended to mean an "exclusive or." As described herein, the term "exemplary" as used throughout this description means "serving as an example, instance, or illustration" and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used throughout this description means "connected electrically, mechanically, or otherwise, whether directly or indirectly through an intervening connection (e.g., a switch)," and is not necessarily limited to a physical connection. Furthermore, the connections may be such that the objects are permanently connected or releasably connected. The connections may be via a switch. As described herein, the term "adjacent" as used throughout this description means "adjacent, in close proximity, next to, or in close proximity." As described herein, the term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0011]

[0027] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) are migrating to deep submicron process nodes due to cost and power consumption considerations. Designing mobile RF transceivers can involve using semiconductor-on-insulator (SOI) technology. Semiconductor-on-insulator (SOI) technology replaces the traditional silicon substrate with a layered semiconductor-insulator-semiconductor substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from traditional silicon devices because the silicon junction resides above an electrical insulator, typically a buried oxide (BOX) layer. However, the reduced thickness of the BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of active devices on the SOI layer to the SOI substrate supporting the BOX layer.

[0012]

[0028] For example, the thickness of a BOX layer determines the distance between an active device and the SOI substrate, which is separated from the active device by the BOX layer. A sufficient distance between the active device and the SOI substrate is important for improving the performance of the active device. However, shrinking the device footprint to meet the specifications of future process nodes reduces the thickness of the BOX layer, which defines the distance between the active device and the SOI substrate. Reducing the thickness of the BOX layer in future process nodes can significantly degrade device performance due to artificial harmonics. That is, increasing the proximity of the active device to the SOI substrate in future process nodes degrades device performance.

[0013]

[0029] Active devices on the SOI layer can include high-performance complementary metal-oxide semiconductor (CMOS) transistors. For example, high-performance CMOS RF switch technologies are currently fabricated using SOI substrates. RF front ends (RFFEs) can rely on these high-performance CMOS RF switch technologies for successful operation. Therefore, processes for fabricating RFFEs require costly SOI wafer integration to support these high-performance CMOS RF switch technologies. Furthermore, support for future RF performance enhancements requires improving device isolation while simultaneously reducing RF losses.

[0014]

[0030] One technique for improving device isolation and reducing RF losses is to fabricate RFFEs using SOI wafers. For example, RF devices (e.g., RF switch devices) may include transistors fabricated using SOI wafers. Unfortunately, transistors fabricated using SOI technology can suffer from the floating-body effect, a phenomenon in which the body of a transistor collects charge generated at the junctions of the transistor device. In this case, charge accumulation in the body causes adverse effects, such as parasitic transistors within the structure and off-state leakage. Furthermore, the accumulated charge also causes the transistor's threshold voltage to depend on its previous state. The floating-body effect can also generate out-of-band harmonic frequencies that are detrimental to future communications enhancements.

[0015]

[0031] Various aspects of the present disclosure provide techniques related to dynamic bias control circuits for improving the breakdown voltage and harmonic performance of RF switch devices. The process flow for semiconductor fabrication of integrated RF circuits having RF switch devices may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term "layer" includes films and should not be construed as indicating vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to the substrate of a diced wafer or the substrate of an undiced wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0016]

[0032] Aspects of the present disclosure relate to a dynamic bias control circuit for improving the performance of an RF switch device. That is, aspects of the present disclosure employ dynamic control of at least one transistor of the dynamic bias control circuit to dynamically bias the body bias of the RF switch device. According to this aspect of the present disclosure, an RF integrated circuit (RFIC) includes a switch field effect transistor (FET) having a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit including at least one transistor coupled between the body region and the gate region of the switch FET.

[0017]

[0033] Some aspects of the present disclosure relate to a dynamic bias control circuit for further improving the performance of an RF switch device. Specifically, aspects of the present disclosure employ a dynamic bias control circuit formed between a gate region and a body region of a switch FET. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by an internal gate resistor. Furthermore, the dynamic bias control circuit includes a second transistor coupled to the body region of the switch FET by an internal body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by a gate resistor.

[0018]

[0034] 1 is a schematic diagram of a wireless device 100 (e.g., a cellular phone or smartphone) including a dynamic bias control circuit for improving the performance of a radio frequency (RF) switch device in accordance with aspects of the present disclosure. The wireless device 100 includes a wireless local area network (WLAN) (e.g., WiFi) module 150 and an RF front-end module 170 for a chipset 110. The WiFi module 150 includes a first diplexer 160 that communicatively couples an antenna 162 to a wireless local area network module (e.g., a WLAN module 152). The RF front-end module 170 includes a second diplexer 190 that communicatively couples an antenna 192 to a wireless transceiver 120 (WTR) via a duplexer 180 (DUP). An RF switch 172 communicatively couples the second diplexer 190 to the duplexer 180. The wireless transceiver 120 and the WLAN module 152 of the WiFi module 150 are coupled to a modem (MSM, e.g., a baseband modem) 130, which is powered by a power supply 102 via a power management integrated circuit (PMIC) 140. The chipset 110 also includes capacitors 112 and 114 and inductor(s) 116 to provide signal integrity. The PMIC 140, modem 130, wireless transceiver 120, and WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to a clock 118. The shape and placement of the various inductor and capacitor components within the chipset 110 can reduce electromagnetic coupling between the components.

[0019]

[0035] The wireless transceiver 120 of the wireless device generally includes a mobile RF transceiver for transmitting and receiving data for two-way communication. The mobile RF transceiver may include a transmit section for transmitting data and a receive section for receiving data. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal having an appropriate output power level, and transmit the amplified RF signal to a base station via an antenna 192. For data reception, the receive section may obtain a received RF signal via the antenna, amplify the received RF signal using a low noise amplifier (LNA), and process the received RF signal to recover the data in the communication signal sent by the base station.

[0020]

[0036] The wireless transceiver 120 may include one or more circuits for amplifying these communication signals. An amplifier circuit (e.g., an LNA / PA) may include one or more amplifier stages, which may have one or more driver stages and one or more amplifier output stages. Each amplifier stage includes one or more transistors configured in various ways to amplify the communication signals. Various options exist for fabricating transistors configured to amplify the communication signals transmitted and received by the wireless transceiver 120.

[0021]

[0037] The wireless transceiver 120 and RF front-end module 170 may be implemented using semiconductor-on-insulator (SOI) technology to fabricate the transistors of the wireless transceiver 120, which helps reduce high-order harmonics in the RF front-end module 170. SOI technology replaces the traditional semiconductor substrate with a layered semiconductor-insulator-semiconductor substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from traditional silicon devices because the silicon junction is above an electrical insulator, typically a buried oxide (BOX) layer. However, the reduced thickness of the BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of active devices on the SOI layer to the SOI substrate supporting the BOX layer. An active device fabricated using SOI technology is shown in FIG. 2.

[0022]

[0038] FIG. 2 shows a cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) 200. As shown in FIG. 2, the RF silicon-on-insulator (SOI) device includes an active device 210 on a buried oxide (BOX) layer 220 supported by an SOI substrate 202 (e.g., a silicon wafer). The RF SOI device may be fabricated as a CMOS transistor using a complementary metal-oxide-semiconductor (CMOS) process. The RF SOI device also includes an interconnect 250 coupled to the active device 210 within a first dielectric layer 206. In this configuration, the parasitic capacitance of the RF SOI device is proportional to the thickness of the BOX layer 220, which determines the distance between the active device 210 and the SOI substrate 202.

[0023]

[0039] The active device 210 on the BOX layer 220 may be a CMOS transistor. For example, high-performance CMOS RF switch technologies are currently fabricated using SOI substrates. The RFFE 170 (FIG. 1) may rely on these high-performance CMOS RF technologies for successful operation. Therefore, the process for fabricating the RFFE 170 requires the integration of SOI wafers to support these high-performance CMOS RF technologies. Furthermore, support for future RF performance enhancements requires improving device isolation while simultaneously reducing RF losses. The RF integrated circuit 200 may be used to implement the RFFE 170 of FIG. 1. For example, the active device 210 may be a switch field-effect transistor (FET) of the RF switch 172 of the RFFE 170.

[0024]

[0040] This configuration of RF integrated circuit 200 improves device isolation and reduces RF losses by using an SOI wafer to implement RFFE 170. Unfortunately, because RF integrated circuit 200 is fabricated using SOI technology, active device 210 can suffer from the floating-body effect, a phenomenon in which the body of a transistor collects charge generated at the junctions of the transistor. Charge accumulation in the body can cause adverse effects, such as parasitic transistors within the structure and off-state leakage (e.g., gate-induced drain leakage (GIDL) current). Furthermore, the accumulated charge can also cause the transistor's threshold voltage to depend on its previous state. The floating-body effect can also generate undesirable out-of-band harmonic frequencies that are detrimental to the communications enhancements integrated within RFFE 170.

[0025]

[0041] During an off state, the active device 210 (e.g., a switch field-effect transistor (FET)) isolates the RF integrated circuit from the input power (P). Isolation of the input power P by the active device 210 is improved by negatively biasing the gate of the active device 210 for hard turn-off of the active device 210. Unfortunately, negatively biasing the gate of the active device 210 can significantly increase the gate-drain voltage (Vgd) of the active device 210. A high gate-drain voltage Vgd causes positive charge to accumulate in the body of the active device 210, triggering a gate-induced drain leakage (GIDL) current. That is, a high potential difference between the gate and drain of the switch FET causes a GIDL current.

[0026]

[0042] Furthermore, when an RF signal is received at the drain of active device 210 that is biased in the off state, transmission of the RF signal along its intended path may be impaired if active device 210 is not completely isolated. For example, if the gate of active device 210 fails to isolate the RF signal from, for example, a power supply coupled to active device 210, the RF signal will be significantly impaired. Isolating the RF signal (e.g., the gate) from the power supply is sometimes referred to as RF isolation.

[0027]

[0043] Current switch products may include a body contact of a switch FET (e.g., active device 210) to extract stored charge in the body of the switch transistor by biasing the body contact independently of the switch FET's gate. Furthermore, a resistor may be used to RF isolate the switch FET's gate from the power supply. While these techniques provide RF isolation, biasing the body independently of biasing the switch FET's gate causes the body to move independently of the gate. This independent body movement may generate undesirable out-of-band harmonics. Furthermore, biasing the gate and body separately may require separate charge pumps to provide external gate and body voltages. However, using separate charge pumps consumes significant chip area on the RF integrated circuit 200.

[0028]

[0044] One technique for preventing independent body movement involves tying the body contact to the gate of the switch FET using a diode. Additionally, an external resistor may be coupled to the node connecting the gate and body to provide RF isolation of the gate from the power supply to protect the RF signal. While the external resistor provides RF isolation, a voltage drop across the external resistor (e.g., due to body current Ib) may reduce the voltage at the gate of the switch FET. This reduction in gate voltage (Vg) results in debiasing the gate of the switch FET by reducing the negative bias applied to the gate. Debiasing the gate of the switch FET prevents its gate from isolating the switch FET from the input power Pin.

[0029]

[0045] Because the breakdown voltage is a function of the gate voltage Vg, lowering the gate voltage Vg also lowers the breakdown voltage of the switch FET. That is, the gate voltage Vg is adversely affected by the body current Ib of the switch FET, which is caused by the voltage drop across an external resistor. As mentioned above, the body current Ib is based on the magnitude of the input power Pin at the gate of the switch FET. As a result, the maximum breakdown voltage of the switch FET is limited by the body current Ib of the switch FET, because the body current effectively lowers the gate voltage Vg.

[0030]

[0046] 3A is a schematic diagram showing a switch field-effect transistor (FET) including a body current bypass resistor for improved breakdown voltage and harmonic performance. In this configuration, an isolation diode is used to tie the gate and body of switch FET 300. In this embodiment, switch FET 300 does not include an external resistor to isolate switch FET 300 from a power supply that may be electrically coupled to the external voltage (Vext) node. Eliminating the external resistor may prevent debiasing of the gate of switch FET 300. Eliminating the external resistor allows the internal gate voltage (Vgint) node to equal the external voltage (Vext) of switch FET 300.

[0031]

[0047] In this configuration, a body bypass resistor (Rb) is coupled between the body and gate of switch FET 300. In this embodiment, an isolation diode is electrically coupled between body bypass resistor Rb and the body of switch FET 300. The resistance of body bypass resistor Rb can be reduced to allow charge to escape from the body of switch FET 300. A small body bypass resistor Rb provides RF isolation of the body by allowing charge to escape from the body through the isolation diode due to an increase in body voltage (Vb) without debiasing the gate. Furthermore, further prevention of gate debiasing can be achieved by electrically coupling a gate isolation resistor (Rg) between body bypass resistor Rb and the gate of switch FET 300.

[0032]

[0048] 3B is a schematic diagram illustrating a switch field-effect transistor (FET) 350 including a body current bypass resistor to further improve breakdown voltage and harmonic performance. In this embodiment, a gate isolation resistor (Rg) is electrically coupled between the gate and an internal voltage (Vint) node of the switch FET 350. Additionally, a body bypass resistor (Rb) is electrically coupled between the isolation diode and the body of the switch FET 350. In this embodiment, the isolation diode and gate isolation resistor Rg are both electrically coupled to the Vint node of the switch FET 350.

[0033]

[0049] 4, the resistance of the gate isolation resistor Rg is greater than or equal to the resistance of the body bypass resistor Rb. Furthermore, the size of the gate isolation resistor Rg is selected to adjust the switching time of the switch FET 350. Furthermore, the resistance of the body bypass resistor Rb can be reduced to allow charge to bleed off from the body of the switch FET 350. A small body bypass resistor Rb provides RF isolation of the body while allowing the regulated GIDL current to flow through the isolation diode to the external voltage (Vext) node without debiasing the gate.

[0034]

[0050] In operation, the isolation diode electrically couples the gate node and the body node of the switch FET 350 to ensure high linearity. Furthermore, the internal voltage Vint as well as the external voltage Vext are determined according to the voltage drop (Vdrop) across the body bypass resistor Rb (Vdrop=Ib * Rb). The switching time of switch FET 350 is adjusted according to gate isolation resistor Rg, independent of body bypass resistor Rb and without affecting gate voltage Vg. Furthermore, this switch FET 350 configuration supports a single charge pump, which significantly saves semiconductor chip area.

[0035]

[0051] The switch FET 300 configuration shown in FIG. 3A and the switch FET 350 configuration shown in FIG. 3B solve some of the previous problems associated with gate debiasing and provide area optimization for level shifters and charge pumps. Nevertheless, these switch FET 300 and switch FET 350 configurations suffer from the problem that the internal body voltage (Vbint) is lower than the external voltage (Vext) (e.g., Vext - diode voltage (Vdiode) - Vdrop ∼ 0.7V). Having an internal body voltage Vbint lower than the external voltage Vext adversely affects the breakdown of short-channel devices. Furthermore, these switch FET 300 and switch FET 350 configurations also suffer from higher real losses (represented by Rp), especially when implemented in a switch product such as that shown in FIG. 4.

[0036]

[0052] 4 is a schematic diagram illustrating a switch stack 400 including switch field effect transistors (FETs) with dynamic bias control circuitry in accordance with aspects of the present disclosure. In this example, the switch stack 400 is connected to an input RF voltage source (V rf ), coupled to an impedance (Z0). The gate voltage source (V g) coupled to the gate of each of the switch FETs in the switch stack 400; g ) in the shunt state (when the switch is open), the gates of the switch FETs in switch stack 400 are negatively biased. The negative bias causes a hard turn-off state that prevents input radio frequency signals (e.g., input power Pin) from passing between the drain and source of the switch FETs. Although described with reference to a semiconductor-on-insulator (SOI) wafer, it should be appreciated that switch stack 400 is not limited to SOI wafers and may be fabricated using bulk semiconductor wafers.

[0037]

[0053] Unfortunately, when the switch stack 400 is implemented using, for example, the switch FET 300 of FIG. 3A or the switch FET 350 of FIG. 3B, the switch stack 400 suffers from a higher real loss (represented by the parameter Rp). As described above, the net effect from parasitic losses to ground is represented by the real loss Rp. For example, the real loss Rp is calculated from measured antenna parameters (e.g., the S-parameter Y(11)), where the real loss Rp is equal to 1 / real[Y(11)]. At low frequencies, the real loss Rp is equal to the resistance (Rb) of all the bias resistors (N) in parallel (e.g., Rg / N).

[0038]

[0054] Switch FET 300 of FIG. 3A and switch FET 350 of FIG. 3B have resistors in both the body and gate regions. At low frequencies, the net loss Rp for this configuration is equal to the resistance Rb of all bias resistors N and the resistance Rb of the parallel bias resistors (e.g., (Rg∥Rb) / N), resulting in an increased net loss Rp. In practice, RF switches with reduced net loss Rp are important to achieve antenna efficiency, as shown, for example, in FIGS. 5-10B.

[0039]

[0055] 5 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) 500 including a switch field effect transistor (FET) 510 and a dynamic bias control circuit 520 for improving the performance of the switch FET 510, in accordance with aspects of the present disclosure. In this configuration, the dynamic bias control circuit 520 is used for dynamic biasing of the body of the switch FET 510. In this example, the switch FET 510 includes an external gate resistor (Rg,ext) for supplying power to the switch FET 510, which may be electrically coupled to an external gate voltage (Vg,ext) node. The gate of the switch FET 510 is coupled to the gate resistor Rg,ext to provide an internal gate voltage (Vg,int).

[0040]

[0056] In this configuration, dynamic bias control circuit 520 is electrically coupled between the body and gate of switch FET 510. In this embodiment, dynamic bias control circuit 520 includes an N-channel metal oxide semiconductor (NMOS) transistor 530 and a P-channel metal oxide semiconductor (PMOS) transistor 540. In these aspects of the disclosure, NMOS transistor 530 includes an NMOS source terminal (S), an NMOS drain terminal (D), an NMOS body terminal (B), and an NMOS gate terminal (G) coupled to the gate region of switch FET 510. Furthermore, PMOS transistor 540 includes a PMOS source terminal (S) coupled to the body region of switch FET 510 and a PMOS drain terminal (D) coupled to the NMOS drain terminal (D). PMOS transistor 540 also includes a PMOS body terminal (B) coupled to the NMOS body terminal (B), and a PMOS gate terminal (G) coupled to the NMOS source terminal (S) and the gate region of switch FET 510.

[0041]

[0057] In this configuration, the NMOS gate terminal (G) is coupled to the PMOS source terminal (S) and the body region of the switch FET 510. Additionally, the NMOS drain terminal (D) is coupled to the PMOS body terminal (B). As further shown in FIG. 5, an external gate resistor Rg,ext is coupled to the NMOS source terminal (S), the PMOS gate terminal (G), and the gate region of the switch FET 510. In some aspects of the present disclosure, the dynamic bias control circuit 520 significantly improves the on-state and off-state performance of the switch FET 510, such as important figures of merit (FOM), such as on-resistance (Ron), breakdown voltage (BVD), and net loss Rp. The dynamic bias control circuit 520 also significantly eliminates leakage issues that may be caused by debiasing the switch FET 510.

[0042]

[0058] 6 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) including a switch FET 610 and a dynamic bias control circuit 620 for improving the performance of the switch FET 610, in accordance with aspects of the present disclosure. As shown in FIG. 6, the RFIC 600 including the dynamic bias control circuit 620 is implemented using a transistor for dynamically biasing the body of the switch FET 610 to improve the performance of the switch FET 610. In this example, the switch FET 610 also includes an external resistor Rg,ext (e.g., a first gate resistor) for supplying power to the switch FET 610, which may be electrically coupled to an external gate voltage node Vg,ext.

[0043]

[0059] 6, dynamic bias control circuit 620 is electrically coupled between the body and gate of switch FET 610. In these examples, dynamic bias control circuit 620 is implemented using an N-channel metal oxide semiconductor field effect transistor (MOSFET). In some aspects of the present disclosure, the N-channel MOSFET includes a MOSFET source terminal coupled to the gate region of switch FET 610 and a MOSFET drain terminal coupled to the body region of switch FET 610. Furthermore, the N-channel MOSFET includes a MOSFET body terminal electrically coupled to the MOSFET gate terminal.

[0044]

[0060] Implementing dynamic bias control circuit 620 with a dynamically controlled N-channel MOSFET significantly improves the performance of switch FET 610. In some embodiments of the present disclosure, improved body biasing of switch FET 610 is achieved by connecting the MOSFET gate terminal and MOSFET body terminal of the N-channel MOSFET together to dynamically vary the gate potential of the N-channel MOSFET and switch FET 610. In operation, the biasing of dynamic bias control circuit 620 (e.g., gate voltage control (Vgcntrl) = body voltage control (Vbcntrl) = 0V) is performed during the on-state of switch FET 610 (e.g., switch gate voltage (Vgswitch) = positive control voltage).

[0045]

[0061] This dynamic bias control circuit 620 biasing results in an improved body voltage of switch FET 610 (e.g., Vbswitch=100 millivolts (mV)). Beneficially, the improved body voltage of switch FET 610 (e.g., Vbswitch=100 mV) exceeds the performance of a simple diode (approximately 0 V) ​​in the on-state and also exceeds independent body switch FET biasing configurations (e.g., Vbody=0). In the off-state of switch FET 610 (e.g., Vgswitch=negative control voltage), the dynamic bias control circuit 620 biasing (e.g., Vgcntrl=Vbcntrl=negative control voltage) is implemented.

[0046]

[0062] This dynamic bias control circuit 620 biasing results in an improved body voltage (e.g., Vbswitch ~ negative control voltage) of the switch FET 610 in the off-state. Beneficially, the improved body voltage (e.g., Vbswitch ~ negative control voltage) of the switch FET 610 exceeds the off-state performance of a simple diode (e.g., Vbint ~ negative control voltage + Vdiode). While similar to an independent body switch FET biasing configuration (e.g., Vbody = negative control voltage), this configuration results in a significantly higher net loss Rp, similar to a diode-connected body switch FET biasing configuration. In some aspects of the present disclosure, the dynamic bias control circuit 620 significantly improves the on-state and off-state performance of the switch FET 610, such as key figures of merit: on-resistance (Ron), breakdown voltage (BVD), and net loss Rp. The dynamic bias control circuit 620 results in a substantial (e.g., on the order of 15% to 25%) overall improvement in area reduction and / or performance improvement.

[0047]

[0063] 7 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) 700 including a switch FET 710 and a dynamic bias control circuit 720 for improving the performance of the switch FET 710, in accordance with aspects of the present disclosure. As shown in FIG. 7, the RFIC 700 includes the dynamic bias control circuit 720, which is also implemented using a transistor for dynamically biasing the body of the switch FET 710 to improve the performance of the switch FET 710. In this example, the switch FET 710 also includes an external resistor Rg,ext for supplying power to the switch FET 710, which may be electrically coupled to an external gate voltage node Vg,ext.

[0048]

[0064] 7, the dynamic bias control circuit 720 is electrically coupled between the body and gate of the switch FET 710. In this example, the dynamic bias control circuit 720 is implemented using a low threshold voltage (Vt) N-channel metal oxide semiconductor (NMOS) transistor. In some aspects of the present disclosure, the low Vt NMOS transistor includes an NMOS source terminal coupled to the gate region of the switch FET 710 and an NMOS drain terminal coupled to the body region of the switch FET 710. Furthermore, the low Vt NMOS transistor includes an NMOS body terminal electrically coupled to the NMOS gate terminal and the body region of the switch FET 710.

[0049]

[0065] Implementing dynamic bias control circuit 720 using a dynamically controlled low Vt NMOS transistor significantly improves the performance of switch FET 710. In some aspects of the present disclosure, connecting the NMOS gate and NMOS body terminals of the low Vt NMOS transistor to the body region of switch FET 710 eliminates additional biasing requirements for switch FET 710. For example, connecting the NMOS gate and NMOS body terminals of the low Vt NMOS transistor to the body region of switch FET 710 eliminates an additional level shifter for the body control transistor of RFIC 600 shown in FIG.

[0050]

[0066] In operation, during the on-state of switch FET 710 (e.g., Vgswitch = positive control voltage), an improved body voltage of switch FET 710 (e.g., Vbswitch = 260 mV) is achieved. Beneficially, the improved body voltage of switch FET 710 (e.g., Vbswitch = 200 mV) exceeds the performance of a simple diode (~7 mV) and also exceeds the performance of a separate body switch FET biasing configuration (e.g., Vbody = 0). During the off-state of switch FET 710 (e.g., Vgswitch = negative control voltage), the biasing of dynamic bias control circuit 720 (e.g., Vgcntrl = Vbcntrl = negative control voltage) is implemented. The biasing of dynamic bias control circuit 720 results in an improved body voltage of switch FET 710 (e.g., Vbswitch ~ negative control voltage).

[0051]

[0067] Beneficially, the improved body voltage of the switch FET 710 (e.g., Vbswitch ~ negative control voltage) exceeds the performance of a single diode configuration (e.g., Vbint ~ negative control voltage + Vdiode). While similar to an independent body switch FET biasing configuration (e.g., Vbody = ~ negative control voltage), this configuration results in significantly higher net losses Rp, similar to the diode configuration shown in Figures 3A and 3B. In some aspects of the present disclosure, the dynamic bias control circuit 720 significantly improves the on-state and off-state performance of the switch FET 710, such as key figures of merit: on-resistance (Ron), breakdown voltage (BVD), and net losses Rp.

[0052]

[0068] 8 is a schematic diagram illustrating a radio frequency integrated circuit (RFIC) including a switch FET 810 and a dynamic bias control circuit 820 for improving the performance of the switch FET 810 in accordance with aspects of the present disclosure. As shown in FIG. 8, the RFIC 800 includes the dynamic bias control circuit 820 implemented using a transistor for dynamically biasing the body of the switch FET 810 to improve the performance of the switch FET 810. In this example, the switch FET 810 also includes an external resistor Rg,ext for supplying power to the switch FET 810, which may be electrically coupled to an external gate voltage node Vg,ext. In some aspects of the present disclosure, the dynamic bias control circuit 820 is implemented by replacing the N-channel metal oxide semiconductor field effect transistor (MOSFET) of FIG. 6 with a P-channel MOSFET of FIG. 8.

[0053]

[0069] FIG. 9 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) 900 including a switch FET 910 and a dynamic bias control circuit 920 for improving the performance of the switch FET 910, according to aspects of the present disclosure. As shown in FIG. 9, the RFIC 900 includes the dynamic bias control circuit 920, which is also implemented using a low threshold voltage (Vt) transistor for dynamically biasing the body of the switch FET 910 to improve the performance of the switch FET 910. In this example, the switch FET 910 also includes an external resistor Rg,ext for supplying power to the switch FET 910, which may be electrically coupled to an external gate voltage node Vg,ext. In some aspects of the present disclosure, the dynamic bias control circuit 920 is implemented by using a low voltage threshold (Vt) P-channel metal oxide semiconductor (PMOS) transistor. In this example, the low Vt PMOS transistor includes a PMOS source terminal coupled to the gate region of the switch FET 910 and a PMOS drain terminal coupled to the body region of the switch FET 910. Additionally, the low Vt PMOS transistor includes a PMOS gate terminal, a PMOS source terminal, and a PMOS body terminal electrically coupled to the body region of the switch FET 910 .

[0054]

[0070] 10A and 10B are schematic diagrams illustrating radio frequency (RF) integrated circuits (RFICs) including switch field effect transistors (FETs) and dynamic bias control circuits for improving the performance of the switch FETs, according to aspects of the present disclosure. As shown in FIG. 10A, RFIC 1000 includes switch FET 810 and dynamic bias control circuit 820 of FIG. 8, as well as resistor 860 electrically coupled to the MOSFET gate terminal. As shown in FIG. 10B, RFIC 1050 includes switch FET 610 and dynamic bias control circuit 620 of FIG. 6, as well as resistor 660 (e.g., a second gate resistor) electrically coupled to the MOSFET gate terminal.

[0055]

[0071] Referring again to FIG. 5, this configuration of dynamic bias control circuit 520 as a combination NMOS / PMOS transistor control circuit eliminates the issues associated with higher on-state currents associated with conventional switch FET biasing configurations. In operation, during the on-state of switch FET 510, the internal body voltage (Vb,int) is approximately equal to 82 mV (e.g., Vb,int ∼ 82 mV), similar to low threshold voltage gate biasing control transistors, such as those shown in FIGS. 6, 8, 10A, and 10B. The dynamic bias control circuit 520 configuration shown in FIG. 5 outperforms both diode-connected and independent body switch FET biasing configurations. In operation, during the off-state, the internal body voltage (Vb,int) of switch FET 510 is approximately equal to ∼ the negative control voltage (e.g., Vbint ∼ the negative control voltage). This off-state behavior is similar to the independent body switch FET biasing configuration, but with twice the actual loss (e.g., ∼2×Rp), and exceeds the performance of the diode-connected body switch FET biasing configuration (e.g., Vbint = ∼negative control voltage + Vdiode).

[0056]

[0072] Various aspects of the present disclosure provide dynamic body-biasing techniques for improving switch FET performance by using dynamic bias control circuits, such as those shown in FIGS. 5-10B. Some aspects of the present disclosure provide a combination NMOS / PMOS transistor control circuit for implementing dynamic body-biasing of a switch FET, for example, as shown in FIG. 5. In other aspects of the present disclosure, the combination NMOS / PMOS transistor control circuit may be replaced with dynamically controlled MOSFETs (e.g., FIGS. 6, 8, 10A, and 10B) and low threshold voltage transistors (e.g., FIGS. 7 and 9). A method of constructing an RFIC with a dynamic body-bias control circuit according to aspects of the present disclosure is shown in FIG. 11.

[0057]

[0073] 11 is a process flow diagram illustrating a method for constructing a radio frequency (RF) integrated circuit (RFIC) with a dynamic bias control circuit according to one embodiment of the present disclosure. Method 1100 begins at block 1102, where a gate region is coupled to a body region of a switch field effect transistor (FET). For example, as shown in FIGS. 5-10B, a gate region is coupled to the body region of switch FETs 510 / 610 / 710 / 810 / 910.

[0058]

[0074] In block 1104, a dynamic bias control circuit is formed between the gate and body region of the switch FET. For example, in FIGS. 5-10B, the dynamic bias control circuit 520 / 620 / 720 / 820 / 920 is formed between the gate and body region of the switch FET 510 / 610 / 710 / 810 / 910. As further shown in FIG. 11, in block 1104, the dynamic bias control circuit includes at least one transistor between the gate and body region of the switch FET. For example, as shown in FIG. 5, the dynamic bias control circuit 520 includes an N-channel metal oxide semiconductor (NMOS) transistor 530 and a P-channel metal oxide semiconductor (PMOS) transistor 540. In this embodiment, the NMOS source terminal is coupled to the gate region of the switch FET 510, and the PMOS drain terminal is coupled to the NMOS drain terminal. Furthermore, the PMOS source terminal is coupled to the body region of the switch FET 510 to perform dynamic body biasing of the switch FET 510. In other aspects of the present disclosure, the control circuitry of the NMOS transistor 530 / PMOS transistor 540 combination of the dynamic bias control circuit 520 may be replaced with dynamically controlled metal oxide semiconductor field effect transistors (MOSFETs) (e.g., FIGS. 6, 8, 10A, and 10B) or low threshold voltage transistors (e.g., FIGS. 7 and 9).

[0059]

[0075] Aspects of the present disclosure relate to a dynamic bias control circuit for improving the performance of an RF switch device. That is, aspects of the present disclosure employ dynamic control of at least one transistor of the dynamic bias control circuit to dynamically bias the body bias of the RF switch device. According to these aspects of the present disclosure, an RFIC includes a switch FET having a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit including at least one transistor coupled between the body region and the gate region of the switch FET.

[0060]

[0076] According to a further aspect of the present disclosure, an RF integrated circuit is described that includes a switch FET. The switch FET includes means for dynamically biasing a body region of the switch FET. The dynamic biasing means may be the dynamic body-bias control circuit shown in FIGS. 5-10B. In another aspect, the means may be any module or any device configured to perform the functions recited by the means.

[0061]

[0077] 12 is a schematic diagram illustrating a radio frequency (RF) integrated circuit (RFIC) 1200 including a switch field effect transistor (FET) 1210 and a dynamic bias control circuit 1220 for improving the performance of the switch FET 1210, according to aspects of the present disclosure. In this configuration, the RFIC 1200 is similar to the RFIC 500 shown in FIG. 5 and will be described using like reference characters and numerals. In some aspects of the present disclosure, the RFIC 1200 incorporates an internal gate resistor (Rg,int) and an internal body resistor (Rb,int) within the dynamic bias control circuit 1220, which improves both the internal body voltage (Vb,int) and the internal gate voltage (Vg,int) of the switch FET 1210.

[0062]

[0078] In this embodiment, the gate region of switch FET 1210 is coupled to an internal gate resistor (Rg,int) and dynamic bias control circuit 1220 to supply power to switch FET 1210, which may be electrically coupled to an external gate voltage (Vg,ext) node. The gate region of switch FET 1210 is coupled to the internal gate resistor (Rg,int) to provide the internal gate voltage (Vg,int). Furthermore, the body region of switch FET 1210 is coupled to an internal body resistor (Rb,int) to provide the internal body voltage (Vb,int).

[0063]

[0079] In this configuration, the dynamic bias control circuit 1220 is also electrically coupled between the body and gate regions of the switch FET 1210. Furthermore, the dynamic bias control circuit 1220 includes an N-channel metal oxide semiconductor (NMOS) transistor 1230 and a P-channel metal oxide semiconductor (PMOS) transistor 1240. In these aspects of the disclosure, the NMOS transistor 1230 includes an NMOS source terminal (S) coupled to the gate region of the switch FET 1210 by an internal gate resistor (Rg,int). Furthermore, the PMOS transistor 1240 includes a PMOS source terminal (S) coupled to the body region of the switch FET 1210 by an internal body resistor (Rb,int). The NMOS transistor 1230 further includes an NMOS drain terminal (D), an NMOS body terminal (B), and an NMOS gate terminal (G). Similarly, PMOS transistor 1240 includes a PMOS source terminal (S) coupled to the body region of switch FET 1210 and a PMOS drain terminal (D) coupled to the NMOS drain terminal (D).

[0064]

[0080] Furthermore, the PMOS transistor 1240 includes a PMOS body terminal (B) coupled to the NMOS body terminal (B) and the PMOS drain terminal (D), and a PMOS gate terminal (G) coupled to the NMOS source terminal (S) and coupled to the gate region of the switch FET 1210 by an internal gate resistor (Rg,int). In some embodiments of the present disclosure, the dynamic bias control circuit 1220 includes a capacitor having a first terminal coupled to the NMOS source terminal (S) and a second terminal coupled to the PMOS source terminal (S). In this configuration, the NMOS gate terminal (G) is coupled to the PMOS source terminal (S) and coupled to the body region of the switch FET 1210 by an internal body resistor (Rb,int). Furthermore, the NMOS drain terminal (D) and the NMOS body terminal (B) are coupled together and to the PMOS body terminal (B) and PMOS drain terminal (D), which are also coupled together. As further shown in FIG. 12, an internal gate resistor (Rg,int) is coupled to the NMOS source terminal (S), the PMOS gate terminal (G), and the gate region of the switch FET 1210.

[0065]

[0081] In some aspects of the present disclosure, the dynamic bias control circuit 1220 significantly improves the on-state and off-state performance of the switch FET 1210, such as the on-resistance (Ron), off-capacitance (Coff), breakdown voltage (BVD), and real loss (Rp), as well as the figure of merit (FOM) according to equation (1) below: FOM=(Ron * Coff) / BVD 2 (1)

[0066]

[0082] The dynamic bias control circuit 1220 eliminates leakage that can be caused by debiasing the switch FET 1210. Furthermore, by selecting appropriate resistance values ​​for the internal gate resistor (Rg,int) and / or the internal body resistor (Rb,int), the dynamic bias control circuit 1220 improves both the internal gate voltage (Vg,int) and the internal body voltage (Vb,int), which also improves the real loss (Rp). In particular, the improved real loss (Rp) results in a significantly improved form of material (FOM) and a reduction in area (e.g., by 21%), which reduces cost and improves performance. The dynamic bias control circuit 1220 advantageously avoids additional level shifters and / or charge pumps to provide dynamic terminal biasing of the switch FET 1210.

[0067]

[0083] The biasing of the dynamic bias control circuit 1220 results in an improved body voltage of the switch FET 1210 (e.g., Vbswitch = 385 millivolts (mV)). Advantageously, the improved body voltage of the switch FET 1210 (e.g., Vbswitch = 385 mV) exceeds the performance of a simple diode (approximately 0 V) ​​in the on-state and also exceeds that of an independent body switch FET biasing configuration (e.g., Vbody = 0). In the off-state of the switch FET 1210 (e.g., Vgswitch = negative control voltage), the biasing of the dynamic bias control circuit 1220 (e.g., Vgcntrl = Vbcntrl = negative control voltage) is implemented. This configuration results in significantly higher net losses (Rp), similar to a diode-connected body switch FET biasing configuration. Advantageously, the dynamic bias control circuit 1220 configuration works for both switch FETs with high gate-induced drain leakage (GIDL) current as well as switch FETs with low GIDL current. A method for constructing an RFIC with dynamic body-bias control circuitry according to these aspects of the disclosure is shown in FIG.

[0068]

[0084] 13 is a process flow diagram illustrating a method for constructing a radio frequency (RF) device with a dynamic bias control circuit according to one embodiment of the present disclosure. The method 1300 begins at block 1302, where a gate region is coupled to a body region of a switch field effect transistor (FET). For example, as shown in FIG. 12, the gate region is coupled to the body region of switch FET 1210.

[0069]

[0085] In block 1304, a dynamic bias control circuit is formed between the gate and body region of the switch FET. For example, in FIG. 12, the dynamic bias control circuit 1220 is formed between the gate and body region of the switch FET 1210. As further shown in FIG. 13, in block 1304, the dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. For example, as shown in FIG. 12, the dynamic bias control circuit 1220 includes an N-channel metal-oxide-semiconductor (NMOS) transistor 1230, where the NMOS source terminal (S) is coupled to the gate region of the switch FET 1210 by an internal gate resistor (Rg,int). Further, as shown in block 1304, the dynamic bias control circuit includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. 12, the dynamic bias control circuit 1220 includes a PMOS transistor 1240, the PMOS source terminal (S) of which is coupled to the body region of the switch FET 1210 by an internal body resistor (Rb,int). As further shown in FIG. 13, in block 1304, the dynamic bias control circuit includes a capacitor coupled to the body region of the switch FET by the body resistor and coupled to the gate region of the switch FET by a gate resistor. For example, as shown in FIG. 12, the dynamic bias control circuit 1220 includes a capacitor (C) coupled to the body region of the switch FET 1210 by an internal body resistor (Rb,int) and coupled to the gate region of the switch FET 1210 by an internal gate resistor (Rg,int).

[0070]

[0086] FIG. 14 is a block diagram illustrating an exemplary wireless communication system 1400 that may advantageously employ an aspect of the present disclosure. For illustrative purposes, FIG. 14 shows three remote units 1420, 1430, and 1450 and two base stations 1440. It will be appreciated that a wireless communication system may have many more remote units and base stations. The remote units 1420, 1430, and 1450 include IC devices 1425A, 1425C, and 1425B that include the disclosed switch field-effect transistors (FETs) and dynamic bias control circuits. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed switch field-effect transistors (FETs) and dynamic bias control circuits. FIG. 14 shows forward link signals 1480 from base station 1440 to remote units 1420, 1430, and 1450, and reverse link signals 1490 from remote units 1420, 1430, and 1450 to base station 1440.

[0071]

[0087] In FIG. 14 , remote unit 1420 is illustrated as a mobile phone, remote unit 1430 is illustrated as a portable computer, and remote unit 1450 is illustrated as a fixed-location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, portable data units such as handheld personal communication systems (PCS) units, personal digital assistants (PDAs), fixed-location data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading equipment, or other communication devices that store or retrieve data or computer instructions, or combinations thereof. While FIG. 14 illustrates remote units according to aspects of the present disclosure, the present disclosure is not limited to these illustrated example units. Aspects of the present disclosure may be suitably employed in many devices, including the disclosed switch field-effect transistors (FETs) and dynamic bias control circuits.

[0072]

[0088] FIG. 15 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components, such as the switch field-effect transistors (FETs) and dynamic bias control circuits disclosed above. The design workstation 1500 includes a hard disk 1501 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 1500 also includes a display 1502 for facilitating the display of a circuit design 1510 or RFIC 1512. A storage medium 1504 is provided for tangibly storing the circuit design 1510 or RFIC 1512. The circuit design 1510 or RFIC 1512 may be stored on the storage medium 1504 in a file format such as GDSII or GERBER. The storage medium 1504 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Additionally, design workstation 1500 includes a drive device 1503 for accepting input from or writing output to storage medium 1504 .

[0073]

[0089] The data recorded on storage medium 1504 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous write tools such as electron beam lithography. The data may also include logic verification data, such as timing diagrams or net circuits associated with logic simulations. Providing data on storage medium 1504 facilitates the design of circuit design 1510 or RFIC 1512 by reducing the number of processes for designing a semiconductor wafer.

[0074]

[0090] The following numbered clauses describe example implementations. 1. A radio frequency (RF) device, comprising: a switch field effect transistor (FET) including a source region, a drain region, a body region, and a gate region; 1. A dynamic bias control circuit comprising: a first transistor coupled to a gate region of the switch FET by a gate resistor; a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor; a capacitor coupled to a body region of the switch FET by a body resistor and to a gate region of the switch FET by a gate resistor. 2. The first transistor is an N-channel metal-oxide-semiconductor (NMOS) transistor, an NMOS source terminal coupled to the gate region of the switch FET by a gate resistor and to a first terminal of the capacitor; an NMOS drain terminal coupled to the second transistor; an NMOS body terminal coupled to the second transistor and coupled to the NMOS drain terminal; 10. The RF device of claim 1, comprising an NMOS transistor; and an NMOS gate terminal coupled to the second transistor. 3. The RF device of clause 2, wherein the NMOS gate terminal is coupled to the body region of the switch FET by a body resistor and to the second terminal of the capacitor. 4. The second transistor is A P-channel metal oxide semiconductor (PMOS) transistor, a PMOS source terminal coupled to the body region of the switch FET by a body resistor; a PMOS drain terminal coupled to the NMOS drain terminal and the NMOS body terminal; a PMOS body terminal coupled to the NMOS transistor; 4. The RF device of any of clauses 2 or 3, comprising a PMOS transistor; and a PMOS gate terminal coupled to the NMOS transistor. 5. The RF device of clause 4, wherein the PMOS source terminal is coupled to the second terminal of the capacitor and to the NMOS gate terminal. 6. The RF device of any of clauses 4 or 5, wherein the PMOS drain terminal is coupled to the NMOS body terminal and to the PMOS body terminal. 7. The RF device of any of clauses 4 to 6, wherein the PMOS body terminal is coupled to the NMOS body terminal and to the NMOS drain terminal and the PMOS drain terminal. 8. The RF device of any of clauses 4 to 7, wherein the PMOS gate terminal is coupled to the NMOS source terminal and to the gate region of the switch FET by a gate resistor, and to a first terminal of the capacitor. 9. The RF device of any of clauses 4 to 8, wherein the NMOS gate terminal is coupled to the PMOS source terminal and to the body region of the switch FET by a body resistor and to the second terminal of the capacitor. 10. The RF device of any of clauses 1 to 9, integrated into an RF front-end module, the RF front-end module being incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer. 11. A method of constructing a radio frequency integrated circuit (RFIC) having a switch field effect transistor (FET), comprising: coupling a gate region to a body region of a switch FET; forming a dynamic bias control circuit between the gate region and the body region of the switch FET, the dynamic bias control circuit comprising: a first transistor coupled to a gate region of the switch FET by a gate resistor; a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor; a capacitor coupled to the body region of the switch FET by a body resistor and to the gate region of the switch FET by a gate resistor. 12. A first transistor is an N-channel metal-oxide-semiconductor (NMOS) transistor, an NMOS source terminal coupled to the gate region of the switch FET by a gate resistor and to a first terminal of the capacitor; an NMOS drain terminal coupled to the second transistor; an NMOS body terminal coupled to the second transistor and coupled to the NMOS drain terminal; 12. The method of clause 11, including an NMOS transistor; and an NMOS gate terminal coupled to the second transistor. 13. The method of clause 12, wherein the NMOS gate terminal is coupled to the body region of the switch FET by a body resistor and to the second terminal of the capacitor. 14. A second transistor is A P-channel metal oxide semiconductor (PMOS) transistor, a PMOS source terminal coupled to the body region of the switch FET by a body resistor; a PMOS drain terminal coupled to the NMOS drain terminal and the NMOS body terminal; a PMOS body terminal coupled to the NMOS transistor; 14. The method of any of clauses 12 or 13, comprising a PMOS transistor including a PMOS gate terminal coupled to the NMOS transistor. 15. The method of clause 14, wherein the PMOS source terminal is coupled to the second terminal of the capacitor and to the NMOS gate terminal. 16. The method of any of clauses 14 or 15, wherein the PMOS drain terminal is coupled to the NMOS body terminal and to the PMOS body terminal. 17. The method of any of clauses 14-16, wherein the PMOS body terminal is coupled to the NMOS body terminal and to the NMOS drain terminal and the PMOS drain terminal. 18. The method of any of clauses 14-17, wherein the PMOS gate terminal is coupled to the NMOS source terminal and to the gate region of the switch FET by a gate resistor and to the first terminal of the capacitor. 19. The method of any of clauses 14-18, wherein the NMOS gate terminal is coupled to the PMOS source terminal and to the body region of the switch FET by a body resistor and to the second terminal of the capacitor. 20. The method of any of clauses 11-19, further comprising integrating the RFIC into an RF front-end module, wherein the RF front-end module is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0075]

[0091] For a firmware and / or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. Implementing the methodologies described herein may involve the use of machine-readable media tangibly embodying instructions. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" may refer to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and should not be limited to a specific type of memory, or a specific number of memories, or to a specific type of medium on which the memory is stored.

[0076]

[0092] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0077]

[0093] In addition to storage on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium contained within a communications device. For example, a communications device may include a transceiver having signals indicative of instructions and data configured to cause one or more processors to implement the functions outlined in the claims.

[0078]

[0094] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "above" and "below" are used in reference to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Furthermore, if placed on its side, above and below may refer to the side of the substrate or electronic device. Furthermore, the scope of the present application is not intended to be limited to the particular configurations of processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. Those skilled in the art will readily appreciate from this disclosure that existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding configurations described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. 1. A radio frequency (RF) device comprising: a switch field effect transistor (FET) including a source region, a drain region, a body region, and a gate region; 1. A dynamic bias control circuit comprising: a first transistor coupled to the gate region of the switch FET by a gate resistor; a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor; a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

2. The first transistor is an N-channel metal oxide semiconductor (NMOS) transistor, an NMOS source terminal coupled to the gate region of the switch FET by the gate resistor and to a first terminal of the capacitor; an NMOS drain terminal coupled to the second transistor; an NMOS body terminal coupled to the second transistor and to the NMOS drain terminal; 10. The RF device of claim 1, comprising an NMOS transistor; and an NMOS gate terminal coupled to said second transistor.

3. 3. The RF device of claim 2, wherein the NMOS gate terminal is coupled to the body region of the switch FET by the body resistor and to a second terminal of the capacitor.

4. The second transistor is a P-channel metal oxide semiconductor (PMOS) transistor, a PMOS source terminal coupled to the body region of the switch FET by the body resistor; a PMOS drain terminal coupled to the NMOS drain terminal and the NMOS body terminal; a PMOS body terminal coupled to the NMOS transistor; 3. The RF device of claim 2, comprising a PMOS transistor including a PMOS gate terminal coupled to said NMOS transistor.

5. 5. The RF device of claim 4, wherein the PMOS source terminal is coupled to the second terminal of the capacitor and to the NMOS gate terminal.

6. 5. The RF device of claim 4, wherein the PMOS drain terminal is coupled to the NMOS body terminal and to the PMOS body terminal.

7. 5. The RF device of claim 4, wherein the PMOS body terminal is coupled to the NMOS body terminal and to the NMOS drain terminal and the PMOS drain terminal.

8. 5. The RF device of claim 4, wherein the PMOS gate terminal is coupled to the NMOS source terminal and to the gate region of the switch FET by the gate resistor and to the first terminal of the capacitor.

9. 5. The RF device of claim 4, wherein the NMOS gate terminal is coupled to the PMOS source terminal and to the body region of the switch FET by the body resistor and to a second terminal of the capacitor.

10. 10. The RF device of claim 1, wherein the RF device is integrated into an RF front-end module, the RF front-end module being incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

11. 1. A method of constructing a radio frequency integrated circuit (RFIC) having switch field effect transistors (FETs), comprising: coupling a gate region to a body region of the switch FET; forming a dynamic bias control circuit between the gate region and the body region of the switch FET, the dynamic bias control circuit comprising: a first transistor coupled to the gate region of the switch FET by a gate resistor; a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor; a capacitor coupled to the body region of the switch FET by the body resistor and to the gate region of the switch FET by the gate resistor.

12. The first transistor is an N-channel metal oxide semiconductor (NMOS) transistor, an NMOS source terminal coupled to the gate region of the switch FET by the gate resistor and to a first terminal of the capacitor; an NMOS drain terminal coupled to the second transistor; an NMOS body terminal coupled to the second transistor and to the NMOS drain terminal; an NMOS gate terminal coupled to the second transistor; and

13. 13. The method of claim 12, wherein the NMOS gate terminal is coupled to the body region of the switch FET by the body resistor and to a second terminal of the capacitor.

14. The second transistor is a P-channel metal oxide semiconductor (PMOS) transistor, a PMOS source terminal coupled to the body region of the switch FET by the body resistor; a PMOS drain terminal coupled to the NMOS drain terminal and the NMOS body terminal; a PMOS body terminal coupled to the NMOS transistor; a PMOS gate terminal coupled to the NMOS transistor.

15. 15. The method of claim 14, wherein the PMOS source terminal is coupled to the second terminal of the capacitor and to the NMOS gate terminal.

16. 15. The method of claim 14, wherein the PMOS drain terminal is coupled to the NMOS body terminal and to the PMOS body terminal.

17. 15. The method of claim 14, wherein the PMOS body terminal is coupled to the NMOS body terminal and to the NMOS drain terminal and the PMOS drain terminal.

18. 15. The method of claim 14, wherein the PMOS gate terminal is coupled to the NMOS source terminal and the gate region of the switch FET by the gate resistor and to the first terminal of the capacitor.

19. 15. The method of claim 14, wherein the NMOS gate terminal is coupled to the PMOS source terminal and to the body region of the switch FET by the body resistor and to a second terminal of the capacitor.

20. 12. The method of claim 11, further comprising integrating the RFIC into an RF front-end module, wherein the RF front-end module is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

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