Bonding layer in semiconductor device and process for manufacturing same

Abstract

The method includes providing a first substrate having a first surface comprising an alkyne moiety. The method includes providing a second substrate having a second surface comprising an azide moiety. The method further includes bonding the first substrate to the second substrate. Bonding the first substrate to the second substrate includes physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 438,362, entitled "BONDING LAYER AND PROCESS," filed January 11, 2023, and U.S. Non-Provisional Patent Application No. 18 / 320,791, entitled "BONDING LAYER AND PROCESS OF FABRICATING THE SAME IN SEMICONDUCTOR DEVICES," filed May 19, 2023, the entire disclosures of which are incorporated herein by reference for all purposes.

[0002] The present disclosure relates to methods of semiconductor manufacturing, and more particularly to bonding multiple semiconductor substrates. [Background technology]

[0003] To continue the power-performance-area-cost (PPAC) scaling of complex circuits, such as those implemented in systems-on-chips (SOCs), wafer-to-wafer bonding, chip-to-chip bonding, and chip-to-wafer bonding (generally substrate bonding) are being implemented. Many bonding techniques, such as direct bonding and hybrid bonding, often utilize high pressure and / or high temperature to achieve reliable oxide-to-oxide bonding adhesion between substrates. Lower temperature bonding techniques with excellent adhesion are desired.

[0004] 1 illustrates several steps of a conventional process for bonding two semiconductor substrates (e.g., wafers) to form a semiconductor structure 100, which is well known and has been abbreviated and simplified here for illustrative purposes. The semiconductor substrate 101 includes a base substrate 102 and a plurality of active devices, metallization, and other circuit features disposed within and / or on the base substrate 102. A dielectric layer 104 is formed on the base substrate 102. The conductive features 106 may include copper (Cu). The conductive features 106 are formed at or below a bonding surface 108 of the dielectric layer 104. The bonding surface 108 is configured to engage and bond to another bonding surface 108 disposed on a different semiconductor substrate 101 to form the semiconductor structure 100. The dielectric layer 104 may include an oxide, nitride, carbide, or the like, or a combination thereof, as is well known and described elsewhere. The conductive features 106 are often recessed below the bonding surfaces 108 to ensure that when the two bonding surfaces are brought together, a strongly bonded dielectric interface is formed in front of the conductive features 106, protruding and contacting each other across the bonding interface 110 therebetween. Referring to FIG. 1A, the bonding surfaces 108 are activated using a plasma (e.g., N plasma and / or O plasma) to prepare the surfaces for bonding. Referring to FIG. 1B, hydration is often provided to further enhance the bonding ability of the bonding surfaces 108. Referring to FIG. 1C, the bonding surfaces 108 of the two semiconductor substrates 101 are aligned and brought into contact at the bonding interface 110. As shown in FIG. 1D, an annealing step may improve the inter-dielectric bond and / or expand the conductive contacts toward each other, forming physical and electrical contact as part of the semiconductor structure 100. One or both of the substrates may be thinned (not shown) as needed for a given application. Summary of the Invention [Problem to be solved by the invention]

[0005] Existing bonding processes can be complex and expensive to implement. Forming Si-O bonds at the bonding interface (between two opposing dielectric layers) can rely on plasma activation, as illustrated in FIG. 1A, followed by a water treatment, as illustrated in FIG. 1B. In some cases, such treatment processes can be subject to queue time lag limitations. Furthermore, the bonding interface can exhibit limited bond strength, which can be reversible using certain techniques, such as inserting a blade into the bonding interface. In some cases, the bond strength can be weakened due to environmental or processing issues. The hydration step (as illustrated in FIG. 1B) can also be problematic in that it can cause oxidation of copper-based conductive features, thereby increasing resistivity. Therefore, an alternative procedure for implementing a direct or hybrid bonding process without relying on activation and hydration processes is desirable. [Means for solving the problem]

[0006] Described herein are structures and techniques for improving bonding between substrates. According to one implementation, a direct covalent bond is formed between two substrates, where a first substrate (or wafer) includes a first bonding surface having a first bonding layer functionalized with azide-terminated moieties, and a second substrate (or wafer) includes a second bonding surface having a second bonding layer functionalized with alkyne-terminated moieties. When the bonding surfaces are brought into contact and a heat treatment is applied, these moieties form triazole bonds at the interface having a cyclic structure with covalent properties, resulting in a stronger bond across the interface.

[0007] In one aspect, the present disclosure provides a method comprising providing a first substrate having a first surface comprising an alkyne moiety. The method comprises providing a second substrate having a second surface comprising an azide moiety. The method further comprises bonding the first substrate to the second substrate. Bonding the first substrate to the second substrate comprises creating physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.

[0008] In some implementations, the alkyne moiety is attached to the first substrate via a first base molecule, and the azide moiety is attached to the second substrate via a second base molecule.

[0009] In some implementations, providing the first substrate includes applying a first self-assembled monolayer (SAM) over the first surface, the first SAM having an alkyne moiety extending from the first surface, hi some implementations, providing the second substrate includes applying a second SAM over the second surface, the second SAM having an azide moiety extending from the second surface.

[0010] In some implementations, the first SAM and the second SAM are each applied using a selective deposition process. In some implementations, providing the first substrate further includes functionalizing the first surface before applying the first SAM, and providing the second substrate further includes functionalizing the second surface before applying the second SAM. In some implementations, applying the first SAM and the second SAM includes depositing the first SAM and the second SAM, respectively, as blanket layers and removing portions of the first SAM and the second SAM. In some implementations, the first surface includes a first conductive feature disposed on a first dielectric layer, and the second surface includes a second conductive feature disposed on a second dielectric layer, and the first SAM and the second SAM are selectively formed on the first dielectric layer and the second dielectric layer, respectively.

[0011] In some implementations, bonding the first substrate to the second substrate includes applying a heat treatment to activate the cycloaddition mechanism.

[0012] In another aspect, the present disclosure provides a method comprising providing a first substrate having a first mating surface comprising an alkyne group. The method comprises providing a second substrate having a second mating surface comprising an azide group. The method comprises bonding the first substrate to the second substrate by establishing physical contact between the first and second mating surfaces to be bonded. The method further comprises performing a thermal treatment to cause a cycloaddition process to occur between the bonded first and second mating surfaces.

[0013] In some implementations, bonding the first substrate to the second substrate includes aligning the first bonding surface with the second bonding surface, hi some implementations, the alkyne group is bonded to the first substrate by a first base molecule and the azide group is bonded to the second substrate by a second base molecule.

[0014] In some implementations, providing the first substrate includes forming a first self-assembled monolayer (SAM) on the first bonding interface, where the first SAM includes an alkyne group, and providing the second substrate includes forming a second SAM on the second bonding surface, where the second SAM includes an azide group. In some implementations, providing the first substrate includes selectively depositing the first SAM on the first bonding surface, and providing the second substrate includes selectively depositing the second SAM on the second bonding surface.

[0015] In some implementations, performing a thermal treatment covalently bonds the alkyne group to the azide group via a cycloaddition process, thereby forming a triazole group.

[0016] In yet another aspect, the present disclosure provides a semiconductor structure comprising a first substrate, a second substrate, and a composite bonding layer bonded to the first substrate and the second substrate, the composite bonding layer comprising a triazole moiety.

[0017] In some implementations, the composite junction layer is covalently bonded to a first surface of a first substrate via first base molecules and to a second surface of a second substrate via second base molecules.

[0018] In some implementations, the first substrate includes a first conductive feature disposed on a first dielectric layer, and the second substrate includes a second conductive feature disposed on a second dielectric layer, and the composite bonding layer extends between the first and second dielectric layers. In some implementations, the composite bonding layer extends to contact sidewalls of each of the first and second conductive features.

[0019] According to one method, an alkyne-azide reaction is used for bonding via so-called click chemistry. An azide-functionalized bonding layer is formed on a first surface, and an alkyne-functionalized bonding layer is formed on a second surface that is bonded to the first surface. The alkyne-functionalized and azide-functionalized surfaces react to form a composite bonding layer containing triazole-bridged (or linked) cyclic structures at the bonding interface. In some instances, forming a triazole-bridged structure between the bonding layers can require lower processing temperatures than existing bonding methods. As an example, Huisgen's 1,3-dipolar cycloaddition (different from copper (Cu)-catalyzed azide-alkyne cycloaddition (CuAAC)) can be used to covalently bond the bonding surfaces of two opposing substrates.

[0020] In some examples, an alkyne-functionalized bonding layer may include multiple base molecules (or functional groups) R1, each terminated with an alkyne moiety (or functional group), and an azide-functionalized bonding layer may include multiple base molecules R2 (or functional groups), each terminated with an azide moiety (or functional group). The thickness and physical properties of the composite bonding layer can be tailored by selecting the specific composition and / or chain length of the base molecules R1 and R2. In one example, the composition of the base molecules R1 and R2 may be controlled to achieve benefits such as resistance to copper diffusion into adjacent dielectric layers. In another example, oligomers and polymers of various lengths (e.g., molecular weights) may be used to create composite bonding layers of various thicknesses between bonded substrates. When using base molecules R1 and R2 with relatively nonpolar bonds (e.g., Si-C type bonds) as backbone components, copper diffusion may be suppressed compared to bonds that are more polar, such as Si-O bonds. In such applications, silicon-containing framework components may be more stable than purely organic (e.g., containing carbon, hydrogen, oxygen, etc.) compounds, but either may be used in the base molecules R1 and R2 depending on the application.

[0021] Bonding by the present methods and use of the materials described herein have several advantages. Utilizing a curable bonding layer in a direct or hybrid bonding process results in the formation of a bond interface with non-polar or less polar bonds (e.g., compared to Si-O bonds typical of bond interfaces without a curable bonding layer). Bonding with a curable bonding layer relies on reactions that are less prone to irreversible or reverse reactions. The use of more stable functional groups can reduce, minimize, or eliminate queue time effects. In this implementation, plasma activation and / or water treatment prior to the bonding process can be omitted, thus saving time and cost in the overall manufacturing process. Consequently, improved bond strength between the two surfaces in the bonded structure is achieved.

[0022] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless indicated as representing background art, the drawings represent aspects of the present disclosure. For clarity, not every component is necessarily labeled in every drawing. [Brief explanation of the drawings]

[0023] [Figures 1A-1D] 1 summarizes an exemplary hybrid bonding process according to conventional techniques. [Figure 2-3] 1A-1C each illustrate a flowchart of an exemplary method for fabricating a semiconductor structure, according to some embodiments. [Figures 4A-4E] 4A and 4B show cross-sectional side views of an exemplary semiconductor structure at intermediate steps of the method shown in one or more of FIGS. 2 and 3, respectively, according to some embodiments. [Figure 5A-5B] 4A and 4B show cross-sectional side views of an exemplary semiconductor structure at intermediate steps of the method shown in one or more of FIGS. 2 and 3, respectively, according to some embodiments. [Figures 6A-6E] 4A and 4B show cross-sectional side views of an exemplary semiconductor structure at intermediate steps of the method shown in one or more of FIGS. 2 and 3, respectively, according to some embodiments. [Figures 7A-7B] 4A and 4B show cross-sectional side views of an exemplary semiconductor structure at intermediate steps of the method shown in one or more of FIGS. 2 and 3, respectively, according to some embodiments. [Figure 8A-8B] 4A and 4B show cross-sectional side views of an exemplary semiconductor structure at intermediate steps of the method shown in one or more of FIGS. 2 and 3, respectively, according to some embodiments. [Figure 9] 1 shows a schematic reaction diagram for joining two substrates having surfaces functionalized with different moieties, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0024] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein. It will be understood, however, that no limitation of the claims or the scope of the present disclosure is intended in this regard. Variations and further modifications to the features of the invention illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which may occur to those skilled in the art in light of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used, or other changes may be made, without departing from the spirit or scope of the present disclosure. The exemplary embodiments described in the detailed description are not intended to limit the presented subject matter.

[0025] According to one implementation, a first substrate is bonded to a second substrate by a modified direct or hybrid bonding technique. A first bonding layer, such as an alkyne-functionalized layer, is formed on the first substrate, and a second bonding layer, such as an azide-functionalized layer, is formed on the second substrate. Each of these layers can be about 1 nm to about 10 nm thick and can be selectively formed or blanket deposited and then thinned using polishing (e.g., a chemical mechanical polishing (i.e., CMP) process) or etching techniques to expose the underlying conductive features (if applicable). In the case of hybrid bonding where the conductive and dielectric materials are exposed at each bonding surface, the first and second bonding layers can be selectively applied as self-assembled monolayers (SAMs) only on the dielectric material, or can be applied on both the conductive and dielectric materials and then treated (e.g., by polishing or etching) to expose the underlying conductive material. The first and second bonding surfaces are then brought together to covalently bond or crosslink the functional groups (i.e., alkyne and azide groups) across the bonding interface. This process can be carried out at a relatively low temperature (such as about 400° C. to about 500° C. or less).

[0026] The use of chemically driven processes for bonding allows for lower processing temperatures than traditional bonding techniques. The use of chemical surface treatments can be selectively formed on oxide or other insulating layers to avoid interference with intermetallic joints used to interconnect conductive features on opposing substrates.

[0027] 2 shows a flowchart of an exemplary method 10 of forming a bonding surface on a semiconductor structure according to some implementations of the present disclosure. FIG. 3 shows a flowchart of an exemplary method 30 of bonding or joining bonding surfaces of two semiconductor structures (e.g., two semiconductor substrates, two semiconductor wafers, two semiconductor dies, etc.) according to some implementations of the present disclosure. It should be noted that methods 10 and 30 are merely examples and are not intended to limit the present disclosure. It should be further understood that additional operations may be provided before, during, and after method 10 of FIG. 2 and / or method 30 of FIG. 3, and that some other operations may be only briefly described herein.

[0028] In various implementations, the operations of method 10 may relate to exemplary semiconductor structures 200 and 250 at various stages of fabrication illustrated in Figures 4A-7B, and the operations of method 30 may relate to exemplary semiconductor structure 300 at various stages of fabrication illustrated in Figures 8A and 8B, which are described in further detail below. Additionally, one or more operations of method 30 may relate to schematic reaction 400 illustrated in Figure 9. It should be understood that semiconductor structures 200, 250, and 300 may each include a number of other devices, such as inductors, fuses, capacitors, coils, etc., without departing from the scope of the present disclosure.

[0029] 2 and 4A, the method 10, in act 12, provides a first semiconductor structure 200 including a semiconductor substrate (eg, a base substrate) 202.

[0030] The semiconductor substrate 202 may include a semiconductor material such as a bulk semiconductor, a semiconductor-on-insulator (SOI), or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate 202 may be or correspond to a wafer (e.g., 202 or 204), such as a silicon wafer. Generally, an SOI includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The semiconductor substrate 202 may include other semiconductor materials, such as multi-layer semiconductor materials or functionally graded semiconductor materials. In some examples, the semiconductor substrate 202 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0031] Thereafter, in operation 14, method 10 forms a dielectric layer (e.g., an insulating layer) 204 on or over semiconductor substrate 202. In this implementation, dielectric layer 204 and the conductive features subsequently formed in dielectric layer 204 constitute a first bonding surface 214 of first semiconductor structure 200. In some implementations, first bonding surface 214 is on a front side of first semiconductor substrate 202 (e.g., on a surface of semiconductor structure 200 that includes device features). Alternatively, first bonding surface 214 can be on a back side of first semiconductor substrate 202 (e.g., on a surface of semiconductor structure 200 opposite the device features).

[0032] Dielectric layer 204 may comprise any suitable material, such as an oxide, a nitride, a carbide, or the like, or a combination thereof. Non-limiting examples include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiCN), a low-k dielectric material (e.g., a dielectric material having a dielectric constant lower than that of silicon oxide, which is about 3.9), or the like, or a combination thereof. Dielectric layer 204 may be formed or deposited using at least one suitable deposition technique, such as chemical vapor deposition (CVD), flowable CVD (FCVD), atomic layer deposition (ALD), spin coating, or the like, or a combination thereof.

[0033] Although not separately shown for simplicity, the first semiconductor structure 200 may include several device features (e.g., transistors, diodes, resistors, etc.) in and / or on the semiconductor substrate 202, and several interconnect structures (alternatively referred to as conductive features, such as vias and conductive lines) formed on the device features. Exemplary transistors may include field-effect transistors (FETs), such as finFETs (e.g., FinFETs), multi-gate FETs, nanosheet FETs, etc., or combinations thereof. The interconnect structures may be configured to electrically connect the device features to one another to form integrated circuits that may function as logic devices, memory devices, input / output devices, etc. The device features may include doped or undoped semiconductor materials that may be similar in composition to the semiconductor substrate 202.

[0034] The interconnect structures may include a conductive material such as Cu, tungsten (W), nickel (Ni), aluminum (Al), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), tantalum (Ta), TiN, TaN, etc., or combinations thereof, disposed in a dielectric (e.g., insulator) material such as an oxide, nitride, carbide, etc., or combinations thereof. The device features and interconnect structures may be formed in an intervening dielectric layer (e.g., an intermetal dielectric layer, an interlevel / interlayer dielectric layer, an etch stop layer, etc.) between the semiconductor substrate 202 and a dielectric layer 204, such as a front-end-of-line (FEOL) layer or a back-end-of-line (BEOL) layer. The intervening dielectric layer may be similar in composition to the dielectric layer 204.

[0035] Continuing to refer to Figures 2 and 4A, in operation 16, method 10 forms conductive features 206 in dielectric layer 204 for interconnection to one or more underlying conductive features (e.g., metallization layers, interconnect structures, device features, etc.).

[0036] The conductive features 206 may comprise any suitable conductive material, including Cu, W, Ni, Al, Ru, Ag, Au, Pt, Ti, Ta, TiN, TaN, etc., or combinations thereof. In the illustrated implementation, the conductive features 206 comprise Cu.

[0037] In some implementations, forming the conductive features 206 includes forming recesses (not shown) in the dielectric layer 204 by performing a patterning process. For example, a patterned mask layer (not shown) can be formed over the dielectric layer 204 using suitable lithography techniques, the patterned mask layer being formed with openings corresponding to the locations of the recesses, and the patterned mask layer can be used as an etch mask to etch or pattern the dielectric layer 204, resulting in the recesses in the dielectric layer 204.

[0038] A conductive layer may then be deposited as a blanket layer over the first semiconductor structure 200 to fill the recess and cover the top surface of the dielectric layer 204. The conductive layer may be deposited by any suitable deposition technique, such as CVD, ALD, PVD, plating (e.g., electroplating, electroless plating, etc.), or the like, or a combination thereof. The blanket layer and any underlying layer may then be etched (e.g., by a dry etching, reactive ion etching (RIE), or wet etching process) or polished (e.g., by a chemical mechanical polishing / planarization, or CMP process) until the top surface of the dielectric layer 204 is exposed, thereby forming conductive features 206 in the dielectric layer 204. The conductive features 206 may be formed as part of a FEOL process, a middle-end-of-line (MEOL) process, or a BEOL process. For example, the conductive features 206 may be formed as bond pads for bonding the first semiconductor structure 200 to another semiconductor structure, die, substrate, etc. as part of a package.

[0039] 4B , in operation 16, method 10 then recesses dielectric layer 204 to expose the tops of conductive features 206, including sidewalls, thereby causing conductive features 206 to protrude from the top surface of recessed dielectric layer 204. Dielectric layer 204 can be recessed by any suitable method. In one example, dielectric layer 204 can be etched back using a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In another example, a sacrificial layer can be formed over dielectric layer 204 before forming conductive features 206 (e.g., in operation 14) and then selectively removed after forming conductive features 206 (e.g., in operation 16), thereby exposing the tops of the conductive features. In yet another example, to accommodate the formation of a thin layer of first bonding layer 209a, conductive features 206 can be flush with or slightly recessed from the top surface of dielectric layer 204. In this regard, recessing of the dielectric layer 204 may be omitted.

[0040] 2 and 4C-4E collectively, method 10, in operation 18, selectively forms a first bonding layer 209a on dielectric layer 204 adjacent conductive feature 206.

[0041] In this implementation, referring to FIG. 9 , the first bonding layer 209a includes a plurality of molecules each terminated with an alkyne (—C≡CH) moiety (or group) 402 extending from the first bonding surface 214. In some implementations, the molecules are organized as a self-assembled monolayer (SAM) extending from the first bonding surface 214. In this implementation, each alkyne moiety 402 is attached to the first bonding surface 214 by a first base molecule R1, which may include an oligomer or polymer having a backbone of repeating monomers. In some implementations, the number of repeating monomers determines the chain length of the first base molecule R1. In this regard, the molecular weight (MW) of the first base molecule R1 varies proportionally to the chain length of the first base molecule R1. The base molecule R1 may further include a side chain functional group attached to the backbone. In some implementations, the properties of the first bonding layer 209a can be adjusted by controlling the chain length of the first base molecule R1 and / or the side chain functional groups attached to the backbone. For example, the thickness of the subsequently formed composite bonding layer 304 can be adjusted by controlling at least the chain length of the first base molecule R1.

[0042] 4C , the first bonding layer 209a is deposited as a blanket SAM over the dielectric layer 204 and the conductive features 206, thereby completely covering the exposed top surfaces of the conductive features 206. The first bonding layer 209a may be deposited by any suitable method, such as spin coating, to form a thickness sufficient to cover the top surfaces of the conductive features 206.

[0043] 4D , method 10 then removes a portion of first bonding layer 209a to expose a top surface of conductive feature 206, thereby leaving a remaining portion of first bonding layer 209a adjacent to conductive feature 206 and overlying dielectric layer 204. In some implementations, the remaining portion of first bonding layer 209a is substantially coplanar with conductive feature 206.

[0044] 4D , portions of the first bonding layer 209 a are removed by applying a CMP process to planarize the top surfaces of the conductive features 206 with the top surfaces of the first bonding layer 209 a. In some implementations, portions of the first bonding layer 209 a are removed by a suitable selective etching process (e.g., a dry etching process, a wet etching process, etc.) to expose the top surfaces of the conductive features 206.

[0045] 4E, method 10 recesses conductive feature 206 such that first bonding layer 209a protrudes from a top surface of recessed conductive feature 206, resulting in first bonding surface 214 on semiconductor substrate 202. Conductive feature 206 may be selectively recessed by a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In some examples, conductive feature 206 may be recessed by about 1 nm to about 5 nm. In some implementations, recessing conductive feature 206 creates a space above conductive feature 206 to allow for its expansion across the bonding interface during subsequent heat treatment, annealing process, and / or bonding process.

[0046] In an alternative implementation, and referring collectively to FIGS. 2, 5A, and 5B, the first bonding layer 209a can be formed in operation 18 by performing a selective deposition process.

[0047] After forming the conductive feature 206 (see FIG. 5A, which is similar to FIG. 4A), a first bonding layer 209a is selectively deposited on the dielectric layer 204 to expose the top surface of the conductive feature 206, resulting in a first bonding surface 214, as shown in FIG. 5B. The first bonding layer 209a may be selectively deposited by any suitable method. For example, the top surface of the dielectric layer 204 may be functionalized with a binding moiety (e.g., the dielectric layer 204 (e.g., comprising silicon dioxide) may be functionalized with a hydroxyl group (—OH), which may then be bonded to a first base molecule R1). Additionally, the top surface of the dielectric layer 204 may be functionalized with a first base molecule R1 prior to attachment of the alkyne moiety 402.

[0048] In some implementations, the top surface of the conductive feature 206 is below the top surface of the first bonding layer 209a. In some implementations, the conductive feature 206 can optionally be recessed such that the top surface of the conductive feature 206 is about 1 nm to about 5 nm below the top surface of the curable bonding layer 209.

[0049] 2 and 6A-7B collectively, operations 12-18 of method 10 are also applicable to form second semiconductor structure 250. In this implementation, second semiconductor structure 250 is formed having second bonding surface 216 that has a different composition than first bonding surface 214.

[0050] 6A and 7B, for example, second bonding surface 216 includes second bonding layer 209b formed on dielectric layer 204 adjacent conductive feature 206. Referring to FIG. 9, second bonding layer 209b includes azide (-N=N + =N -The second bonding layer 209b includes a plurality of molecules terminated by azide moieties (or groups) 412. In some implementations, the molecules are organized as a self-assembled adhesive (SAM) extending from the second bonding surface 216. In this implementation, each azide moiety 412 is attached to the second bonding surface 216 by a second base molecule R2, which may include an oligomer or polymer having a backbone of repeating monomers. In some implementations, the number of repeating monomers determines the chain length of the second base molecule R2 such that the MW of the second base molecule R2 varies proportionally with the chain length of the second base molecule R2. The second base molecule R2 may further include side chain functional groups attached to the backbone. Similar to the first bonding layer 209a, the properties of the second bonding layer 209b can be tailored by controlling the chain length of the second base molecule R2 and / or the side chain functional groups attached to the backbone. For example, the thickness of the subsequently formed composite bonding layer 304 can be tailored by controlling the chain length of the first base molecule and / or the second base molecule R2.

[0051] In some implementations, the second semiconductor structure 250 may be formed by the same method as the semiconductor structure 200, i.e., method 10. For example, the implementation of the second semiconductor structure 250 shown in Figures 6A-6E corresponds to the implementation of the first semiconductor structure 200 shown in Figures 4A-4E, and the implementation of Figures 7A and 7B corresponds to the implementation of Figures 5A and 5B.

[0052] Now, referring to Figures 3, 8A and 8B, method 30 provides an exemplary process for bonding or joining a first bonding surface 214 of a first semiconductor structure 200 to a second bonding surface 216 of a second semiconductor structure 250.

[0053] 3 and 8A, method 30, in operation 32, provides a first semiconductor structure 200 and a second semiconductor structure 250, where first semiconductor structure 200 includes a first bonding surface 214 formed according to method 10 provided herein, and second semiconductor structure 250 includes a second bonding surface 216 formed according to method 10 provided herein. For example, first bonding surface 214 includes a first bonding layer 209a overlying dielectric layer 204 and a conductive feature 206 disposed on dielectric layer 204, and second bonding surface 216 includes a second bonding layer 209b overlying dielectric layer 204 and a conductive feature 206 disposed on dielectric layer 204.

[0054] 3 and 8A , method 30 then, in operation 34, aligns and bonds first bonding surface 214 and second bonding surface 216 to form direct physical contact therebetween, resulting in semiconductor structure (e.g., bonded structure) 300. In this implementation, the direct physical contact establishes a bonding interface 302 between first bonding surface 214 and second bonding surface 216. In some implementations, second semiconductor structure 250 (or first semiconductor structure 200) is first inverted or flipped (e.g., rotated 180°) during the alignment process so that first bonding surface 214 and second bonding surface 216 are positioned opposite each other and bonded in a face-to-face configuration.

[0055] The first bonding surface 214 and the second bonding surface 216 may be bonded by any suitable process, such as a hybrid bonding process or a direct bonding process. In this regard, the bonding process may be performed by aligning similar features of the first bonding surface 214 and the second bonding surface 216 with each other such that metal-to-metal contact can be formed via the bonding interface 302 between the conductive features 206 and dielectric-to-dielectric contact can be formed via the bonding interface 302 between the dielectric layers 204.

[0056] 1A and 1B , respectively, the bonding process described in method 30 does not include any surface treatment processes, such as a plasma treatment to activate first bonding surface 214 and / or second bonding surface 216 and a hydration process to enhance the bonding ability of first bonding surface 214 and / or second bonding surface 216. As described in more detail below, method 30 directly proceeds to applying a heat treatment (e.g., an annealing process) to bonded first bonding surface 214 and second bonding surface 216, thereby chemically reacting first bonding layer 209 a with second bonding layer 209 b to form irreversible (or less reversible) covalent bonds in composite bonding layer 304 (see FIG. 9 ) at bonding interface 302.

[0057] In particular, eliminating the surface preparation process prior to aligning and contacting the first mating surface 214 and the second mating surface 216 reduces the number of modules (e.g., operations) performed on the mating platform (e.g., reducing processing complexity, time, and / or cost) and reduces queue time requirements for manufacturing. In existing implementations, the surface preparation process generally results in a reversible bond between the mating surfaces, which can be relatively unstable and result in processing constraints. Such processing constraints can include a reduced processing time allowed between the surface preparation process and the subsequent bonding process, thereby imposing stricter queue time requirements.

[0058] In contrast, reacting first bonding layer 209 a with second bonding layer 209 b results in irreversible covalent bonds in composite bonding layer 304 with improved bond strength at bonding interface 302, thereby mitigating (e.g., minimizing or eliminating) the queue time requirement inherent in bonding surfaces that have undergone surface treatment. Additionally, incorporating first bonding layer 209 a and second bonding layer 209 b into first bonding surface 214 and second bonding surface 216, respectively, allows more stable functional groups (e.g., alkyne moiety 402 and azide moiety 412) to participate in the bonding process, improving properties of semiconductor structure 300, such as resistance to metal (e.g., copper) diffusion, reduced processing temperatures, tunable chain length and thickness of the bonding interface, and / or the like.

[0059] 3 and 8B, in operation 36, the method 30 performs a thermal treatment (e.g., an annealing process) 80 to anneal the semiconductor structure 300, thereby allowing the first bonding surface 214 and the second bonding surface 216 to chemically react and form a composite bonding layer 304 at the bonding interface 302 according to the schematic reaction 400 shown in FIG. 9.

[0060] 9 , it should be noted that the illustrations of the first semiconductor structure 200 and the second semiconductor structure 250 omit depictions of the dielectric layer 204 and the conductive feature 206, respectively, for simplicity. In operation 32, the first semiconductor structure 200 is provided to include a first bonding layer 209a having an alkyne moiety 402 bonded to a first base molecule R1 extending from the semiconductor substrate 202, and the second semiconductor structure 250 is provided to include a second bonding layer 209b having an azide moiety 412 bonded to a second base molecule R2 extending from the semiconductor substrate 202. After inverting one of the first semiconductor structure 200 and the second semiconductor structure 250, in operation 34, the alkyne moiety 402 is adjacent to the azide moiety 412 at the bonding interface 302.

[0061] In operation 36, heat treatment 80 is performed by applying sufficient thermal energy to activate click chemistry, which couples alkyne moiety 402 to azide moiety 412 via a cycloaddition mechanism, as shown. In some implementations, the cycloaddition mechanism is a 1,3-dipolar cycloaddition mechanism that does not rely on the use of copper catalysis. In this implementation, reacting alkyne moiety 402 with azide moiety 412 forms triazole moiety (or group) 422, which includes a ring structure, and this triazole moiety (or group) 422 covalently bonds (or bridges) first interface 214 to second interface 216 via first base molecule R1 and second base molecule R2, respectively. In this regard, triazole moiety 422 serves as a bridge point between first semiconductor structure 200 and second semiconductor structure 250.

[0062] In some examples, the heat treatment 80 may be performed at a temperature lower than that typically employed to bond the dielectric layers 204 of the first and second bonding surfaces 214, 216, i.e., to bond bonding surfaces that are not functionalized with groups such as alkynes and azides. In some implementations, the heat treatment 80 provides sufficient thermal energy to cause the conductive features 206 of the respective first and second bonding surfaces 214, 216 to expand across the bonding interface 302, resulting in metal-to-metal contact at the bonding interface 302.

[0063] The resulting composite bonding layer 304 is disposed at the bonding interface 302 and is covalently bonded to the first bonding surface 214 via the first base molecule R1 and to the second bonding surface 216 via the second base molecule R2. If the thermal treatment 80 provides sufficient thermal energy to expand the conductive features 206, the composite bonding layer 304 may extend along the sidewalls of the bonded conductive features 206. In some implementations, the thickness T of the composite bonding layer 304 is the sum of the chain lengths of at least the first base molecule R1 and the second base molecule R2. In this regard, the present disclosure provides methods for adjusting the thickness T by controlling the size (e.g., type of monomer, molecular weight, etc.) of the first base molecule R1 and / or the second base molecule R2. In some implementations, adjusting the thickness T may improve the properties of the composite bonding layer 304, including, for example, resistance to metal (e.g., copper) diffusion, reduced processing temperatures, and / or the like.

[0064] In some implementations, an additional heat treatment may be applied after forming the composite bonding layer 304 to expand the conductive features 206 across the bond interface 302. In this regard, the temperature at which the additional heat treatment is applied is higher than the temperature applied to the heat treatment 80 in operation 36, such as from about 250° C. to about 400° C. In some implementations, the heat treatment 80 may be applied at a temperature that allows both the general reaction 400 and the expansion of the conductive features 206 to occur simultaneously.

[0065] In the above description, specific details have been disclosed, such as the particular geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the techniques described herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and redundant description may be omitted.

[0066] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed as to imply that the operations described are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described above may be performed in a different order than in the embodiments described above. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0067] As used herein, "substrate" or "target substrate" generally refers to an object to be processed by the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may include a base substrate structure, such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, such as a thin film. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is considered to include such a layer or base structure, and any combination of layers and / or base structures. While the present specification may refer to a particular type of substrate, this is for illustrative purposes only.

[0068] Those skilled in the art will also appreciate that many variations on the operation of the above-described techniques are possible while still achieving the same objectives of the present invention. Such variations are intended to be included within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations on embodiments of the present invention are set forth in the following claims.

Claims

1. providing a first substrate having a first surface comprising an alkyne moiety; providing a second substrate having a second surface comprising azide moieties; bonding the first substrate to the second substrate, providing physical contact between the first surface and the second surface at an interface; and chemically reacting the alkyne moiety with the azide moiety via a cycloaddition mechanism, thereby forming a triazole moiety-attached layer at the interface; and A method comprising:

2. 2. The method of claim 1, wherein the alkyne moiety is attached to the first substrate via a first base molecule and the azide moiety is attached to the second substrate via a second base molecule.

3. providing the first substrate includes disposing a first self-assembled monolayer (SAM) on the first surface, the first SAM having the alkyne moieties extending from the first surface; 10. The method of claim 1, wherein providing the second substrate comprises depositing a second SAM on the second surface, the second SAM having the azide moieties extending from the second surface.

4. The method of claim 3 , wherein the steps of depositing the first SAM and the second SAM each comprise performing a selective deposition process.

5. providing the first substrate further comprises functionalizing the first surface prior to depositing the first SAM; The method of claim 4 , wherein the step of providing a second substrate further comprises functionalizing the second surface prior to the step of depositing the second SAM.

6. 4. The method of claim 3, wherein providing the first SAM and the second SAM comprises depositing each of the first SAM and the second SAM as a blanket layer and removing a portion of the first SAM and the second SAM.

7. the first surface includes a first conductive feature disposed in a first dielectric layer; the second surface includes a second conductive feature disposed in a second dielectric layer; The method of claim 3 , wherein the first SAM and the second SAM are selectively formed on the first dielectric layer and the second dielectric layer, respectively.

8. 10. The method of claim 1, wherein bonding the first substrate to the second substrate comprises applying a heat treatment to activate the cycloaddition mechanism.

9. The method of claim 8 , wherein the heat treatment is performed at a temperature lower than a temperature for forming the first SAM on the first dielectric layer.

10. providing a first substrate having a first bonding surface comprising an alkyne group; providing a second substrate having a second bonding surface comprising an azide group; bonding the first substrate to the second substrate by creating physical contact between the first bonding surface and the second bonding surface; performing a heat treatment, thereby causing a cycloaddition process to occur between the joined first and second mating surfaces; A method comprising:

11. The method of claim 10 , wherein bonding the first substrate to the second substrate comprises aligning the first bonding surface with the second bonding surface.

12. the alkyne group is attached to the first substrate by a first base molecule; The method of claim 10 , wherein the azide group is attached to the second substrate by a second base molecule.

13. providing the first substrate includes forming a first self-assembled monolayer (SAM) on the first bonding surface, the first SAM including the alkyne group; 11. The method of claim 10, wherein the step of providing a second substrate comprises forming a second SAM on the second bonding surface, the second SAM including the azide group.

14. forming the first SAM comprises selectively depositing the first SAM on the first bonding surface; 14. The method of claim 13, wherein forming the second SAM comprises selectively depositing the second SAM over the second bonding surface.

15. 11. The method of claim 10, wherein the step of performing a heat treatment covalently bonds the alkyne groups to the azide groups via the cycloaddition process, thereby forming triazole groups in the composite bonding layer.

16. The method of claim 10 , wherein the heat treatment is performed at a temperature lower than a temperature for depositing a first SAM on the first joining surface.

17. 1. A semiconductor structure comprising: a first substrate; a second substrate; a composite bonding layer covalently bonded to the first substrate and the second substrate, the composite bonding layer comprising a triazole moiety; 1. A semiconductor structure comprising:

18. 20. The semiconductor structure of claim 17, wherein the composite bonding layer is covalently bonded to a first surface of the first substrate via first base molecules and to a second surface of the second substrate via second base molecules.

19. the first substrate includes a first conductive feature disposed in a first dielectric layer; the second substrate includes a second conductive feature disposed in a second dielectric layer; 20. The semiconductor structure of claim 17, wherein the composite bonding layer extends between the first dielectric layer and the second dielectric layer.

20. 20. The semiconductor structure of claim 19, wherein the composite bonding layer extends to contact a sidewall of each of the first and second conductive features.

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