Variable composition ternary compound semiconductor alloys, structures, and devices

Abstract

InN containing photovoltaic devices featuring epitaxial layers with different in-plane lattice constants a and different InN mole fractions x Al y Ga 1-x-y N semiconductor structures are disclosed. The active regions are configured to emit radiation at different wavelength ranges and are characterized by a strain state within a range of approximately 1% to 2% compressive strain. The epitaxial layers are patterned InP on a single substrate. x Al y Ga 1-x-y The InGaN grown on the N seed region is a (0001) InGaN layer characterized by different in-plane lattice constants a and different InN mole fractions. x Al y Ga 1-x-y Provides a growth surface. x Al y Ga 1-x-y N semiconductor structures can be used in optoelectronic devices, for example, in lighting sources and display applications.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63 / 436,309, filed December 30, 2022, which is incorporated by reference in its entirety.

[0002] This application is related to U.S. Application No. 16 / 689,064, filed November 19, 2019, and published as U.S. Patent No. 10,847,625, and PCT International Application No. PCT / US2020 / 061377, filed November 19, 2020, which are incorporated herein by reference in their entireties.

[0003] Field The present disclosure provides substantially relaxed, device-quality, single-crystalline relaxed (0001) InP with different in-plane lattice constants a. x Al y Ga 1-x-y Indium-aluminum-gallium nitride (InN) x Al y Ga 1-x-y The present invention relates to devices fabricated from substantially relaxed wurtzite (0001) InGaN layers, and relaxed InGaN layers. x Al y Ga 1-x-y The N region has an in-plane lattice constant "α" of 3.19 Å or greater. x Al y Ga 1-x-y The N region is made up of multiple patterned GaN, In x Ga 1-x N, Al y Ga 1-y N, In x Al y Ga 1-x-y The seed regions are grown on a group III nitride seed region such as InN (where x and y are not 0), or a related alloy seed region. During growth, the InN grown on the patterned seed region is x Al y Ga 1-x-yAfter relaxation, N coalesces to form a substantially relaxed (0001) In that can be used as a growth surface for other semiconductor materials and epitaxial layers. x Al y Ga 1-x-y Provides N growth region. Substantially relaxed (0001) In x Al y Ga 1-x-y The N region can be used in the manufacture of optical and electronic devices for use as light sources in systems used in lighting and display applications. [Background technology]

[0004] Micro-light-emitting diode (LED) and micro-laser-based devices are expected to revolutionize the display and lighting industries. However, for displays, high pixel-per-inch (PPI) and form-factor constraints necessitate multicolor emitters, such as red / green / blue (RGB) pixels with dimensions on the order of microns. This means that the dimensions of each emitter must be on the order of microns or submicrons. At this scale, mass transfer becomes challenging for diced emitters, which are fabricated using multiple wafers, with each wafer containing a single color emitter. Depositing multiple active regions in tandem is an alternative approach, but forcing multiple InGaN active regions with different InN content grown on GaN to a single in-plane lattice constant a can result in different strain states and potentially degrade quality. To fabricate high-density multiwavelength emitters, variable-composition InN with different in-plane lattice constants a on the same growth substrate is required. x Al y Ga 1-x-y It is desirable to realize an N alloy.

[0005] Compound semiconductor materials are typically deposited or grown atomically lattice matched to the growth substrate to avoid the introduction of growth defects such as dislocations. In some cases, it is desirable to modify the in-plane lattice constant, a, of the compound semiconductor material to provide materials and / or devices and / or systems with particular properties.

[0006] In x Ga 1-x InN is currently the material of choice for the active layer(s) of GaN-based visible spectrum optoelectronic devices, including the blue- or violet-emitting light-emitting diodes (LEDs) that underpin most commercialized LED-based lighting and display systems to date, as well as the violet-emitting laser diodes (LDs) that underpin the Blu-ray™ industry. Currently, such devices are fabricated using InGaN active layers pseudomorphically grown on gallium nitride (GaN) epitaxial layers. Unfortunately, because the crystal atomic lattice constant of InGaN is larger than that of GaN, increasing the InN mole fraction or increasing the thickness of InGaN grown on GaN (InGaN / GaN) results in significant strain and increasingly degraded material quality. This limits the performance of InGaN / GaN-based optoelectronic devices, including LEDs and LDs.

[0007] Attempts to grow high-quality, planar, relaxed InGaN for device applications have so far been unsuccessful in commercial applications. The graded-layer approach used in certain III-V material systems has been attempted for InGaN using low-temperature molecular beam epitaxy (MBE). However, these growth conditions lead to material with a high density of defects (e.g., point defects), which are difficult to improve and result in poor material quality. Similar approaches using metalorganic chemical vapor deposition (MOCVD), which is commercially favored for c-plane InGaN, are compromised by the lack of a slip system for (polar) c-plane growth, and past attempts to utilize nonpolar and semipolar growth planes have resulted in material with high defect densities and / or devices requiring nonpolar and semipolar active regions. Hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers with the aim of reducing crystal defects, but this approach is not ideal for low-cost manufacturing because it is limited in terms of the achievable InN mole fraction and is only applicable to N-polar surfaces. To facilitate relaxation, attempts have been made to grow strained InGaN layers that can be exfoliated and bonded to compliant carriers, but this method limits lattice expansion and results in nonplanar, grooved surfaces. The use of nanocolumn or nanorod device structures designed to circumvent the strain limitations of conventional heteroepitaxy results in nonplanar device geometries that are unsuitable for manufacturing. Finally, techniques have been demonstrated to produce porous GaN material as a compliant substrate for subsequent growth of InGaN, but this is complicated by the limitations of lattice expansion and the need for regrowth after the porosification process.

[0008] The use of patterning and regrowth has been used to grow high-quality lattice-mismatched heteroepitaxy of single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc-blende semiconductors. However, similar approaches for wurtzite semiconductors and / or ternary alloys such as InGaN have not been successful. Summary of the Invention

[0009] According to the present invention, the wurtzite III-nitride crystalline semiconductor structure comprises: a substrate including a first substrate region and a second substrate region; a first (0001) In layer overlying the first substrate region; x1 Al y1 Ga 1-x1-y1 The first In containing N growth region x1 Al y1 Ga 1-x1-y1 N growth layer, A second patterned In overlying the second substrate region. x2s Al y2s Ga 1-x2s-y2s N seed regions; Second Patterned In x2s Al y2s Ga 1-x2s-y2s A second (0001) In layer located above the N seed region x2 Al y2 Ga 1-x2-y2 The second In containing N growth region x2 Al y2 Ga 1-x2-y2 and an N growth layer, The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane lattice constant, a, Second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by a second in-plane lattice constant, a, the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; 0<x2≦1であり、0≦y2≦1であり、かつx2+y2≦1、x2> Let's say x1.

[0010] According to the invention, a wafer comprises a semiconductor structure according to the invention.

[0011] According to the invention, an optoelectronic component comprises a semiconductor structure according to the invention.

[0012] According to the invention, a polychromatic photovoltaic device comprises a semiconductor structure according to the invention.

[0013] According to the invention, a semiconductor device comprises a semiconductor structure according to the invention.

[0014] According to the invention, an illumination system or a display system comprises a semiconductor device according to the invention.

[0015] In accordance with the present invention, a method for fabricating a wurtzite III-nitride crystalline semiconductor structure comprises: (a) A first In located on a first substrate region of a substrate. x1 Al y1 Ga 1-x1-y1 depositing a N growth layer; (b) a second In overlying a second substrate region of the substrate; x2 Al y2 Ga 1-x2-y2 depositing a second In N growth layer; x2 Al y2 Ga 1-x2-y2 The N growth layer is then patterned with a second In x2s Al y2s Ga 1-x2s-y2s Located above the N seed region, First In x1 Al y1 Ga 1-x1-y1 The N growth layer is a first (0001) InN layer characterized by a first in-plane lattice constant a. x1 Al y1 Ga 1-x1-y1 N growth region, Second In x2 Al y2 Ga 1-x2-y2 The N growth layer is a second (0001) In layer characterized by a second in-plane lattice constant a. x2 Al y2 Ga 1-x2-y2 N growth region, the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; 0<x2≦1であり、0≦y2≦1であり、かつx2+y2≦1、x2> This includes letting x1.

[0016] In accordance with the present invention, a semiconductor structure comprises a semiconductor structure manufactured using a method in accordance with the present invention.

[0017] Those skilled in the art will understand that the drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure. [Brief explanation of the drawings]

[0018] [Figure 1A] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 1B] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 1C] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 1D] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 1E] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention.

[0019] [Figure 2A] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 2B] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 2C] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 2D] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 2E] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention.

[0020] [Figure 3A] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 3B] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 3C] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 3D] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention. [Figure 3E] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present invention.

[0021] [Figure 4A] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure. [Figure 4B] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure. [Figure 4C] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure. [Figure 4D]1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure. [Figure 4E] 1 illustrates an example process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure.

[0022] [Figure 5] Examples of positive etch masks with various shapes, dimensions, and orientations relative to the (1-100) and (11-20) crystallographic directions of III-nitride wurtzite materials are shown.

[0023] [Figure 6] Examples of negative etch masks with various shapes, dimensions, and orientations for the (1-100) and (11-20) crystallographic directions of GaN or InxAlyGa1-x-yN III-nitride wurtzite materials are shown.

[0024] [Figure 7] The transition is shown from an InGaN lattice (solid circles), characterized by a lattice constant "a" similar to that of GaN, to a more relaxed InGaN lattice (shaded circles), characterized by a lattice constant "a'".

[0025] [Figure 8] 1 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present invention.

[0026] [Figure 9A] 1 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present disclosure. [Figure 9B] 1 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present disclosure. [Figure 9C] 1 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present disclosure. [Figure 9D] 1 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present disclosure.

[0027] [Figure 10] 1 shows an example of a laser diode (LD) incorporating a III-nitride semiconductor structure provided by the present invention.

[0028] [Figure 11] 1A-1C illustrate examples of lighting devices and systems in which LEDs provided by the present disclosure can be incorporated.

[0029] [Figure 12] 1A-1C illustrate examples of display devices and systems in which LEDs provided by the present disclosure can be incorporated.

[0030] [Figure 13] 1 shows a cross-sectional view of an example of a III-nitride semiconductor structure provided by the present invention.

[0031] [Figure 14A] The range of InN mole fraction and lattice constant a as a function of the peak emission wavelength of the relaxed (0001) InGaN region is shown. [Figure 14B] The range of InN mole fraction and lattice constant a as a function of the peak emission wavelength of the relaxed (0001) InGaN region is shown.

[0032] [Figure 15A] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 15B] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 15C] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 15D] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 15E] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 15F] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region.

[0033] [Figure 16A] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 16B] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 16C] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 16D] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 16E] 1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region. [Figure 16F]1 illustrates an example process flow provided by the present disclosure for fabricating a relaxed InxAlyGa1-x-yN layer having a relaxed (0001) InxAlyGa1-x-yN region.

[0034] [Figure 17A] 1 illustrates a cross-sectional view of an example III-nitride semiconductor structure having a relaxed (0001) InxAlyGa1-x-yN region provided by the present disclosure. [Figure 17B] 1 illustrates a cross-sectional view of an example III-nitride semiconductor structure having a relaxed (0001) InxAlyGa1-x-yN region provided by the present disclosure.

[0035] [Figure 18A] We present an example of the stepwise growth of InxAlyGa1-x-yN on the (10-11) facet of a group III nitride semiconductor, filling a "V-pit" structure. [Figure 18B] We present an example of the stepwise growth of InxAlyGa1-x-yN on the (10-11) facet of a group III nitride semiconductor, filling a "V-pit" structure. [Figure 18C] We present an example of the stepwise growth of InxAlyGa1-x-yN on the (10-11) facet of a group III nitride semiconductor, filling a "V-pit" structure.

[0036] [Figure 19] We show that InxAlyGa1-x-yN grows gradually on the (10-11) GaN seed facet to provide relaxed (0001) InxAlyGa1-x-yN regions.

[0037] [Figure 20] An example is shown in which InxAlyGa1-x-yN is grown gradually on a (10-11) GaN seed facet to provide a relaxed (0001) InxAlyGa1-x-yN region.

[0038] [Figure 21]1 illustrates an example of an optoelectronic device provided by the present disclosure, comprising three optoelectronic elements configured to emit light in three different wavelength regions grown on three different relaxed InGaN growth layers having different relaxed (0001) InxAlyGa1-x-yN regions located on the same growth layer.

[0039] [Figure 22] The relationship between the in-plane lattice constant a and the peak emission wavelength for different InGaN compositions deposited at different growth temperatures is shown.

[0040] [Figure 23] 1A-1C illustrate epitaxial layers during intermediate steps in the fabrication of a multi-wavelength photovoltaic device provided by the present invention.

[0041] [Figure 24] 1 illustrates an example of a photovoltaic device provided by the present disclosure, the photovoltaic device having three isolated photovoltaic elements configured to emit radiation in different wavelength ranges grown on three different relaxed InxAlyGa1-x-yN growth layers located on a single growth layer.

[0042] [Figure 25] 1 shows an example of a stacked photovoltaic structure provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0043] "Substantially uniform lattice constant" refers to a semiconductor layer characterized by local lattice constants of the semiconductor layer that vary by less than 1% relative to the average lattice constant, e.g., less than 0.5% relative to the average lattice constant, or less than 0.1% relative to the average lattice constant.

[0044] "Defect density" refers to the density of extended defects such as dislocations in a semiconductor layer in a plan view. Defect density can be measured, for example, by etching (and measuring etch pit density (EPD)), by observing and measuring dark spots with cathodoluminescence, or by observing and measuring small pits with an atomic force microscope (AFM).

[0045] Lattice constants can be measured by X-ray diffraction (XRD) and reciprocal space mapping (RSM) analysis. High-angle, or near-grazing incidence, XRD techniques can be used to measure the lattice constant of upper layers in structures where the lattice constant varies with depth.

[0046] "III-V material" refers to a compound semiconductor material that includes at least one element from Group III and at least one element from Group V of the periodic table. III-V materials include InN, such as GaN, AlN, InN, InGaN, or (In)(Al)GaN (e.g., GaN, AlGaN, InAlGaN). x Al y Ga 1-x-y It can be N.

[0047] "Growth plane" refers to a plane parallel to the deposition plane of a planar material, such as that of a conventional substrate growth plane.

[0048] "Substantially perpendicular to the growth surface" refers to a surface that forms an angle of about 90 degrees with respect to the growth surface, for example, 88 degrees to 92 degrees with respect to the growth surface.

[0049] Wurtzite GaN, or GaN, is characterized by a wurtzite crystal structure with lattice constants a and c of approximately 3.189 Å and 5.185 Å at room temperature. Crystal planes perpendicular to the lattice constant c direction (the "c direction") are c-planes, including the Ga-face (0001) and the N-face (000-1). Planes containing the c direction and perpendicular to the lattice constant a direction (the "a direction") are {11-20} planes, or "a-planes." Planes containing the c direction and parallel to the lattice constant a direction are {1-100} planes, or "m-planes."

[0050] Wurtzite Inx Al y Ga 1-x-y N, In x Ga 1-x N, and Al y Ga 1-y InN has the same crystal structure as wurtzite GaN, but may contain a non-zero mole fraction x of InN, thereby forming a ternary compound in which a certain proportion of group III atoms are In and the remainder are substantially Ga. InN has lattice constants a and c of 3.545 Å and 5.703 Å, respectively, at room temperature. x Ga 1-x N has a lattice constant a and a lattice constant c at room temperature that are between those of GaN and InN, depending on the mole fraction.

[0051] Wurtzite In x1 Al y1 Ga 1-x1-y1 InN or InAlGaN has the same crystal structure as wurtzite GaN, but may contain a non-zero mole fraction x of InN or a non-zero mole fraction y of AlN, thereby forming ternary or quaternary compounds in which a certain percentage of the group III atoms are In and / or Al and the remainder is substantially Ga. AlN has lattice constants a and c of about 3.112 Å and 4.982 Å, respectively, at room temperature, and Al y Ga 1-y N has a lattice constant a and a lattice constant c at room temperature that are between those of GaN and AlN, depending on the mole fraction.

[0052] Although this description focuses on growing (0001) InGaN on GaN seed surfaces, this method has also been used to grow InGaN on AlN. x Al y Ga 1-x-yThe present invention is also applicable to other wurtzite materials, such as AlGaN on GaN, AlGaN on AlN, and AlGaN on GaN. If the seed contains InGaN, the mole fraction of InN in the overlying InGaN layer may differ from the mole fraction of InN in the InGaN seed. For example, the mole fraction of InN in the overlying InGaN layer may be greater than the mole fraction of InN in the InGaN seed. Furthermore, the present invention is applicable to non-basal plane wurtzite structures, such as so-called nonpolar and semipolar GaN and related materials. The present invention is also applicable to other compound semiconductor systems, including zinc-blende materials, such as InGaAs on GaAs, InGaAsP on InP, InGaSb on GaSb, and II-VI compound semiconductor systems.

[0053] "Relaxed InGaN" refers to an InGaN material that exhibits an in-plane lattice constant, a, equal to or nearly equal to that of fully relaxed InGaN material. For example, relaxed InGaN in the wurtzite form x Al y Ga 1-x-y InN has an in-plane lattice constant a of greater than 3.189 Å (0% InN) to 3.545 Å (100% InN) at room temperature. This is in contrast to strained InGaN materials such as InGaN, which are grown pseudomorphic with GaN and thereby exhibit an in-plane lattice constant a equal to or nearly equal to the in-plane lattice constant a of about 3.189 Å of GaN, regardless of the InN mole fraction. Such strained or unrelaxed InGaN materials are referred to as InGaN / GaN.

[0054] "Pseudomorphic" refers to a layer grown on a base layer or substrate that is epitaxially aligned to the base layer, even though its intrinsic (relaxed) lattice constant differs from that of the base layer or substrate. Thus, a pseudomorphic layer is substantially fully strained. For wurtzite crystalline materials characterized by lattice constants c and a, a pseudomorphic layer is adjusted to match the base layer or substrate. In this case, the c / a ratio of the pseudomorphic layer differs from that of the base layer or substrate, depending on the growth direction. Growth in the (0001) direction under compressive strain results in a pseudomorphic layer with a larger c / a ratio than that of the base layer or substrate, whereas growth in the tensile direction results in a pseudomorphic layer with a smaller c / a ratio than that of the base layer or substrate. For growth in nonpolar directions, such as the <10-10> or <11-20> directions, under compressive strain the c / a ratio of the pseudomorphic layer is smaller than that of the base layer or substrate, whereas under tensile strain the c / a ratio of the pseudomorphic layer is larger than that of the base layer or substrate. For semipolar growth directions, the strain depends on whether the growth direction is within 45 degrees of the <0001> direction, i.e., more vertical, or more than 45 degrees away from the <0001> direction, i.e., more lateral. For example, for growth in the semipolar <10-11> direction, under compressive strain the c / a ratio of the pseudomorphic layer is smaller than that of the base layer or substrate, whereas under tensile strain the c / a ratio of the pseudomorphic layer is larger than that of the base layer or substrate.

[0055] According to the present invention, In x Al y Ga 1-x-y In located above the N seed region x Al y Ga 1-x-y N is not pseudomorphic to the seed region.

[0056] "In-plane lattice constant" refers to the crystal lattice spacing in the growth plane. For (0001) materials such as InGaN, the in-plane lattice constant is the lattice constant a.

[0057] "Lateral growth" refers to growth in a direction other than perpendicular to the growth plane, including a direction parallel to the growth plane.

[0058] "Crystallographically equivalent" refers to semiconductor crystal planes that have the same atomic arrangement due to the symmetry of the crystal lattice. These planes are equivalent because they can be transformed into one another by symmetry operations inherent in semiconductor crystal structures, such as rotation and reflection. For wurtzite materials such as group-III nitride semiconductors, an example of a crystallographically equivalent plane is the m-plane set {10-10}: (10-10), (01-10), (0-110), (0-1-10), (-1010), and (-1100). Another example of a crystallographically equivalent plane is the a-plane set {11-20}: (11-20), (1-120), (-2110), (-12-10), (2-110), and (21-10). Another example of crystallographically equivalent planes is the semipolar set {10-11}: (10-11), (01-11), (0-111), (0-1-11), (-1011), and (-1101). Of course, as one skilled in the art will appreciate, there are many other crystallographically equivalent plane sets.

[0059] "Critical thickness" refers to the maximum thickness of an epitaxial film that can be grown on a base layer or substrate without forming dislocations due to lattice mismatch between the film and the base layer or substrate. Above the critical thickness, the strain energy exceeds the energy required for dislocation formation, and dislocations form to relieve the strain, resulting in relaxation of the epitaxial film. The transition from a pseudomorphic film (below the critical thickness) to a partially relaxed film due to dislocation formation is called plastic deformation.

[0060] "Overlying," as in "overlying layer," refers to a layer, such as an epitaxial layer, that is located above an underlying layer. The overlying layer may be in contact with the underlying layer. An overlying layer, such as an overlying InGaN layer, may have a homogeneous composition or a heterogeneous composition parallel and / or perpendicular to the growth plane. There may be one or more distinct epitaxial layers between the overlying and underlying layers.

[0061] p-type In x Al y Ga 1-x-y A "layer," such as an N-layer or an active layer, refers to a single layer or a layer that includes one or more sublayers, such as 1 to 100 sublayers. Each sublayer that makes up a layer may have the same elemental composition, or at least one sublayer may have a different elemental composition from the other sublayers. For example, p-type In x Al y Ga 1-x-y The N layer is made up of In with different p-type dopant concentrations. x Al y Ga 1-x-y Each sub-layer forming the layer may be independently deposited under the same or different deposition conditions and may independently comprise the same or different elemental composition.

[0062] "In x Al y Ga 1-x-y "N" refers to alloys of gallium and nitrogen, aluminum and nitrogen, and possibly indium and / or aluminum. For example, In x Al y Ga 1-x-y N is GaN, AlN, In x Ga 1-x N, Al y Ga 1-y N, and In x Al y Ga 1-x-y N (where x and y are not 0).

[0063] "In x1s Al y1s Ga 1-x1s-y1s "N" refers to the In associated with the first seed region. x Al y Ga 1-x-y Refers to N alloy.

[0064] "In x2s Al y2s Ga 1-x2s-y2s N' refers to the In associated with the second seed region. x Al y Ga 1-x-y Refers to N alloy.

[0065] "In x1 Al y1 Ga 1-x1-y1 N” refers to the In associated with the first growth layer and the first (0001) growth region. x Al y Ga 1-x-y Refers to N alloy.

[0066] "In x2 Al y2 Ga 1-x2s-y2s N” refers to the In associated with the second growth layer and the second (0001) growth region. x Al y Ga 1-x-y Refers to N alloy.

[0067] "Co-deposition" refers to the deposition or growth of epitaxial layers on different regions of a growth substrate at the same time, with the same reactor growth conditions, such as substrate temperature, gas temperature, reactants, flow rates, pressure, etc.

[0068] "Sequential deposition" refers to the deposition or growth of epitaxial layers on different regions of a growth substrate at different times under the same or different reactor growth conditions, such as substrate temperature, gas temperature, reactants, flow rates, pressure, etc.

[0069] While much of this disclosure has focused on the growth of InGaN over a patterned (In)GaN seed region and the formation of a relaxed InGaN region, the present invention is directed to the growth of InGaN over a patterned In x1 Al y1 Ga 1-x1-y1 In located above the N seed region x2 Al y2 Ga 1-x2-y2 N growth and moderated In x2 Al y2 Ga 1-x2-y2and forming an N region, where 0≦x1<1, 0≦y1<1, and x1+y1≦1, characterized by a wurtzite III-nitride crystal structure, where 0≦x2<1, 0≦y2<1, x2+y2≦1, x2>x1, characterized by a wurtzite III-nitride crystal structure. For example, the seed region may comprise GaN, AlN, InGaN, AlGaN, or InAlGaN, the overlying growth region may comprise InGaN, AlGaN, or InAlGaN, and the relaxed (0001) region may comprise InGaN, AlGaN, or InAlGaN.

[0070] Reference will now be made in detail to specific embodiments of materials, semiconductor structures, photovoltaic devices, and methods. The disclosed embodiments are not intended to limit the scope of the claims. On the contrary, the claims are intended to cover all alternatives, modifications, and equivalents.

[0071] The present invention teaches the formation of large-area, planar, coherent, at least partially, but substantially uniformly, relaxed layers of compound semiconductor materials for use in optical and / or electronic devices. Large area refers to a size larger than the light-emitting diameter of a single photovoltaic device, such as an LED or VCSEL. Similar to micro-LEDs and micro-VCSELs, large areas are typically 0.25 μm. 2 However, depending on the application, it may be 1mm 2 or 1 cm 2"Planar" refers to a semiconductor layer having at least one substantially flat surface and no substantial thickness variations over large areas. A planar semiconductor region can serve as a growth surface for an overlying epitaxial semiconductor layer. For example, a planar semiconductor layer can have an RMS roughness of less than 1 nm as measured using an atomic force microscope. The thickness of a planar semiconductor layer can be, for example, within ±10% of the average thickness of the planar semiconductor layer. "Coherent" refers to the property of a material being substantially crystalline rather than amorphous. "Relaxed" refers to the property of a material having an in-plane lattice constant that is approximately equal to the lattice constant of a free-standing, coherent, 100% relaxed version of a material with the same elemental composition. "Substantially relaxed" refers to a material having an in-plane lattice constant that is within 30% of the lattice constant of a free-standing, coherent, 100% relaxed version of a material with the same elemental composition. "Uniformly" refers to the property of having an in-plane lattice constant that varies weakly or does not vary substantially over large areas, based on which optical and / or electronic device structures can be fabricated. Furthermore, the present invention is applicable to a wide range of semiconductor crystal systems, including wurtzite crystal structures, and higher alloys, including ternary and quaternary alloys. Finally, the present invention is suitable for structures grown by a variety of growth methods, such as molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD).

[0072] In particular, the present invention teaches the formation of large-area, planar, coherent, at least partially, but substantially uniformly, relaxed indium gallium nitride (InGaN) material layers for use as base layers in optical and / or electronic devices. Various compositions, such as InN mole fractions, can be achieved. "Uniformly relaxed" refers to a layer in which the in-plane lattice constant remains largely unchanged over a large area within a plane containing the growth surface. Such relaxed InGaN material is referred to herein as relaxed InGaN, such as native InGaN® (Opnovix, Inc.).

[0073] The present invention further provides a method for treating a mitigated In x Aly Ga 1-x-y N, e.g. In x Ga 1-x The present invention teaches the formation of N-based optical and / or electrical devices and systems, which may include relaxed InGaN (i.e., InGaN / InGaN) and other InGaN layers pseudomorphically grown, such as native InGaN®.

[0074] The present invention further provides a method for growing a multi-layer structure of different In layers on a single growth layer. x Al y Ga 1-x-y The device includes a photovoltaic device having two or more photovoltaic elements configured to emit light at different wavelengths grown on an N growth layer.

[0075] Other features and aspects of the present invention will become apparent from the following description and accompanying drawings. In particular, the teachings of the present invention are directed to indium gallium nitride (In x Ga 1-x N), aluminum gallium nitride (Al y Ga 1-y N), aluminum gallium indium nitride (In x Al y Ga 1-x-y The present invention is also applicable to other compound semiconductor device materials such as III-N, III-As materials, III-P materials, and III-Sb materials.

[0076] The present invention discloses recording the crystal growth of compound semiconductor materials using a semiconductor seed material deposited on a substrate. The seed material has multiple seed regions with edges that are planar seed surface regions, each of which has a crystallographically equivalent direction that is not parallel to the normal of the larger area of ​​the substrate. The limited number of crystallographically equivalent directions (preferably one) of the exposed planar seed surface ensures uniform relaxation and compositional control of the InGaN material grown thereon, thereby avoiding problems associated with competing growth modes, non-uniform InN incorporation, rough surfaces, and other uncontrolled compositional content. This occurs when variable seed surface directions are simultaneously presented for InGaN growth. The dimensions of the seed surface region are limited to allow seeding of additional compound semiconductor material to facilitate relaxation toward the relaxed in-plane lattice constant during growth. The resulting "relaxed" compound semiconductor material then grows, coalesces, and grows over a large area (i.e., 0.25 μm). 2 The extensively relaxed compound semiconductor material films provide templates for the growth of improved optical and / or electronic device structures.

[0077] In particular, the present invention relates to InGaN, i.e., In x Ga 1-x In such as N x Al y Ga 1-x-y The present invention discloses the use of a GaN seed region having a seed surface region for recording the crystal growth of In. x Ga 1-x N is GaN and / or In depending on the application x Ga 1-x N. Although embodiments of the present disclosure focus on InGaN, these embodiments may also include In x Al y Ga 1-x-yThe dimensions of the GaN seed surface(s) and the associated geometry are constrained to allow seeding of InGaN material and facilitate relaxation toward the relaxed in-plane lattice constant of the InGaN material during growth. The crystallographic direction characterized by the normal to the planar seed surface region can be a nonpolar direction, such as (11-20) or (1-100), or a plane rotated between nonpolar directions, or a semipolar direction, such as (1-101). The InGaN layer is then grown and coalesces into a planar, broad-area relaxed InGaN film. The relaxed InGaN film or layer features a planar, relaxed (0001) region that can serve as a growth substrate for overlying epitaxial layers. The broad-area relaxed InGaN film provides a template for the growth of improved InGaN-based optical and / or electronic device structures.

[0078] An example of a method for growing a relaxed InGaN layer having a relaxed (0001) InGaN region is shown in Figures 1A-1E.

[0079] As shown in FIG. 1A, a predominantly (0001), or c-plane, GaN (or AlN) layer 102 can be grown on a substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include artificial substrates such as silicon-on-insulator (SOI). The thickness of the GaN layer 102 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The GaN layer 102 can be covered with a masking layer 103 of a material that rejects or slows down the nucleation of III-nitride materials. Suitable masking materials include, for example, dielectrics such as silicon nitride, silicon oxide, and aluminum oxide, but also other materials such as metals and semiconductors (single crystal or polycrystalline). The masking layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography, such as nanolithography and wet or dry etching techniques, to form the desired pattern as shown in Figure 1B. Suitable etching techniques include wet chemical etching, electrochemical etching, photochemical etching, photoelectrochemical etching, reactive ion etching (RIE), inductively coupled plasma RIE, and chemically assisted ion beam etching (CAIBE).

[0080] The etched regions 104, from which the mask and GaN material have been removed, expose GaN seed surfaces 102a. The seed surfaces 102a may be substantially perpendicular to the GaN (0001) c-plane. As shown in FIG. 1C, the GaN seed surfaces 102a may be used for lateral growth of at least InGaN 105 to form a non-coplanar InGaN / GaN heterojunction with the substrate 101. Each exposed GaN seed surface 102a may have an equivalent crystallographic orientation. For example, the GaN seed surfaces 102a may be primarily (1-100), i.e., m-plane, or primarily (11-20), i.e., a-plane, or any plane rotated between the m-plane and the a-plane. Furthermore, the seed surfaces 102a may be intentionally misoriented relative to the primary GaN crystal plane, for example, to promote favorable uniform growth characteristics. FIG. 1D shows InGaN 106 grown to fill the etch cavities and cover a portion of the mask layer 103. 1E shows that InGaN layer 106 continues to grow and coalesce to form relaxed InGaN layer 109 with relaxed (0001) InGaN regions 110 overlying mask regions 103 and substrate 101. FIG. 1E shows through relaxed InGaN region 109 a plane 108a coplanar with the (0001) InGaN surface 107, a plane 108b that bisects seed regions 102, and the InGaN regions between seed regions 102. The centers of the seed regions are indicated by 108c, and the centers of the InGaN regions between seed regions 102 are indicated by 108d.

[0081] Another technique for achieving facets in the seed region involves the formation of preferred facets through material redistribution via mass transfer, which involves controlled thermal annealing in specific gas environments. Heating a material to high temperatures in a controlled atmosphere (e.g., inert or reducing gases, or vapors containing specific chemical elements) increases the mobility of surface atoms, allowing mass transfer to occur. This process leads to the formation and growth of specific crystalline facets that are energetically favorable, resulting in the exposure of preferred facet sets. For example, when GaN is heated to high temperatures, it undergoes surface reconstruction, allowing gallium and nitrogen atoms to diffuse to the surface, preferentially forming and exposing specific crystalline facets determined by detailed conditions such as the gas environment (e.g., the ratio of nitrogen to ammonia and / or hydrogen).

[0082] The orientation of the GaN seed surface 102a can be determined by the patterning and growth direction of the underlying GaN layer 101. The orientation of the seed surface 102a further depends on the angle of the etched surface of the GaN layer 102. For example, for a (0001) GaN layer and a near-vertical etch, the orientation of the GaN seed surface can vary from about (1-100) to (11-20) and any orientation rotating therebetween. This orientation can be selected to optimize the InGaN growth conditions and the quality of the InGaN material.

[0083] For InGaN growth on certain GaN seed surfaces, particularly surfaces that are substantially perpendicular to the primary surface of the substrate, it may be desirable to promote lateral versus vertical growth by optimizing growth conditions and / or selecting an orientation of the GaN seed surface that enhances growth rate in order to promote coalescence of the relaxed InGaN layer.

[0084] The small dimensions of the GaN seed surface facilitate relaxation of the InGaN material deposited thereon, providing a planar crystallographic orientation and promoting coherent InGaN growth. During growth, InGaN grows coherently, relaxing toward the relaxed lattice constant and eventually merging with adjacent InGaN growth surfaces originating from adjacent etched regions. Referring to FIG. 1C, InGaN 105 grows from the opposing GaN seed surface 102a. In FIG. 1D, InGaN 106 grows to fill the etch cavity and cover a portion of the mask layer 103. As InGaN growth continues, InGaN grows and coalesces on the GaN seed surface in adjacent cavities. The relaxed InGaN layer then grows on the masking layer, forming a continuous, planar relaxed (0001) InGaN region 110 on the top InGaN surface 107. This can serve as a relaxed (0001) InGaN growth surface or template.

[0085] This InGaN growth method allows for lateral, or twist, relaxation, rather than the tilt that occurs when InGaN is grown directly on a (0001) GaN surface. Direct growth of InGaN on (0001) GaN introduces a vertical strain gradient in the InGaN, causing problems during subsequent growth and coalescence of the InGaN. Instead, the present invention reduces the tilt, resulting in a final coalesced film that is substantially free of strain and / or compositional inhomogeneities, thereby providing a high-quality, planar, relaxed (0001) InGaN large-area surface for semiconductor growth. Furthermore, because relaxation occurs nearly uniformly across the GaN seed surface, the vertical strain gradient that can occur when a strained layer is first grown pseudomorphically (and then etched and relaxed) is avoided or minimized.

[0086] In the InGaN growth method provided by the present disclosure, InGaN growth occurs primarily on the surface of the GaN seed material, while InGaN growth on other exposed surfaces is minimized or completely avoided. Therefore, it can be beneficial to etch the GaN seed material down to the underlying substrate, moving the substrate growth surface away from the InGaN nucleation region. Furthermore, the growth conditions for the InGaN layer can be selected to promote growth on one or more GaN seed surfaces, as opposed to nucleation and growth of InGaN on the substrate, thereby demonstrating a competitive growth mode. This approach is illustrated in Figures 2A-2E, where both the GaN layer and a portion of the substrate are etched. By etching the substrate, the distance between competing growth (at the substrate surface) and desired growth on one or more surfaces of the GaN seed material is increased, with the goal of making the InGaN grown on the substrate non-competitive. Furthermore, etching the substrate can inhibit nucleation and growth of InGaN on the substrate, further reducing the likelihood of disrupting the competitive growth mode.

[0087] FIG. 2A shows a substrate 201, an overlying GaN layer 202, and an overlying mask layer 203. In FIG. 2B, the mask layer 203, the GaN layer 202, and a portion of the substrate 201 have been etched to form a cavity 204 with an exposed GaN seed surface 202a. As shown in FIG. 2C, InGaN 205 grows on the GaN seed surface 202a and grows laterally out of the individual cavities 204 and above the substrate 201. As shown in FIG. 2D, as the growth of InGaN 206 continues, the laterally grown regions coalesce and grow out of the cavities 209 and above the mask layer 203. A portion of the cavity 209, i.e., a void, forms between the substrate 201 and the coalesced InGaN 206 within the cavity. In some embodiments, such a void can be used to aid light extraction, such as in an LED device. As InGaN growth continues, the InGaN grown from adjacent cavities coalesces, forming an InGaN layer 209 having relaxed (0001) InGaN regions 210 and a relaxed (0001) InGaN surface 207, which can be used to grow overlying semiconductor layers, as shown in Figure 2E. Figure 2E shows a plane 208a through the relaxed InGaN (0001) regions 210 and coplanar with the relaxed (0001) InGaN surface 207, a plane 208b that bisects the seed regions 202, and the InGaN regions between the seed regions 202. The centers of the seed regions are indicated by 208c, and the centers of the InGaN regions between the seed regions 202 are indicated by 208d.

[0088] FIG. 13 is a detailed cross-sectional view of a structure resulting from the process flow illustrated in FIGS. 2A-2E. A substrate 1301, such as (0001) sapphire, includes regions 1306 extending into the substrate 1301 that may be etched. GaN (or AlN) seed layer material 1302, characterized by an in-plane lattice constant a of a1, is located on the substrate 1301 in the unetched regions and beneath a masking layer 1303. InGaN 1305 nucleates at the edges of the seed layer material 1302 on the GaN seed surfaces, forming an InGaN / GaN heterojunction 1307 (i.e., a heterojunction located at the interface between the InGaN and GaN seed regions) perpendicular to the surface, sharing an equivalent crystallographic direction that is not parallel to the primary surface of the substrate 1301. The InGaN material 1305 grows at least partially laterally in the InGaN regions between the GaN seed surfaces 1307, relaxing toward the in-plane lattice constant a of the relaxed InGaN, a2. A plane 1308b parallel to the major surface of the substrate 1301 and bisecting the GaN seed surface 1307 is characterized by different in-plane lattice constants a at different locations within the cross section. For example, at the center point within the GaN seed region, the lattice constant along plane 1308b is characterized by a lattice constant a1 that matches the lattice constant a of GaN. At the center point 1305 between the GaN seed surfaces 1307, the lattice constant along plane 1308b is approximately a2, corresponding to the lattice constant of at least partially relaxed InGaN due to the average mole fraction of InN in the InGaN layer. The average mole fraction of InN in the InGaN layer is determined by the epitaxial growth conditions, such as temperature and the relative flow rates of organometallic precursors, such as trimethylindium (TMI) compared to trimethylgallium (TMG) in MOCVD. In the region between the midpoints of a1 and a2, the lattice constant along plane 1308b is characterized by an in-plane lattice constant a that is greater than a1 and less than a2 because a2 > a1. In a plan view (not shown), the variation in the in-plane lattice constant a within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see FIGS. 5 and 6).

[0089] Referring to FIG. 13, InGaN material 1305 coalesces on masking layer 1303 to form relaxed InGaN region 1304 with a planar (0001) InGaN surface 1305c. Plane 1308a, parallel to the primary surface of the original growth substrate and located within relaxed InGaN region 1304, is characterized by an in-plane lattice constant a of primarily a2. In particular, at center point 1305b between the GaN seed planes, the InGaN lattice constant along plane 1308a is characterized by the in-plane lattice constant a2. At the center point above the GaN seed planes, the InGaN in-plane lattice constant a along plane 1308a is slightly smaller than a2. In a plan view (not shown), the variation in the in-plane lattice constant a within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see FIGS. 5 and 6). Changes in the in-plane lattice parameter a of InGaN can be detected using, for example, X-ray diffraction (XRD) and reciprocal space mapping (RSM), and analyzed at the sub-micrometer scale using techniques known in the art, and in the relaxed (0001) InGaN region using grazing incidence angle techniques.

[0090] The midpoint of the plane 1308b within the seed region is shown as 1308c, and the midpoint of the plane 1308b between the seed regions is shown as 1308d.

[0091] The in-plane dimensions of the GaN seed regions 1302 may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1302 may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302, e.g., the width of the GaN seed regions 1302, may be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 may be, for example, 0.01 μm to 1 μm, 0.02 μm to 0.8 μm, 0.05 μm to 0.5 μm, or 0.1 μm to 0.4 μm.

[0092] 3A-3E show an example process flow for fabricating relaxed InGaN using a silicon-on-insulator (SOI) substrate. In this embodiment, it may be desirable to include a strain-controlling interlayer, such as a GaN, AlGaN, InGaN, or InAlGaN interlayer, in the semiconductor structure (not shown) to control wafer bow, as is well known for the growth of GaN on Si.

[0093] FIG. 3A shows substrate 301, oxide layer 301a, silicon layer 301b, seed layer 302, and masking layer 303. FIG. 3B shows cavity 304 after etching down to silicon layer 301b, thereby forming a seed region and seed surface from seed layer 302. FIG. 3C shows lateral overgrowth of InGaN from seed layer 302 within cavity 304 onto the seed surface of the seed region. This InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. In FIG. 3D, InGaN growth 306 from seed layer 302 occurs, with the InGaN growth surface coalescing, filling the cavity, and extending over a portion of mask layer 303. As InGaN growth continues, a planar relaxed InGaN layer 307 is formed, as shown in FIG. 3E. 3E shows a plane 308a through the relaxed InGaN region and coplanar with the surface-relaxed (0001) InGaN surface 307, a plane 308b that bisects the seed region 302, and the InGaN regions between the seed regions 302. The centers of the seed regions are shown as 308c, and the centers of the InGaN regions between the seed regions 302 are shown as 308d.

[0094] Figures 4A-4E show another example of a process flow for fabricating relaxed InGaN layers using an SOI substrate. This example is similar to the example of Figures 3A-3E, except that the top silicon layer and buried oxide layer 401a of the SOI substrate 401b are etched away (in region 404) to minimize competing growth of InGaN on the silicon substrate and promote InGaN growth on the seed surface.

[0095] FIG. 4A shows a silicon-on-insulator (SOI) substrate 401, oxide layer 401a, silicon layer 401b, seed layer 402, and overlying mask layer 403. FIG. 4B shows a cavity 404 resulting from etching down to the substrate 401, thereby forming a seed region from seed layer 402. In FIG. 4C, lateral InGaN growth 405 extends from the edge surface of seed layer 402 into cavity 404. This InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. As InGaN growth 406 continues, as shown in FIG. 4D, InGaN grown from the opposite seed surface coalesces and then grows vertically, filling the top of the cavity and extending over mask layer 403. Preferential growth from the seed surface compared to growth on the substrate results in the formation of a space 409, or void, between substrate 401 and InGaN layer 406. As InGaN growth continues, a planar relaxed (0001) InGaN surface 407 is formed, as shown in Figure 4E. Figure 4E shows a plane 408a through the relaxed InGaN region and coplanar with surface 407, a plane 408b that bisects seed region 402, and the InGaN regions between seed regions 402. The centers of the seed regions are shown as 408c, and the centers of the InGaN regions between seed regions 402 are shown as 408d.

[0096] FIG. 5 shows examples of mask patterns for etching seed material, including stripes, rectangles, triangles, and hexagons. For wurtzite materials, such as III-nitride materials, including InGaN, preferred pattern features are those with edges that share equivalent crystallographic directions, such as hexagons and triangles. Other shapes and other relative dimensions are also possible. The minimum dimension of the mask pattern may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern can be aligned to a specific crystallographic plane. For example, for a wurtzite material with a (0001) primary growth plane, the edges of the mask can be aligned to the (1-100) plane or the (11-20) plane, or any direction in between, to facilitate the growth of a high-quality, relaxed InGaN layer.

[0097] FIG. 6 shows another set of mask patterns that are the inverse of, but otherwise similar to, the mask patterns shown in FIG.

[0098] Figure 7 shows a conceptual planar cross-section of a patterned GaN seed material with lattice constant a, flanked by InGaN layers grown by lateral heteroepitaxy and relaxed to a relaxed lattice constant a by twist. Figure 7 illustrates the transition from an InGaN lattice 701 / 701a (solid circles), characterized by a lattice constant "a" similar to that of GaN, to a more relaxed InGaN lattice 702 / 702a (shaded circles), characterized by a lattice constant "a'". For sufficiently small dimensions, the deformation is entirely elastic, and no defects are formed. For larger dimensions, some plastic deformation may occur, but this is tolerable if the final defect density in subsequently deposited overlying semiconductor layers is sufficiently low. For example, the extended defect density in subsequently deposited semiconductor layers is 5E9 cm. 2 Less than, for example, 5E8cm 2 Less than 5E7cm 2 Less than 5E7cm 2 Less than 5E6cm 2 Less than or equal to 5E5cm 2 The lateral InGaN growth and coalescence methods provided by the present disclosure can promote the annihilation of threading dislocations in III-nitride materials.

[0099] Further control over the thickness and composition uniformity of relaxed InGaN growth can be achieved by growing multilayer structures rather than using bulk InGaN layers. For example, a 25% bulk InGaN layer can be grown using, for example, 3 nm thick GaN and 1 nm thick InN, or 2 nm thick GaN and 2 nm thick InN. 0.5 Ga 0.5The thickness of each layer can range from 0.5 nm to 100 nm, e.g., 1 nm to 30 nm. Multilayer structures are not limited to base and / or buffer layers, but may be used throughout the epitaxial stack, including semiconductor device layers such as n-type InGaN, p-type InGaN, and active layers overlying a relaxed InGaN layer, or layers between the relaxed InGaN layer and the overlying device layer. Such multilayer structures are sometimes referred to as superlattice layers. Multilayer structures are not limited to GaN and InGaN but may include other alloys available in the III-nitride system. For example, layers may include InAlGaN, InGaN, AlGaN, InAlN, and other selected compositions. In addition to InGaN / GaN, layer pairs may include InGaN / AlGaN, InGaN / InAlGaN, InAlGaN / InAlGaN, InGaN / InAlN, InAlN / GaN, etc.

[0100] Stepwise compositional growth can also be used to transition from the seed region to relaxed InGaN material. For example, the InN mole fraction in a layer grown on a GaN seed region can be slowly increased from approximately 0% to the target InN mole fraction to uniformly distribute stress and relaxation mechanisms (e.g., defects) outside the seed region. As another example, using a higher InN mole fraction adjacent to the GaN seed region can rapidly induce strain relaxation, and then the InN mole fraction can be gradually reduced as needed to achieve optimal growth conditions for the overlying relaxed InGaN layer.

[0101] When the in-plane lattice constant of the relaxed InGaN layer is increased relative to that of InGaN / GaN, the growth of subsequently deposited semiconductor layers can be performed at much higher temperatures than in the InGaN / GaN case. For example, InGaN with an in-plane lattice constant a of 3.205 Å has been shown to incorporate approximately 7% InN, compared to approximately 4% for InGaN / GaN. Because the incorporation of InN mole fraction into GaN is inversely proportional to the growth temperature using MOCVD, this suggests that increasing the in-plane lattice constant a of InGaN by approximately 0.015 Å to 0.020 Å can increase the useful growth temperature by approximately 50°C. Further increasing the in-plane lattice constant a of InGaN allows the use of even higher temperatures for the same InN mole fraction. This effect can be exploited not only to achieve higher quality semiconductor layers grown on relaxed InGaN due to reduced point defect formation at higher temperatures, but also to reduce or eliminate pits that occur at the sites of threading dislocations at the surface of the InGaN film. Ideally, the growth temperature of the InGaN layer is kept high enough to eliminate the pits or at least limit their diameter to much smaller than 1 μm, e.g., less than 200 nm, or even less than 50 nm. Small pits can be "filled" using a thin, high-temperature GaN or AlGaN layer grown on top of the pitted InGaN film.

[0102] The methods provided by the present disclosure may include recursion, which may be useful for obtaining large lattice constant changes. For example, a relaxed InGaN layer can be used as a seed layer to provide a seed surface for the growth of a relaxed InGaN layer with a higher InN mole fraction. The resulting new relaxed InGaN layer can then be used as a seed layer in another step of the process. This approach may be useful for obtaining relaxed InGaN layers with very high InN mole fractions, which may be suitable as a base layer for the growth of active semiconductor layers configured to emit radiation at longer wavelengths, such as beyond the red, deep red, or even infrared wavelengths (e.g., wavelengths in the 700 nm to 1.6 μm subrange). Similarly, such approaches can be used to form photosensitive materials optimized for photovoltaic applications.

[0103] The relaxed InGaN layers provided by the present disclosure can serve as templates and / or support structures for growing optical and / or electrical devices, and very large area wafers are possible, including 150 mm, 200 mm, or larger diameter wafers, thereby facilitating high volume, low cost manufacturing of these devices.

[0104] As an example, Figure 8 shows an LED structure formed by growing an n-type layer 806 (e.g., with doped Si or Ge) on the relaxed (0001) InGaN surface of an InGaN layer 804, followed by an InGaN-containing active region 807, an optional p-type electron blocking layer 808 comprising, for example, GaN, AlGaN, or InGaN (or a multilayer comprising an alloy thereof), and a p-type layer 809 overlying the p-type GaN or InGaN layer. A heavily doped, e.g., Mg-doped, p-type contact layer 810, comprising, for example, GaN or InGaN, overlies the p-type layer 809 and provides an ohmic contact to the p-side of the device. As shown in Figure 8, the semiconductor structure underlying the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. To the extent that there is a refractive index difference between these various features, the presence of a refractive index difference can help improve light extraction from the device. In a related embodiment, an air gap is formed below region 805, and further light extraction benefits may be realized. The resulting semiconductor wafer can undergo a series of process steps, such as lithography, etching, and semiconductor deposition, to form isolated LED regions with appropriate electrical contact materials for the n-type and p-type layers. Such contact materials can include those with suitable optical properties, such as high optical reflectivity and / or transparency. Electrode metallization 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned to provide electrical connections, for example, using wire bonds. Various transparent conductive oxide (TCO) materials, such as indium tin oxide (ITO), can be used to fabricate the current spreading layer 811, particularly for the resistive p-type layer. After fabricating the semiconductor structures, the wafer can be diced to provide individual optoelectronic elements and devices that can be mounted into appropriate optoelectronic packages by various means, such as epoxy die attach, gold-gold bonding, or soldering.Electrical contact can be made to the p-type and n-type layers, for example using wire bonds, to ultimately form a functional optoelectronic element or device that can be powered. The device can further include a light-emitting down-conversion material and / or an encapsulation material, such as silicone, to provide desirable light output characteristics, including white light for lighting applications. These devices can be used in systems for lighting and / or displays.

[0105] The blocking layer 808 may be located directly above the active region 807, or may be spaced from the active region by a spacer layer (not shown in FIG. 8). Typically, the spacer layer is nominally undoped and may be a layer for which the CpMg source is turned on during MOCVD growth to allow for p-type doping of the blocking layer or the layer above the blocking layer.

[0106] As shown in Figures 9A-9D, various flip-chip (FC) LED architectures are possible, including (a) standard, (b) thin film flip-chip (TFFC) where the initial growth substrate is removed but the mask and seed layer portions are retained, (c) TFFC where the mask and seed layer portions are removed, and (d) TFFC where the mask and seed layer portions are removed and the exposed InGaN layer is textured (for light extraction purposes), such as by photolithography and / or chemical-based etching techniques.

[0107] The semiconductor structure shown in Figures 9A-9D includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and initial InGaN growth region 905, an n-type layer 906, an InGaN-containing active region 907, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization 911, and an n-side electrode metallization 912. In Figure 9B, the substrate has been removed, in Figure 9C, the growth region and mask region have been removed, and in Figure 9D, a portion of the relaxed InGaN region 904 has been removed and / or roughened 904a, for example, to improve certain optical properties of the device.

[0108] FIG. 10 shows a laser diode structure grown on a relaxed InGaN layer. As shown in FIG. 10, a relaxed InGaN layer 1004 including an initial InGaN region 1005 is located above a mask region 1003, a seed region 1002, and a substrate 1001. The laser diode can be formed by growing an n-type optical confinement ("cladding") layer 1007 on the relaxed InGaN material 1004 and an n-type InGaN contact layer 1006, then growing an InGaN-based active region 1009 including a waveguiding region including waveguiding layers 1008 and 1010 on either side of the InGaN-containing active layer 1009, followed by growing a p-type optical confinement ("cladding") layer 1011. Layers 1012 and 1013 are located on top of the p-cladding layer(s) 1011 and may include a p-type AlGaN "electron blocker layer" and a p-type GaN layer, respectively. Wafer fabrication of laser diodes is similar to that of LEDs, except that the devices are formed in stripes to form the laser cavity. After dicing or other singulation techniques and the formation of etched or cleaved mirror facets, highly reflective and anti-reflective dielectric coatings can be deposited on the back and front facets, respectively (not shown). Depending on the material selection and application details, the laser diode can be mounted epi-side down or substrate-side down in a suitable optoelectronic package. Electrical contact can be made to the heavily doped p-type contact layer 1014 and n-type contact layer 1006 via electrode metallizations 1015a and 1015b, respectively, to form and power a functional optoelectronic element or device. Laser diodes are used in systems for illumination and / or display.

[0109] The relaxed InGaN layers provided by this disclosure are applicable to a wide range of compound semiconductor devices to affect the performance of a wide range of system solutions for various applications, including lighting devices and systems (FIG. 11) and display devices and systems (FIG. 12). This approach can also be applied to photovoltaics.

[0110] The target composition of the relaxed InGaN layer can be selected depending on the intended device, application, and performance requirements. For conventional InGaN light-emitting diodes lattice-matched to GaN, the best performance is achieved in devices emitting in the violet wavelength range. At these wavelengths, the strain state of the InGaN quantum wells relative to the GaN base layer is approximately 1% to 2% compressive. The corresponding compositional difference is large enough to enable bandgap engineering to achieve very high quantum efficiency devices. Meanwhile, the strain state is low enough to allow the formation of relatively thick InGaN quantum well (QW) layers, reducing carrier density and mitigating nonradiative Auger recombination (also known as "droop"). Applying this acceptable range of strain state to other emission wavelengths, the preferred composition range of the relaxed InGaN base layer provided by the present disclosure can be calculated for a wide range of emitters, from blue (approximately 450 nm) to infrared (approximately 1.3 μm) wavelengths. The preferred ranges are listed in Tables 1 and 2. [Table 1] [Table 2]

[0111] 14A and 14B graphically illustrate the preferred ranges of InN mole fraction and lattice constant, a, for relaxed (0001) InGaN layers used as templates for fabricating light emitting diodes and laser diodes, consistent with the parameters shown in Tables 1 and 2, depending on the peak emission wavelength. x Ga 1-x The InN mole fraction x of the N-based layer is determined by the peak emission wavelength λ. min ≦x≦x max This suggests that the following condition should be satisfied, where X min and X max are defined by EQN.1 and EQN.2, respectively: xmin =-6.046E-07λ 2 +1.837E-03λ-6.917E-01(λ≧440nm) EQN.1 x max =-6.152E-07λ 2 +1.847E-03λ-6.142E-01(λ≧440nm) EQN.2

[0112] Similarly, the relaxed In x Ga 1-x The in-plane lattice constant a of the N-based layer is determined according to the peak emission wavelength λ. min ≦a≦a max The following condition should be satisfied, where a min and a max are defined by EQN.3 and EQN.4, respectively: a min =-2.067E-07λ 2 +6.366E-04λ-2.951(λ≧440nm) EQN.3 a max =-2.190E-07λ 2 +6.575E-04λ-2.970(λ≧440nm) EQN.4

[0113] The methods and semiconductor structures provided by the present disclosure can be adapted to fabricate vertical cavity surface emitting lasers (VCSELs). The composition selection of the relaxed InGaN-based layer for LDs or VCSELs is similar to that for LEDs and is shown in Tables 1 and 2.

[0114] FIGS. 15A-15F illustrate example steps in a method for fabricating a relaxed InGaN layer on the edge surface of a faceted GaN seed region. The method includes providing a (0001) GaN or AlN seed layer 1502 on a substrate 1501. FIG. 15A shows the substrate 1501, the seed layer 1502 thereon, and the mask layer 1503 thereon. The GaN seed layer may have a thickness of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. Referring to the process flow illustrated in FIGS. 15A-15F, the seed layer 1502 may be covered with a masking layer 1503 comprising a material that rejects or slows down the GaN nucleation. The masking layer 1503 can be patterned and etched into the various patterns described herein using any suitable photolithography, including nanolithography and etching methods (wet, dry, or a combination thereof). The exposed GaN in the openings in the mask 1504 formed by etching can then be used to nucleate GaN seed material 1506. As shown in Figures 15C and 15D, GaN seed material 1506 is grown from the openings in the mask, and by appropriately selecting growth conditions, a seed region with edges that are triangular facets with a hexagonal base can be formed. For example, the structure can be a hexahedron with a hexagonal base and have triangular facets that are {1-101} equivalent planes. After the facets are fully formed as shown in Figure 15D, the triangular facet surfaces 1507 can be used as seed surfaces for lateral overgrowth of at least InGaN, forming a heterojunction that is not coplanar with the substrate surface. The small dimensions of the GaN seed surface (facet) and the selection of the InGaN target composition promote relaxation of the overgrown InGaN as the InGaN thickness increases, providing a flat, crystallographically equivalent orientation and ensuring consistency. The InGaN 1508 grows coherently and relaxes towards its relaxed lattice constant, forming hexagonal structures with triangular facets that are the relaxed InGaN as shown in Figure 15E.These InGaN facets can grow further and eventually coalesce with adjacent InGaN growth surfaces of other planar seed facets. As shown in Figure 15F, the coalesced InGaN is then grown on top of the masking layer and seed region, and growth conditions (e.g., growth temperature and TMI flow rate) are selected to form a continuous, planar relaxed InGaN layer or template 1509 with a relaxed (0001) InGaN surface as the top region of the structure. An advantage of this method is that it does not require etching of the GaN (or InGaN, AlGaN, or AlN) seed material to provide a seed surface area for InGaN nucleation. Furthermore, this method is well suited when the growth substrate is a III-nitride material, such as a GaN or AlN substrate. Therefore, this method achieves low dislocation densities (e.g., 5E7 cm for GaN substrates) for long-life operation (>10,000 hours). -2 This facilitates the fabrication of LD devices where a lower annealing rate (less than 1000 nm) is desired.

[0115] FIGS. 16A-16F illustrate another method for fabricating relaxed InGaN layers on faceted GaN surfaces. This method is similar to the method shown in FIGS. 15A-15F, except that GaN seed material is nucleated directly on the substrate. In this approach, a substrate 1601 suitable for GaN nucleation, such as sapphire, SiC, sapphire, AlN, or GaN, may be provided. Referring to FIG. 16A, the substrate 1601 may be covered with a masking layer 1602 of a material that slows down GaN nucleation. As shown in FIG. 16B, the masking layer 1602 is patterned and etched into various patterns 1604 using photolithography, such as nanolithography, and etching techniques (wet, dry, or a combination thereof). The substrate 1603 exposed through the mask openings formed by the etching can be used for the nucleation of GaN seed material 1605, as shown in FIG. 16C. This seed material grows through the mask openings. By selecting appropriate growth conditions, a GaN seed region with triangular facet edges and a hexagonal base can be formed. For example, the seed region can be hexahedral, with triangular facets that are {1-101} crystallographically equivalent planes. As shown in Figure 16D, after the seed region is fully formed, the triangular facet surfaces 1607 are used as seed surfaces for the lateral overgrowth of at least InGaN, forming six heterojunctions on crystallographically equivalent planes that are not coplanar with the substrate. The small dimensions of the GaN seed surfaces and the selection of the target composition of the grown InGaN material promote relaxation of the InGaN grown on the seed surfaces. Furthermore, each seed surface provides a flat, crystallographically equivalent orientation, ensuring consistency throughout the grown InGaN material. The InGaN grows coherently, relaxing toward its relaxed lattice constant and forming relaxed InGaN facets 1608, as shown in Figure 16E. These facets continue to grow and eventually merge with adjacent InGaN growth surfaces grown from other seed regions.As shown in Figure 16F, the coalesced InGaN is then grown on the masking layer, and growth conditions (e.g., growth temperature and TMI flow rate) are selected to form a continuous, planar relaxed InGaN region 1609, or template, across the entire substrate, with a relaxed (0001) InGaN surface. An advantage of this method is that it does not require etching of the GaN (or AlN) material to provide a seed surface for InGaN nucleation. Another advantage of this method is that the entire process can be accomplished in a single epitaxial growth process. Furthermore, this method is well suited when the growth substrate is a III-nitride material, such as a GaN or AlN substrate.

[0116] FIG. 17A provides a detailed cross-sectional view of the structure resulting from the process flow illustrated in FIGS. 15A-15F. A substrate 1701, such as (0001) sapphire, can serve as the primary growth substrate for a GaN (or InGaN, AlGaN, or AlN) seed layer 1702, characterized by an in-plane lattice constant a of a1. The GaN seed layer 1702 is grown between masked regions 1703, forming a GaN seed region 1702a with exposed edges of a crystallographically equivalent, planar GaN seed surface. InGaN material nucleates on the triangular GaN seed surface of the GaN seed region, forming a heterojunction 1707 that is not parallel to the primary surface of the original growth substrate 1701. The heterojunction 1707 may be formed on a stable, crystallographically equivalent facet of the GaN seed region, such as a {1-101} crystallographically equivalent facet. The InGaN material grows at least partially laterally, relaxing toward an in-plane lattice constant a of a2 for the relaxed InGaN in the region 1705 between the GaN seed surfaces. A plane 1708b, parallel to the primary surface of the original growth substrate and bisecting the GaN seed material, is characterized by different in-plane lattice constants a at different locations along the plane. In particular, at the center point within the GaN seed region 1702a, the GaN material is characterized by an in-plane lattice constant a of a1, while at the center point 1705 between the GaN seed regions 1702a, the in-plane lattice constant a is approximately a2. In the GaN region between these two center points, the in-plane lattice constant a is greater than a1 but less than a2, because a2 > a1. In a plan view (not shown), the variation in the GaN in-plane lattice constant a within the plane 1708b is characterized by a two-dimensional mask pattern applied to the GaN seed layer material (see Figures 5 and 6).

[0117] As shown in Figures 17A and 17B, plane 1708b intersects the edge of seed region 1702a, placing heterojunction 1709b at the interface between InGaN region 1704 and seed region 1702a. The heterojunction is coplanar with the first crystallographic plane or first facet of the seed region. Any plane, such as plane 1708b, that is parallel to the primary growth plane and intersects both an InGaN region (e.g., 1708c) and seed region 1702a intersects the edge of seed region 1702a, placing heterojunction 1709c at the interface between the InGaN region and the seed region, coplanar with the second crystallographic plane or second facet of the seed region. As shown in Figures 17A and 17B, the first and second crystallographic planes are the same. The first and second crystallographic planes or facets may be crystallographically equivalent crystallographic planes or facets.

[0118] The InGaN material coalesces on the masking layer 1703, forming a relaxed InGaN layer 1704 with a planar relaxed (0001) InGaN surface 1705c. Plane 1708a, parallel to the primary surface of the original growth substrate and located within InGaN layer 1704 near surface 1705c, is characterized primarily by an in-plane lattice constant a of InGaN of a2. At center points 1705 between the GaN seed regions, the InGaN lattice constant a is a2; at center points within the GaN seed regions, the in-plane lattice constant a may be slightly smaller than a2. In a plan view (not shown), any variation in the in-plane lattice constant a within plane 1708b is characterized by a two-dimensional mask pattern applied to the seed layer material (see Figures 5 and 6). Variations in the in-plane lattice constant a are detectable by measurement techniques such as XRD and RSM and can be analyzed on a submicron scale. The midpoint along plane 1708b within seed region 1702a is shown as 1708c, and the midpoint between seed regions 1702a is shown as 1708d.

[0119] The in-plane dimensions of GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of mask material 1703 may be, for example, 0.01 μm to 1 μm.

[0120] FIG. 17B provides a detailed cross-sectional view of the structure resulting from the process flow of FIGS. 16A-15F. This structure is similar to the structure shown in FIG. 17A, and like elements are identified with the same numbers. However, in the structure of FIG. 17B, the planar starting GaN (or AlN) seed layer 1702 is not present. Instead, GaN (or AlN) seed material is nucleated directly on the substrate 1701 in the openings between the mask regions 1703. The substrate may be sapphire, GaN, AlN, silicon carbide, silicon, etc.

[0121] The wurtzite III-nitride crystalline semiconductor structure may, for example, include a substrate including a first substrate region and a second substrate region, and a first (0001) In layer overlying the first substrate region. x1 Al y1 Ga 1-x1-y1 The first In containing N growth region x1 Al y1 Ga 1-x1-y1 The N growth layer and the second patterned In layer on top of the second substrate region. x2s Al y2s Ga 1-x2s-y2s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2s A second (0001) In layer on top of the N seed region x2 Al y2 Ga 1-x2-y2 The second In containing N growth region x2 Al y2 Ga 1-x2-y2 and a first (0001) InN growth layer. x1 Al y1 Ga 1-x1-y1The N growth region is characterized by a first in-plane lattice constant a and a second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by a second in-plane lattice constant a, the second in-plane lattice constant a being greater than the first in-plane lattice constant a, where 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1, 0≦x1≦1, 0≦y1≦1, and x1+y1≦1, and 0<x2≦1であり、0≦y2≦1であり、x2+y2≦1、x2> Let's say x1.

[0122] The substrate may comprise sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator, gallium oxide, or aluminum nitride.

[0123] Second Patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes GaN.

[0124] First Patterned In x1s Al y1s Ga 1-x1s-y1s An N seed region may be located over the first substrate region, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1. x1 Al y1 Ga 1-x1-y1 The N growth layer is first patterned. x1s Al y1s Ga 1-x1s-y1s The first patterned In may be located above the N seed region. x1s Al y1s Ga 1-x1s-y1s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region may include GaN. x1s Al y1s Ga 1-x1s-y1s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2sThe first patterned In and N seed regions may have the same composition. x1s Al y1s Ga 1-x1s-y1s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region may have a different composition.

[0125] A first surface parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region is such that an intersection of the first surface and a first edge of the second patterned seed region is a first In. x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction, and the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the first crystal face of the seed region. x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction may include a compositional step from x1s and y1s to x1 and y1.

[0126] Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region is a second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 Determine the location of the N heterojunction and add the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1The N heterojunction is coplanar with the second crystal face of the seed region, and the first crystal face and the second crystal face are crystallographically equivalent.

[0127] A first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region is formed such that an intersection of the first plane with a first edge of the first patterned seed region is a first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The first In is characterized by determining the position of the N heterojunction. x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the first crystal face of the seed region. x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction may include compositional steps from x2s and y2s to x2 and y2.

[0128] Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region is a second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 Determine the location of the N heterojunction and add the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the second crystal face of the seed region.

[0129] The group III nitride semiconductor structure is (a) In x Ga 1-xa seed region including N (0≦x≦1) and a wurtzite III-nitride crystal structure; and (b) a first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region, the intersection of the first plane and a first edge of the seed region being In. x Ga 1-x N / In y Ga 1-y Determine the location of the N heterojunction, where 0<y≦1であり、かつy> Let x and In x Ga 1-x N / In y Ga 1-y The N heterojunction may comprise: (c) a first plane that is coplanar with a first crystallographic face of the seed region; (d) an optional second plane that is parallel to a (0001) plane of the wurtzite III-nitride crystal structure and intersects a second edge of the seed region, wherein the III-nitride heterojunction is coplanar with the second crystallographic face of the seed region; and (d) a relaxed (0001) InGaN region overlying the seed region, wherein the relaxed (0001) InGaN region is characterized by an in-plane lattice constant a greater than 3.19 Å, and wherein each of the first and second crystallographic faces are crystallographically equivalent.

[0130] The group III nitride semiconductor structure is (a) In x Ga 1-x a seed region including N (0≦x≦1) and a wurtzite III-nitride crystal structure; and (b) a first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region, the intersection of the first plane and a first edge of the seed region being In. x Ga 1-x N / In y Ga 1-y Determine the location of the N heterojunction, where 0<y≦1であり、かつy> Let x and In x Ga 1-x N / In y Ga 1-yThe N heterojunction may comprise: (c) a first plane that is coplanar with a first crystallographic face of the seed region; and (d) an optional second plane that is parallel to a (0001) plane of the wurtzite III-nitride crystal structure and intersects a second edge of the seed region, wherein the III-nitride heterojunction is coplanar with the second crystallographic face of the seed region; and (d) a relaxed (0001) InGaN region overlying the seed region, wherein the relaxed (0001) InGaN region is characterized by an in-plane lattice constant a greater than 3.19 Å, and wherein each of the first and second crystallographic faces are crystallographically equivalent.

[0131] The first parallel plane may intersect two facets of the seed region. An example is plane 1708b in Figures 17A and 17B. The facets of the seed region are parallel to a crystal plane of the seed region, such as a crystal plane of a wurtzite crystal structure. The facets of the seed region may be crystallographically equivalent facets. The intersection of the first parallel plane and the facets of the seed region is defined by In x Ga 1-x N / In y Ga 1-y Determine the location of the heterojunction, such as N, where 0≦x<1 and 0<y≦1であり、かつy> x, or 0≦x≦1, and 0<y≦1であり、かつy> Let's say x.

[0132] An optional second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the seed region defines the location of the III-nitride heterojunction. An example is plane 1708c in FIGS. 17A and 17B . The second plane may intersect the same facet as the first plane. The second plane may intersect a facet of the seed region that is coplanar with a crystal plane of the seed region. Each of the crystal planes may be crystallographically equivalent planes. Each of the seed regions is characterized by a facet parallel to a crystal plane of the seed region, such as a crystal plane of the wurtzite crystal structure. Each of the crystal planes may be crystallographically equivalent planes. Each of the crystal planes may be crystallographically equivalent to a {10-11} plane. Each of the crystal planes may be crystallographically equivalent to a {1-100} plane. Each of the crystal planes may be crystallographically equivalent to a {11-20} plane. Each of the crystal planes may be a plane between the (1-100) plane or the (11-20) plane.

[0133] The InGaN regions are located between the seed regions. The InGaN regions between the seed regions, or at least some of the InGaN regions, may be partially relaxed InGaN regions. The InGaN regions comprise multiple InGaN layers or regions, each having a different elemental composition. The relaxed (0001) InGaN region may be located above the seed regions. The relaxed (0001) InGaN region may be a fully relaxed (0001) InGaN region and may have an in-plane lattice constant a greater than 3.19 Å (e.g., 3.20 Å to 3.50 Å).

[0134] The seed region may have two or more facets, such as two, three, four, five, or six facets. The seed region may have six facets. The seed region may have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. The seed region may have a triangular base or a hexagonal base. The seed region may have a hexagonal base.

[0135] Each seed region may comprise, for example, (0001) GaN and may have, for example, an in-plane lattice constant a of about 3.189 Å. Each seed region may comprise GaN, and the edges of each seed region may be inclined to In. x Ga 1-x The location of the InGaN / GaN heterojunction can be determined where x>0 and the III-nitride heterojunction is a GaN-InGaN heterojunction.

[0136] Each seed region may comprise, for example, (0001) GaN and may have, for example, an in-plane lattice constant a of about 3.189 Å. Each seed region may comprise GaN, and the edges of each seed region may be Al y Ga 1-y The N / GaN heterojunction can be located where x>0 and the III-nitride heterojunction is a GaN-AlGaN heterojunction.

[0137] Each seed region is, for example, (0001)In x Ga 1-x Each seed region may contain InN and may have an in-plane lattice constant a of, for example, greater than 3.189 Å. x Ga 1-x N, and the edge of each seed region may include In x Ga 1-x N / In y Ga 1-y The N heterojunction can be located where x>y and the III-nitride heterojunction is an InGaN-InGaN heterojunction.

[0138] Each seed region may be, for example, In x1 Al y1 Ga 1-x1-y1 N (where 0≦x1<1, 0≦y1<1, and x1+y1≦1) and a wurtzite III-nitride crystal structure. x1 Al y1 Ga 1-x1-y1 N, and the edge of each seed region may include In x1 Al y1 Ga 1-x1-y1 N / In x2 Al y2 Ga1-x2-y2 The position of the N heterojunction (where 0≦x2<1, 0≦y2<1, x2+y2≦1, and x2>x1) can be determined, and it is an (In)(Al)GaN / (In)(Al)GaN heterojunction.

[0139] 18-20 illustrate embodiments of the present invention. Figures 18A, 18B, and 18C show top-view schematics of so-called "V-pit" structures that can form during growth of III-nitrides on a base surface. Particularly for III-nitride materials grown at low temperatures, such as GaN grown using MOCVD at temperatures below 800°C, adatom kinetics ensures that the semiconductor material does not tend to fill near the dislocation core, and that the pit forms from the stable (10-11) plane with the dislocation core at its center. As growth continues under low-temperature conditions, the pit grows (Figure 18B) and impinges (Figure 18C). As the pit grows, the total surface area of ​​the exposed (10-11) facets becomes equal to or larger than the area of ​​the exposed (0001) surface. The presence of this large surface area (10-11) facet provides an opportunity to form high quality relaxed InGaN on a (10-11) seed surface such as GaN, with each facet being crystallographically equivalent, as envisioned in this invention.

[0140] For example, as shown in Figure 19, GaN can be nucleated at low temperatures on suitable substrates such as GaN, sapphire, Si, SiC, and AlN. After a GaN epitaxial film of reasonably high quality is obtained, for example by growing the GaN epitaxial film at a high temperature (e.g., above 900 °C), the growth conditions can be changed again to form V-pits, for example by growing GaN at a temperature below 800 °C. Growth is then stopped, the growth structure is removed from the MOCVD reactor, and the GaN epitaxial film is then deposited on SiO2 or SiN. xA suitable growth mask layer, such as a dielectric layer, can be selectively deposited on the (0001) GaN surface but not on the (10-11) GaN surface. This can be achieved in a variety of ways, including high-angle sputtering and deposition, or selectively depositing photoresist in the V-pits followed by deposition and stripping. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. Next, InGaN, optionally preceded by the deposition of a thin layer of GaN, can be selectively grown on the exposed GaN seed region material on the (10-11) facet. By targeting the InN mole fraction, the increased thickness of the InGaN layer can induce large strains and promote relaxation. InGaN continues to grow on the masked regions and coalesce with InGaN grown from adjacent seed regions, thereby providing a flat, high-quality relaxed (0001) InGaN region and surface that can serve as a template for device fabrication, as described in this disclosure. InGaN layers can be grown at temperatures higher than those typical for InGaN / GaN growth, such as temperatures above 900°C. This is because relaxed InGaN material incorporates In much more readily than InGaN, which is pseudomorphic to GaN. The increased growth temperature can fill V-pit defects and provide a coalesced, planar film. Control over the morphology and compositional uniformity of relaxed InGaN growth can be facilitated by growing multilayer structures rather than using bulk InGaN layers. For example, a 25% bulk InGaN layer can be grown with 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In. 0.5 Ga 0.5 N alternating layers. The thickness of each individual layer ranges from 0.5 nm to 100 nm, for example, from 1 nm to 30 nm. Many levels of such multilayer structures can be used, for example, 2 to 10 layers, 2 to 100 layers, or more than 100 layers.

[0141] In another example, the masking step can be omitted, and the entire process can be completed in situ in the growth chamber. For example, as shown in FIG. 20, GaN can be nucleated on a suitable substrate, such as GaN, sapphire, Si, or AlN. After a certain level of high-quality GaN epitaxial film is obtained, for example, by growing at a high temperature (e.g., above 900°C), the growth conditions can be changed again to grow GaN at a temperature below 800°C, for example, to form a V-pit. The V-pit can be grown such that the exposed surface area of ​​the {10-11} equivalent facet is larger than that of the (0001) GaN. The exposed surface area of ​​the (10-11) facet can be more than twice that of the (0001) GaN, e.g., 10 times that of the (0001) GaN. Then, InGaN can be selectively grown on the (10-11) facet, which serves as the seed region. The InN composition can be targeted to induce large strains and thus relaxation as the thickness of the InGaN layer increases beyond a critical thickness. The InGaN continues to grow and coalesces with InGaN grown from adjacent seed regions, thereby providing planar, high-quality relaxed (0001) InGaN regions that can serve as templates for device fabrication.

[0142] Because the (0001) GaN growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing InGaN to relax and become the dominant growth surface as the film thickness increases. It can be useful to grow the InGaN layer at temperatures higher than those typical for InGaN / GaN growth. This is possible because relaxed InGaN material can incorporate In much more easily than InGaN, which is pseudomorphic to GaN. The increased growth temperature fills the V-pit defects, forming a coalesced, planar film. Control over the morphology and compositional uniformity of relaxed InGaN growth can be facilitated by growing a multilayer structure rather than using a bulk InGaN layer. For example, a 25% bulk InGaN layer can be composed of 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In. 0.5 Ga 0.5 N alternating layers. The thickness of each individual layer can range from 0.5 nm to 100 nm, for example, from 1 nm to 30 nm. Many levels of such multilayer structures can be used, for example, 2 to 10 layers, 2 to 100 layers, or more than 100 layers.

[0143] For example, a c-plane (0001) sapphire substrate can be loaded into an MOCVD reactor that can supply at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be applied, followed by high-temperature GaN growth, which can include three-dimensional island formation before coalescence into a two-dimensional (0001) GaN film. This three-dimensional to two-dimensional transition helps redirect threading dislocations laterally, reducing the overall threading dislocation density at the growth surface, which can be as low as 1E9 cm. -2 Finally, the planar GaN layer can be reduced to less than 1E8 cm -2A dislocation density of 10-11 can be achieved. The growth temperature can then be reduced (e.g., below 800°C) to form V-pit structures at the dislocation core, characterized by inclined (10-11) planes. These planes can form an angle of approximately 63 degrees with respect to the (0001) growth plane. The thickness of the low-temperature layer controls the height of the V-pits, which increases with growth, so that the total surface area of ​​the exposed {10-11} facets is greater than that of the (0001) plane, as shown in Table 3 for this particular example. [Table 3]

[0144] For example, if the dislocation density is 1E8cm -2 In this case, the target V-pit height is 0.14 μm or more.

[0145] Lower dislocation densities can be achieved through a variety of mechanisms, including starting with a substrate with lower dislocation density, "freestanding" GaN substrates, in-situ SiN x This can be achieved by utilizing various threading dislocation filtering methods such as layers, epitaxial lateral overgrowth techniques, or simply by increasing the growth thickness. By these and other means known in the art, dislocation densities can be reduced to 1E7 cm. -2 Less than 1E6cm -2 Less than or even 1E5cm -2 Such lower dislocation densities are particularly beneficial to the performance and reliability of laser diodes.

[0146] After the desired surface area ratio between the (10-11) and (0001) materials is achieved, trimethylindium (TMI) is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed region to induce strain relaxation. The InGaN layers can be periodically interleaved with GaN layers. For example, each InGaN layer can be 0.5 nm to 100 nm thick, e.g., 1 nm to 30 nm thick, sandwiched between GaN layers of similar thickness. To induce strain relaxation, the average composition of the strain-relieved layer must be reasonably high. For example, the average InN content can be greater than 5%. The growth temperature can be increased after or before the onset of strain relaxation to help planarize the growth and achieve a planar, uniformly relaxed (0001) InGaN layer for device fabrication.

[0147] Planarization techniques apply not only to this embodiment but to all embodiments disclosed herein and include modifying growth conditions such as growth temperature, V / III ratio, use of dopants (e.g., Mg doping) to promote lateral versus vertical growth, etc. Composition can also play a role, including the use of multilayer films (as described elsewhere herein) to promote planarization of epitaxial films.

[0148] While the above discussion focuses on V-pits, which rely on the formation of dislocation cores, other means of forming semipolar facets across III-nitride-based materials or substrates can also be employed, such as annealing and decomposition techniques designed to reveal specific growth planes within the system. These techniques do not necessarily rely on dislocation cores and can provide techniques that provide the desired seed region facets without relying on dislocations.

[0149] While the preceding discussion has focused on GaN seed regions, it is important to note that it is also possible to utilize InGaN (or AlGaN) seed regions, as long as that material is pseudomorphic to any underlying GaN layers, such as the GaN nucleation and / or buffer layers. The seed region is the region in the vicinity of the InGaN-GaN (or InGaN-InGaN) heterojunction that ultimately induces relaxation. The seed material beneath these regions is referred to as the seed material, not the seed region.

[0150] Relaxed InGaN layers and semiconductor structures including relaxed InGaN layers provided by the present disclosure can be used in the fabrication of electronic and optoelectronic devices, including InGaN-based optoelectronic devices such as LEDs, LDs, and VCSELs. LEDs and LDs including relaxed InGaN layers provided by the present disclosure can be used in lighting and display systems. In the case of LEDs in particular, devices may be formed on a relaxed InGaN-based layer that is located on a substrate. The substrate can be thinned by techniques such as grinding, lapping, or etching, and diced to provide individual LED chips or dies by means known in the art, such as sawing, scribe-and-break, or laser scribe-and-break. More typical LED chip or die dimensions are, for example, 100 x 100 μm. 2 ~5×5mm 2 The device dimensions of the micro LED may be 100 x 100 μm. 2 Less than 0.5 x 0.5 μm 2Individual LED chips can be mounted in suitable packaging elements, providing leads for electrical contact and heat dissipation of the device. For small devices, such as microLEDs with dimensions less than 30 μm, die attachment can be achieved using suitable methods, such as epoxy or silicone attachment, solder-based attachment, or mass transfer techniques. Electrical connection between the chip and the package can be completed using bond wires, such as Au or Ag wire, to connect the anode and cathode leads in the package to the respective contact metallization, or electrodes, on the LED chip. For flip-chip devices, electrical contact can be made through an intermediate submount positioned between the LED chip and the package. The chip electrodes can be attached to a submount carrier by means such as solder attachment or Au bump attachment. After dicing, the submount carrier can be attached to the package by any suitable method.

[0151] The desired emission color from a packaged LED device can be achieved by fabricating and providing a relaxed InGaN-based LED with the desired peak emission wavelength. Multiple such LED chips, possibly with different peak emission wavelengths, can be packaged separately or combined into a multi-chip package. For example, a single package can contain red-, green-, and blue-emitting LED chips, arranged in a circuit and electrically coupled to driver circuitry within or outside the package to drive the LEDs. Circuit details and drivers can be selected to operate the different colored LEDs individually or together, providing a wide range of overall emission characteristics, such as white light for use in lighting applications or as backlights for liquid crystal display (LCD) devices, such as television displays, computer monitors, mobile phone displays, and wearable display devices.

[0152] One or more LED chips can be combined with a luminescent downconversion material to provide a desired emission spectrum. Such luminescent downconversion materials can include phosphors, semiconductor nanoparticles such as quantum dots, or perovskite materials. Multiple luminescent downconversion materials can be combined in a single package. The LED chip's emission wavelength can be selected to excite the luminescent downconversion material, resulting in light emission from the package being a combination of the LED chip's direct emission and the luminescent downconversion material's emission. Alternatively, light emission can be primarily from the luminescent downconversion material, with the LED chip's light being almost completely absorbed by the luminescent downconversion material or blocked or filtered from emitting light from the package. Packaged LEDs using luminescent downconversion materials can be used to generate white light, which can be useful for lighting applications. Such devices can be electrically coupled to a driver circuit, powered from an external power source such as a mains or battery power source, thermally coupled to a heat sink, and optically coupled to various optics or lenses to provide lighting devices such as LED lamps and LED luminaires.

[0153] According to the present invention, LED chips with smaller dimensions can be manufactured, especially 0.5 x 0.5 μm. 2 ~50×50μm 2Devices with dimensions of 1000 um, so-called "micro LEDs," can be fabricated. Conventional dicing techniques are not well suited for micro LEDs, so other means for device singulation can be employed. For example, singulation can be achieved by forming LEDs of the desired dimensions on a substrate, then adhering the top surface of the LED to a carrier, such as blue tape or a submount carrier, and then removing the substrate. Individual devices can then be picked up and placed into a packaging element or onto the backplane of a micro LED-based display. Advanced die handling techniques known in the art can be used to handle micro LED devices. In particular, red-, green-, and blue-emitting LEDs according to the present invention can be formed into micro LEDs and arranged to provide micro LED displays, which can be integrated into systems such as televisions, computer monitors, tablets, mobile phones, and wearable devices. Generally, singulation techniques other than conventional dicing include laser cutting, stealth dicing, chemical etching, and plasma etching.

[0154] LDs incorporating relaxed InGaN layers provided by the present disclosure can also be incorporated into a variety of systems. The LD packages are similar to the LED packages described herein, except that they include means for thermally managing the high power density of the LD device and for optically accessing the laser facets. LDs of multiple emission colors can be provided in separate packages or combined into a single package. LDs can be coupled with luminescent down-conversion materials to provide the desired emission spectrum. LDs are useful in applications requiring very high light density, such as automotive forward lighting systems and projection displays, which may include light modulation means such as raster optics, micromirror devices, and LCD modulators.

[0155] Examples of illumination and display systems are shown in Figures 11 and 12, respectively.

[0156] The controlled crystal lattice engineering described in the preceding paragraphs can be utilized to achieve the deposition of high-quality, variable-composition III-V compound semiconductor alloys on the same growth substrate. Controlled crystal lattice engineering refers to the ability to fabricate high-quality relaxed layers of III-V materials using patterned growth layers that allow for the incorporation of different InN contents, determined by the composition of the patterned growth layers, to provide photovoltaic devices configured to emit radiation within a desired wavelength range.

[0157] In one method of fabricating a polychromatic photovoltaic device, groups of photovoltaic elements, each characterized by a similar in-plane lattice constant a and a similar InN content, can be successively fabricated on the same growth substrate, such as a GaN layer. For example, a first group of photovoltaic elements can be fabricated on a first portion of the growth substrate, a second group of photovoltaic elements can be fabricated on a second portion of the growth substrate, and a third group of photovoltaic elements can be fabricated on a third portion of the growth substrate. Each of the first, second, and third groups of photovoltaic elements can be characterized by a different in-plane lattice constant a and a different InN content and can be configured to emit radiation within different wavelength ranges.

[0158] For example, as shown in FIG. 21, a first wavelength (λ1) photovoltaic device 2103a can be grown on a suitable substrate including a conventional GaN buffer layer 2102 having an in-plane lattice constant a of a0.

[0159] The substrate may be masked and etched to expose a first region 2102 a of the GaN buffer layer 2102 .

[0160] An optional first relaxed InGaN growth layer (including pattern 1) 2104a can be deposited on the first region 2102a of the GaN buffer layer 2102, such that the upper (0001) InGaN growth region 2110a of the first relaxed InGaN growth layer 2104a has an in-plane lattice constant a, where a1≧a0. The in-plane lattice constant a of the overlying InGaN layer adopts an in-plane lattice constant a, where a1≧a0. Epitaxial layers, such as an n-type InGaN layer 2105a, an active layer 2106a, and a p-type InGaN layer 2107a, can be deposited on or above the first relaxed (0001) InGaN surface 2110a of the first relaxed InGaN growth layer 2104a to provide a first optoelectronic device 2103a.

[0161] Alternatively, the relaxed InGaN growth layer may not be located on the first region 2102a of the GaN buffer layer 2102, and the epitaxial layers of the photovoltaic device may be grown directly on the GaN buffer layer 2102, pseudomorphic to GaN and having an in-plane lattice constant a of a0.

[0162] After the first photovoltaic element 2103a is fabricated, the wafer containing the first photovoltaic element is masked and etched to expose the second region 2102b of the GaN buffer layer 2102, allowing a second relaxed InGaN growth layer and a (0001) InGaN growth region to be grown under optimized conditions. A second relaxed InGaN growth layer 2104b (including Pattern 2) is deposited on top of the second region 2102b of the GaN buffer layer 2102 to allow for a controlled degree of lattice relaxation, which allows the in-plane lattice constant a of this layer to be a2, which is greater than a1.

[0163] Epitaxial layers can be deposited on or above the second relaxed (0001) InGaN surface 2110b of the second relaxed (0001) InGaN growth region 2110b to provide the second optoelectronic element 2103b. The in-plane lattice constant a of the overlying InGaN layer is a2, which is greater than a1. Epitaxial layers, such as an n-type InGaN layer 2105b, an active layer 2106b, and a p-type InGaN layer 2107b, can be deposited on the second relaxed InGaN growth layer 2104b to provide the second optoelectronic element 2103b.

[0164] After the second photovoltaic element 2103b is fabricated, the wafer is masked and etched to expose the third region 2102c of the GaN buffer layer 2102 so that a third relaxed InGaN growth layer 2104c can be grown on the third region 2102c of the GaN buffer layer 2102 under optimized conditions.

[0165] A third relaxed InGaN growth layer 2104c (including pattern 3) is deposited on the third region 2102c of the GaN buffer layer 2102 to allow a controlled degree of further lattice relaxation, such that the in-plane lattice constant a of the (0001) InGaN growth region 2110c of the third relaxed InGaN growth layer 2104c can become a3, which is greater than a2;

[0166] Epitaxial layers can then be deposited on or above the third relaxed (0001) InGaN surface 2110c of the third relaxed (0001) InGaN growth region 2110c to provide a third optoelectronic element 2103c. The in-plane lattice constant a of the overlying layers is a3, which is greater than a2. Epitaxial layers, such as an n-type InGaN layer 2105c, an active layer 2106c, and a p-type InGaN layer 2107c, can be deposited on the third relaxed InGaN growth layer 2104c to provide a third optoelectronic element 2103c.

[0167] Each of the relaxed InGaN growth layers 2104a / 2104b / 2104c can include a different pattern, configured so that the (0001) InGaN growth surfaces 2110a / 2110b / 2110c of the relaxed InGaN growth layers 2104a / 2104b / 2104c, respectively, are characterized by different in-plane lattice constants a and different InN contents. Alternatively, at least one of these layers may be unpatterned. The relaxed InGaN growth layers may be configured to impart different in-plane lattice constants a and different InN mole fractions to overlying epitaxial layers, such as the InGaN layers. The different InN mole fractions in the active layer can cause the photovoltaic device to emit radiation in different wavelength ranges.

[0168] Each of the relaxed InGaN growth regions 2104a / 2104b / 2104c includes a relaxed (0001) InGaN surface 2110a / 2110b / 2110c overlying a relaxed (0001) InGaN region overlying a partially relaxed InGaN region overlying a seed region.

[0169] The structure, pattern, and / or elemental composition of each of the seed regions of each of the relaxed InGaN growth regions 2104a / 2104b / 2104c may be independently the same or different depending on the selected emission wavelength. An optoelectronic device may include multiple optoelectronic elements capable of emitting radiation within a particular wavelength range.

[0170] For example, referring to FIG. 21 , a multicolor photovoltaic device may include a plurality of photovoltaic elements 2103a, a plurality of photovoltaic elements 2103b, and a plurality of photovoltaic elements 2103c. The photovoltaic elements 2103a / 2103b / 2103c may be arranged to form pixels. The multicolor photovoltaic device may include, for example, 1 to 10 or 1 to 3 subgroups of photovoltaic elements having relaxed (0001) InGaN regions provided by the present disclosure, each subgroup comprising a plurality of photovoltaic elements capable of emitting radiation at a different wavelength. For example, the photovoltaic device may include three subgroups of photovoltaic elements having relaxed (0001) InGaN regions provided by the present disclosure, each subgroup comprising a plurality of photovoltaic elements capable of emitting radiation at a different wavelength. For example, the multicolor photovoltaic device may include two subgroups of photovoltaic elements having relaxed (0001) InGaN regions provided by the present disclosure, each subgroup comprising a plurality of photovoltaic elements capable of emitting radiation at a different wavelength.

[0171] In a polychromatic photovoltaic device capable of emitting light at multiple wavelengths, the composition of the relaxed (0001) InGaN surface overlying the relaxed (0001) InGaN region is different for each wavelength.

[0172] In another method for fabricating a polychromatic photovoltaic device, a relaxed InGaN growth layer formed on a GaN buffer layer can include groups of InGaN growth layers, each group of relaxed InGaN growth layers characterized by a relaxed (0001) InGaN growth region having a different in-plane lattice constant a and a different InN content. Epitaxial layers can then be deposited on the relaxed InGaN growth layers to provide groups of photovoltaic elements located on respective groups of relaxed InGaN growth layers, where each group of photovoltaic elements is configured to emit radiation within a different wavelength range.

[0173] The first optoelectronic device may include a first InGaN active layer and a second InGaN active layer, where the first active layer is characterized by a first in-plane lattice constant a and the second InGaN active layer is characterized by a second in-plane lattice constant a, the second in-plane lattice constant a being greater than the first in-plane lattice constant a. For example, the second in-plane lattice constant a may be greater than the first in-plane lattice constant a by more than 0.005 Å, more than 0.01 Å, more than 0.05 Å, or more than 0.1 Å. For example, the second in-plane lattice constant a may be greater than the first in-plane lattice constant a by 0.005 Å to 0.05 Å. For example, the second in-plane lattice constant a may be greater than the first in-plane lattice constant a by 0.01 Å to 0.55 Å, or 0.01 Å to 0.1 Å.

[0174] Figure 22 shows the relationship between the peak emission wavelength of the light-emitting diode and the in-plane lattice constant a of each active layer. Figure 22 shows the MOCVD growth temperature (T g )(line 2201), T g -20K (line 2202), T g -40K (line 2203), and T g The graph shows the relationship between the in-plane lattice constant a of the active region and the peak emission wavelength of the light-emitting diode at +20 K (line 2204). g In this example, an active region with an in-plane lattice constant a of about 3.187 Å has a peak emission wavelength of about 458 nm, an active region with an in-plane lattice constant a of about 3.213 Å has a peak emission wavelength of about 528 nm, and an active region with an in-plane lattice constant a of about 3.250 Å has a peak emission wavelength of about 635 nm. The band edge of the InGaN alloy is shown by line 2205. The data associated with lines 2206 and 2207 are for the T GaN bands with their respective in-plane lattice constants a, as shown in Even et al., Applied Physics Letters 110, 262103, 2017. g Temperature of -20K (wire 2206) and T g (Line 2207) represents experimental measurements of the peak emission wavelength of the LED at temperature.

[0175] Controlled crystal lattice engineering allows light-emitting active regions with different emission wavelengths to be grown on a single wafer, such as light-emitting diodes (LEDs), ultrabright light-emitting diodes, laser diodes (LDs), and vertical-cavity surface-emitting lasers (VCSELs). Because lattice engineering can be controlled at the submicron level within selected growth regions, single-color active regions can be fabricated at the micron or submicron level on a single wafer.

[0176] Controlled crystal lattice engineering can also be utilized to achieve the simultaneous deposition of high-quality tunable-composition III-V compound semiconductor alloys, allowing the growth of light-emitting active regions with different emission wavelengths, such as light-emitting diodes (LEDs), ultrabright light-emitting diodes (ULDs), laser diodes (LDs), and vertical-cavity surface-emitting lasers (VCSELs), in a single epitaxial deposition process.

[0177] As described, controlled crystal lattice engineering can be used to fabricate high-quality optoelectronic elements and devices on large area wafers, with each of a plurality of optoelectronic elements configured to emit radiation within substantially the same wavelength range. In this method, epitaxial layers containing the optoelectronic elements are grown on a patterned growth layer having a single pattern across the entire surface of the wafer.

[0178] Controlled crystal lattice engineering can be extended to fabricate photovoltaic devices configured to emit radiation within different wavelength ranges. In this fabrication method, a relaxed InGaN growth layer may include multiple GaN seed regions with different pattern configurations (e.g., feature size, shape, spacing). InGaN is grown on the growth surface of the GaN seed regions. As InGaN growth continues, InGaN grows from adjacent GaN seed regions and coalesces, forming relaxed InGaN regions between the GaN seed regions. Further InGaN growth forms relaxed InGaN regions, each of which has a (0001) InGaN growth region overlying the GaN seed region and characterized by an in-plane lattice constant a. Depending on the configuration of the GaN seed regions, the coalesced relaxed InGaN growth layers have different in-plane lattice constants a and incorporate different amounts of InN into the III-V semiconductor crystal lattice. Photovoltaic devices grown on different relaxed InGaN growth layers can emit radiation within wavelength ranges consistent with the incorporated InN content.

[0179] As described herein, III-nitride epitaxial layers on a growth substrate or GaN buffer layer can be grown using any suitable semiconductor deposition, lithography (including nanolithography), and etching techniques, including SiO x , SiN x , or AlO xThe InGaN seed region can be selectively patterned with a dielectric material such as SiO 2 . The degree of patterning is intentionally selected to create a desired in-plane strain state in the overlying InGaN layer. For example, growing InGaN on an unpatterned (0001) GaN seed layer can result in an InGaN layer lattice-matched to GaN (i.e., pseudomorphic to GaN). Growing InGaN on a densely patterned GaN seed region results in an overlying InGaN layer that is substantially relaxed and characterized by an in-plane lattice constant a close to that of a fully relaxed InGaN layer of the same composition. Finally, a region with a pattern density between the unpatterned and densely patterned GaN seed region can exhibit the in-plane lattice constant a of partially relaxed InGaN.

[0180] By controlling the in-plane lattice constant, a, active regions with different compositions can have similar strain states that are optimal for device performance. For example, the optimal strain state for InGaN-based emitters is between about 1% and about 2% compressive strain, regardless of the emission wavelength. One way to ensure that the emitters exhibit similar beneficial strain states while varying the InGaN composition in each active region to enable emission at different wavelengths, such as in the blue-to-green-to-red wavelength range, is to adjust the in-plane lattice constant, a, of the underlying material on which the InGaN-based emitters are grown.

[0181] III-nitride epitaxial layers on a growth substrate can be selectively patterned with a dielectric material to define GaN seed regions using known deposition, lithography (including nanolithography), and etching techniques. The patterning can be purposefully selected to produce a desired strain state in the relaxed InGaN growth layer grown on the GaN seed regions.

[0182] Because the in-plane lattice constants a of the relaxed InGaN growth layers located on various patterned GaN seed regions are different, the incorporated InN mole fractions in each relaxed InGaN growth layer are different, even if the epitaxial TMI / III ratio and growth temperature used to deposit the InGaN layer on each relaxed InGaN growth layer are the same. Using this method, it is possible to selectively and simultaneously grow multiple color active regions with micron- or submicron-scale resolution on a single growth substrate in a single growth run.

[0183] FIG. 23 shows the epitaxial layers of a polychromatic photovoltaic structure at an intermediate step in the fabrication process.

[0184] As shown in FIG. 23 , three different relaxed InGaN growth layers 2304 a / 2304 b / 2304 c can be grown on a growth substrate, such as a GaN buffer layer 2302. The three relaxed InGaN growth layers 2304 a / 2304 b / 2304 c include GaN seed regions with different patterns, e.g., in terms of size, shape, fill factor, etc. The InGaN grown on the differently patterned GaN seed regions coalesce to form relaxed InGaN regions with respective (0001) InGaN growth regions 2310 a / 2310 b / 2310 c, characterized by different in-plane lattice constants a and different InN mole fractions. As shown in FIG. 23 , region 2304 a can include GaN and have an in-plane lattice constant a of a1 = a0. Region 2304 a can include a relaxed (0001) InGaN region with an in-plane lattice constant a of a1 > a0.

[0185] Because the in-plane lattice constants a of the two or three (0001) InGaN growth regions 2310a / 2310b / 2310c are different, the epitaxial InGaN layers, including the active regions, grown on each of the three (0001) InGaN growth regions are characterized by different in-plane lattice constants a and different InN mole fractions.

[0186] In a first step in an exemplary manufacturing process for creating a polychromatic photovoltaic structure, a GaN buffer layer 2302 characterized by an in-plane lattice constant a of a0 can be deposited on a substrate 2301.

[0187] Individual relaxed InGaN growth layers 2304a / 2304b / 2304c can be independently deposited on separate portions of GaN buffer layer 2301. As shown in FIG. 23, relaxed InGaN growth layer 2304 includes three relaxed InGaN growth layers 2304a / 2304b / 2304c. Examples of relaxed InGaN growth layers are shown in FIGS. 1-6, 13, 15-17, 19, and 20. Each relaxed InGaN growth layer may include a patterned GaN seed region, a patterned masking region, a relaxed InGaN region, and a partially or substantially relaxed (0001) InGaN region.

[0188] The configuration of the patterned GaN seed regions and patterned masking regions can be different for each group of relaxed InGaN growth layers, and can be selected such that each group of relaxed InGaN growth layers 2304a / 2304b / 2304c is configured to emit radiation within a selected wavelength range.

[0189] For example, each relaxed InGaN growth layer of the first group of relaxed InGaN growth layers can include the same or similar pattern of GaN seed regions and can be configured to emit radiation within a first wavelength range, such as within the red wavelength range of 625 nm to 740 nm.

[0190] For example, each relaxed InGaN growth layer of the second group of relaxed InGaN growth layers can include the same or similar pattern of GaN seed regions and can be configured to emit radiation in a second wavelength range, such as in the green wavelength range of 515 nm to 570 nm.

[0191] For example, each relaxed InGaN growth layer of the third group of relaxed InGaN growth layers can include the same or similar pattern of GaN seed regions and can be configured to emit radiation in a third wavelength range, such as within the blue wavelength range of 400 nm to 495 nm.

[0192] The relaxed InGaN growth layers of different groups can be arranged in a regular array and can also be configured to form pixels on the substrate. The configuration or array can be Cartesian or triangular (i.e., triangular or hexagonal). Multiple relaxed InGaN growth layers can be arranged in an interleaved array.

[0193] The pattern of the relaxed InGaN growth layer for each group may be different, for example, with respect to the pitch of the GaN seed structures, the height / depth of the GaN seed structures, the shape of the GaN seed structures, the lateral dimensions of the GaN seed structures, and / or the growth facets of the GaN seed structures.

[0194] The polychromatic photovoltaic device shown in FIG. 23 has three different relaxed InGaN growth layers 2304a / 2304b / 2304c, each having a relaxed (0001) InGaN growth region 2310a / 2310b / 2310c with a relaxed (0001) InGaN surface characterized by a different in-plane lattice constant a and a different InN mole fraction.

[0195] 23, relaxed (0001) InGaN growth region 2310a and the relaxed (0001) InGaN surface of relaxed InGaN growth layer 2304a may have an in-plane lattice constant a of a1 that is greater than or equal to the in-plane lattice constant a of GaN buffer layer 2302. For example, epitaxial layers grown on (0001) InGaN growth region 2310a of relaxed InGaN growth layer 2304a, including n-type InGaN layer 2305a, active region 2306a, and p-type InGaN layer 2307a, may have an in-plane lattice constant a of a1 with a matched InN mole fraction and emit radiation in a first wavelength range.

[0196] 23, relaxed (0001) InGaN growth region 2310b and the relaxed (0001) InGaN surface of relaxed InGaN growth layer 2304b may have an in-plane lattice constant a of a2, which is greater than a1. For example, epitaxial layers grown on (0001) InGaN growth region 2310b of relaxed InGaN growth layer 2304b, including n-type InGaN layer 2305b, active region 2306b, and p-type InGaN layer 2307b, have an in-plane lattice constant a of a2 with a matched InN mole fraction and may emit radiation in the second wavelength range.

[0197] 23, relaxed (0001) InGaN growth region 2310c and the relaxed (0001) InGaN surface of relaxed InGaN growth layer 2304c may have an in-plane lattice constant a of a3, which is greater than a2. Epitaxial layers grown on (0001) InGaN growth region 2310c of relaxed InGaN growth layer 2304c, including n-type InGaN layer 2305c, active region 2306c, and p-type InGaN layer 2307c, have an in-plane lattice constant a of a3 with a matched InN mole fraction and may emit radiation in a third wavelength range.

[0198] The structure can include additional groups of relaxed InGaN grown layers configured to emit radiation in additional wavelength ranges.

[0199] Relaxed InGaN growth layers can be fabricated as described herein to provide (0001) InGaN growth regions with desired InN mole fraction and in-plane lattice constant, a.

[0200] For example, as shown in FIG. 23, a first optoelectronic structure configured to emit radiation at wavelength λ can be grown on a suitable substrate or on a conventional GaN buffer layer with an in-plane lattice constant a of a0.

[0201] An optional first mask (Pattern 1) is deposited over a first region 2304a of GaN buffer layer 2302, while different mask patterns (Pattern 2 and Pattern 3) are deposited in regions 2304b and 2304c.

[0202] The wafer can then be etched to expose the GaN buffer layer 2302 in each patterned GaN seed region.

[0203] After the GaN buffer layer is exposed in each region, epitaxial growth is performed to form a GaN seed region in each of the patterned regions. Once the GaN seed regions are formed, growth is switched to InGaN, which coalesces on top of the patterned GaN seed regions to form (0001) InGaN growth regions 2310a / 2310b / 2310c of respective relaxed InGaN growth layers 2304a / 2304b / 2304c. The different (0001) InGaN growth regions have different lattice constants, a, depending on the patterning of the GaN seed regions. Then, in a single epitaxial deposition process, an n-type InGaN layer 2305 can be deposited on top of each of the (0001) InGaN growth regions. The n-type InGaN layer 2305 includes three n-type InGaN regions 2305a / 2305b / 2305c characterized by different in-plane lattice constants a and different mole fractions of InN matched to the (0001) InGaN growth regions 2310a / 2310b / 2310c underlying the relaxed InGaN growth layers 2304a / 2304b / 2304c, respectively.

[0204] The portion of n-type InGaN layer 2305a overlying relaxed InGaN growth layer 2304a may have an in-plane lattice constant a1 where a1>a0, the portion of n-type InGaN layer 2305b overlying relaxed InGaN growth layer 2304b may have an in-plane lattice constant a2 where a1>a2, and the portion of n-type InGaN layer 2305c overlying relaxed InGaN growth layer 2304c may have an in-plane lattice constant a3 where a3>a2.

[0205] After the n-type InGaN layer 2305 is deposited, an active layer 2306 can be deposited on the n-type InGaN layer 2305 in the same single epitaxial deposition process. The active layer 2306 may include a single epitaxial layer or multiple epitaxial layers. The active layer 2306 may include active regions 2306a / 2306b / 2306c having an in-plane lattice constant a and an InN mole fraction that match the growth plane 2310 of the underlying portions of the n-type InGaN layer 2205 and relaxed InGaN growth layers 2304a / 2304b / 2304c.

[0206] After the active layer 2306 is deposited, a p-type InGaN layer 2307 can be deposited on the active layer 2306 in a single epitaxial deposition process. Like the underlying layer, the p-type InGaN layer 2307 can include a p-type InGaN region (not specified) having an in-plane lattice constant a and an InN content that matches the growth plane 2310 of the underlying active layer, n-type InGaN layer, and relaxed InGaN growth layer 2304a / 2304b / 2304c.

[0207] The semiconductor structure shown in FIG. 23 may include additional epitaxial layers such as cladding layers, electron blocking layers, reflective layers, and the like.

[0208] 23 shows three different photovoltaic devices corresponding to relaxed InGaN growth layers 2304a / 2304b / 2304c, n-type InGaN regions 2305a / 2305b / 2305c, active regions 2306a / 2306b / 2306c, and p-type InGaN regions 2307a / 2307b / 2307c characterized by different in-plane lattice constants a and InN mole fractions. However, more than three different relaxed InGaN growth layers with different relaxed (0001) InGaN growth regions can be fabricated on a wafer. The relaxed InGaN growth layers may be configured to form pixels. Multiple relaxed InGaN growth layers may be arranged in an interleaved array.

[0209] The InGaN growth layer may include regions that do not include a patterned GaN seed region, in which case the (0001) InGaN growth region and the overlying epitaxial layer are pseudomorphic to GaN. This is reflected in Figure 23, where region 2304 may be an unpatterned GaN seed region, and the n-type InGaN region may be pseudomorphic to GaN and characterized by an in-plane lattice constant a of a0, the same as In-free GaN.

[0210] The semiconductor structure shown in Figure 23 can then be processed to separate the individual photovoltaic elements and add electrodes.

[0211] The wafer can then be etched and metallized to provide electrical contacts.

[0212] A transparent conductive oxide (TCO), such as indium tin oxide (ITO), electrical contact may be used in an "epi-up" configuration on the p-type InGaN layer 2307. Alternatively, a reflective contact, such as an Ag-based contact, can be used in an inverted configuration.

[0213] The cathodes can be connected in common or separated by isolating the individual photovoltaic elements, such as by trench etching between the individual elements down to an insulating mask layer or substrate, such as sapphire. The cathode metallization to the n-type InGaN layer 2305 can be, for example, TiAl. The first wavelength (λ1), second wavelength (λ2), and third wavelength (λ3) can be, for example, blue, green, and red, respectively. However, photovoltaic elements configured to emit radiation within other wavelength ranges can be fabricated using the methods provided by the present disclosure.

[0214] After the epitaxial layers are grown as described in FIG. 23, the wafer can be etched and metallized to provide contacts to the electrodes, as shown in FIG.

[0215] An example of a photovoltaic device configured to emit radiation in three different wavelength ranges is shown in FIG.

[0216] As shown in Figure 24, boundaries between base layers with different strain states, which could result in defects, can be eliminated by etching down to the GaN buffer layer. Electrical contacts, such as transparent conductive oxide (TCO) contacts, can be deposited on the p-type InGaN layer in an "epi-up" configuration. Alternatively, reflective contacts, such as Ag-based contacts, can be applied to the p-type InGaN layer in an inverted configuration. As shown in Figure 24, the cathode can be common, or the individual photovoltaic elements can be isolated by isolating them, such as by trench etching down to an insulating mask layer or insulating substrate, such as a sapphire substrate, between the individual photovoltaic elements.

[0217] The individual photovoltaic elements can be separated and a portion of the n-InGaN layer of each of the elements can be exposed using known semiconductor fabrication methods.

[0218] A device with three photoelectric elements is shown in FIG.

[0219] A cathode 2409a / 2409b / 2409c can be applied over each of the n-type InGaN regions, and an anode 2408a / 2408b / 2408c can be applied over each of the p-type InGaN regions.

[0220] As shown in FIG. 24, the optoelectronic device comprises a growth substrate 2401, a GaN buffer layer 2402, and three optoelectronic elements on top of the GaN buffer layer 2402.

[0221] Photovoltaic elements 2403a / 2403b / 2403c comprise relaxed InGaN growth layers 2409a / 2409b / 2409c, n-type InGaN regions overlying the relaxed InGaN growth layers, active regions 2405a / 2405b / 2405c overlying the n-type InGaN regions, and p-type InGaN regions 2407a / 2407b / 2407c overlying the respective active regions.

[0222] As shown in Figure 24, each of the photoelectric elements emits radiation within a different wavelength range λ1, λ2, λ3.

[0223] The growth can be selectively patterned, and the overlying epitaxial layer can be deposited directly on the selectively patterned substrate. The use of a selectively patterned substrate eliminates the need for an intermediate GaN buffer layer between the growth substrate and the relaxed InGaN growth layer(s).

[0224] The number, size, and shape of the light-emitting apertures of the various photoelectric elements can be independently adjusted to optimize overall performance such as efficiency, contrast, brightness uniformity, etc. The light-emitting apertures can also be independently adjusted to achieve a desired optical effect.

[0225] In Figure 24, the photovoltaic elements are configured as LEDs. This structure can be fabricated into edge-emitting laser diodes that are configured into substantially coplanar stripes and emit different colors.

[0226] The active region can also be integrated into a vertical cavity, such as a distributed Bragg reflector layer stack, to provide multiple coplanar VCSELs emitting in different wavelength ranges and grown on the same substrate.

[0227] An example of a stacked photovoltaic device is shown in Figure 25. In the example shown in Figure 25, the stacked photovoltaic element is configured to emit radiation in three different wavelength ranges λ1, λ2, and λ3.

[0228] The stacked optoelectronic device shown in Figure 25 comprises a growth substrate 2501 and an overlying GaN layer 2502 having an in-plane lattice constant a of a0.

[0229] The first optoelectronic element 2503a comprises a first n-type GaN layer 2505a, a first active region 2506a thereon, and a first p-type InGaN layer 2507a thereon. Alternatively, the first optoelectronic element may comprise a first patterned region above the GaN layer 2502 and below the first n-type InGaN layer.

[0230] The second optoelectronic element 2503b comprises a first relaxed InGaN growth layer 2504b coalesced on the second patterned GaN seed region, an overlying second n-type InGaN layer 2505b having an in-plane lattice constant a such that a2>a1, an overlying second active layer 2506b, and a second p-type InGaN layer 2507b overlying the second active layer 2506b.

[0231] The third stacked optoelectronic device 2503c comprises a second relaxed InGaN growth layer 2504c coalescing on the second patterned GaN seed region and on the second p-type InGaN layer 2507b, an n-type InGaN layer having an in-plane lattice constant a of a3 > a2 and on the second relaxed InGaN growth layer 2540c, a third active layer 2506c on the third n-type InGaN layer, and a third p-type InGaN layer 2507c on the third active layer 2506c.

[0232] Transparent electrodes 2508a / 2508b / 2508c overlie p-type InGaN layers 2507a / 2507b / 2507c, respectively, and are configured to pass radiation emitted from the underlying photovoltaic elements.

[0233] The stacked photovoltaic device shown in FIG. 25 comprises cathodes 2509a / 2509b / 2509c overlying and electrically interconnected with n-type InGaN layers 2505a / 2505b / 2505c, respectively.

[0234] The first photoelectric element is configured to emit radiation in a first wavelength range λ1, the second photoelectric element is configured to emit radiation in a second wavelength range λ2, and the third photoelectric element is configured to emit radiation in a third wavelength range λ3.

[0235] It is desirable for the materials comprising each photovoltaic element to be transparent to radiation emitted from the active region of the underlying photovoltaic element. In other words, an epitaxial stack that is "fully transparent" to all emission wavelengths corresponding to radiation from the different active regions is desired. To achieve this, the growth conditions and composition of the base layer with the highest InN mole fraction are selected to transmit light emitted from the active layer associated with the region with the lowest InN mole fraction. For example, in the case of an RGB light-emitting device, the composition of the base layer of the red-emitting active region is selected to be substantially transparent to light emitted from the underlying blue-emitting active region. Using known InGaN bandgap versus alloy composition parameters, this epitaxial total transparency can be achieved, for example, for red, green, and blue emitters grown on an InGaN base layer having regions with different InGaN compositions and in-plane lattice constants, a, with the overlying InGaN layer deposited in a single epitaxial growth process.

[0236] In certain aspects, a semiconductor structure comprises a first optoelectronic element and a second optoelectronic element, the first optoelectronic element comprising a first active layer characterized by a first in-plane lattice constant a, and the second optoelectronic element comprising a second active layer characterized by a second in-plane lattice constant a, the second in-plane lattice constant a being greater than the first in-plane lattice constant a.

[0237] The first and second optoelectronic elements may or may not be located on a common substrate. The semiconductor structure may be incorporated into an optoelectronic device.

[0238] In certain embodiments, the semiconductor structure may comprise an InGaN layer, such as a GaN buffer layer, or a first relaxed InGaN growth layer and a second relaxed InGaN growth layer. The first relaxed InGaN growth layer may comprise a first relaxed (0001) InGaN region having a first in-plane lattice constant a, and the second relaxed InGaN growth layer may comprise a second relaxed (0001) InGaN region having a second in-plane lattice constant a, the second in-plane lattice constant a being greater than the first in-plane lattice constant a. For example, the first in-plane lattice constants a may differ by, for example, more than 0.005 Å, more than 0.0075 Å, more than 0.01 Å, more than 0.05 Å, more than 0.1 Å, or more than 0.2 Å. For example, the first in-plane lattice constants a may differ by, for example, more than 0.2%, more than 0.3%, more than 0.5%, more than 1%, or more than 3%. The semiconductor structures may be located on a common substrate. The semiconductor structures may include an overlying epitaxial layer for forming a plurality of photovoltaic devices. The photovoltaic devices may or may not be located on a common substrate. The semiconductor structures may be located on a common GaN buffer layer.

[0239] Although this disclosure describes specific embodiments directed to the InGaN-GaN material system, the invention is not limited thereto and can be applied to other systems as well, such as the AlGaN-AlN system, which is of interest for ultraviolet emitters and detectors.

[0240] Aspects of the invention The present invention is further defined by one or more of the following aspects.

[0241] Aspect 1 a first relaxed (In)GaN growth layer including a first (0001) (In)GaN growth region; Patterned GaN seed regions and a second relaxed InGaN growth layer including a second (0001) InGaN growth region overlying the patterned GaN seed region; the first (0001) (In)GaN growth region is characterized by a first in-plane lattice constant, a; the second (0001) InGaN growth region is characterized by a second in-plane lattice constant, a; The semiconductor structure, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0242] Aspect 2 2. The semiconductor structure of embodiment 1, wherein the first relaxed (In)GaN growth layer and the second relaxed InGaN growth layer are located on a common substrate, a common GaN buffer layer, or both a common substrate and a common GaN buffer layer.

[0243] Aspect 3 the substrate comprises a first substrate region and a second substrate region; a first relaxed (In)GaN growth layer overlying the first substrate region; 3. The semiconductor structure of embodiment 2, wherein a second relaxed InGaN growth layer overlies the second substrate region.

[0244] Aspect 4 The semiconductor structure of embodiment 2 or 3, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[0245] Aspect 5 the GaN buffer layer comprises a first GaN buffer region and a second GaN buffer region; a first relaxed (In)GaN growth layer overlying the first GaN buffer region; The semiconductor structure of any one of embodiments 2-4, wherein the second relaxed InGaN growth layer overlies the second GaN buffer region.

[0246] Aspect 6 The semiconductor structure of embodiment 5, wherein the GaN buffer layer has an in-plane lattice constant, a, of 3.189 Å.

[0247] Aspect 7 a first photovoltaic element located on the first relaxed (In)GaN growth layer; The semiconductor construction of any one of embodiments 1-6, comprising: a second optoelectronic element overlying the second relaxed InGaN growth layer.

[0248] Aspect 8 Each of the first photoelectric elements independently: an n-type (In)GaN layer overlying the relaxed (In)GaN growth layer; an active layer located on the n-type (In) GaN layer; a p-type (In)GaN layer overlying the active layer.

[0249] Aspect 9 9. The semiconductor structure of embodiment 8, wherein the active layer is characterized by the in-plane lattice constant a of the underlying (0001) InGaN growth region.

[0250] Aspect 10 10. The semiconductor structure of any one of embodiments 1-9, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a by more than 0.005 Å.

[0251] Aspect 11 The semiconductor structure of any one of Aspects 1 to 9, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a by 0.005 Å to 3.54 Å.

[0252] Aspect 12 12. The semiconductor structure of any one of embodiments 1-11, wherein the first relaxed (In)GaN growth layer does not include a patterned GaN seed region.

[0253] Aspect 13 Each of the first relaxed (In)GaN growth layer and the second relaxed InGaN growth layer independently comprises: a plurality of GaN seed regions; coalesced InGaN regions between adjacent GaN seed regions; a relaxed InGaN region overlying the plurality of GaN seed regions and the coalesced InGaN region; 12. The semiconductor structure of any one of embodiments 1-11, comprising: a (0001) InGaN growth region overlying the relaxed InGaN region.

[0254] Aspect 14 14. The semiconductor structure of any one of embodiments 1-13, wherein the first (0001) (In)GaN growth region is characterized by an in-plane lattice constant, a, of 3.189 Å.

[0255] Aspect 15 14. The semiconductor structure of any one of embodiments 1-13, wherein the first (0001) (In)GaN growth region is characterized by an in-plane lattice constant a greater than 3.189 Å.

[0256] Aspect 16 16. The semiconductor structure of any one of embodiments 1-15, wherein the second (0001) grown InGaN region is characterized by an in-plane lattice constant a greater than 3.189 Å.

[0257] Aspect 17 16. The semiconductor structure of any one of embodiments 1-15, wherein the second (0001) grown InGaN region is characterized by an in-plane lattice constant, a, between 3.189 Å and 3.545 Å.

[0258] Aspect 18 the first (0001) (In)GaN growth region is characterized by an in-plane lattice constant a between 3.189 Å and 3.545 Å; 14. The semiconductor structure of any one of embodiments 1 to 13, wherein the second (0001) InGaN growth region is characterized by an in-plane lattice constant a between 3.189 Å and 3.545 Å.

[0259] Aspect 19 the first (0001) (In)GaN growth region includes a first InN mole fraction; the second (0001) InGaN growth region comprises a second InN mole fraction; 19. The semiconductor structure of any one of embodiments 1-18, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0260] Aspect 20 20. The semiconductor structure of embodiment 19, wherein the first InN mole fraction is 0 mol %.

[0261] Aspect 21 20. The semiconductor structure of embodiment 19, wherein each of the first InN mole fraction and the second InN mole fraction is independently between 0 mol % and 100 mol %.

[0262] Aspect 22 22. The semiconductor structure of any one of embodiments 1-21, wherein the first (In)GaN growth layer comprises GaN.

[0263] Aspect 23 22. The semiconductor structure of any one of embodiments 1-21, wherein the first (In)GaN growth layer comprises InGaN.

[0264] Aspect 24 the first (In)GaN growth layer includes first InGaN, the first (In)GaN growth layer including a first plurality of GaN seed regions characterized by a first pattern; the second InGaN growth layer includes a second plurality of GaN seed regions characterized by a second pattern; 22. The semiconductor construction of any one of embodiments 1-21, wherein the first second pattern is different from the first pattern.

[0265] Aspect 25 25. The semiconductor structure of embodiment 24, wherein the first and second patterns differ in GaN seed region size, GaN seed region shape, GaN seed region fill factor, GaN seed region spacing, GaN seed region crystal orientation, seed region pattern, or a combination of any of the foregoing.

[0266] Aspect 26 26. The semiconductor structure of any one of embodiments 1-25, comprising a dielectric region adjacent each of the GaN seed regions.

[0267] Aspect 27 27. The semiconductor structure of embodiment 26, wherein the dielectric region comprises SiOx, SiNx, or AlOx.

[0268] Aspect 28 28. The semiconductor structure of any one of embodiments 1-27, wherein each of the GaN seed regions has a growth surface coplanar with the GaN crystal plane.

[0269] Aspect 29 a first (0001) InGaN region overlying the first plurality of GaN seed regions, the first (0001) InGaN growth region characterized by a first in-plane lattice constant, a, and a first InN mole fraction; 2. The semiconductor structure of embodiment 1, wherein a second (0001) InGaN growth region is located on the second plurality of GaN seed regions, the second (0001) InGaN region characterized by a second in-plane lattice constant, a, and a second InN mole fraction.

[0270] Aspect 30 30. The semiconductor structure of embodiment 29, wherein the (0001) InGaN growth region is characterized by an in-plane lattice constant a greater than 3.189 Å.

[0271] Aspect 31 30. The semiconductor structure of embodiment 29, wherein the in-plane lattice constant a is in the range of 3.19 Å to 3.54 Å.

[0272] Aspect 32 Each of the GaN seed regions is In x Ga 1-x 32. The semiconductor structure of any one of embodiments 29-31, comprising N(0≦x<1) and a wurtzite III-nitride crystal structure.

[0273] Aspect 33 33. The semiconductor structure of any one of embodiments 29-32, wherein each of the GaN seed regions has six planar GaN seed facets.

[0274] Aspect 34 34. The semiconductor structure of any one of embodiments 29-33, wherein each of the GaN seed regions is characterized by a hexagonal base.

[0275] Aspect 35

[0039] Embodiment 35. The semiconductor structure of any one of embodiments 29-34, wherein each of the GaN seed regions comprises a seed surface coplanar with a crystallographic plane of the GaN.

[0276] Aspect 36 36. The semiconductor structure of embodiment 35, wherein each of the crystallographic planes is a crystallographically equivalent {10-11} plane.

[0277] Aspect 37 36. The semiconductor structure of embodiment 35, wherein each of the crystallographic planes is a crystallographically equivalent {1-100} plane.

[0278] Aspect 38 36. The semiconductor structure of embodiment 35, wherein each of the crystallographic planes is a crystallographically equivalent {11-20} plane.

[0279] Aspect 39 36. The semiconductor structure of embodiment 35, wherein each of the crystallographic planes is a plane rotated about a {1-100} plane or a {11-20} plane.

[0280] Aspect 40 36. The semiconductor structure of embodiment 35, wherein the region at the midpoint between the GaN seed regions is a coalesced InGaN region.

[0281] Aspect 41 41. The semiconductor structure of any one of embodiments 29-40, wherein the relaxed InGaN layer comprises a plurality of relaxed InGaN regions, each relaxed InGaN region having a different InN mole fraction.

[0282] Aspect 42 41. The semiconductor structure of any one of embodiments 29-40, wherein each of the first relaxed InGaN growth layer and the second relaxed InGaN growth layer is independently configured to provide a (0001) InGaN growth region having a defined degree of in-plane lattice relaxation, a.

[0283] Aspect 43 43. The semiconductor structure of any one of embodiments 29-42, wherein each of the first InGaN growth layer and the second InGaN growth layer is independently configured to have a (0001) InGaN growth region characterized by a different in-plane lattice constant a.

[0284] Aspect 44 44. The semiconductor structure of any one of embodiments 29-43, wherein each of the first InGaN growth layer and the second InGaN growth layer is independently configured to have a (0001) InGaN growth region characterized by a different InN mole fraction.

[0285] Aspect 45 a first n-type (In)GaN layer overlying the first relaxed (In)GaN growth layer; a first active layer located on the first n-type (In) GaN layer; a first p-type (In) GaN layer located on the first active layer; a second n-type (In)GaN layer overlying the second relaxed (In)GaN growth layer; a second active layer located on the second n-type (In) GaN layer; 45. The semiconductor construction of any one of embodiments 1-44, comprising: a second p-type (In)GaN layer overlying the second active layer.

[0286] Aspect 46 46. ​​The semiconductor structure of embodiment 45, wherein the first n-type (In)GaN layer comprises GaN.

[0287] Aspect 47 46. ​​The semiconductor structure of embodiment 45, wherein the first n-type (In)GaN layer comprises InGaN.

[0288] Aspect 48 48. The semiconductor structure of embodiment 47, wherein each of the first n-type InGaN layer and the second n-type InGaN layer independently has an in-plane lattice constant, a, equivalent to a respective underlying (0001)(In)GaN region.

[0289] Aspect 49 the first n-type (In)GaN layer is characterized by a first in-plane lattice constant, a; the second n-type InGaN layer is characterized by a second in-plane lattice constant, a; 49. The semiconductor structure of any one of embodiments 45 to 48, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0290] Aspect 50 50. The semiconductor structure of any one of embodiments 45-49, wherein each of the first n-type InGaN layer and the second n-type InGaN layer is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of the respective underlying (0001)(In)GaN region.

[0291] Aspect 51 the first n-type (In)GaN layer comprises a first InN mole fraction; the second n-type InGaN layer comprises a second InN mole fraction; 51. The semiconductor structure of any one of embodiments 45-50, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0292] Aspect 52 52. The semiconductor construction of any one of embodiments 45-51, wherein the first active layer comprises a plurality of first active layers.

[0293] Aspect 53 53. The semiconductor construction of any one of embodiments 45-52, wherein the second active layer comprises a plurality of active layers.

[0294] Aspect 54 52. The semiconductor construction of any one of embodiments 45-51, wherein the first active layer and the second active layer each comprise a plurality of active layers.

[0295] Aspect 55 The semiconductor construction of any one of embodiments 45-54, wherein the first active region includes 1-40 active layers and the second active region includes 1-40 active layers, or wherein each of the first active layer and the second active layer includes 1-40 active layers.

[0296] Aspect 56 the first active layer comprises a first InN mole fraction; the second active layer comprises a second InN mole fraction; 56. The semiconductor structure of any one of embodiments 45 to 55, wherein the second InN mole fraction is greater than the second InN mole fraction.

[0297] Aspect 57 the first active layer is characterized by a first in-plane strain value; the second active layer is characterized by a second in-plane strain value; 57. The semiconductor construction of any one of embodiments 45-56, wherein the first strain value is the same as the second strain value.

[0298] Aspect 58 58. The semiconductor structure of embodiment 57, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

[0299] Aspect 59 58. The semiconductor structure of embodiment 57, wherein the second in-plane strain value is within 1% of the first in-plane strain value.

[0300] Aspect 60 58. The semiconductor structure of embodiment 57, wherein each of the first strain value and the second strain value is independently within a range of 1% to 2% of compressive strain.

[0301] Aspect 61 61. The semiconductor construction of any one of embodiments 45-60, wherein the first active layer and the second active layer each comprise a multiple quantum well structure.

[0302] Aspect 62 The semiconductor construction of any one of embodiments 45-61, wherein the first active layer and the second active layer each comprise a light emitting diode structure.

[0303] Aspect 63 The semiconductor construction of any one of embodiments 45-62, wherein the first active layer and the second active layer each comprise a laser diode structure.

[0304] Aspect 64 the first p-type (In)GaN layer is characterized by a first in-plane lattice constant, a; the second p-type InGaN layer is characterized by a second in-plane lattice constant, a; The semiconductor structure of any one of embodiments 45 to 63, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0305] Aspect 65 65. The semiconductor structure of any one of embodiments 45-64, wherein each of the first p-type InGaN layer and the second p-type InGaN layer is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of the respective underlying (0001)(In)GaN region.

[0306] Aspect 66 the first p-type (In)GaN layer comprises a first InN mole fraction; the second p-type InGaN layer comprises a second InN mole fraction; 66. The semiconductor structure of any one of embodiments 45 to 65, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0307] Aspect 67 The semiconductor structure of any one of embodiments 45-66, wherein the first p-type (In)GaN layer and the second p-type InGaN layer each independently have an in-plane lattice constant a in the range of 3.19 Å to 3.35 Å.

[0308] Aspect 68 68. The semiconductor construction of any one of embodiments 7-67, wherein the first photoelectric element and the second photoelectric element are configured to emit radiation in different wavelength ranges.

[0309] Aspect 69

[00130] Aspect 69. The semiconductor construction of any one of aspects 7-68, wherein the first optoelectronic element and the second optoelectronic element each independently comprise a light emitting diode, a laser diode, or a vertical cavity surface emitting laser.

[0310] Aspect 70 a cathode electrically connected to each of the first n-type (In)GaN layer and the second InGaN layer; 70. The semiconductor construction of any one of embodiments 7-69, further comprising: an anode electrically connected to each of the first p-type (In)GaN layer and the second p-type InGaN layer.

[0311] Aspect 71 71. The semiconductor structure of embodiment 70, wherein the cathode comprises Ti and Al.

[0312] Aspect 72 72. The semiconductor structure of embodiment 70 or 71, wherein the cathode is commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0313] Aspect 73 The semiconductor structure of any one of embodiments 70-72, wherein the cathode is commonly and independently interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0314] Aspect 74 The semiconductor construction of any one of embodiments 73-73, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

[0315] Aspect 75 75. The semiconductor structure of embodiment 73 or 74, wherein the anode is commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0316] Aspect 76 76. The semiconductor structure of any one of embodiments 73-75, wherein the anode is commonly and independently interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0317] Aspect 77 77. The semiconductor construction of any one of embodiments 7-76, wherein each of the first photoelectric element and the second photoelectric element is electrically isolated from one another.

[0318] Aspect 78 A semiconductor device comprising the semiconductor structure of any one of embodiments 1 to 77.

[0319] Aspect 79 An illumination system or a display system comprising the semiconductor device of embodiment 78.

[0320] Aspect 80 (a) depositing a first relaxed (In)GaN growth layer overlying a first substrate region of a substrate; (b) depositing a second relaxed InGaN growth layer overlying the second substrate region of the substrate, the second relaxed InGaN growth layer comprising a patterned GaN seed region; the first relaxed (In)GaN growth layer comprises a first (0001) (In)GaN region characterized by a first in-plane lattice constant, a; the second relaxed InGaN growth layer comprises a second (0001) InGaN region characterized by a second in-plane lattice constant, a; A method of fabricating a semiconductor structure, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0321] Aspect 81 depositing a second relaxed InGaN growth layer; Fabricating a patterned GaN seed region; growing InGaN on the GaN seed region, whereby the InGaN grows on adjacent seed regions and coalesces to form relaxed InGaN regions; 81. The method of embodiment 80, comprising: growing the relaxed InGaN region to provide a (0001) InGaN growth region.

[0322] Aspect 82 81. The method of embodiment 80, comprising depositing a first relaxed (In)GaN growth layer, depositing a second relaxed InGaN growth layer, and then fabricating a first optoelectronic element located on the first relaxed InGaN growth layer, and fabricating a second optoelectronic element located on the second relaxed InGaN growth layer.

[0323] Aspect 83 the first optoelectronic element comprises an epitaxial layer overlying the first relaxed (In)GaN growth layer; The method of any one of embodiments 80-82, wherein the second optoelectronic device comprises an epitaxial layer overlying the second relaxed InGaN growth layer.

[0324] Aspect 84 The method of any one of embodiments 80-83, wherein the epitaxial layer comprises an n-type (In)GaN layer, an active layer, a p-type (In)GaN layer, or a combination of any of the foregoing.

[0325] Aspect 85 The method of any one of embodiments 80-84, wherein the first relaxed (In)GaN growth layer comprises GaN.

[0326] Aspect 86 The method of any one of embodiments 80-85, wherein the first relaxed (In)GaN growth layer comprises a first GaN seed region.

[0327] Aspect 87 The method of any one of embodiments 80-86, comprising simultaneously fabricating the first photoelectric element and the second photoelectric element.

[0328] Aspect 88 The method of any one of embodiments 80-87, comprising sequentially fabricating the first photoelectric element and the second photoelectric element.

[0329] Aspect 89 89. The method of any one of embodiments 80-88, wherein each of the first optoelectronic element and the second optoelectronic element is independently selected from a light emitting diode, a laser diode, and a vertical cavity surface emitting laser.

[0330] Aspect 90 After depositing a first relaxed (In)GaN growth layer and a second relaxed InGaN growth layer, (c) depositing a first n-type (In)GaN layer overlying the first relaxed (In)GaN growth layer and depositing a second n-type InGaN layer overlying the second relaxed InGaN growth layer; (d) depositing a first active layer overlying the first n-type (In)GaN layer and a second active layer overlying the second n-type InGaN layer; (e) depositing a first p-type (In)GaN layer overlying the first active layer and a second p-type InGaN layer overlying the second active layer; the first active layer is characterized by a first in-plane lattice constant a; the second active layer is characterized by a second in-plane lattice constant, a; 89. The method of any one of embodiments 80 to 89, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0331] Aspect 91 91. The method of embodiment 90, wherein depositing the first n-type (In)GaN layer and depositing the second n-type InGaN layer comprise co-depositing.

[0332] Aspect 92 91. The method of embodiment 90, wherein depositing the first n-type (In)GaN layer and depositing the second n-type InGaN layer comprise independent depositing.

[0333] Aspect 93 The method of any one of embodiments 90-92, wherein depositing the first active layer and depositing the second active layer comprises concurrently depositing.

[0334] Aspect 94 The method of any one of embodiments 90-92, wherein depositing the first active layer and depositing the second active layer comprise independent depositing.

[0335] Aspect 95 The method of any one of embodiments 90-94, wherein depositing the first p-type (In)GaN layer and depositing the second p-type InGaN layer comprise co-depositing.

[0336] Aspect 96 The method of any one of embodiments 90-94, wherein depositing the first p-type (In)GaN layer and depositing the second p-type InGaN layer comprise independent depositing.

[0337] Aspect 97 97. The method of any one of embodiments 90-96, wherein simultaneously depositing comprises depositing using the same deposition conditions.

[0338] Aspect 98 97. The method of any one of embodiments 90-96, wherein independently depositing comprises depositing using different deposition conditions.

[0339] Aspect 99 The method of any one of embodiments 80-98, comprising depositing an electrical contact overlying each of the n-type (In)GaN layers.

[0340] Aspect 100 The method of any one of embodiments 80-99, comprising depositing an electrical contact overlying each of the p-type (In)GaN layers.

[0341] Aspect 101 A semiconductor structure fabricated using the method of any one of embodiments 80-100.

[0342] Aspect 102 A semiconductor device comprising the semiconductor structure of embodiment 101.

[0343] Aspect 103 The semiconductor device of embodiment 102, comprising an illumination system or a display system.

[0344] Aspect 1A a substrate including a first substrate region and a second substrate region; a first (0001) In layer overlying the first substrate region; x1 Al y1 Ga 1-x1-y1 The first In containing N growth region x1 Al y1 Ga 1-x1-y1 N growth layer, A second patterned In overlying the second substrate region. x2s Al y2s Ga 1-x2s-y2s N seed regions; Second Patterned In x2s Al y2s Ga 1-x2s-y2s A second (0001) In layer located above the N seed region x2 Al y2 Ga 1-x2-y2 The second In containing N growth region x2 Al y2 Ga 1-x2-y2 and an N growth layer, The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane lattice constant, a, Second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by a second in-plane lattice constant, a, the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; 0<x2≦1であり、0≦y2≦1であり、かつx2+y2≦1、x2> x1, a wurtzite III-nitride crystalline semiconductor structure.

[0345] Aspect 2A First In x1 Al y1 Ga 1-x1-y1 The InGaN growth layer is a GaN layer including a first (0001) GaN growth region, the semiconductor structure of Aspect 1A.

[0346] Aspect 3A First In x1 Al y1 Ga 1-x1-y1 The InGaN growth layer is an InGaN layer including a first (0001) InGaN growth region, the semiconductor structure of Aspect 1A. x1 Ga 1-x1 N growth region, the semiconductor structure of Aspect 1A. x1 Ga 1-x1 N layer, the semiconductor structure of Aspect 1A.

[0347] Aspect 4A First In x1 Al y1 Ga 1-x1-y1 The InAlGaN growth layer is an InAlGaN layer including a first (0001) InAlGaN growth region, x1 Al y1 Ga 1-x1-y1 N growth region, x1 Al y1 Ga 1-x1-y1 N layer, where 0 ≦ x1 < 1, 0 < y1 < 1, and x1 + y1 ≦ 1, the semiconductor structure of Aspect 1A.

[0348] Aspect 5A The second patterned InAlGaN seed region comprises a patterned GaN seed region, the semiconductor structure of any one of Aspects 1A to 4A. x2s Al y2s Ga 1-x2s-y2s The second patterned InAlGaN seed region comprises a patterned GaN seed region, the semiconductor structure of any one of Aspects 1A to 4A.

[0349] Aspect 6A The second patterned InAlGaN seed region x2s Al y2s Ga 1-x2s-y2s The second patterned InAlGaN seed region comprises a patterned InGaN seed region, x2s Ga 1-x2s N seed region, the semiconductor structure of any one of Aspects 1A to 4A.

[0350] Aspect 7A The second patterned Inx2s Al y2s Ga 1-x2s-y2s The N seed region is a patterned In x2s Al y2s Ga 1-x2s-y2s N seed region, with 0 ≦ x2s < 1, 0 < y2s < 1, and x2s + y2s ≦ 1, is any one of the semiconductor structures of Aspect 1A - 4A.

[0351] Aspect 8A The second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is the second (0001) In x2 Ga 1-x2 N growth region, and is any one of the semiconductor structures of Aspect 1A - 7A.

[0352] Aspect 9A The second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region is a patterned AlN seed region, and is any one of the semiconductor structures of Aspect 1A - 7A.

[0353] Aspect 10A<​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​y1 Ga 1-x1-y1 The first patterned In layer located under the N growth region x1s Al y1s Ga 1-x1s-y1s comprising an N seed region, 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; First Patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2s The semiconductor structure of any one of Embodiments 1A-9A, wherein each of the N seed regions comprises a different composition.

[0355] Aspect 12A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 11A, wherein the N growth layer comprises a different composition.

[0356] Aspect 13A The first patterned In is parallel to the (0001) plane of the wurtzite III-nitride structure. x1s Al y1s Ga 1-x1s-y1s A first plane intersecting the N seed region is formed such that an intersection of the first plane and a first edge of the first patterned seed region forms a first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 determining the position of the N heterojunction, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; First In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1The semiconductor structure of any one of Embodiments 1A to 12A, wherein the N heterojunction is coplanar with the first crystallographic plane of the seed region, a facet of the seed region, or a combination thereof.

[0357] Aspect 14A First In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of embodiment 13A, wherein the N heterojunction comprises a compositional step of x1s and y1s to x1 and y1.

[0358] Aspect 15A Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region is a second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 Determine the location of the N heterojunction and add the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of embodiment 13A or 14A, wherein the N heterojunction is coplanar with the second crystallographic face of the seed region.

[0359] Aspect 16A The semiconductor structure of embodiment 15A, wherein each of the first crystallographic plane and the second crystallographic plane are crystallographically equivalent.

[0360] Aspect 17A The semiconductor structure of any one of Aspects 1A to 12A, The second patterned In parallel to the (0001) plane of the wurtzite III-nitride structure x2s Al y2s Ga 1-x2s-y2s The first plane that intersects the N seed regions is

[0361] The intersection of the first plane and the first edge of the first patterned seed region defines a first In. x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 characterized by determining the position of the N heterojunction,

[0362] First In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the first crystal face of the seed region.

[0363] Aspect 18A First In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 17A, wherein the N heterojunction comprises a compositional phase of x2s and y2s to x2 and y2.

[0364] Aspect 19A Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region is a second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 Determine the location of the N heterojunction and add the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 17A or 18A, wherein the N heterojunction is coplanar with the second crystallographic face of the seed region.

[0365] Aspect 20A The semiconductor structure of embodiment 19A, wherein each of the first crystallographic plane and the second crystallographic plane are crystallographically equivalent.

[0366] Aspect 21A The first (0001) In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of any one of Embodiments 1A to 20A, wherein the N growth region is characterized by an in-plane lattice constant, a, of 3.19 Å.

[0367] Aspect 22A Second (0001) In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A-20A, wherein the N growth region is characterized by an in-plane lattice constant, a, greater than about 3.19 Å.

[0368] Aspect 23A The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane lattice constant, a, greater than 3.19 Å; Second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by a second in-plane lattice constant, a, greater than 3.19 Å; The semiconductor structure of any one of Embodiments 1A to 20A, wherein the first in-plane lattice constant a differs from the second in-plane lattice constant a by more than 0.2%.

[0369] Aspect 24A The semiconductor construction of any one of Embodiments 1A to 23A, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), gallium oxide, or aluminum nitride.

[0370] Aspect 25A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 24A, wherein the N growth layer is overlying a common GaN buffer layer, which is overlying a substrate.

[0371] Aspect 26A the GaN buffer layer includes a first GaN buffer region and a second GaN buffer region; First In x1 Al y1 Ga 1-x1-y1 an N growth layer overlying the first GaN buffer region; Second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 25A, wherein the N growth layer overlies the second GaN buffer region.

[0372] Aspect 27A The semiconductor structure of embodiment 25A, wherein the GaN buffer layer has an in-plane lattice constant, a, of about 3.189 Å.

[0373] Aspect 28A The semiconductor structure is (a) First In x1 Al y1 Ga 1-x1-y1 a first photovoltaic element located on the N growth layer; (b) Second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A-27A, comprising: a second photovoltaic element overlying the N growth layer.

[0374] Aspect 29A The semiconductor structure is (a) First (0001) In x1 Al y1 Ga 1-x1-y1 a first photovoltaic element located above the N growth region; (b) Second (0001) In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A-24A, comprising: a second photovoltaic element overlying the N growth region.

[0375] Aspect 30A The first photoelectric element is The first (0001) In x1 Al y1 Ga 1-x1-y1 n-type In on top of the N growth layer x1 Al y1 Ga 1-x1-y1 N layer and n-type In x1 Al y1 Ga 1-x1-y1 The first In layer located above the N layer x1 Al y1 Ga 1-x1-y1 N active region; First In x1 Al y1 Ga 1-x1-y1 p-type In on top of the N active region x1 Al y1 Ga 1-x1-y1 N layers, The second photoelectric element is Second (0001) In x2 Al y2 Ga 1-x2-y2 n-type In on top of the N growth layer x2 Al y2 Ga 1-x2-y2 N layer and n-type In x2 Al y2 Ga 1-x2-y2 The second In layer located above the N layer x1 Al y1 Ga 1-x1-y1 N active region; Second In x1 Al y1 Ga 1-x1-y1 p-type In on top of the N active region x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 28A or 29A, comprising:

[0376] Aspect 31A The semiconductor structure of embodiment 30A, wherein each of the first active region and the second active region is characterized by the in-plane lattice constant, a, of an underlying (0001) growth region.

[0377] Aspect 32A the first active region is characterized by a first in-plane lattice constant, a; the second active region is characterized by a second in-plane lattice constant, a; The semiconductor structure of embodiment 30A or 31A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a by more than 0.005 Å.

[0378] Aspect 33A The semiconductor structure of Embodiment 32A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a by between 0.005 Å and 0.54 Å.

[0379] Aspect 34A First In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of any one of Aspects 1A to 33A, wherein the N growth layer is a GaN growth layer.

[0380] Aspect 35A First In x1 Al y1 Ga 1-x1-y1 The N growth layer is In x1 Ga 1-x1 The semiconductor structure of any one of Embodiments 1A to 33A, wherein the semiconductor structure is an N-grown layer.

[0381] Aspect 36A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers independently overlies a patterned GaN seed region; and a coalescence region between adjacent GaN seed regions; The semiconductor structure of any one of Embodiments 1A to 33A, comprising: a (0001) growth region overlying a region.

[0382] Aspect 37A The first (0001) In x1 Al y1 Ga 1-x1-y1The semiconductor structure of any one of Embodiments 1A to 36A, wherein the N growth regions are (0001) GaN growth regions characterized by an in-plane lattice constant, a, of about 3.189 Å.

[0383] Aspect 38A The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by an in-plane lattice constant a greater than about 3.189 Å, which is the (0001) In x1 Ga 1-x1 The semiconductor structure of any one of Embodiments 1A to 36A, wherein the semiconductor structure is an N-growth region.

[0384] Aspect 39A Second (0001) In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 38A, wherein the N growth region is characterized by an in-plane lattice constant a greater than 3.189 Å.

[0385] Aspect 40A Second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by an in-plane lattice constant a larger than 3.189 Å, i.e., (0001) In x2 Ga 1-x2 The semiconductor structure of any one of Embodiments 1A to 38A, wherein the semiconductor structure is an N-growth region.

[0386] Aspect 41A Second (0001) In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 38A, wherein the N growth region is characterized by an in-plane lattice constant, a, between 3.190 Å and 3.545 Å.

[0387] Aspect 42A The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane lattice constant a between 3.189 Å and 3.545 Å; Second (0001) Inx2 Al y2 Ga 1-x2-y2 The N growth region is characterized by a second in-plane lattice constant, a, between 3.189 Å and 3.545 Å; The semiconductor structure of any one of Aspects 1A to 38A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0388] Aspect 43A The first (0001) In x1 Al y1 Ga 1-x1-y1 N growth region and the second (0001) In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 42A, wherein each of the N growth regions is independently characterized by an in-plane lattice constant, a, in the range of 3.190 Å to 3.50 Å.

[0389] Aspect 44A The first (0001) In x1 Al y1 Ga 1-x1-y1 the N growth region comprises a first InN mole fraction; Second (0001) In x2 Al y2 Ga 1-x2-y2 the InN growth region comprises a second InN mole fraction; The semiconductor structure of any one of Embodiments 1A to 43A, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0390] Aspect 45A The semiconductor construction of embodiment 44A, wherein the first InN mole fraction is 0 mol %.

[0391] Aspect 46A The semiconductor construction of embodiment 44A, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol %.

[0392] Aspect 47A The semiconductor construction of embodiment 44A, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol % and less than 100 mol %.

[0393] Aspect 48A First In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of Embodiment 1A, wherein the N growth layer is a GaN growth layer.

[0394] Aspect 49A First In x1 Al y1 Ga 1-x1-y1 The N growth layer is In x1 Ga 1-x1 The semiconductor structure of embodiment 1A, wherein the N-grown layer.

[0395] Embodiment 50A The first In x1 Al y1 Ga 1-x1-y1 The N growth layer is then patterned with a first In layer featuring a first pattern. x1s Al y1s Ga 1-x1s-y1s Located above N seed regions, 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The second In x2 Al y2 Ga 1-x2-y2 The N growth layer is then patterned with a second In pattern. x2s Al y2s Ga 1-x2s-y2s Located above the N seed region, The semiconductor construction of any one of Embodiments 1A to 49A, wherein the first second pattern is different from the first pattern.

[0396] Aspect 51A First Patterned In x1s Al y1s Ga 1-x1s-y1s the N seed region is the first patterned GaN region; Second Patterned In x2s Aly2s Ga 1-x2s-y2s The semiconductor structure of embodiment 50A, wherein the N seed region is a second patterned GaN region.

[0397] Aspect 52A The semiconductor structure of any one of embodiments 50A or 51A, wherein the first and second patterns differ in size of the seed regions, shape of the seed regions, fill factor of the seed regions, spacing of the seed regions, crystal orientation of the seed regions, base geometry of the seed regions, two-dimensional pattern of the seed regions, or a combination of any of the foregoing.

[0398] Aspect 53A The semiconductor construction of any one of Embodiments 1A-52A, comprising a dielectric region adjacent each of the seed regions.

[0399] Aspect 54A The dielectric region is SiO x , SiN x , AlO x or a combination of any of the foregoing.

[0400] Aspect 55A The first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth region is first patterned In x1s Al y1s Ga 1-x1s-y1s Located above N seed regions, 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; First Patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and a second patterned In x2s Al y2s Ga 1-x2s-y2s The semiconductor structure of any one of Embodiments 1A-54A, wherein each of the N seed regions comprises a growth surface coplanar with a wurtzite III-nitride crystal plane.

[0401] Aspect 56A The first (0001) Inx1 Al y1 Ga 1-x1-y1 The N growth region is first patterned In x1s Al y1s Ga 1-x1s-y1s N seed regions, and 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; x1 Al y1 Ga 1-x1-y1 the InN growth region is characterized by a first in-plane lattice constant, a, and a first InN mole fraction; Second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is then patterned with a second In x2s Al y2s Ga 1-x2s-y2s Located above the N seed region, a second (0001) In x2 Al y2 Ga 1-x2-y2 the InN growth region is characterized by a second in-plane lattice constant, a, and a second InN mole fraction; the first in-plane lattice constant a is different from the second in-plane lattice constant a; The semiconductor structure of any one of Embodiments 1A to 54A, wherein the first InN mole fraction is different from the second InN mole fraction.

[0402] Aspect 57A The semiconductor structure of embodiment 54A or 55A, wherein each of the first in-plane lattice constant a and the second in-plane lattice constant a is independently greater than 3.189 Å.

[0403] Aspect 58A The semiconductor structure of embodiment 54A or 55A, wherein each of the first in-plane lattice constant a and the second in-plane lattice constant a is independently in the range of 3.189 Å to 3.54 Å.

[0404] Aspect 59A The first patterned seed region is In x1s Ga 1-x1s and characterized by a wurtzite III-nitride crystal structure, where 0≦x1s<1, and the second patterned seed region is Inx2s Ga 1-x2s A semiconductor structure according to any one of Aspects 55A to 58A, which contains GaN and is characterized by a wurtzite-type Group III nitride crystal structure, where 0 ≦ x2s < 1.

[0405] Aspect 60A The first patterned seed region is In x1s Ga 1-x1s A semiconductor structure according to any one of Aspects 55A to 58A, which contains GaN and is characterized by a wurtzite-type Group III nitride crystal structure, where 0 < x1s < 1, The second patterned seed region is In x2s Ga 1-x2s A semiconductor structure according to any one of Aspects 55A to 58A, which contains GaN and is characterized by a wurtzite-type Group III nitride crystal structure, where 0 < x2s < 1.

[0406] Aspect 61A Each of the first and second patterned seed regions is a semiconductor structure according to any one of Aspects 55A to 58A, which contains GaN and is characterized by a wurtzite-type Group III nitride crystal structure.

[0407] Aspect 62A Each of the first and second patterned seed regions has a semiconductor structure of Aspect 61A with six planar seed facets.

[0408] Aspect 63A Each of the first and second patterned seed regions has a semiconductor structure of Aspect 61A, which is characterized by a hexagonal base. <002778>[[ID=''39]]

[0409] Aspect 64A Each of the first and second seed regions has a semiconductor structure according to any one of Aspects 61A to 63A, with a seed surface coplanar with the crystal plane of the wurtzite-type Group III nitride.

[0410] Aspect 65A Each of the crystal planes is a crystallographically equivalent {10-11} plane in the semiconductor structure of Aspect 64A.

[0411] Aspect 66A The semiconductor structure of embodiment 64A, wherein each of the crystallographic planes is a crystallographically equivalent {1-100} plane.

[0412] Aspect 67A The semiconductor structure of embodiment 64A, wherein each of the crystallographic planes is a crystallographically equivalent {11-20} plane.

[0413] Aspect 68A The semiconductor structure of embodiment 64A, wherein each of the crystallographic planes is a plane rotated between a {1-100} plane and a {11-20} plane.

[0414] Aspect 69A 65. The semiconductor structure of embodiment 64, wherein the region at the midpoint between adjacent seed regions is a coalescence growth region.

[0415] Embodiment 70A The semiconductor construction of any one of Embodiments 61A-65A, wherein each of the first and second seed regions is substantially free of a (0001) facet.

[0416] Aspect 71A First In x1 Al y1 Ga 1-x1-y1 The N growth layer is composed of multiple In x1 Al y1 Ga 1-x1-y1 N growth region, each In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of any one of Embodiments 1A to 70A, wherein the N growth regions have different InN mole fractions.

[0417] Aspect 72A Second In x2 Al y2 Ga 1-x2-y2 The N growth layer is composed of multiple In x2 Al y2 Ga 1-x2-y2 Each In x2 Al y2 Ga 1-x2-y2The semiconductor structure of any one of Embodiments 1A to 71A, wherein the N growth regions have different InN mole fractions.

[0418] Aspect 73A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 72A, wherein each of the N growth layers is independently configured to provide a (0001) growth region having a defined degree of in-plane lattice relaxation, a.

[0419] Aspect 74A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 72A, wherein each of the N growth layers is independently configured to have a (0001) growth region characterized by a different in-plane lattice constant, a.

[0420] Aspect 75A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 72A, wherein each of the N growth layers is independently configured to have a (0001) growth region characterized by a different InN mole fraction.

[0421] Aspect 76A The first (0001) In x1 Al y1 Ga 1-x1-y1 The first n-type In layer is located above the N growth region. x1 Al y1 Ga 1-x1-y1 N layer and First n-type In x1 Al y1 Ga 1-x1-y1a first active region located on the N layer; a first p-type In semiconductor layer located above the first active region; x1 Al y1 Ga 1-x1-y1 N layer and Second (0001) In x2 Al y2 Ga 1-x2-y2 A second n-type In layer is located above the N growth region. x2 Al y2 Ga 1-x2-y2 N layer and Second n-type In x2 Al y2 Ga 1-x2-y2 a second active region located on the N layer; a second p-type In semiconductor layer located above the second active region; x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 1A to 75A, comprising:

[0422] Aspect 77A First n-type In x1 Al y1 Ga 1-x1-y1 The semiconductor structure of embodiment 76A, wherein the N layer comprises GaN.

[0423] Aspect 78A First n-type In x1 Al y1 Ga 1-x1-y1 The N layer is In x1 Ga 1-x1 The semiconductor structure of embodiment 76A, comprising N.

[0424] Aspect 79A First n-type In x1 Al y1 Ga 1-x1-y1 N layer and second n-type In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 76A, wherein each of the N layers independently has an in-plane lattice constant a equivalent to the in-plane lattice constant a of the respective underlying (0001) growth region.

[0425] Embodiment 80A First n-type Inx1 Al y1 Ga 1-x1-y1 The N growth layer is characterized by a first in-plane lattice constant, a, Second n-type In x2 Al y2 Ga 1-x2-y2 The N growth layer is characterized by a second in-plane lattice constant, a, The semiconductor structure of any one of Embodiments 76A to 79A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0426] Aspect 81A First n-type In x1 Al y1 Ga 1-x1-y1 N layer and second n-type In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of embodiments 76A-79A, wherein each of the N layers is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of a respective underlying (0001) growth region.

[0427] Aspect 82A First n-type In x1 Al y1 Ga 1-x1-y1 the N layer includes a first InN mole fraction; Second n-type In x2 Al y2 Ga 1-x2-y2 the N layer includes a second InN mole fraction; The semiconductor structure of any one of Embodiments 76A to 79A, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0428] Aspect 83A The semiconductor construction of any one of Embodiments 76A-82A, wherein the first active region comprises a plurality of first active layers.

[0429] Aspect 84A The semiconductor construction of any one of Embodiments 76A-83A, wherein the second active region comprises a plurality of active layers.

[0430] Aspect 85A The semiconductor construction of any one of Embodiments 76A-84A, wherein the first active region and the second active region each independently comprise a plurality of active layers.

[0431] Aspect 86A The semiconductor construction of any one of embodiments 76A to 85A, wherein the first active region comprises 1 to 40 active layers and the second active region comprises 1 to 40 active layers, or each of the first active region and the second active region comprises 1 to 40 active layers.

[0432] Aspect 87A The semiconductor construction of any one of Embodiments 76A-86A, wherein each of the first active region and the second active region independently comprises one or more quantum wells or quantum dots comprising an In-containing III-nitride material.

[0433] Aspect 88A the first active region comprises a first InN mole fraction; the second active region comprises a second InN mole fraction; The semiconductor structure of any one of Embodiments 76A to 87A, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0434] Aspect 89A the first active region is characterized by a first in-plane strain value; the second active region is characterized by a second in-plane strain value; The semiconductor construction of any one of Embodiments 76A to 83A, wherein the first strain value is the same as the second strain value.

[0435] Aspect 90A The semiconductor structure of embodiment 89A, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

[0436] Aspect 91A The semiconductor structure of embodiment 89A, wherein the second in-plane strain value is within 1% of said first in-plane strain value.

[0437] Aspect 92A The semiconductor structure of embodiment 89A, wherein each of the first strain value and the second strain value is independently between 1% and 2% of compressive strain.

[0438] Aspect 93A The semiconductor construction of any one of Embodiments 76A-92A, wherein the first active region and the second active region each comprise a multiple quantum well structure.

[0439] Aspect 94A The semiconductor construction of any one of Embodiments 76A-92A, wherein the first active region and the second active region each comprise a light emitting diode structure.

[0440] Aspect 95A The semiconductor construction of any one of Embodiments 76A-92A, wherein the first active region and the second active region each comprise a laser diode structure.

[0441] Aspect 96A First p-type In x1 Al y1 Ga 1-x1-y1 The N layer is characterized by a first in-plane lattice constant a, Second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is characterized by a second in-plane lattice constant a, The semiconductor structure of any one of Embodiments 76A to 92A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0442] Aspect 97A First p-type In x1 Al y1 Ga 1-x1-y1 N layer and second p-type In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of embodiments 76A-96A, wherein each of the N layers is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of a respective underlying (0001) growth region.

[0443] Aspect 98A First p-type In x1 Aly1 Ga 1-x1-y1 the N layer includes a first InN mole fraction; Second p-type In x2 Al y2 Ga 1-x2-y2 the N layer includes a second InN mole fraction; The semiconductor structure of any one of Embodiments 76A to 97A, wherein the second InN mole fraction is greater than the first InN mole fraction.

[0444] Aspect 99A First p-type In x1 Al y1 Ga 1-x1-y1 N layer and second p-type In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of Embodiments 76A to 98A, wherein each of the N layers independently has an in-plane lattice constant a in the range of 3.19 Å to 3.35 Å.

[0445] Embodiment 100A The semiconductor structure of any one of Embodiments 76A-99A, further comprising a capping layer comprising an Al-containing III-nitride material, the capping layer interposed between the active region and the overlying p-type III-nitride layer.

[0446] Aspect 101A The semiconductor construction of any one of Embodiments 22A to 100A, wherein each of the first photoelectric element and the second photoelectric element is configured to emit electromagnetic radiation within a different wavelength range.

[0447] Aspect 102A The semiconductor construction of any one of Embodiments 28A-33A, wherein the first optoelectronic element and the second optoelectronic element each independently comprise a light emitting diode, a superluminescent light emitting diode, a laser diode, or a vertical cavity surface emitting laser.

[0448] Aspect 103A First n-type In x1 Al y1 Ga 1-x1-y1 N layer and second In x2 Aly2 Ga 1-x2-y2 a cathode electrically connected to each of the N layers; First p-type In x1 Al y1 Ga 1-x1-y1 N layer and second p-type In x2 Al y2 Ga 1-x2-y2 103. The semiconductor structure of embodiment 102, further comprising: an anode electrically connected to each of the N layers.

[0449] Aspect 104A The semiconductor construction of embodiment 103A, wherein the cathode comprises Ti and Al.

[0450] Aspect 105A The cathode is a common first n-type In x1 Al y1 Ga 1-x1-y1 N layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 103A or 104A, interconnected with each of the N layers.

[0451] Embodiment 106A The cathode is independently and commonly a first n-type In x1 Al y1 Ga 1-x1-y1 N layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of embodiment 103A or 104A, interconnected with each of the N layers.

[0452] Aspect 107A The semiconductor construction of any one of Embodiments 103A to 106A, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

[0453] Aspect 108A The anode is a common first n-type In x1 Al y1 Ga 1-x1-y1 N layer and second In x2 Al y2 Ga 1-x2-y2The semiconductor structure of any one of embodiments 103A-107A, interconnected with each of the N layers.

[0454] Aspect 109A The anode is connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and second In x2 Al y2 Ga 1-x2-y2 The semiconductor structure of any one of embodiments 103A-107A, interconnected with each of the N layers.

[0455] Aspect 110A The semiconductor construction of any one of Embodiments 103A-109A, wherein the first photoelectric element and the second photoelectric element are electrically isolated from each other.

[0456] Aspect 111A A wafer comprising the semiconductor structure of any one of embodiments 1A to 108A.

[0457] Aspect 112A A photoelectric device comprising the semiconductor structure of any one of Embodiments 1A to 108A.

[0458] Aspect 113A A multicolor photovoltaic device comprising the semiconductor structure of any one of Embodiments 1A-108A.

[0459] Aspect 114A A semiconductor device comprising the semiconductor structure of any one of embodiments 1A to 108A.

[0460] Aspect 115A An illumination or display system comprising the semiconductor device of embodiment 114A.

[0461] Aspect 116A 1. A method for fabricating a wurtzite III-nitride crystalline semiconductor structure, comprising: (a) A first In layer located on a first substrate region of a substrate. x1 Al y1 Ga 1-x1-y1depositing a N growth layer; (b) a second In overlying a second substrate region of the substrate; x2 Al y2 Ga 1-x2-y2 depositing a second In N growth layer; x2 Al y2 Ga 1-x2-y2 The N growth layer is then patterned with a second In x2s Al y2s Ga 1-x2s-y2s and overlie N seed regions; First In x1 Al y1 Ga 1-x1-y1 The N growth layer is a first (0001) InN layer characterized by a first in-plane lattice constant a. x1 Al y1 Ga 1-x1-y1 N growth region, Second In x2 Al y2 Ga 1-x2-y2 The N growth layer is a second (0001) In layer characterized by a second in-plane lattice constant a. x2 Al y2 Ga 1-x2-y2 N growth region, the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; 0<x2≦1であり、0≦y2≦1であり、かつx2+y2≦1、x2> Let's say x1.

[0462] Aspect 117A Before step (a), A first patterned In overlying the first substrate region. x1s Al y1s Ga 1-x1s-y1s depositing N seed regions, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; First Patterned In x1s Al y1s Ga1-x1s-y1s The first In is located above the N seed region. x1 Al y1 Ga 1-x1-y1 The method of embodiment 116A, comprising: depositing an N growth layer.

[0463] Aspect 118A First Patterned In x1s Al y1s Ga 1-x1s-y1s The method of embodiment 117A, wherein the N seed region comprises a first GaN seed region.

[0464] Aspect 119A Second Patterned In x1s Al y1s Ga 1-x1s-y1s The method of embodiment 117A or 118A, wherein the N seed region comprises a second patterned GaN seed region.

[0465] Embodiment 120A First In x1 Al y1 Ga 1-x1-y1 N growth layer and second In x2 Al y2 Ga 1-x2-y2 The method of any one of Embodiments 117A-119A, wherein the N growth layers have different elemental compositions.

[0466] Aspect 121A First In x1 Al y1 Ga 1-x1-y1 The N growth layer is the first In x1 Ga 1-x1 N-growth layer, Second In x2 Al y2 Ga 1-x2-y2 The N growth layer is the second In x2 Ga 1-x2 N-growth layer, First In x1 Ga 1-x1 N growth layer and second In x2 Ga 1-x2 121. The method of any one of embodiments 117-120, wherein the N growth layers have different elemental compositions.

[0467] Aspect 122A First In x1 Al y1 Ga 1-x1-y1 The method of any one of Embodiments 117A-121A, wherein depositing an N growth layer includes growing a GaN growth layer to provide a (0001) GaN growth region.

[0468] Aspect 123A First In x1 Al y1 Ga 1-x1-y1 Depositing a N growth layer is A first patterned In film is formed on the first substrate portion. x1s Al y1s Ga 1-x1s-y1s producing N seed regions, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; First Patterned In x1s Al y1s Ga 1-x1s-y1s In on N seed region x1 Al y1 Ga 1-x1-y1 N is grown, thereby x1 Al y1 Ga 1-x1-y1 N is adjacent patterned In x1s Al y1s Ga 1-x1s-y1s The first In grows on the N seed region and coalesces. x1 Al y1 Ga 1-x1-y1 forming an N growth layer; First In x1 Al y1 Ga 1-x1-y1 N growth layer is grown and (0001) In x1 Al y1 Ga 1-x1-y1 The method of any one of embodiments 117A to 122A, comprising: providing an N growth region.

[0469] Aspect 124A Second In x2 Al y2Ga 1-x2-y2 Depositing a N growth layer is Second Patterned In x2s Al y2s Ga 1-x2s-y2s producing an N seed region; Second Patterned In x2s Al y2s Ga 1-x2s-y2s In on N seed region x2 Al y2 Ga 1-x2-y2 N is grown, thereby x2 Al y2 Ga 1-x2-y2 N is the adjacent In x2s Al y2s Ga 1-x2s-y2s N grows on the seed region and coalesces, and In x2 Al y2 Ga 1-x2-y2 forming an N growth layer; In x2 Al y2 Ga 1-x2-y2 N growth layer is grown and (0001) In x2 Al y2 Ga 1-x2-y2 The method of any one of embodiments 117A to 123A, providing an N growth region.

[0470] Aspect 125A First In x1 Al y1 Ga 1-x1-y1 A second In layer is deposited. x2 Al y2 Ga 1-x2-y2 After depositing the N growth layer, the first (0001) In x1 Al y1 Ga 1-x1-y1 Fabricating a first photoelectric element located on the N growth region and a second (0001) In x2 Al y2 Ga 1-x2-y2 The method of any one of embodiments 117A-124A including: fabricating a second photovoltaic element overlying the N growth region.

[0471] Aspect 126A The first photoelectric element is a first (0001) In x1 Al y1 Ga 1-x1-y1 an epitaxial layer overlying an N growth region; The second photoelectric element is a second (0001) In x2 Al y2 Ga 1-x2-y2 The method of embodiment 125A, comprising an epitaxial layer overlying the N growth region.

[0472] Aspect 127A The method of embodiment 126A, wherein the epitaxial layer comprises an n-type layer, an active region, a p-type layer, or a combination of any of the foregoing.

[0473] Aspect 128A First In x1 Al y1 Ga 1-x1-y1 The method of embodiment 126A or 127A, wherein the N growth layer comprises GaN.

[0474] Aspect 129A First In x1 Al y1 Ga 1-x1-y1 The N growth layer is In x1 Ga 1-x1 The method of embodiment 126A or 127A, comprising N.

[0475] Aspect 130A Second In x2 Al y2 Ga 1-x2-y2 The N growth layer is In x2 Ga 1-x2 The method of embodiment 126A or 127A, comprising N.

[0476] Aspect 131A The method of any one of Embodiments 126A-130A, wherein the method includes simultaneously fabricating the first photoelectric element and the second photoelectric element.

[0477] Aspect 132A The method of any one of Embodiments 126A-130A, wherein the method includes sequentially fabricating a first photoelectric element and a second photoelectric element.

[0478] Aspect 133A The method of any one of embodiments 126A to 132A, wherein each of the first photoelectric element and the second photoelectric element is independently selected from a light emitting diode, a superluminescent light emitting diode, a laser diode, and a vertical cavity surface emitting laser.

[0479] Aspect 134A First In x1 Al y1 Ga 1-x1-y1 A second In layer is deposited. x2 Al y2 Ga 1-x2-y2 After depositing the N growth layer, (c)In x1 Al y1 Ga 1-x1-y1 The first n-type In layer is located on top of the N growth layer. x1 Al y1 Ga 1-x1-y1 Deposit an N layer and a second In x2 Al y2 Ga 1-x2-y2 A second n-type In layer is located on top of the N growth layer. x2 Al y2 Ga 1-x2-y2 depositing an N layer; (d) First n-type In x1 Al y1 Ga 1-x1-y1 A first active region is deposited on top of the N layer, and a second n-type In x2 Al y2 Ga 1-x2-y2 depositing a second active region overlying the N layer; (e) a first p-type In layer located over the first active region; x1 Al y1 Ga 1-x1-y1 An N layer is deposited, and a second p-type In layer is deposited over the second active region. x2 Al y2 Ga 1-x2-y2 depositing an N layer; the first active region is characterized by a first in-plane lattice constant, a; the second active region is characterized by a second in-plane lattice constant, a; The method of any one of Embodiments 117A to 133A, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

[0480] Aspect 135A First n-type In x1 Al y1 Ga 1-x1-y1 Depositing an N layer and a second n-type In x2 Al y2 Ga 1-x2-y2 The method of embodiment 134A, wherein depositing the N layer includes simultaneously depositing.

[0481] Aspect 136A First n-type In x1 Al y1 Ga 1-x1-y1 Depositing an N layer and a second n-type In x2 Al y2 Ga 1-x2-y2 The method of embodiment 134A, wherein depositing the N layer comprises independently depositing.

[0482] Aspect 137A The method of any one of Embodiments 134A-136A, wherein depositing the first active region and depositing the second active region include concurrently depositing.

[0483] Aspect 138A The method of any one of Embodiments 134A-136A, wherein depositing the first active region and depositing the second active region include independent depositing.

[0484] Aspect 139A First p-type In x1 Al y1 Ga 1-x1-y1 Depositing an N layer and a second p-type In x2 Al y2 Ga 1-x2-y2The method of any one of Embodiments 134A-138A, wherein depositing an N layer includes simultaneously depositing.

[0485] Aspect 140 First p-type In x1 Al y1 Ga 1-x1-y1 Depositing an N layer and a second p-type In x2 Al y2 Ga 1-x2-y2 The method of any one of Embodiments 134A-138A, wherein depositing an N layer includes independently depositing.

[0486] Aspect 141A The method of any one of embodiments 134A-140A, wherein simultaneously depositing includes depositing using the same deposition conditions.

[0487] Aspect 142A The method of any one of embodiments 134A-140A, wherein independently depositing includes depositing using different deposition conditions.

[0488] Aspect 143A The method of any one of embodiments 134A-142A, including depositing an electrical contact overlying each of the n-type layers.

[0489] Aspect 144A The method of any one of embodiments 134A-143A, including depositing an electrical contact overlying each of the p-type layers.

[0490] Aspect 145A A semiconductor structure fabricated using the method of any one of embodiments 116A-144A.

[0491] Aspect 146 A semiconductor wafer comprising the semiconductor structure of any one of embodiments 1A to 110A.

[0492] Aspect 147A A multi-wavelength photovoltaic device comprising the semiconductor structure of any one of Embodiments 1A to 110A.

[0493] Aspect 148A A semiconductor device comprising the photoelectric element of embodiment 147A. Aspect 149A An illumination or display system comprising the semiconductor device of embodiment 148A.

[0494] Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein, and therefore the present embodiments should be considered illustrative rather than restrictive, and the claims should not be limited to the details set forth herein, but may be modified within the scope and equivalents thereof.

Claims

1. a substrate including a first substrate region and a second substrate region; a first (0001) In overlying the first substrate region; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The first In containing N growth region ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an N growth layer; a second patterned In overlying the second substrate region; ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N seed regions; and The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ A second (0001) In layer located above the N seed region ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ A second In containing N growth region ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ an N-grown layer; The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth region is characterized by a first in-plane lattice constant, a; The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth region is characterized by a second in-plane lattice constant, a; the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; A wurtzite Group III nitride crystalline semiconductor structure, in which 0<x2≦1, 0≦y2≦1, and x2+y2≦1, x2>x1.

2. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 10. The semiconductor structure of claim 1, wherein the N growth layer is a GaN layer that includes a first (0001) GaN growth region.

3. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is the first (0001) In ｘ１ Ga １－ｘ１ In containing N growth region ｘ１ Ga １－ｘ１ The semiconductor structure of claim 1 , which is an N layer.

4. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is the first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ In containing N growth region ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 2. The semiconductor structure of claim 1, wherein the semiconductor structure is an N layer, and 0≦x1<1, 0<y1<1, and x1+y1≦1.

5. The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The semiconductor structure of any one of claims 1 to 4, wherein the N seed region comprises a patterned GaN seed region.

6. The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The N seed region is patterned In ｘ２ｓ Ga １－ｘ２ｓ The semiconductor structure of any one of claims 1 to 4, comprising an N seed region.

7. The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The N seed region is patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ 5. The semiconductor structure of claim 1, comprising an N seed region, wherein 0≦x2s<1, 0<y2s<1, and x2s+y2s≦1.

8. The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth region is the second (0001) In ｘ２ Ga １－ｘ２ The semiconductor structure of any one of claims 1 to 7, comprising an N growth region.

9. The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The semiconductor structure of any one of claims 1 to 7, wherein the N seed region comprises a patterned AlN seed region.

10. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The first patterned In layer located under the N growth region ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed regions; 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed region and the second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The semiconductor structure of any one of claims 1 to 9, wherein each of the N seed regions comprises the same composition.

11. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The first patterned In layer located under the N growth region ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed regions; 0≦x1s≦1, 0≦y1s≦, and x1s+y1s≦1; The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed region and the second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ The semiconductor structure of any one of claims 1 to 9, wherein each of the N seed regions comprises a different composition.

12. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The semiconductor structure of any one of claims 1 to 11, wherein the N-growth layer comprises different compositions.

13. A first patterned In parallel to the (0001) plane of the wurtzite III-nitride structure ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ A first plane intersecting the N seed region is formed such that an intersection of the first plane and a first edge of the first patterned seed region forms a first In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N / In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ determining the position of an N heterojunction, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The first In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N / In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The semiconductor structure of any one of claims 1 to 12, wherein an N heterojunction is coplanar with a first crystallographic plane of the seed region, a facet of the seed region, or a combination thereof.

14. The first In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N / In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 14. The semiconductor structure of claim 13, wherein the N heterojunction comprises a compositional step from x1s and y1s to x1 and y1.

15. Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region is a second In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N / In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ Determine the position of the N heterojunction and ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N / In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 15. The semiconductor structure of claim 13 or 14, wherein an N heterojunction is coplanar with the second crystallographic face of the seed region.

16. 16. The semiconductor structure of claim 15, wherein each of the first crystal plane and the second crystal plane are crystallographically equivalent.

17. The second patterned In is parallel to the (0001) plane of the wurtzite III-nitride structure. ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ A first plane intersecting the N seed region is formed such that an intersection of the first plane and a first edge of the first patterned seed region forms a first In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N / In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ determining the position of an N heterojunction; The first In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N / In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The semiconductor structure of any one of claims 1 to 12, wherein an N heterojunction is coplanar with the first crystallographic face of the seed region.

18. The first In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N / In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 18. The semiconductor structure of claim 17, wherein the N heterojunction comprises a compositional step from x2s and y2s to x2 and y2.

19. Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region is a second In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N / In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ Determine the position of the N heterojunction and ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ N / In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 19. The semiconductor structure of claim 17 or 18, wherein an N heterojunction is coplanar with the second crystallographic face of the seed region.

20. 20. The semiconductor structure of claim 19, wherein each of the first crystal plane and the second crystal plane are crystallographically equivalent.

21. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 21. The semiconductor structure of any one of claims 1 to 20, wherein the N growth region is characterized by an in-plane lattice constant a of 3.19 Å.

22. The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 21. The semiconductor structure of any one of claims 1 to 20, wherein the N growth region is characterized by an in-plane lattice constant a greater than about 3.19 Å.

23. First (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth region is characterized by a first in-plane lattice constant, a, greater than 3.19 Å; Second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth region is characterized by a second in-plane lattice constant, a, greater than 3.19 Å; 21. The semiconductor structure of any preceding claim, wherein the first in-plane lattice constant a differs from the second in-plane lattice constant a by more than 0.2%.

24. The semiconductor structure of any one of claims 1 to 23, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), gallium oxide, or aluminum nitride.

25. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The semiconductor structure of any one of claims 1 to 24, wherein the N growth layer is overlying a common GaN buffer layer, the common GaN buffer layer overlying the substrate.

26. the GaN buffer layer includes a first GaN buffer region and a second GaN buffer region; The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an N growth layer overlies the first GaN buffer region; The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 26. The semiconductor structure of claim 25, wherein an N growth layer overlies the second GaN buffer region.

27. 26. The semiconductor structure of claim 25, wherein the GaN buffer layer has an in-plane lattice constant, a, of about 3.189 Å.

28. The semiconductor structure comprises: (a) the first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a first photovoltaic element located on the N growth layer; (b) the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ A second photovoltaic element located above the N-growth layer.

29. The semiconductor structure comprises: (a) the first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a first photovoltaic element overlying the N growth region; (b) the second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ A semiconductor structure according to any preceding claim, comprising: a second photovoltaic element overlying the N growth region.

30. The first photoelectric element is The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ n-type In located on top of the N growth layer ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer, The n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The first In layer located on the N layer ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an N active region; The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ A p-type In layer overlying an N active region ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layers, The second photoelectric element is The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ n-type In located on top of the N growth layer ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N layer, The n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The second In layer located on the N layer ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an N active region; The second In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ A p-type In layer overlying an N active region ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 30. The semiconductor structure of claim 28 or 29, comprising: an N layer.

31. 31. The semiconductor structure of claim 30, wherein each of the first active region and the second active region is characterized by the in-plane lattice constant a of the underlying (0001) growth region.

32. the first active region is characterized by a first in-plane lattice constant, a; the second active region is characterized by a second in-plane lattice constant, a; 32. The semiconductor structure of claim 30, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a by more than 0.005 Å.

33. 33. The semiconductor structure of claim 32, wherein the second in-plane lattice constant a is between 0.005 Å and 0.54 Å greater than the first in-plane lattice constant a.

34. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The semiconductor structure of any one of claims 1 to 33, wherein the N growth layer is a GaN growth layer.

35. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is In ｘ１ Ga １－ｘ１ The semiconductor structure of any one of claims 1 to 33, which is an N-grown layer.

36. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ Each of the N growth layers independently overlies a patterned GaN seed region; and coalescence regions between adjacent GaN seed regions; 34. The semiconductor structure of claim 1, further comprising a (0001) growth region overlying said region.

37. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 37. The semiconductor structure of any one of claims 1 to 36, wherein the N growth region is a (0001) GaN growth region characterized by an in-plane lattice constant a of about 3.189 Å.

38. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth region is characterized by an in-plane lattice constant a greater than about 3.189 Å, i.e., (0001) In. ｘ１ Ga １－ｘ１ The semiconductor structure of any one of claims 1 to 36, which is an N-growth region.

39. The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 39. The semiconductor structure of any one of claims 1 to 38, wherein the N growth region is characterized by an in-plane lattice constant a greater than 3.189 Å.

40. The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth region is characterized by an in-plane lattice constant a larger than 3.189 Å, i.e., (0001) In. ｘ２ Ga １－ｘ２ The semiconductor structure of any one of claims 1 to 38, which is an N-growth region.

41. The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 39. The semiconductor structure of any one of claims 1 to 38, wherein the N growth region is characterized by an in-plane lattice constant a between 3.190 Å and 3.545 Å.

42. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth region is characterized by a first in-plane lattice constant, a, between 3.189 Å and 3.545 Å; The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth region is characterized by a second in-plane lattice constant, a, between 3.189 Å and 3.545 Å; 39. The semiconductor structure of any preceding claim, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

43. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth region and the second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 43. The semiconductor structure of any one of claims 1 to 42, wherein each of the N growth regions is independently characterized by an in-plane lattice constant, a, in the range of 3.190 Å to 3.50 Å.

44. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth region comprises a first InN mole fraction; The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth region comprises a second InN mole fraction; 44. The semiconductor structure of any one of claims 1 to 43, wherein the second InN mole fraction is greater than the first InN mole fraction.

45. 45. The semiconductor structure of claim 44, wherein the first InN mole fraction is 0 mol%.

46. 45. The semiconductor structure of claim 44, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol%.

47. 45. The semiconductor structure of claim 44, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol% and less than 100 mol%.

48. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The semiconductor structure of claim 1 , wherein the N growth layer is a GaN growth layer.

49. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is In ｘ１ Ga １－ｘ１ The semiconductor structure of claim 1 , wherein the semiconductor structure is an N-grown layer.

50. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is then patterned with a first patterned InN layer. ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ Located above N seed regions, with 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is formed by the second patterned In layer characterized by a second pattern. ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ Located above the N seed region, 50. The semiconductor structure of any one of claims 1 to 49, wherein the first and second patterns are different from the first pattern.

51. The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ the N seed region is the first patterned GaN region; The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ 51. The semiconductor structure of claim 50, wherein the N seed region is a second patterned GaN region.

52. 52. The semiconductor structure of claim 50, wherein the first and second patterns differ in size of the seed regions, shape of the seed regions, fill factor of the seed regions, spacing of the seed regions, crystal orientation of the seed regions, base geometry of the seed regions, two-dimensional pattern of the seed regions, or a combination of any of the foregoing.

53. 53. The semiconductor structure of any one of claims 1 to 52, comprising a dielectric region adjacent each of said seed regions.

54. The dielectric region is SiO ｘ , SiN ｘ , AlO ｘ 54. The semiconductor structure of claim 53, comprising:

55. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth region is formed by the first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ Located above N seed regions, with 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed region and the second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ 55. The semiconductor structure of any one of claims 1 to 54, wherein each of the N seed regions comprises a growth surface coplanar with a wurtzite III-nitride crystal plane.

56. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth region is formed by the first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ N seed region, and 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth region is characterized by a first in-plane lattice constant, a, and a first InN mole fraction; The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth region is formed by the second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ the second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth region is characterized by a second in-plane lattice constant, a, and a second InN mole fraction; the first in-plane lattice constant a is different from the second in-plane lattice constant a; 55. The semiconductor structure of any one of claims 1 to 54, wherein the first InN mole fraction is different from the second InN mole fraction.

57. 56. The semiconductor structure of claim 54 or 55, wherein each of the first in-plane lattice constant a and the second in-plane lattice constant a is independently greater than 3.189 Å.

58. 56. The semiconductor structure of claim 54 or 55, wherein each of the first in-plane lattice constant a and the second in-plane lattice constant a is independently in the range of 3.189 Å to 3.54 Å.

59. The first patterned seed region is In ｘ１ｓ Ga １－ｘ１ｓ N and characterized by a wurtzite III-nitride crystal structure, 0≦x1s<1; The second patterned seed region is In ｘ２ｓ Ga １－ｘ２ｓ 59. The semiconductor structure of any one of claims 55 to 58, comprising N and characterized by a wurtzite III-nitride crystal structure, with 0≦x2s<1.

60. The first patterned seed region is In ｘ１ｓ Ga １－ｘ１ｓ N and characterized by a wurtzite Group III nitride crystal structure, 0<x1s<1, The second patterned seed region is In ｘ２ｓ Ga １－ｘ２ｓ 59. The semiconductor structure of any one of claims 55 to 58, comprising N and characterized by a wurtzite III-nitride crystal structure, with 0<x2s<1.

61. 59. The semiconductor structure of any one of claims 55 to 58, wherein each of the first and second patterned seed regions comprises GaN and is characterized by a wurtzite III-nitride crystal structure.

62. 62. The semiconductor structure of claim 61 , wherein each of the first and second patterned seed regions has six planar seed facets.

63. 62. The semiconductor structure of claim 61 , wherein each of the first and second patterned seed regions is characterized by a hexagonal base.

64. 64. The semiconductor structure of any one of claims 61 to 63, wherein each of the first and second seed regions comprises a seed surface coplanar with a crystallographic plane of wurtzite Group III nitride.

65. 65. The semiconductor structure of claim 64, wherein each of said crystallographic planes is a crystallographically equivalent {10-11} plane.

66. 65. The semiconductor structure of claim 64, wherein each of said crystallographic planes is a crystallographically equivalent {1-100} plane.

67. 65. The semiconductor structure of claim 64, wherein each of said crystallographic planes is a crystallographically equivalent {11-20} plane.

68. 65. The semiconductor structure of claim 64, wherein each of said crystal planes is a plane rotated between a {1-100} plane and a {11-20} plane.

69. 65. The semiconductor structure of claim 64, wherein the region at the midpoint between adjacent seed regions is a coalescence growth region.

70. 66. The semiconductor structure of any one of claims 61 to 65, wherein each of the first and second seed regions is substantially free of a (0001) facet.

71. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is made up of multiple In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth region, each In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 71. The semiconductor structure of any one of claims 1 to 70, wherein the N growth regions have different InN mole fractions.

72. The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is made up of multiple In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N growth region, each In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 72. The semiconductor structure of any one of claims 1 to 71, wherein the N growth regions have different InN mole fractions.

73. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 73. The semiconductor structure of any one of claims 1 to 72, wherein each of the N growth layers is independently configured to provide a (0001) growth region having a defined degree of in-plane lattice relaxation, a.

74. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 73. The semiconductor structure of any one of claims 1 to 72, wherein each of the N growth layers is independently configured to have a (0001) growth region characterized by a different in-plane lattice constant a.

75. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 73. The semiconductor structure of any one of claims 1 to 72, wherein each of the N growth layers is independently configured to have a (0001) growth region characterized by a different InN mole fraction.

76. The first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a first n-type In layer overlying the N growth region; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer, The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a first active region located on the N layer; a first p-type In layer located above the first active region; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer, The second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ a second n-type In layer overlying the N growth region; ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N layer, The second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ a second active region located on the N layer; a second p-type In layer located above the second active region; ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 76. The semiconductor structure of any one of claims 1 to 75, comprising: an N layer.

77. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 77. The semiconductor structure of claim 76, wherein the N layer comprises GaN.

78. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N layer is In ｘ１ Ga １－ｘ１ 77. The semiconductor structure of claim 76, comprising N.

79. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 77. The semiconductor structure of claim 76, wherein each of the N layers independently has an in-plane lattice constant a equivalent to the in-plane lattice constant a of said respective underlying (0001) growth region.

80. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N growth layer is characterized by a first in-plane lattice constant, a; The second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N growth layer is characterized by a second in-plane lattice constant, a; 80. The semiconductor structure of any one of claims 76 to 79, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

81. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 80. The semiconductor structure of any one of claims 76-79, wherein each of the N layers is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of said respective underlying (0001) growth region.

82. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N layer includes a first InN mole fraction; The second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N layer includes a second InN mole fraction; 80. The semiconductor structure of any one of claims 76 to 79, wherein the second InN mole fraction is greater than the first InN mole fraction.

83. 83. The semiconductor structure of any one of claims 76 to 82, wherein the first active region comprises a plurality of first active layers.

84. 84. The semiconductor structure of any one of claims 76 to 83, wherein the second active region comprises a plurality of active layers.

85. 85. The semiconductor structure of any one of claims 76 to 84, wherein each of the first active region and the second active region independently comprises a plurality of active layers.

86. 86. The semiconductor structure of any one of claims 76-85, wherein the first active region comprises 1 to 40 active layers and the second active region comprises 1 to 40 active layers, or the first active region and the second active region each comprise 1 to 40 active layers.

87. 87. The semiconductor structure of any one of claims 76-86, wherein each of the first active region and the second active region independently comprises one or more quantum wells or quantum dots comprising an In-containing Group III-nitride material.

88. the first active region comprises a first InN mole fraction; the second active region includes a second InN mole fraction; 88. The semiconductor structure of any one of claims 76 to 87, wherein the second InN mole fraction is greater than the first InN mole fraction.

89. the first active region is characterized by a first in-plane strain value; the second active region is characterized by a second in-plane strain value; 84. The semiconductor structure of any one of claims 76 to 83, wherein the first strain value is similar to the second strain value.

90. 90. The semiconductor structure of claim 89, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

91. 90. The semiconductor structure of claim 89, wherein the second in-plane strain value is within 1% of the first in-plane strain value.

92. 90. The semiconductor structure of claim 89, wherein each of the first strain value and the second strain value is independently between 1% and 2% compressive strain.

93. 93. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a multiple quantum well structure.

94. 93. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a light emitting diode structure.

95. 93. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a laser diode structure.

96. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N layer is characterized by a first in-plane lattice constant a; The second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N layer is characterized by a second in-plane lattice constant a; 93. The semiconductor structure of any one of claims 76 to 92, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

97. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 97. The semiconductor structure of any one of claims 76-96, wherein each of the N layers is independently characterized by an in-plane lattice constant a that is equivalent to the in-plane lattice constant a of said respective underlying (0001) growth region.

98. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ the N layer includes a first InN mole fraction; The second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ the N layer includes a second InN mole fraction; 98. The semiconductor structure of any one of claims 76 to 97, wherein the second InN mole fraction is greater than the first InN mole fraction.

99. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 99. The semiconductor structure of any one of claims 76 to 98, wherein each of the N layers independently has an in-plane lattice constant, a, in the range of 3.19 Å to 3.35 Å.

100. 100. The semiconductor structure of any one of claims 76 to 99, comprising a capping layer comprising an Al-containing III-nitride material, said capping layer interposed between said active region and said overlying p-type III-nitride layer.

101. 101. The semiconductor structure of any one of claims 22 to 100, wherein each of the first and second photoelectric elements is configured to emit electromagnetic radiation within a different wavelength range.

102. 34. The semiconductor structure of any one of claims 28 to 33, wherein each of the first optoelectronic element and the second optoelectronic element independently comprises a light emitting diode, a superluminescent light emitting diode, a laser diode, or a vertical cavity surface emitting laser.

103. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ a cathode electrically connected to each of the N layers; The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 103. The semiconductor structure of claim 102, further comprising: an anode electrically connected to each of the N layers.

104. 104. The semiconductor structure of claim 103, wherein the cathode comprises Ti and Al.

105. The cathode is commonly the first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 105. The semiconductor structure of claim 103 or 104, interconnected with each of the N layers.

106. The cathodes are independently and commonly connected to the first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 105. The semiconductor structure of claim 103 or 104, interconnected with each of the N layers.

107. 107. The semiconductor structure of any one of claims 103 to 106, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

108. The anodes are commonly connected to the first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 108. The semiconductor structure of any one of claims 103 to 107, interconnected with each of the N layers.

109. The anodes are independently and commonly connected to the first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 108. The semiconductor structure of any one of claims 103 to 107, interconnected with each of the N layers.

110. 110. The semiconductor structure of any one of claims 103 to 109, wherein the first photoelectric element and the second photoelectric element are electrically isolated from each other.

111. A wafer comprising the semiconductor structure of any one of claims 1 to 108.

112. An optoelectronic device comprising a semiconductor structure according to any one of claims 1 to 108.

113. A multicolor photovoltaic device comprising a semiconductor structure according to any one of claims 1 to 108.

114. A semiconductor device comprising the semiconductor structure of any one of claims 1 to 108.

115. 115. A lighting or display system comprising a semiconductor device according to claim 114.

116. 1. A method of fabricating a wurtzite Group III-nitride crystalline semiconductor structure, comprising: (a) a first In layer overlying a first substrate region of a substrate; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ depositing an N growth layer; (b) a second In overlying a second substrate region of the substrate; ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ depositing an N growth layer, ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is then patterned with a second In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ and overlying the N seed regions; The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is a first (0001) InN layer characterized by a first in-plane lattice constant a. ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth region, The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is a second (0001) InN layer characterized by a second in-plane lattice constant a. ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N growth region, the second in-plane lattice constant a is greater than the first in-plane lattice constant a; 0≦x2s≦1, 0≦y2s≦1, and x2s+y2s≦1; 0≦x1≦1, 0≦y1≦1, and x1+y1≦1; A method in which 0<x2≦1, 0≦y2≦1, and x2+y2≦1, x2>x1.

117. Before step (a), a first patterned In overlying the first substrate region; ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ depositing an N seed region, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ the first In located above the N seed region; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ and depositing an N growth layer.

118. The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ 118. The method of claim 117, wherein the N seed region comprises a first GaN seed region.

119. The second patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ 119. The method of claim 117 or 118, wherein the N seed region comprises a second patterned GaN seed region.

120. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The method of any one of claims 117 to 119, wherein the N growth layers have different elemental compositions.

121. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is the first In ｘ１ Ga １－ｘ１ N-grown layer; The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is the second In ｘ２ Ga １－ｘ２ N-grown layer; The first In ｘ１ Ga １－ｘ１ N growth layer and the second In ｘ２ Ga １－ｘ２ The method of any one of claims 117 to 120, wherein the N growth layers have different elemental compositions.

122. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The method of any one of claims 117 to 121, wherein depositing an N growth layer comprises growing a GaN growth layer to provide a (0001) GaN growth region.

123. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ Depositing an N growth layer comprises: A first patterned In on the first substrate portion. ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ fabricating N seed regions, where 0≦x1s≦1, 0≦y1s≦1, and x1s+y1s≦1; The first patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ In on the N seed region ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N is grown, thereby ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N is adjacent to the patterned In ｘ１ｓ Al ｙ１ｓ Ga １－ｘ１ｓ－ｙ１ｓ The first In grows on the N seed region and coalesces. ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ forming an N growth layer; The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ N growth layer is grown to form (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ providing an N growth region.

124. The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ Depositing an N growth layer comprises: The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ fabricating an N seed region; The second patterned In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ In on the N seed region ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N is grown, thereby ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N is adjacent In ｘ２ｓ Al ｙ２ｓ Ga １－ｘ２ｓ－ｙ２ｓ It grows on the N seed region and coalesces, and In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ forming an N growth layer; The In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ N growth layer is grown to form (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ A method according to any one of claims 117 to 123, providing an N growth region.

125. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ An N growth layer is deposited to form the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ After depositing the N growth layer, the first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ fabricating a first photovoltaic element located on the N growth region; and fabricating the second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ and fabricating a second optoelectronic element overlying the N growth region.

126. The first photoelectric element is the first (0001) In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an epitaxial layer overlying an N growth region; The second photoelectric element is the second (0001) In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 126. The method of claim 125, comprising an epitaxial layer overlying an N growth region.

127. 127. The method of claim 126, wherein the epitaxial layer comprises an n-type layer, an active region, a p-type layer, or a combination of any of the foregoing.

128. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ 128. The method of claim 126 or 127, wherein the N growth layer comprises GaN.

129. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ The N growth layer is In ｘ１ Ga １－ｘ１ 128. The method of claim 126 or 127, comprising N.

130. The second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The N growth layer is In ｘ２ Ga １－ｘ２ 128. The method of claim 126 or 127, comprising N.

131. 131. The method of any one of claims 126 to 130, wherein the method comprises simultaneously fabricating the first photovoltaic element and the second photovoltaic element.

132. 131. The method of any one of claims 126 to 130, wherein the method comprises sequentially fabricating the first photoelectric element and the second photoelectric element.

133. 133. The method of any one of claims 126 to 132, wherein each of the first and second optoelectronic elements is independently selected from a light emitting diode, a superluminescent light emitting diode, a laser diode, and a vertical cavity surface emitting laser.

134. The first In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ An N growth layer is deposited to form the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ After depositing the N growth layer, (c) The above In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ A first n-type In layer located on the N growth layer ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ an N layer is deposited, and the second In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ A second n-type In layer located on the N growth layer ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ depositing an N layer; (d) the first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a first active region located on the N layer; ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ depositing a second active region overlying the N layer; (e) a first p-type In layer located over the first active region; ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ a second p-type InN layer overlying the second active region; ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ depositing an N layer; the first active region is characterized by a first in-plane lattice constant, a; the second active region is characterized by a second in-plane lattice constant, a; 134. The method of any one of claims 117 to 133, wherein the second in-plane lattice constant a is greater than the first in-plane lattice constant a.

135. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ depositing an N layer and the second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 135. The method of claim 134, wherein depositing the N layer comprises simultaneously depositing.

136. The first n-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ depositing an N layer and the second n-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ 135. The method of claim 134, wherein depositing the N layer comprises independently depositing.

137. 137. The method of any one of claims 134 to 136, wherein depositing the first active region and depositing the second active region comprises simultaneously depositing.

138. 137. The method of any one of claims 134 to 136, wherein depositing the first active region and depositing the second active region comprises independently depositing.

139. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ depositing an N layer and the second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The method of any one of claims 134 to 138, wherein depositing an N layer comprises simultaneously depositing.

140. The first p-type In ｘ１ Al ｙ１ Ga １－ｘ１－ｙ１ depositing an N layer and the second p-type In ｘ２ Al ｙ２ Ga １－ｘ２－ｙ２ The method of any one of claims 134 to 138, wherein depositing an N layer comprises independently depositing.

141. The method of any one of claims 134 to 140, wherein simultaneously depositing comprises depositing using the same deposition conditions.

142. The method of any one of claims 134 to 140, wherein independently depositing comprises depositing using different deposition conditions.

143. A method according to any one of claims 134 to 142, comprising depositing an electrical contact overlying each of the n-type layers.

144. A method according to any one of claims 134 to 143, comprising depositing an electrical contact overlying each of the p-type layers.

145. A semiconductor structure manufactured using the method of any one of claims 116 to 144.

146. A semiconductor wafer comprising the semiconductor structure of any one of claims 1 to 110.

147. A multi-wavelength photovoltaic device comprising a semiconductor structure according to any one of claims 1 to 110.

148. A semiconductor device comprising the photoelectric element of claim 147.

149. 149. A lighting or display system comprising the semiconductor device of claim 148.

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