Chiplet communication using optical communication substrate

Abstract

Disclosed herein is a computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer; an inner interface including a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface including a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, the outer interface at least partially surrounding the inner interface.

Description

[Technical Field]

[0001] The present disclosure relates to chiplet communication using optical communication substrates. [Background technology]

[0002] Computer systems include random access memory (RAM) for storing data and machine code. RAM is typically volatile memory, meaning that stored information is lost when power is removed. In modern implementations, the memory takes the form of integrated circuits. Each integrated circuit contains multiple memory cells. The memory is placed in electrical communication with the processor to allow access to the stored data and machine code. Typically, these electrical communications are implemented as metal traces formed on a substrate on which the memory and processor are placed. Summary of the Invention

[0003] Some embodiments relate to a computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer; an inner interface including a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface including a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, the outer interface at least partially surrounding the inner interface.

[0004] In some embodiments, each port of the first plurality of ports and the second plurality of ports comprises an electrical connection connecting a surface of the electronic die to the interposer and a SerDes coupled to the electrical connection.

[0005] In some embodiments, the SerDes is formed on the electronics die. In some embodiments, the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, and the SerDes couples to the TIA, the modulator driver, or both.

[0006] In some embodiments, at least one port of the outer interface is positioned within 1 mm of the periphery of the electronic die. In some embodiments, at least one port of the inner interface is positioned more than 1 mm away from the outer periphery of the electronic die.

[0007] In some embodiments, the surface of the electronic die is 25 mm 2 ~625mm 2 is. In some embodiments, the interior interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer.

[0008] In some embodiments, the photonic interposer further comprises an off-chip optical coupler, and the photonic network couples the off-chip optical coupler to at least one port of the inner interface.

[0009] In some embodiments, each port of the first plurality of ports and the second plurality of ports includes an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface.

[0010] Some embodiments relate to a computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches, the photonic interposer having a surface configured to bond to an electronic die; and an interface including a two-dimensional array of ports configured to electrically couple the electronic die to the photonic interposer when the electronic die is bonded to the surface of the photonic interposer, the array being arranged with at least three columns and at least three rows of ports.

[0011] In some embodiments, each port of the two-dimensional array comprises an electrical connection configured to connect an electronics die to a surface of the interposer and a SerDes coupled to the electrical connection.

[0012] In some embodiments, the SerDes is formed on the electronics die. In some embodiments, the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, and the SerDes couples to the TIA, the modulator driver, or both.

[0013] In some embodiments, at least one port of the inner interface is positioned more than 1 mm away from the periphery of the electronic die when the electronic die is bonded to the surface of the photonic interposer.

[0014] In some embodiments, the photonic interposer further comprises an off-chip optical coupler, and the photonic network couples the off-chip optical coupler to at least one port of the two-dimensional array.

[0015] In some embodiments, each port of the two-dimensional array includes an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface.

[0016] Some embodiments relate to a method of manufacturing a computing system, comprising: obtaining a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; and bonding an electronic die to the photonic interposer through a surface of the electronic die, wherein the bonding comprises connecting the electronic die to the photonic interposer using: an inner interface including a first plurality of ports that electrically couple the electronic die to the photonic interposer through the surface; and an outer interface including a second plurality of ports that electrically couple the electronic die to the photonic interposer through the surface, the outer interface at least partially surrounding the inner interface.

[0017] In some embodiments, at least one port of the outer interface is positioned within 1 mm of the periphery of the electronic die. In some embodiments, at least one port of the inner interface is positioned more than 1 mm away from the outer periphery of the electronic die.

[0018] In some embodiments, the surface of the electronic die is 25 mm 2 ~625mm 2 is. Some embodiments include a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; and a first electronic die having a first surface bonded to the photonic interposer, the first electronic die having a first inner interface including a first plurality of ports electrically coupling the first electronic die to the photonic interposer; and a first outer interface including a second plurality of ports electrically coupling the first electronic die to the photonic interposer, the first outer interface at least partially surrounding the first inner interface. The present invention relates to a computing system comprising: a second electronic die having a bonded surface, the second electronic die having a second inner interface including a third plurality of ports electrically coupling the second electronic die to a photonic interposer; and a second outer interface including a fourth plurality of ports electrically coupling the second electronic die to the photonic interposer, the second outer interface at least partially surrounding the second inner interface; and an optical network optically coupling at least one port of the first inner interface to at least one port of the second inner interface.

[0019] In some embodiments, each port of the first and second pluralities of ports comprises an electrical connection connecting the first electronics die to the interposer and a SerDes coupled to the electrical connection.

[0020] In some embodiments, the SerDes is formed on the first electronics die. In some embodiments, the at least one port of the first outer interface is positioned within 1 mm of the periphery of the first electronic die.

[0021] In some embodiments, the at least one port of the first inner interface is positioned more than 1 mm away from the outer periphery of the first electronic die. In some embodiments, the interior interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer.

[0022] Various aspects and embodiments of the present application are described with reference to the following figures. It should be understood that the drawings are not necessarily drawn to scale. Items that appear in more than one figure are designated with the same reference numeral in the figures in which they appear. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 illustrates a package containing a die. [Figure 2A] FIG. 1 illustrates a package including multiple dies connected to each other via an interface. [Figure 2B] FIG. 1 illustrates a package containing multiple pluggable optical modules. [Figure 2C] FIG. 1 illustrates a package containing co-packaged optics (CPO) chiplets. [Figure 3] FIG. 1 illustrates a package including a photonic interposer and multiple dies connected to each other, according to some embodiments. [Figure 4A] FIG. 1 illustrates an electronic die mounted on a photonic interposer, according to some embodiments. [Figure 4B] FIG. 1 illustrates multiple ports connecting an electronics die to a photonic interposer according to some embodiments. [Figure 5A] FIG. 4C is a cross-sectional view taken along line AA of FIG. 4B, according to some embodiments. [Figure 5B] 5B illustrates a portion of the cross-sectional view of FIG. 5A in further detail, according to some embodiments. [Figure 5C]5B illustrates a portion of the cross-sectional view of FIG. 5A in further detail, according to some embodiments. [Figure 6] 1 is a cross-sectional view illustrating multiple electronic dies mounted on a common photonic interposer according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present inventors have developed computer architectures that use chip-on-optical silicon solutions (e.g., photonic interposers) to significantly improve the bandwidth of inter-die communication between chiplets. The architectures developed by the inventors and described herein enable electronic dies to communicate with each other from anywhere within the area of ​​the die, without requiring data to pass through from the edge of the die (this is often referred to as the "beachfront limit"), as is the case with some conventional architectures. Thus, these architectures eliminate the inter-die bandwidth limitations that arise from the fact that common input / output (I / O) interfaces are located only near the edge of the die.

[0025] Power and performance improvements in silicon technology are not scaling as quickly as in the past. Currently, there are two approaches to producing high-performance application-specific integrated circuits (ASICs). One approach involves creating larger and larger silicon dies and systems-on-chip (SoCs). Given the on-chip nature of communication channels, larger dies provide greater bandwidth. However, creating larger and larger silicon dies has a serious drawback: large dies have lower manufacturing yields, especially at advanced nodes. This means that of all chips produced, only a small percentage of these are ultimately deployed to customers. This significantly increases manufacturing costs.

[0026] FIG. 1 illustrates an example of a large monolithic electronic die 102. As shown, the die 102 is part of a package 100 and includes multiple logic units (e.g., computational units, memory units, buffer units, etc.). A network of on-chip electrical interconnects 110 enables communication between the various units. In this example, a communication link 112 is established that enables data transmission from a sending logic unit 104 to a receiving logic unit 106. Given the on-chip nature of the interconnects, the bandwidth is relatively large despite the fact that units 104 and 106 are not adjacent. Unfortunately, manufacturing such large die (e.g., using typical ASML reticle sizes) with advanced nodes (e.g., 7 nm) results in low yields, making this approach prohibitively expensive.

[0027] The second approach involves splitting a large die into multiple smaller dies, often called "chiplets," that are interconnected using electronic interposers, substrates, or printed circuit boards. This approach improves manufacturing yields, but is bandwidth-limited in that die-to-die communication channels require significant area and are limited to short distances because otherwise power consumption would be excessive. Die-to-die communication between chiplets is implemented using various 2.5D technologies.

[0028] These technologies are all short-reach technologies and therefore can only communicate from the edge of the transmitting die to the edge of the receiving die. Therefore, die-to-die communication bandwidth is limited by the ports that can fit around the periphery of the die. Because these communication channels pass through large features (e.g., bumps and SerDes), the total communication bandwidth density is typically limited to approximately 400 Gbit / s per mm of die edge. This level of communication density is significantly lower than what can be achieved on-chip. Additionally, this solution requires data to be transferred from the transmitting logic unit to an I / O unit located near the edge of the die before the data can be transferred off-chip. This increases latency, area, and power consumption.

[0029] FIG. 2A shows an example package 200 including smaller electronic dies 202. As in FIG. 1, each die 202 includes multiple logic units, but the dies 202 are significantly smaller than the dies 102. An interface 220, including off-chip electrical interconnects, enables communication between the dies 202. To limit the latency and power consumption associated with the off-chip electrical interconnects, the length of the interface 220 should be limited to 2 cm or less. This means that data can only be transferred from adjacent edges of the dies, thus significantly limiting bandwidth density. The latency and power consumption arise from the presence of parasitic capacitance inherent in the electrical interconnects. In this example, a communication link 212 is established that enables data transmission from a sending logic unit 204 to a receiving logic unit 206. While a portion of the link 212 is on-chip, another portion of the link is off-chip (through the interface 220).

[0030] While optical solutions have been proposed, these solutions do not address the beachfront limitations discussed above. Figure 2B shows a package 200 having an electronic die 202 and a pluggable optical module 240. The pluggable optical module 240 is connected to an optical fiber 242 configured to transfer data between the die 202 and a device external to the package. The pluggable optical module 240 may be configured, for example, as a Small Form Factor Pluggable (SFP) transceiver, a Quadrature Small Form Factor Pluggable (QSFP) transceiver, or a C form-factor pluggable (CFP) transceiver. A set of electrical traces 231 connects the die 202 to the pluggable optical module 240. The traces may be defined on an electronic interposer or other type of substrate on which the die 202 is mounted.

[0031] At relatively high frequencies, the maximum length of trace 231 is determined by signal integrity considerations, as in the example of FIG. 2A. Beyond approximately 2 cm, signal integrity degrades significantly, and therefore the length is limited to approximately 2 cm. As in the example of FIG. 2A, this means that port 230 needs to be positioned near the edge of die 202 adjacent to the pluggable module. If the port were positioned anywhere else within die 202, the length of trace 231 would exceed 2 cm, resulting in errors in the data.

[0032] Solutions based on co-packaged optics (CPO) suffer from similar problems. An example is shown in FIG. 2C. Here, a CPO chiplet 250 is positioned near one of the edges of a die 202. Other CPO chiplets (not shown) may be positioned near other edges of the die 202. The CPO chiplet 250 is connected to a fiber 252. Unlike the pluggable module of FIG. 2B, the CPO chiplet 250 is co-packaged with the die 202. However, the result is nearly the same as in FIG. 2B. The ports in the die 202 need to be positioned near the edge adjacent to the CPO chiplet; otherwise, traces with lengths exceeding 2 cm would be required.

[0033] In summary, each of the chiplet solutions described above (FIGS. 2A-2C) suffers from a beachfront limitation. The architecture described herein uses a photonic interposer to remove this limitation. The photonic interposer enables die-to-die communication in the optical domain. Unlike their electrical counterparts, optical channels are not subject to parasitic capacitance, thereby suppressing the inverse relationship that exists between channel length and signal integrity. As explained in more detail below, removing the beachfront limitation can result in substantial bandwidth increases, in that, in principle, any location within the electronic die can serve as a connection point, not just areas near the edge. In other words, ports can be placed virtually anywhere within the die.

[0034] 3 shows a package having a photonic interposer 301 mounted with a pair of electronic dies 302. The dies 302 may be processors, memories, graphic processing units (GPUs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), among other examples. Each die 302 includes an internal electrical network 310 that couples together the various units (e.g., computational units, memory units, buffer units, etc.) of the respective die.

[0035] The photonic interposer 301 includes an optical network (not shown) with optical waveguides and controllable optical switches. Communication between dies is performed optically through the photonic interposer 301's optical network. Because optical channels (unlike electrical channels) do not experience signal integrity degradation at higher frequencies, the lengths of these optical channels can be significantly longer than the 2 cm limit discussed for electrical connections. This opens up the ability to directly connect any part of a die to any part of another die without first having to pass through the edge of the die. The inventors understand that moving data within a single die is costly in terms of power and latency (the more data that must be sent back and forth, the more congestion can result). When data processed by one die is immediately needed by another die, this approach allows the data to be sent directly to the die that needs it, without having to send it to the edge where I / O units are located in traditional settings. Furthermore, data arriving at the other die can be located in close proximity to the computation, switch, or processing block that needs the data.

[0036] 3, the sending logic unit 304 can transmit data off-chip to the receiving logic unit 306 using a direct optical communication link 312. Link 312 is established using a portion of the optical network of the interposer 301. Because the off-chip data transfer occurs within the photonic interposer, the channel does not necessarily have to pass through a port positioned adjacent to the edge of the die.

[0037] 4A shows an exemplary implementation of an electronic die 302 mounted on a photonic interposer 301. Die 302 has a width W and a length L in the xy plane. Die 302 may be a relatively small chiplet. For example, the length L may be, for example, 5 mm to 60 mm, 5 mm to 55 mm, 5 mm to 50 mm, 5 mm to 45 mm, 5 mm to 40 mm, 5 mm to 35 mm, 5 mm to 30 mm, 5 mm to 25 mm, 5 mm to 20 mm, 5 mm to 15 mm, 5 mm to 10 mm, 10 mm to 60 mm, 10 mm to 55 mm, 10 mm to 50 mm, 10 mm to 45 mm, 10 mm to 40 mm, 10 mm to 35 mm, 10 mm to 30 mm, 10 mm to 25 mm, 10 mm to 20 mm, 10 mm to 15 mm, 15 mm to 60 mm, 15 mm to 55 mm, 15 mm to 50 mm, 15 mm to 45 mm, 15 mm to 40 mm, 15 mm to 35 mm, 15 mm to 30 mm, 15 mm to 25 mm, or 15 mm to 20 mm. The width W may be, for example, 5 mm to 60 mm, 5 mm to 55 mm, 5 mm to 50 mm, 5 mm to 45 mm, 5 mm to 40 mm, 5 mm to 35 mm, 5 mm to 30 mm, 5 mm to 25 mm, 5 mm to 20 mm, 5 mm to 15 mm, 5 mm to 10 mm, 10 mm to 60 mm, 10 mm to 55 mm, 10 mm to 50 mm, 10 mm to 45 mm, 10 mm to 40 mm, 10 mm to 35 mm, 10 mm to 30 mm, 10 mm to 25 mm, 10 mm to 20 mm, 10 mm to 15 mm, 15 mm to 60 mm, 15 mm to 55 mm, 15 mm to 50 mm, 15 mm to 45 mm, 15 mm to 40 mm, 15 mm to 35 mm, 15 mm to 30 mm, 15 mm to 25 mm, or 15 mm to 20 mm. In some embodiments, the surface (W×L) of the die 302 is, for example, 25 mm 2 ~3600mm2 , 100mm 2 ~3600mm 2 , 225mm 2 ~3600mm 2 , 400mm 2 ~3600mm 2 , 625mm 2 ~3600mm 2 , 900mm 2 ~3600mm 2 , 1225mm 2 ~3600mm 2 , 1600mm 2 ~3600mm 2 , 2025mm 2 ~3600mm 2 , 3025mm 2 ~3600mm 2 , 100mm 2 ~1600mm 2 , 225mm 2 ~1600mm 2 , 400mm 2 ~1600mm 2 , 625mm 2 ~1600mm 2 , 900mm 2 ~1600mm 2 , 1225mm 2 ~1600mm 2 , 50mm 2 ~625mm 2 , 100mm 2 ~625mm 2 , 225mm 2 ~625mm 2 , or 400mm 2 ~625mm 2 may be.

[0038] Ports 230 allow die 302 to communicate with the underlying photonic substrate 301 (along the z-axis). As shown in FIG. 4A , ports 230 are not limited to being positioned near the edge of 302. Instead, ports 230 may be positioned substantially anywhere on the surface of die 302. Each port may include a conductive pad formed on the bottom surface of die 302, an inter-chip connection (e.g., a conductive bump, pillar, via, or ball), and another conductive pad formed on the top surface of interposer 301. The inter-chip connection electrically connects the conductive pads to each other. In some embodiments, each port may further include an I / O unit formed on the side of the die, another I / O unit formed on the side of the interposer, and optionally a SerDes.

[0039] An off-chip optical coupler 340 allows for coupling of optical signals between a waveguide formed in the interposer and a fiber 342. The coupler 340 may include, for example, multiple edge couplers and / or multiple grating couplers.

[0040] 4B shows the arrangement of ports in more detail. Ports 230 can be considered to form an outer interface 400 and an inner interface 402. Outer interface 400 is disposed between the periphery 401 of die 302 and inner interface 402. Thus, outer interface 400 can be considered to surround inner interface 402. In some embodiments, outer interface 400 can be considered to partially surround inner interface 402 in that there may be no ports adjacent to one of the edges (or adjacent to more than one edge). Note that the outer interface need not be directly adjacent to the periphery of the die.

[0041] The ports 230 may be organized in a two-dimensional array having rows and columns. In some embodiments, there may be at least three columns and three rows of ports. In some embodiments, the interior interface may span a surface of the die that is at least 20%, at least 30%, at least 40%, or at least 50% of the area of ​​the die surface.

[0042] In some embodiments, each port (or at least one port) of outer interface 400 may be within 1 mm (or, for example, within 0.1 mm, 0.25 mm, 0.5 mm, 0.75 mm, 1.5 mm, 2 mm, or 3 mm) of outer periphery 401. In some embodiments, each port (or at least one port) of inner interface 402 may be more than 1 mm (or, for example, more than 0.1 mm, 0.25 mm, 0.5 mm, 0.75 mm, 1.5 mm, 2 mm, or 3 mm) from outer periphery 401.

[0043] 5A is a cross-sectional view (in the xz plane) taken along line AA of FIG. 4B. As shown, die 302 is mounted on photonic interposer 301. Outer connections 500 are part of outer interface 400, and inner connections 502 are part of inner interface 402. The inner and outer connections may be implemented as conductive bumps, pillars, vias, or balls, and electrically couple the die to the interposer.

[0044] 5B-5C are functional diagrams of a portion of the cross section of FIG. 5A (designated "B" in FIG. 5A) according to two alternative implementations. In the implementation of FIG. 5B, the SerDes is formed on die 302. In the implementation of FIG. 5C, the SerDes is formed on interposer 301. In either implementation, SerDes 501 is used to convert the parallel data stream to a serial data stream for transmission and then convert the received serial data back to parallel data at the receiving end. The serializer portion of the SerDes takes the parallel data, representing multiple bits of data transmitted simultaneously, and converts it back to a serial data stream. This is useful for transmission over bandwidth-limited channels or to simplify the interconnect between different components. At the receiving end, the deserializer takes the serial data stream and converts it back to parallel data. This is useful for extracting the original parallel data from the transmitted serial stream.

[0045] Each logic unit 500 may be a computational unit, a memory unit, a buffer unit, etc., and may be configured to transmit / receive data to / from other units on the die or units on another die. The I / O units 502 and 504 may include circuitry for transmitting and receiving information. For example, either or both I / O units may include a modulator driver and a transimpedance amplifier (TIA). The I / O units may be configured to implement any suitable protocol, including Advanced Interface Bus (AIB), Universal Chiplet Interconnect Express (UCIe), Low-Voltage-In-Package-INTERCONnect (LIPINCON), Bunch of Wires (BoW), etc. The TX / RX 506 includes an optical transceiver that converts data from the electrical domain to the optical domain and vice versa. For example, the TX / RX 506 may include at least one modulator and at least one photodetector. The modulator may be driven by a modulator driver, and the TIA may amplify the signal detected by the photodetector.

[0046] The TX / RX unit 506 couples to a waveguide 510, which couples to a controllable optical switch 512. The controllable optical switch 512 may be controlled to route optical signals to one of several outputs of the switch (although only one output is shown in FIGS. 5B-5C). Having multiple optical switches allows the network to dynamically route data from any logical unit on the die to any other logical unit. The controllable optical switch 512 may be implemented in any suitable manner, including, for example, using a Sach-Zehnder interferometer (MZI), a ring resonator, a disk resonator, and other types of controllable optical devices (e.g., having electrical, thermal, mechanical, or optical control).

[0047] FIG. 6 is a cross-sectional view illustrating a photonic interposer having multiple electronic dies 302 mounted thereon. Each die may have ports arranged in the manner described in connection with FIGS. 4A-4B and 5A-5C. As shown, the architecture illustrated in FIG. 6 removes the beachfront restriction in that any logic unit on one die can communicate directly with any logic unit on another die without first having to internally transfer data to ports positioned at the edge of the die. This is because the logic units in FIG. 6 have direct access to ports positioned within the inner interface 402. The direct communication link 312 uses some of the waveguides and optical switches of the interposer 301.

[0048] Having thus described several aspects and embodiments of the technology of the present application, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. Accordingly, the foregoing embodiments are presented by way of example only, and it should be understood that, within the scope of the appended claims and their equivalents, the embodiments of the present invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is within the scope of the present disclosure, provided that such features, systems, articles, materials, and / or methods are not mutually inconsistent.

[0049] Also, as described, some aspects may be embodied as one or more methods. The actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed that perform actions in an order different from that described, and example embodiments may include performing some actions simultaneously, even though they are shown as sequential actions.

[0050] All definitions defined and used herein should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0051] As used in this specification and the claims, the indefinite articles "a" and "an" should be understood to mean "at least one," unless clearly indicated to the contrary. As used in this specification and claims, the term "and / or" should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.

[0052] As used in this specification and claims, the phrase "at least one," when referring to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed in the list of elements, and not excluding any combinations of elements in the list of elements. This definition also allows for elements other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether related or unrelated to the specifically identified elements, may optionally be present.

[0053] The terms "approximately" and "about" can be used to mean, in some embodiments, within ±20% of a target value, in some embodiments, within ±10% of a target value, in some embodiments, within ±5% of a target value, and even in some embodiments, within ±2% of a target value. The terms "approximately" and "about" can include the target value.

Claims

1. 1. A computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; an electronics die having a surface bonded to the photonic interposer; an inner interface including a first plurality of ports electrically coupling the electronics die to the photonic interposer through the surface; an outer interface including a second plurality of ports electrically coupling the electronics die to the photonic interposer through the surface, the outer interface at least partially surrounding the inner interface.

2. Each port of the first plurality of ports and the second plurality of ports comprises: an electrical connection connecting the surface of the electronic die to the interposer; 10. The computing system of claim 1, further comprising: a SerDes coupled to the electrical connection.

3. The computing system of claim 2 , wherein the SerDes is formed on the electronics die.

4. 4. The computing system of claim 3, wherein the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, and wherein the SerDes couples to the TIA, the modulator driver, or both.

5. The computing system of claim 1 , wherein at least one port of the outer interface is positioned within 1 mm of a periphery of the electronics die.

6. The computing system of claim 5 , wherein at least one port of the inner interface is positioned more than 1 mm from the outer periphery of the electronics die.

7. The surface of the electronic die is 25 mm ２ ~625mm ２ 2. The computing system of claim 1, wherein:

8. The computing system of claim 1 , wherein the interior interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer.

9. The computing system of claim 1 , wherein the photonic interposer further comprises an off-chip optical coupler, and the photonic network couples the off-chip optical coupler to at least one port of the inner interface.

10. 10. The computing system of claim 1, wherein each port of the first plurality of ports and the second plurality of ports includes an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface.

11. 1. A computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches, the photonic interposer having a surface configured to mate with an electronic die; an interface including a two-dimensional array of ports configured to electrically couple the electronic die to the photonic interposer when the electronic die is bonded to the surface of the photonic interposer, the array being arranged in at least three columns and at least three rows of ports.

12. Each port of the two-dimensional array is an electrical connection configured to connect the electronic die to the surface of the interposer; 12. The computing system of claim 11, further comprising: a SerDes coupled to the electrical connection.

13. The computing system of claim 12 , wherein the SerDes is formed on the electronics die.

14. 14. The computing system of claim 13, wherein the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, and wherein the SerDes couples to the TIA, the modulator driver, or both.

15. 12. The computing system of claim 11, wherein at least one port of the inner interface is positioned more than 1 mm away from an outer periphery of the electronic die when the electronic die is bonded to the surface of the photonic interposer.

16. The computing system of claim 11 , wherein the photonic interposer further comprises an off-chip optical coupler, and the photonic network couples the off-chip optical coupler to at least one port of the two-dimensional array.

17. 12. The computing system of claim 11, wherein each port of the two-dimensional array comprises an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface.

18. 1. A method of manufacturing a computing system, comprising: Obtaining a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; bonding the electronic die to the photonic interposer through a surface of the electronic die, the bonding comprising: an inner interface including a first plurality of ports electrically coupling the electronics die to the photonic interposer through the surface; an outer interface including a second plurality of ports that electrically couple the electronic die to the photonic interposer through the surface, the outer interface at least partially surrounding the inner interface; and connecting the electronic die to the photonic interposer using the outer interface.

19. 20. The method of claim 18, wherein the at least one port of the outer interface is positioned within 1 mm of a periphery of the electronics die.

20. 20. The method of claim 19, wherein at least one port of the inner interface is positioned more than 1 mm away from the outer periphery of the electronics die.

21. The surface of the electronic die is 25 mm ２ ~625mm ２ 21. The method of claim 20, wherein:

22. 1. A computing system comprising: a photonic interposer having an optical network including a plurality of waveguides and a plurality of controllable optical switches; a first electronic die having a first surface bonded to the photonic interposer, the first electronic die comprising: a first inner interface including a first plurality of ports electrically coupling the first electronics die to the photonic interposer; a first electronics die having a first outer interface including a second plurality of ports electrically coupling the first electronics die to the photonic interposer, the first outer interface at least partially surrounding the first inner interface; a second electronic die having a surface bonded to the photonic interposer, the second electronic die comprising: a second inner interface including a third plurality of ports electrically coupling the second electronics die to the photonic interposer; a second electronics die having a second outer interface including a fourth plurality of ports electrically coupling the second electronics die to the photonic interposer, the second outer interface at least partially surrounding the second inner interface; The optical network optically couples at least one port of the first internal interface to at least one port of the second internal interface.

23. Each port of the first plurality of ports and the second plurality of ports comprises: an electrical connection connecting the first electronic die to the interposer; 23. The computing system of claim 22, further comprising: a SerDes coupled to the electrical connection.

24. 24. The computing system of claim 23, wherein the SerDes is formed on the first electronics die.

25. 23. The computing system of claim 22, wherein at least one port of the first outer interface is positioned within 1 mm of a periphery of the first electronics die.

26. 26. The computing system of claim 25, wherein at least one port of the first inner interface is positioned more than 1 mm from the outer periphery of the first electronics die.

27. 23. The computing system of claim 22, wherein the interior interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer.

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