Data transmission method, communication device and storage medium

Abstract

A data transmission method, a communication device, and a storage medium, which relate to the field of communication technology and are used to improve error correction performance in communication, include the steps of: performing error correction encoding on a first bit sequence to obtain a second bit sequence; obtaining a third bit sequence to be stored in a ring buffer based on the second bit sequence, wherein a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, and the length of the first subsequence is an integer greater than 0; performing bit selection on the third bit sequence to obtain a rate-matched fourth bit sequence; and transmitting the fourth bit sequence to a second transmission node.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. 202310125012.6, filed on February 9, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present application relates to the technical field of communications, and in particular to a data transmission method, a communication device and a storage medium. [Background technology]

[0003] With the development of industries such as intelligent transportation, smart industrial control, and smart logistics, high performance requirements are required for at least one of data transmission speed, throughput, reliability, and latency when transmitting data between different user devices in wireless communication networks, such as ultra-low latency and ultra-high reliability.

[0004] In order to meet the above-mentioned high performance requirements, the related art uses channel coding to add some redundant information to the data to be transmitted, so that the receiving side can restore the data to be transmitted through this redundant information, and further eliminate some of the distortion that occurs during data transmission, thereby improving the performance of data transmission. However, the above-mentioned method has a relatively small effect of eliminating distortion and cannot further improve the data transmission performance, so that the error correction performance of this method is reduced, and the robustness of the wireless communication network is reduced. Summary of the Invention [Means for solving the problem]

[0005] SUMMARY OF THE INVENTION The embodiments of the present application provide a data transmission method, a communication device, and a storage medium for improving error correction performance in communication.

[0006] In one aspect, a data transmission method is provided, comprising the steps of error correction coding a first bit sequence to obtain a second bit sequence; obtaining a third bit sequence based on the second bit sequence, the third bit sequence being stored in a ring buffer; performing bit selection on the third bit sequence to obtain a fourth bit sequence; and transmitting the fourth bit sequence, wherein a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, wherein a length of the first subsequence is an integer greater than 0.

[0007] In another aspect, there is provided a data transmission method comprising the steps of receiving a fourth bit sequence and error correction decoding the fourth bit sequence based on information of the first sub-sequence, wherein the fourth bit sequence is obtained by performing bit selection on a third bit sequence stored in a ring buffer, a target sub-sequence of the third bit sequence is obtained by interleaving a second sub-sequence of the second bit sequence based on a first sub-sequence of the second bit sequence, and the second bit sequence is obtained by error correction coding the first bit sequence.

[0008] In another aspect, a first transmission node is provided, comprising: an encoding module for error correction encoding a first bit sequence to obtain a second bit sequence, obtaining a third bit sequence based on the second bit sequence to be stored in a ring buffer, and performing bit selection on the third bit sequence to obtain a fourth bit sequence; and a transmitting module for transmitting the fourth bit sequence, wherein a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence.

[0009] In another aspect, a second transmission node is provided, comprising: a receiving module for receiving a fourth bit sequence; and a decoding module for error correction decoding the fourth bit sequence based on information of the first sub-sequence, wherein the fourth bit sequence is obtained by performing bit selection on a third bit sequence stored in a ring buffer, a target sub-sequence of the third bit sequence is obtained by interleaving a second sub-sequence of the second bit sequence based on a first sub-sequence of the second bit sequence, and the second bit sequence is obtained by error correction coding the first bit sequence.

[0010] In yet another aspect, a method includes a memory and a processor, the memory and the processor being coupled, the memory being for storing a computer program, and the processor executing the computer program, The A communication device is provided that implements the data transmission method.

[0011] In yet another aspect, computer program instructions are stored, which, when executed by a computer (e.g., a communication device, a first transmitting node, or a second transmitting node), The A computer-readable storage medium embodying a data transmission method is provided.

[0012] In yet another aspect, when executed by a processor, The A computer program including computer program instructions for implementing a data transmission method. Mu Provided.

[0013] In an embodiment of the present application, data to be transmitted is error-correction coded and redundant information is added to the data to be transmitted, thereby obtaining data to which the redundant information has been added (e.g., a second bit sequence). Furthermore, by interleaving the subsequences of the data to which the redundant information has been added, the data is less likely to be continuously mutated during transmission, thereby improving the error correction performance of communication. [Brief description of the drawing]

[0014] In order to more clearly describe the technical solutions described in the present application, the drawings used in some embodiments of the present application will be briefly described below. Obviously, the drawings described below are only for some embodiments of the present application, and a person skilled in the art can obtain other drawings based on these drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram of a physical model of a communication system according to some embodiments of the present application. [Figure 2] 1 is a flowchart 1 of a data transmission method according to some embodiments of the present application; [Figure 3] FIG. 2 is a schematic diagram of an implementation of cyclic shift-based interleaving according to some embodiments of the present application; [Figure 4] FIG. 2 is a schematic diagram of an implementation of block interleaving according to some embodiments of the present application; [Figure 5] 1 is a schematic diagram 1 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 6] 2 is a schematic diagram 2 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 7] 3 is a schematic diagram 3 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 8] 4 is a schematic diagram 4 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 9] 5 is a schematic diagram 5 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 10] 6 is a schematic diagram 6 of the implementation process of a data transmission method according to some embodiments of the present application; [Figure 11] FIG. 1 is a schematic diagram of one performance analysis scenario according to some embodiments of the present application. [Figure 12]2 is a flowchart 2 of a data transmission method according to some embodiments of the present application; [Figure 13] FIG. 2 is a structural schematic diagram of a first transmission node according to some embodiments of the present application; [Figure 14] FIG. 2 is a structural schematic diagram of a second transmission node according to some embodiments of the present application; [Figure 15] 1 is a structural schematic diagram of a communication device according to some embodiments of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, the technical solutions of the present application will be clearly and completely described with reference to the drawings of the present application, and it is obvious that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments, and all other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without any creative efforts belong to the protection scope of the present application.

[0017] It should be noted that, in this application, terms such as "exemplary" or "for example" are used to illustrate, illustrate, or explain. Any embodiment or design solution described in this application as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or design solutions. Specifically, terms such as "exemplary" or "for example" are used with the intention of presenting related concepts in a concrete format.

[0018] Hereinafter, the terms "first" and "second" are merely for descriptive purposes and do not indicate or suggest relative importance or implicitly specify the number of the indicated technical features. Thus, a feature qualified by "first" or "second" may explicitly or implicitly include one or more of the feature.

[0019] In the description of this application, unless otherwise specified, " / " means "or," for example, A / B can represent A or B. In this specification, "and / or" is simply used to describe the relationship between related objects, and indicates that three types of relationships may exist. For example, "A and / or B" can indicate three situations: only A exists, A and B exist simultaneously, and only B exists. Also, "at least one" means one or more, and "multiple" means two or more.

[0020] As described in the background art, with the development of industries such as intelligent transportation, smart industrial control, and smart logistics, high performance requirements are required for at least one of data transmission speed, throughput, reliability, and delay when transmitting data between different user devices in a wireless communication network, such as ultra-low delay and ultra-high reliability.

[0021] To meet the high performance requirements, the related art uses a data transmission method in which a transmitter channel-codes data to be transmitted to obtain a bit sequence, maps the bit sequence to constellation modulation symbols, and transmits the resulting sequence to a receiver. Correspondingly, a receiver channel-decodes the received constellation modulation symbols to restore the data to be transmitted. In a data transmission channel, the data to be transmitted may be affected by factors such as multipath, noise, and interference, which may cause errors in the data to be transmitted. The transmitter adds some redundant information to the data to be transmitted by performing channel coding, allowing the receiver to restore the data to be transmitted through the redundant information and further eliminate some of the distortion that occurs during data transmission.

[0022] However, the above method has a relatively small effect of eliminating distortion and cannot further improve data transmission performance, which results in a problem that the error correction performance of this method is reduced and the robustness of the wireless communication network is reduced.

[0023] In this regard, the embodiments of the present application propose a data transmission method, the core idea of ​​which is to perform error correction coding on the data to be transmitted and add redundant information to the data to be transmitted, thereby obtaining data with the added redundant information (e.g., a second bit sequence). Furthermore, by interleaving the subsequences of the data with the added redundant information, the data is less likely to be continuously mutated during transmission, thereby improving the error correction performance of communication.

[0024] The following describes application scenarios of the technical solutions according to the embodiments of the present application: Explain Reveal.

[0025] The data transmission method according to the embodiment of the present application can be applied to various communication systems. For example, systems to which the embodiment of the present application can be applied include, but are not limited to, next-generation communication systems such as Long Term Evolution (LTE) systems, various versions based on LTE, fifth-generation (5G) systems, and new radio access technologies (NR). In addition, the data transmission method according to the embodiment of the present application can also be applied to communication technologies that will be developed in the future.

[0026] To explain the solution more clearly, Figure 1 provides a diagram of a physical model of a communication system.

[0027] Referring to FIG. 1, a communication system 100 includes a first transmission node 101 and a second transmission node 102.

[0028] Of these, the first transmission node 101 is the data transmitting or receiving side and is used for transmitting or receiving data. In some embodimentsThe first transmitting node 101 may perform a data transmission method according to an embodiment of the present application. Furthermore, the first transmitting node may be a terminal device, a base station, or another network device. For example, the first transmitting node may include devices referred to by those skilled in the art as a mobile station, a user station, a mobile unit, a user unit, a radio unit, a remote unit, a mobile device, a radio device, a wireless communication device, a remote device, a user device station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a portable device, a user agent, a mobile client, a client, a passive tag (Passive Tap), or other appropriate terms. The first transmitting node may also be a cellular phone, a personal digital assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a tablet computer, a laptop computer, a cordless phone, a wireless local loop (WLL) station, or the like. Various terminal devices may communicate with various types of base stations and network devices (including macro eNBs, small cell eNBs, relay base stations, etc.). The embodiments of the present application are not particularly limited thereto.

[0029] The second transmission node 102 is a data sender or receiver. Similarly, the second transmission node 102 may be a terminal device, a base station, or other network device. ,above The above description of the first transmission node 101 can be referred to, and the description thereof will be omitted here.

[0030] In some embodiments, when the first transmission node 101 is the sender, the second transmission node 102 is the receiver, or when the first transmission node 101 is the receiver, the second transmission node 102 is the sender. Hereinafter, the communication process of the communication system 100 will be described in detail, with the first transmission node 101 as the sender and the second transmission node 102 as the receiver.

[0031] In some examples, the first transmission node 101 may source code, channel code (also called error correction code), and frequency modulate the data to be transmitted before transmitting it to the second transmission node 102. Correspondingly, the second transmission node 102 may perform corresponding demodulation, channel decoding, source decoding, etc. on the received data. Furthermore, after receiving the data, the second transmission node 102 may first perform noise removal or amplification processing, etc. on the received data, thereby obtaining more accurate data and improving communication reliability.

[0032] In some examples, the first transmitting node 101 may support one or more of the following coding schemes when performing channel coding: a Low Density Parity Check Code (LDPC), a Turbo code, a Polar code, or a Convolutional code.

[0033] In some examples, the first transmitting node 101 and the second transmitting node 102 support Hybrid Automatic Repeat Request (HARQ) and may also support Incremental Redundancy (IR) merging.

[0034] In some examples, if the second transmitting node 102 fails to decode, the second transmitting node 102 may store the received data and request a retransmission of the data from the first transmitting node 101. Correspondingly, the first transmitting node 101 may transmit the retransmitted data to the second transmitting node 102 after receiving the retransmission request.

[0035] Furthermore, after receiving the retransmission data, the second transmission node 102 can merge the received retransmission data with the previously received data and then re-decode it. Since the retransmission data includes added redundant bits (bits not included in the initially transmitted data), the retransmission has a certain diversity gain, which reduces the number of retransmissions and thus reduces delays.

[0036] It should be understood that the physical models, system architectures, and scenes of the communication system described in the embodiments of the present application are intended to more clearly explain the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application. Those skilled in the art should understand that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions of the embodiments of the present application can be similarly applied to similar technical problems.

[0037] The following technical solutions of this application are described with reference to the drawings: Explain Reveal.

[0038] FIG. 2 is a flowchart of a data transmission method according to an embodiment of the present application. The method can be performed by the first transmission node, the second transmission node, or other devices with data processing capabilities. Hereinafter, the method will be described by taking the first transmission node as an example. The theory Referring to FIG. 2, the data transmission method is as follows: 、S 101 ~S Including 104.

[0039] In S101, a first bit sequence is error-correction coded to obtain a second bit sequence.

[0040] In some embodiments, the first bit sequence includes at least significant information bits. For example, the first bit sequence may include only significant information bits. As another example, the first bit sequence may include significant information bits and a padding sequence.

[0041] In some embodiments, the valid information bits are determined by the information sequence and a Cyclic Redundancy Check (CRC). parity In some examples, since the information sequence may be encoded into a transmission block during transmission, the effective information bits may be considered to be composed of the transmission block and a CRC. This application is not specifically limited in this regard.

[0042] In some cases, a CRC check is performed on the transmission block to be transmitted. parity A bit sequence to be divided into blocks is obtained by adding a sequence. When dividing a bit sequence to be divided into blocks, if there is only one block, the information sequence is the bit sequence to be divided into blocks. As another example, when dividing a bit sequence to be divided into blocks, if there is one or more blocks, the information sequence is the sub-blocks obtained by dividing the block. Here, the size of the transport block (TBS) is an integer greater than 0, and the CRC check is performed. parity The length of the sequence is an integer greater than 0.

[0043] The first bit sequence may be a bit sequence input to an error correction coding process, and the length of the first bit sequence is an integer greater than 0. The second bit sequence is an output bit sequence that has been error correction coded, and the length of the second bit sequence is an integer greater than 0.

[0044] It should also be understood that error correction coding, also known as channel coding, is the addition of supervisory code elements to the data to be transmitted, which provides error detection or correction capabilities and improves communication reliability.

[0045] In some embodiments, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than one.

[0046] In some embodiments, the error correction coding may include system coding or non-system coding. When the first bit sequence is system coded, the second bit sequence includes a contiguous portion of the first bit sequence.

[0047] For example, 、S 101 is , th The system may be implemented by system-encoding a first bit sequence, calculating redundancy check bits of the first bit sequence, and merging the first bit sequence with the redundancy check bits of the first bit sequence to obtain a second bit sequence. Here, the redundancy check bits (also called check bits) of the first bit sequence can assist a receiving side corresponding to the first transmission node in correcting or detecting errors in the first bit sequence. Furthermore, when system-encoding is used, decoding efficiency at the receiving side corresponding to the first transmission node can be improved.

[0048] In some embodiments, before error correction encoding the first bit sequence, the first bit sequence may be bit padded so that the number of bits in the first bit sequence is equal to the number of system bits that have been error correction encoded.

[0049] In some embodiments, the first transmitting node may error correction code the first bit sequence based on an LDPC code, a turbo code, a polar code, or a convolutional code.

[0050] Among them, LDPC codes are defined by a sparse (or low-density) parity check matrix, and the decoding performance can be improved by iterative decoding such as belief propagation (BP) decoding.

[0051] A turbo code is a parallel cascaded convolutional code in which two or more component codes are connected in parallel, and the output of the turbo code may be a system code. In some embodiments,The turbo code may be a turbo coding method defined in the LTE (Long Term Evolution) system, which includes two-way component codes and system bits, and the coding rate of the parent code is 1 / 3.

[0052] Polar codes are linear block codes proposed based on channel polarization theory. In some embodiments, A polar code is defined by the n-th order Kronecker product of a matrix G, where G is a 2-by-2 matrix. In some embodiments, The matrix G may be written in the following form G=[1 0; 1 1]. In some embodiments In a polar code, each time one information bit is input, a sequence of n0 coded bits may be output, where n is a positive integer. For example, n may be equal to 1, 2, 4, 8, or 16.

[0053] Take LDPC codes as an example. 、S 101 is , Pa The parity check matrix is ​​determined based on a lifting size and a basis matrix, and the first bit sequence is error-correction-encoded to obtain a second bit sequence.

[0054] In some examples, the parity check matrix includes multiple sub-matrix blocks, and each sub-matrix block is a unit matrix or an all-zero square matrix. Each element of the basis matrix corresponds to one sub-matrix block, and the basis matrix includes two types of elements: an element representing a cyclic shift of the unit matrix and an element representing an all-zero square matrix. The lift value indicates the dimension number of the unit matrix and the all-zero square matrix, and is a positive integer.

[0055] In some examples, when the lift value is Z, if an element of the basis matrix is ​​-1, a negative value, an empty value, or null, the sub-matrix block corresponding to the element is an all-zero square matrix of dimension Z*Z. If an element of the basis matrix is ​​0 or greater, the sub-matrix block corresponding to the element is an identity matrix of dimension Z*Z, and the element Number of The value indicates the cyclic shift value of the identity matrix, i.e., the number of bits of the cyclic shift of the identity matrix. The cyclic shift value of the identity matrix is ​​usually written as a single integer, and Number of The value directly represents the amount by which the identity matrix should be circularly shifted. Elements of an all-zero square matrix are usually represented by one of the following terms: -1, a negative value, an empty value, or null.

[0056] For example, suppose the basis matrix h0 (2 rows, 3 columns) of the parity check matrix is ​​as follows:

number

[0057] For a lift value of 3, the parity check matrix H corresponding to h0 is as follows:

number

[0058] In some examples, when the dimension of a basis matrix is ​​a*b and the lift value is Z, the dimension of a parity check matrix corresponding to the basis matrix is ​​a*Z rows and b*Z columns. For example, when the basis matrix has 4 rows and 16 columns and the lift value is 8, the size of the parity check matrix determined based on the basis matrix and the lift value is 4*8 rows and 16*8 columns, that is, 32 rows and 128 columns.

[0059] In some examples, the columns of the parity check matrix include systematic columns and check columns, and the number of systematic columns is equal to the difference between the number of columns and the number of rows of the parity check matrix.For example, in the case of a parity check matrix with a*Z rows and b*Z columns, the number of systematic columns of the parity check matrix is ​​equal to b*Za*Z, that is, bZ-aZ.In the following description, bZ represents b*Z, and aZ represents a*Z.Detailed description thereof is omitted.The length of the first bit sequence is equal to the number of systematic columns of the parity check matrix, that is, bZ-aZ.

[0060] In some examples, the first bit sequence is error correction coded based on a parity check matrix to obtain a second bit sequence, the length of the second bit sequence being equal to the number of columns of the parity check matrix.

[0061] In some examples, the second bit sequence includes a system bit sequence and parity It contains a bit sequence.

[0062] In some examples, the systematic bit sequence of the second bit sequence encoded based on the parity check matrix corresponds to a systematic column of the parity check matrix, and parity The bit sequence is the parity check matrix parity corresponds to a column.

[0063] For example, when the parity check matrix H=[Hs, Hp], the matrix formed by the systematic column is Hs, and the matrix formed by the check column is Hp. The second bit sequence generated based on the parity check matrix is ​​C=[S; P], where S is the system bit sequence, and all bits in S may be called system bits. P is parityis a bit sequence, and all bits in P may be called check bits. Then, according to the error correction coding rules, H×C=0 is satisfied. Here, the 0 is an all-zero vector with length H and number of rows, so H×C=[Hs,Hp]×[S;P]=Hs×S+Hp×P=0. The system bit sequence of the second bit sequence corresponds to the systematic column of the parity check matrix, and the system bit sequence of the second bit sequence corresponds to the systematic column of the parity check matrix. parity It can be seen that the bit sequence corresponds to the check sequence of the parity check matrix. In one example, the first bit sequence is the system bit sequence.

[0064] In some examples, for a parity check matrix with a size of aZ rows and bZ columns, the parity check matrix may correspond to a basis matrix with a size of a rows and b columns. The lift value is Z, and the systematic columns of the parity check matrix are composed of the leading bZ-aZ columns, and the corresponding indices of the systematic columns may be {0, 1, 2, ..., bZ-aZ-1}. The check columns of the parity check matrix are composed of the trailing aZ columns, and the corresponding indices of the check columns may be {bZ-aZ, bZ-aZ+1, ..., bZ-1}. For example, if the lift value is Z=11 and the dimension of the basis matrix is ​​42 rows and 52 columns, a parity check matrix with a length of 462 rows and 572 columns can be determined based on the lift value and the basis matrix. In this 462-by-572 parity check matrix, the indices of the systematic columns are {0, 1, ..., 109}, and the indices of the check columns are {110, 111, ..., 571}. Correspondingly, in the second bit sequence after error correction coding, the indices of the system bit sequence are {0, 1, ..., 109}, parity The bit sequence indices are {110, 111, ..., 571}.

[0065] In some examples, the parity check matrix, the first bit sequence, and the second bit sequence satisfy the relationship H×C=0, C=[S;P], V∈S, where H represents the parity check matrix, C represents the second bit sequence, V represents the first bit sequence, S represents the system bit sequence of the second bit sequence, and P represents the system bit sequence of the second bit sequence. parityrepresents a bit sequence, where a first bit sequence V is a subset of a system bit sequence S of a second bit sequence C. The length of the first bit sequence is equal to the length of the system bit sequence.

[0066] In some examples, the first bit sequence is determined based on a transmission block. for example The transmission block is divided into blocks to obtain an information sequence. The first bit sequence is the information sequence and CRC parity Here, the transport block size (TBS) may be referred to as the length of the transport block, and the transport block size is an integer greater than 0, and the CRC parity The length of the sequence is an integer greater than 0.

[0067] where: One example In the above, the size of a transmission block is a positive integer smaller than T1, where T1 is an integer equal to or greater than 64. Example In this case, T1 may be equal to 64, 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 624, 1024, or 2048. That is, when the size of the transmission block is small, applying this data processing method can achieve good data transmission reliability gain.

[0068] one In the embodiment, the length of the first bit sequence is smaller than T2, where T2 is an integer greater than or equal to 64. Example In the above, T2 may be equal to 64, 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 560, 624, 640, 1024, or 2048.

[0069] In S102, a third bit sequence to be stored in the ring buffer is obtained based on the second bit sequence, and a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence.

[0070] For ease of understanding, S Explain related concepts related to 102.

[0071] 1. First subsequence

[0072] (1) Contents of the first sub-series

[0073] In some embodiments, the first subsequence consists of one or more consecutive bits in the second bit sequence, i.e., the first subsequence is a consecutive subsequence in the second bit sequence.

[0074] It should be understood that when the first subsequences are consecutive subsequences in the second bit sequence, interleaving the second subsequences based on the first subsequences allows the first subsequences to be quickly determined from the second bit sequence, eliminating the need for excessive addressing, and improving data processing efficiency.Furthermore, at the receiving end corresponding to the first transmitting node, the decoding process at the receiving end can be simplified, improving data processing efficiency.

[0075] In some embodiments, the first sub-sequence is the same as one sub-sequence in the first bit sequence, ie, the first bit sequence includes the first sub-sequence.

[0076] In some embodiments, the first sub-sequence does not include padding bits. Illustratively, if padding bits are present in the first bit sequence, the first sub-sequence does not include padding bits.

[0077] In some embodiments, the first subsequence does not include system puncture bits, which are system bits in a code word output to error correction coding that are never transmitted in the transmitted data. In some examples, in an error correction coded code word, all system puncture bits may constitute the system puncture sequence.

[0078] for example 、S When the system code is used in 101, the second bit sequence includes the first bit sequence and the Parity Bit Furthermore, one sub-sequence may be extracted from the first bit sequence included in the second bit sequence to be used as the first sub-sequence.

[0079] (2) Length of the first subsequence

[0080] In some embodiments, the length of the first subsequence is an integer greater than zero.

[0081] In some embodiments, the length of the first subsequence is less than the length of the second subsequence.

[0082] In some embodiments, the sum of the length of the first subsequence and the length of the second subsequence is less than or equal to the length of the second bit sequence.

[0083] In some embodiments, the length of the first subsequence is determined based on the length of the first bit sequence. Illustratively, if the length of the first bit sequence is K and the length of the first subsequence is L, the length L of the first subsequence is equal to the integer obtained by taking the logarithm to the base 2 of K and then performing a truncation operation. That is, the length of the first subsequence satisfies the following relationship:

number

[0084] where:

number

[0085] In some embodiments, the length of the first subsequence is determined based on the length of the effective information bits. Illustratively, if the effective information bit length is K' and the length of the first subsequence is L, the length L of the first subsequence is equal to the integer obtained by taking the logarithm to the base 2 of K' and then performing a truncation operation. That is, the length of the first subsequence satisfies the following relationship:

number

[0086] where:

number

[0087] In some embodiments, the length of the first subsequence is determined from the lift value. for example , the length of the first subsequence is:

number

[0088] where d is a positive integer and Z is the lift value, which is an integer greater than 0. d may be equal to 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0089] (3) Index of the first subsequence

[0090] In some embodiments, when the error correction coding uses an LDPC code, the index in the second bit sequence of the first element of the first subsequence is equal to a non-negative integer multiple of the lift value.

[0091] Illustratively, the index in the second bit sequence of the first element of the first subsequence may be equal to 1*Z, 2*Z, 3*Z, 4*Z, 5*Z, 6*Z, or 7*Z, where Z is the lift value.

[0092] for example、S In 101, when error correction coding is performed using an LDPC-based coding scheme, if the lift value is 16, the index of the first element of the first subsequence in the second bit sequence may be 16d, where d is a non-negative integer and 16d is smaller than the length of the second bit sequence. For example, the index of the first element of the first subsequence in the second bit sequence may be 16, 32, 48, ... (and so on). In some embodiments, d may be a preset constant.

[0093] As another example, in step S101, when error correction coding is performed using an LDPC-based coding method, if the parity check matrix is ​​a low-density parity check coding determined from a 4-row, 16-column basis matrix and a lift value of 8, the size of the corresponding parity check matrix will be 4*8 rows, 16*8 columns. Example , the index in the second bit sequence of the first element of the first subsequence is equal to a positive integer multiple of the lift value. For low-density parity-check coding determined from a basis matrix of size 4x16 and a lift value of 8, if the length of the second bit sequence is 16*8=128 bits, the index in the second bit sequence of the first element of the first subsequence may be equal to 2*8=16, 3*8=16, or 4*8=32.

[0094] In some embodiments, when an LDPC code is used in error correction coding, the parity check matrix includes a systematic column and a check column, and each column of the parity check matrix corresponds to an index of the second bit sequence, and the index of the element of the first subsequence in the second bit sequence is equal to the index of the systematic column of the parity check matrix.

[0095] In some examples, the set of indices in the second bit sequence of the elements of the first subsequence is equal to the set of indices of all systematic columns of the parity check matrix or is a subset of the set of indices of all systematic columns of the parity check matrix.

[0096] In some embodiments, the indices of the L elements of the first subsequence in the second bit sequence are the indices of the L columns in the parity check matrix that have the smallest column weights, where L is the length of the first subsequence and is a positive integer. Here, the column weight is used to represent the number of ones in a column. For example, if the number of ones in the first column of the parity check matrix is ​​2, the column weight of the first column is 2. As a further example, if the number of ones in the fourth column of the parity check matrix is ​​3, the column weight of the fourth column is 3.

[0097] In some other embodiments, the indices in the second bit sequence of the L elements of the first subsequence are the indices of the L systematic columns with the smallest column weights in the parity check matrix, where L is the length of the first subsequence and is a positive integer.

[0098] (4) Method for determining the first subsequence

[0099] In some embodiments, the first subsequence is determined based on one or more of the second bit sequence, the length of the predetermined fourth bit sequence, the length of the first bit sequence, the effective information bit length, the modulation order, the coding rate, the number of resources, the higher layer signaling, the type of user device, and the size of the transmission block.

[0100] Based on this, both the receiving side and the transmitting side (e.g., the first transmitting node and the receiving side corresponding to the first transmitting node) can identify the position and length of the first subsequence in the second bit sequence, so that the transmitting side (e.g., the first transmitting node) can extract the first subsequence and interleave the second subsequence based on the first subsequence, which makes the decoding process at the receiving side convenient and improves the receiving and processing efficiency.

[0101] In some embodiments, the first subsequence is determined from the second bit sequence based on the index in the second bit sequence of the first element of the first subsequence and the length of the first subsequence. Illustratively, if the index in the second bit sequence of the first element of the first subsequence is v and the length of the first subsequence is L, the first subsequence can be obtained by extracting the vth to v+L-1th elements from the second bit sequence.

[0102] In some embodiments, the indices of the L elements of the first subsequence in the second bit sequence are determined based on the column weights of the parity check matrix. For example, taking a parity check matrix with a matrix size of 60 rows and 120 columns, the column indices of columns with a column weight of 2 in the parity check matrix range from 64 to 119, the column indices of columns with a column weight of 3 in the parity check matrix range from 32 to 63, the column indices of columns with a column weight of 5 in the parity check matrix range from 20 to 31, and the column indices of columns with a column weight of 6 in the parity check matrix range from 0 to 19. The indices of the L columns with the lightest column weights in the parity check matrix are used as the indices of the L elements of the first subsequence in the second bit sequence. When L is 4, the index sequence of the L elements of the first subsequence in the second bit sequence may be determined to be {64, 65, 66, 67}. Alternatively, for example, the indices of the L columns with the heaviest column weights in the parity check matrix are used as the indices of the L elements of the first subsequence in the second bit sequence. If L is 5, the index sequence in the second bit sequence of the L elements of the first subsequence may be determined to be {0, 1, 2, 3, 4}.

[0103] In one embodiment, a base graph ) A parity check matrix is ​​determined based on the first bit sequence, and then the first bit sequence is error-correction-encoded to obtain a second bit sequence. Hu is Second Basic Graph Fu be.

[0104] In some instances, the basic graph Fu There are two basic graphics centre( For example, the first basic graph Fuo and the second basic graph centre) where the first basic graph Fu The size of the corresponding basis matrix is ​​46 rows and 68 columns, and the second basic graph Fu The size of the corresponding basis matrix is ​​42 rows and 52 columns. If at least one of the following conditions 1 to 3 is satisfied, the second basis graph is Fu Condition 1: The size of the transmission block is 292 or less; Condition 2: The size of the transmission block is 3824 or less and the coding rate is less than 0.67; Condition 3: The coding rate is less than 0.25. If none of the above conditions 1 to 3 are met, the first basic graph is used. Fu The parity check matrix is ​​determined based on the Example So, the first basic graph Fu The corresponding basis matrix and second basis graph Fu The corresponding basis matrix is ​​the basis matrix defined in 3GPP (registered trademark) standard protocol 38.212. Fu There are more types of basic graphs Fu It should be understood that the present application does not make any specific limitations in this regard.

[0105] In one example, the basic graph Fu Second Basic Graph Fu In some cases, the length of the first subsequence is greater than 0. Fu First basic graph Fu In some cases, the length of the first subsequence is equal to 0. When the length of the first subsequence is equal to 0, the target subsequence of the third bit sequence is simply equal to the second subsequence of the second bit sequence, and no interleaving is required.

[0106] In one embodiment, the number of rows in the basis matrix is ​​less than or equal to a predetermined threshold number of rows, or the number of columns in the basis matrix is ​​less than or equal to a predetermined threshold number of columns, or the number of systematic columns in the basis matrix is ​​less than or equal to a predetermined threshold number of systematic columns, or the number of encoded systematic columns is less than or equal to a fifth threshold, where the number of systematic columns in the basis matrix is ​​equal to the difference between the number of columns and the number of rows in the basis matrix, and the number of encoded systematic columns is a positive integer not exceeding the number of systematic columns in the basis matrix and is used to calculate the lift value.

[0107] In one embodiment, the lift value is less than or equal to a preset threshold lift value, where the preset threshold lift value may be equal to 32, 48, 56, 64, 72, 80, 88, 96, 104, or 128.

[0108] For example, the preset threshold for the number of rows may be 42, and the preset threshold for the number of columns may be 52. In this case, the base matrix may be the second base graph. Fu The predetermined threshold for the number of systematic columns may be equal to 10, and the fifth threshold may be equal to any of 6, 8, 9, and 10. For example, the fifth threshold is equal to 6, or the fifth threshold is equal to 8, or the fifth threshold is equal to 9.

[0109] For example, if the index of the first element of the first subsequence in the second bit sequence is 6 and the length of the first subsequence is 10, the bit sequence consisting of bits in the second bit sequence with index 6 to bit with index 15 may be determined as the first subsequence.

[0110] 2. Second subseries

[0111] (1) Contents of the second subseries

[0112] In some embodiments, the second subsequence consists of one or more consecutive bits of the second bit sequence, i.e., the second subsequence is a consecutive subsequence of the second bit sequence.

[0113] It should be understood that when the second subsequence is a consecutive subsequence of the second bit sequence, interleaving the second subsequence based on the first subsequence can quickly determine the second subsequence from the second bit sequence without requiring excessive addressing, thereby improving data processing efficiency. Also, for the receiving side corresponding to the first transmitting node, the decoding process on the receiving side can be simplified, thereby improving data processing efficiency.

[0114] In some embodiments, the second sub-sequence does not include padding bits. Illustratively, if padding bits are present in the first bit sequence, the second sub-sequence does not include padding bits.

[0115] In some embodiments, the second subsequence does not include system puncture bits. System puncture bits are system bits that are not always transmitted in the transmitted data in the codeword output to the error correction coding. In some examples, all system puncture bits in the codeword in the error correction coding can constitute the system puncture sequence.

[0116] (2) Length of the second subsequence

[0117] In some embodiments, the length of the second subsequence is an integer greater than one.

[0118] In some embodiments, the sum of the length of the first subsequence and the length of the second subsequence is less than or equal to the length of the second bit sequence.

[0119] In some embodiments, the length of the second subsequence is equal to the length of the first bit sequence. 、SWhen the system code is used in 101, the second bit sequence includes the first bit sequence and the Parity Bit When the first bit sequence included in the second bit sequence is determined as the second sub-sequence, the length of the second sub-sequence is equal to the length of the first bit sequence.

[0120] In some other embodiments, the length of the second subsequence is less than the length of the first bit sequence. 、S When the system code is used in 101, the second bit sequence includes the first bit sequence and the Parity Bit When a subsequence of the first bit sequence included in the second bit sequence is determined as the second subsequence, the length of the second subsequence is shorter than the length of the first bit sequence. 、S When a non-system code is used in 101, a subsequence having a length shorter than that of the first bit sequence may be extracted from the second bit sequence as the second subsequence, where the length of the second subsequence is shorter than that of the first bit sequence.

[0121] It should be understood that if the length of the second subsequence is less than or equal to the length of the first bit sequence, the bit selection process can ensure that the second subsequence is included in the fourth bit sequence after bit selection, thereby ensuring the block error rate (BLER) performance of the initially transmitted data.

[0122] In some further embodiments, the length of the second subsequence is greater than the length of the first bit sequence. For example, 、S When a system code is used to perform error correction coding in 101, the second subsequence includes the first bit sequence and the first bit sequence. Parity Bit It may include part or all of the series. 、SWhen a non-system code is used in error correction coding in 101, a subsequence having a length greater than that of the first bit sequence may be extracted from the second bit sequence as the second subsequence, where the length of the second subsequence is greater than that of the first bit sequence.

[0123] It should be understood that if the length of the second subsequence is greater than the length of the first bit sequence, the transmission coding rate when the first transmission node transmits data can be improved, and thus the decoding efficiency of the receiving side corresponding to the first transmission node can be improved.

[0124] In some embodiments, the length of the second subsequence does not exceed the value obtained by subtracting the length of the first subsequence from the length of the second bit sequence. For example, if the second bit sequence includes only the first and second subsequences, the length of the second subsequence is equal to the value obtained by subtracting the length of the first subsequence from the length of the second bit sequence. As another example, if the second bit sequence includes the first subsequence, the second subsequence, and other sequences, the length of the second subsequence is less than the value obtained by subtracting the length of the first subsequence from the length of the second bit sequence.

[0125] In some embodiments, the length of the second sub-sequence is determined based on the lift value. for example , the length of the second subsequence is equal to d·Z, where d is a positive integer and Z is a lift value, which is an integer greater than 0. d may be equal to 1, 2, 3, 4, 5, or 6.

[0126] In some embodiments, the length of the second subsequence is determined based on at least one of the length of the first subsequence, the length of the second bit sequence, the length of the first bit sequence, the length of the useful information bits, the number of columns of the basis matrix, the lift value, or the length of the system puncture sequence, where the number of columns of the basis matrix, the lift value, and the length of the system puncture sequence are all integers greater than 0. , decided For the determination method, the following explanations of Examples 1 to 13 may be referred to.

[0127] In some embodiments, the length of the second subsequence is determined based on the parameters of the length of the first subsequence and a coding rate, where the coding rate is a real number greater than 0.8 and less than 1. In one example, the coding rate is equal to the highest target coding rate indicated in a Modulation and Coding Scheme (MCS) table. The coding rate may be equal to the maximum target coding rate in a currently used MCS table indicated by higher layer signaling. In another example, the coding rate may be equal to the maximum of the maximum target coding rates in all MCS tables. In another example, the coding rate is equal to at least any of 948 / 1024, 772 / 1024, or 0.95.

[0128] one Example Then, the length of the second subsequence is determined based on the following formula: f(K / R0), where K is the length of the first subsequence, R0 is the code rate, and the function f(x) represents rounding to the nearest integer using a truncation, raise, or rounding operation for the real number x.

[0129] In some embodiments, the length of the second subsequence is determined based on a parameter called a lift value, where the lift value is an integer greater than 0. Example In the example, the length of the second subsequence is equal to Z*d, where Z is a lift value and d is an integer greater than 0. In one example, d is greater than a parameter kb for LDPC coding. Here, kb is equal to or less than the number of systematic columns of the basis matrix, and the number of columns of the systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix. In one example, the number of columns of the systematic columns of the basis matrix is ​​equal to 10, and kb is determined based on the size of the transmission block TBS. For example, if TBS is equal to or less than 192, kb is equal to 6. If TBS is greater than 192 and less than or equal to 560, kb is equal to 8. If TBS is greater than 560 and less than or equal to 640, kb is equal to 9. If TBS is greater than 640, kb is equal to 10. Next, a lift value is determined based on the parameter kb. ExampleIn the above, d is equal to any one of kb, kb+1, kb+2, kb+3, and kb+4.

[0130] (3) Index of the second subsequence

[0131] In some embodiments, the indices of the elements of the second subsequence in the second bit sequence are different from the indices of the elements of the first subsequence in the second bit sequence, i.e., the intersection of the set of indices of each element of the first subsequence in the second bit sequence and the set of indices of each element of the second subsequence in the second bit sequence is the empty set.

[0132] For example, the index set of the indexes in the second bit sequence of each element of the first subsequence is [0,1,2,3,4,5], i.e., the first subsequence occupies the 0th to 5th bits of the second bit sequence. Then, the index set of the indexes in the second bit sequence of each element of the second subsequence does not include any index in [0,1,2,3,4,5]. For example, the index set of the indexes in the second bit sequence of each element of the second subsequence may be [6,7,8,...,63], i.e., the second subsequence occupies the 6th to 63rd bits of the second bit sequence. As can be seen, the intersection of the index set [6,7,8,...,63] and the index set [0,1,2,3,4,5] is the empty set. Here, each index element in the index set Number of It should be understood that the values ​​are merely exemplary and the embodiments of the present application are not particularly limited thereto.

[0133] (4) Method for determining the second subsequence

[0134] In some embodiments, the second subsequence is determined from the second bit sequence based on an index in the second bit sequence of a first element of the second subsequence and a length of the second subsequence.

[0135] In some embodiments, the index in the second bit sequence of the first element of the second subsequence may be determined based on the lift value. Example Then, the index in the second bit sequence of the first element of the second subsequence may be equal to d*Z, where d is a positive integer and Z is the lift value.

[0136] In some embodiments, the index in the second bit sequence of the first element of the second subsequence may be determined based on the lift value and the length of the second subsequence. Example Then, the index in the second bit sequence of the first element of the second subsequence may be equal to d*Z+L, where d is a positive integer, Z is the lift value, and L is the length of the second subsequence.

[0137] In some embodiments, the length of the second subsequence is equal to Z, and the index in the second bit sequence of the first element of the second subsequence is equal to d*Z, where d is a non-negative integer and Z is a lift value.

[0138] In some embodiments, the length of the second subsequence is equal to d1*Z, and the index in the second bit sequence of the first element of the second subsequence is equal to d2*Z, where d1 is a positive integer, d2 is a non-negative integer, and Z is a lift value, where d1 may be equal to 1, 2, 3, 4, or 5, and d2 may be equal to 0, 1, 2, 3, 4, or 5.

[0139] 3. Third bit sequence

[0140] (1) Contents of the third bit sequence

[0141] In some embodiments, the third bit sequence includes a target sub-sequence.

[0142] In some embodiments, the third bit sequence includes the first sub-sequence. In this way, if the third bit sequence includes the first sub-sequence, S 10 3 Therefore, the receiver can easily determine the first subsequence directly, which makes the decoding process more convenient.

[0143] In some embodiments In this way, the third bit sequence does not include the first sub-sequence. Not yet In this case, the transmission coding rate during data transmission can be improved, and communication efficiency can be improved as well.

[0144] The third bit sequence may also include other types of sequences, such as a padding sequence or a system puncture sequence.

[0145] (2) Length of the third bit sequence

[0146] In some embodiments, the length of the third bit sequence is determined based on the length of the first sub-sequence.

[0147] In some embodiments, the length of the third bit sequence is equal to the length of the second bit sequence minus the length of the first sub-sequence.

[0148] In some embodiments, the length of the third bit sequence is less than the length of the second bit sequence minus the length of the first subsequence. For example, if the third bit sequence does not include the first subsequence and the padding sequence, the length of the third bit sequence may be less than the length of the second bit sequence minus the length of the first subsequence.

[0149] In some embodiments, the length of the third bit sequence is equal to the length of the second bit sequence. For example, if the third bit sequence includes the first subsequence and the padding sequence, the length of the third bit sequence may be equal to the length of the second bit sequence.

[0150] In some embodiments, the length of the third bit sequence is not less than the sum of the lengths of the first and second subsequences. For example, if the third bit sequence includes only the first and second subsequences, the length of the third bit sequence is equal to the sum of the lengths of the first and second subsequences. As another example, the third bit sequence may include the first subsequence, the second subsequence, and other sequences (e.g., system puncture sequences, padding sequences, or sequences of the first bit sequence). Parity Bit When the third bit sequence is included, the length of the third bit sequence is greater than the sum of the lengths of the first and second subsequences.

[0151] In some embodiments, when the error correction coding is LDPC coding, the length of the third bit sequence is equal to the length of the second bit sequence minus the length of the first subsequence minus sZ, where s is a non-negative integer and Z is a lift value of a parity check matrix used for the LDPC coding. In some examples, s is equal to 0, 1, or 2.

[0152] In some embodiments, when the error correction coding is LDPC coding, the length of the third bit sequence is equal to the length of the second bit sequence minus sZ, where s is a non-negative integer and Z is a lift value of a parity check matrix used for the LDPC coding. In some examples, s is equal to 0, 1, or 2.

[0153] 4. Target subseries

[0154] (1) Contents of the target subseries

[0155] The target subsequence is a sequence obtained by interleaving the second subsequence of the second bit sequence based on the first subsequence of the second bit sequence.

[0156] In some embodiments, the target sub-sequence consists of one or more consecutive bits in the third bit sequence, i.e., the target sub-sequence is a consecutive sub-sequence in the third bit sequence.

[0157] It should be understood that when the target subsequence is a consecutive subsequence in the third bit sequence, the receiving side (e.g., the receiving side corresponding to the first transmission node) can quickly determine the target subsequence from the third bit sequence, without requiring excessive addressing processing, which can simplify the decoding processing process of the receiving side and ultimately improve data processing efficiency.

[0158] (2) Length of the target subsequence

[0159] In some embodiments, the length of the target subsequence is less than the length of the third bit sequence.

[0160] In some embodiments, the length of the target subsequence is equal to the length of the second subsequence.

[0161] (3) Target subsequence position

[0162] In some embodiments, the target subsequence is located at the beginning of the third bit sequence. Based on this, the first transmitting node includes as many target subsequences as possible in the initial transmission data. It should be understood that including as many target subsequences of the third bit sequence as possible in the initial transmission data can improve data transmission performance during the initial transmission and also makes it easier for the receiving side to perform retransmission processing if the initial transmission data is lost.

[0163] In some embodiments, the position of the first element of the target subsequence in the third bit sequence is equal to the start position corresponding to the redundancy version (RV) with index 0. In this way, the target subsequence can be positioned at the beginning of the third bit sequence. Example , the position in the third bit sequence of the first element of the target subsequence is equal to 0, and the starting position corresponding to the redundancy version with index 0 is also equal to 0.

[0164] (4) How to determine the target subsequence

[0165] In some embodiments, the target sub-sequence of the third bit sequence is obtained by interleaving a second sub-sequence of the second bit sequence based on an interleaving index sequence corresponding to the first sub-sequence.

[0166] 5. Interleaving

[0167] In some embodiments, the interleaving includes one or more of circular interleaving, interleaving based on an interleave index sequence, or block interleaving.

[0168] For ease of understanding, several interleaving methods according to embodiments of the present application are briefly described below.

[0169] (1) Cyclic interleaving

[0170] The cyclic interleaving process includes at least one of left cyclic shift interleaving, right cyclic shift interleaving, upper cyclic shift interleaving, and lower cyclic shift interleaving. Typically, the left cyclic shift interleaving and right cyclic shift interleaving correspond to row vector sequences (i.e., sequences in which elements are arranged along rows), and the upper cyclic shift interleaving and lower cyclic shift interleaving correspond to column vector sequences (i.e., sequences in which elements are arranged along columns).

[0171] In some embodiments, if the interleaving process is a circular interleaving process, interleaving a second sub-sequence based on the first sub-sequence to obtain a target sub-sequence may be performed. , th The binary sequence corresponding to the subsequence of 1s is converted into a decimal integer S representing the number of shift bits, and the second subsequence is cyclically shifted based on the integer S to obtain an interleaved sequence. In some examples, interleaving the second subsequence based on the integer S can be implemented as follows: , th It is implemented as cyclically shifting two subsequences to the left by S bits, or cyclically shifting the second subsequence to the right by S bits, where S is a non-negative integer.

[0172] In some embodiments, a second bit sequence is obtained by error correction encoding a first bit sequence based on a parity check matrix, where the parity check matrix is ​​determined based on a lift value and a basis matrix. The interleaving process includes cyclic shift interleaving Z bits in the second subsequence based on the first subsequence. Here, an index in the second bit sequence of a first element of the Z bits in the second subsequence may be equal to c*Z, where c is a non-negative integer and z is the lift value. Alternatively, the cyclic interleaving process includes cyclic shift interleaving each of a plurality of bit groups in the second subsequence based on the first subsequence, where the length of each bit group is equal to Z and the index in the second bit sequence of a first element of each bit group is equal to a non-negative integer multiple of the lift value, where Z is the lift value. In one example, each of d1 bit groups in the second subsequence is cyclic shift interleaved based on the first subsequence. If the length of each bit group is equal to Z and the integer corresponding to the first subsequence is S, the number of bits of cyclic shift interleaving performed on the i-th bit group among the d1 bit groups is mod(floor(S / (Z i )),Z). Here, mod(x1,x2) represents the remainder operation, for example, mod(11,8)=3, and floor( x)represents the rounding down operation for a real number x, for example, floor(2.6)=2, and x1 x2 represents x2 of x1, for example, 7 2 = 49. Because cyclic shift interleaving is performed only within each bit group, the interleaving network in error correction decoding can be multiplexed during decoding, reducing the complexity of decoding.

[0173] For example, if the number of bits in first subsequence 210 is 5, the corresponding integer for first subsequence [1 0 1 1 1] is 23. As shown in FIG. 3, when the left bit is the most significant bit and the right bit is the least significant bit, for second subsequence 220 having 58 bits, if a left cyclic shift is performed based on first subsequence [1 0 1 1 1], the 23rd bit of the second subsequence is the 0th bit of target subsequence 310 obtained after interleaving, and the 24th bit of the second subsequence is the 1st bit of target subsequence 310 obtained after interleaving. Similar analogies are used, and further explanations are omitted.

[0174] (2) Interleaving based on the interleave index sequence

[0175] In some embodiments, the index of an element in the interleaving index sequence corresponds to the first bit to be interleaved in the second subsequence, and the value of an element in the interleaving index sequence corresponds to the second bit that needs to be interleaved with the first bit in the target subsequence. The interleaving index sequence is used to exchange the values ​​of elements in corresponding positions in the second subsequence and the target subsequence. The interleaving index sequence is used to identify subscripts in the pre-interleaving sequence (e.g., the second subsequence) for all elements in the interleaved sequence (e.g., the target subsequence). For example, F=F(A), where F is the target subsequence, F is the second subsequence, and A is the interleaving index sequence, i.e., the ith element of F is equal to the A(i)th element of F, where i is an integer from 0 to w−1, and w is the length of the second subsequence F.

[0176] For example, the second subsequence includes [a1, a2, a3, a4], where the index of a1 in the second bit sequence is 0, the index of a2 in the second bit sequence is 1, the index of a3 in the second bit sequence is 2, and the index of a4 in the second bit sequence is 3, and the interleaved index sequence corresponding to the first subsequence is [3, 2, 0, 1], then the element with index 3 in the second subsequence is set to the element with index 0 in the target subsequence, the element with index 2 in the second subsequence is set to the element with index 1 in the target subsequence, the element with index 0 in the second subsequence is set to the element with index 2 in the target subsequence, and the element with index 1 in the second subsequence is set to the element with index 3 in the target subsequence, and the target subsequence becomes [a4, a3, a1, a2].

[0177] In some examples, two interleaving index sequences corresponding to any two different first sub-sequences, respectively, are different.

[0178] In some examples, two interleaved index sequences corresponding to any two different first subsequences, respectively, have at most T elements with the same value at the same position, where T is a positive integer. In some examples, T is 1, 2, 3, 4, or 5. In some examples, T is less than a first threshold.

[0179] In some examples, in two interleaved index sequences corresponding to any two different first subsequences, the percentage of elements having the same element value at the same position is at most W%, where W is a real number greater than 0 and less than 20. In some examples, W is 1, 2, 3, 4, or 5. For example, if W is 1 and the length of the interleaved index sequences is 128, in any two interleaved index sequences, at most two index positions have the same elements, i.e., T is 2. In some examples, W is less than a second threshold.

[0180] In addition, if there are many elements with the same value at the same position in multiple interleaved index sequences, a problem called "codeword approximation" may occur. That is, the interleaved sequences output corresponding to different second bit sequences may be exactly the same, which may result in incorrect decoding or errors in the decoding process on the receiving side. Therefore, if T is smaller than the first threshold or W is smaller than the second threshold, the number of elements with the same value at the same position can be limited, thereby improving the decoding efficiency on the corresponding receiving side.

[0181] (3) Block interleaving

[0182] The block interleaving process includes at least one of writing row by row and reading column by column, and writing column by column and reading row by row. As shown in FIG. 4, the block interleaving process line Write down each columnWhen block interleaving is performed by writing to each column and reading to each row, the first transmission node writes to each column in the direction indicated by the arrow in Fig. 4(1) and reads to each row in the direction indicated by the arrow in Fig. 4(2). When block interleaving is performed by writing to each column and reading to each row in the direction indicated by the arrow in Fig. 4(2), the first transmission node writes to each column in the direction indicated by the arrow in Fig. 4(2) and reads to each row in the direction indicated by the arrow in Fig. 4(1).

[0183] In some examples, when the length of the second bit sequence is large, the number of rows or columns of the block interleaving is determined by the length of the second subsequence.

[0184] In some examples, the difference between the number of rows and the number of columns of the block interleave is less than or equal to 1. The number of rows of the block interleave is the number of rows of the matrix written in the block interleave process, and the number of columns of the block interleave is the number of columns of the matrix written. Hereinafter, the explanation thereof will be omitted.

[0185] In some examples, where the number of rows in the block interleave is r and the number of columns is c, the number of rows in the block interleave r is equal to the integer obtained by taking the logarithm to the base 2 of the length of the second subsequence and then performing a truncation operation. That is, the number of rows in the block interleave r satisfies the following relationship:

number

[0186] Furthermore, if the length of the second subsequence is d, the number of columns in the block interleave is the smallest integer that is not less than the real number obtained by dividing the length of the second subsequence d by the number of rows in the block interleave, i.e., the number of columns in the block interleave, c, satisfies the following relationship:

number

[0187] In some other examples, where the number of rows in the block interleave is r and the number of columns is c, the number of columns in the block interleave, c, is equal to the integer obtained by taking the logarithm to the base 2 of the length of the second subsequence and then performing a truncation operation. That is, the number of columns in the block interleave, c, satisfies the following relationship:

number

[0188] Furthermore, if the length of the second subsequence is d, the number of rows in the block interleave is the smallest integer that is not less than the real number obtained by dividing the length of the second subsequence by the number of columns in the block interleave, i.e., the number of rows in the block interleave, r, satisfies the following relationship:

number

[0189] After the block interleaving is completed, the block interleaved sequence is cyclic shift interleaved based on the first subsequence to obtain the target subsequence, that is, interleaving can be achieved by combining multiple interleaving processing methods.

[0190] For example, as shown in Figure 4(3), Figure 4(3) shows an implementation of interleaving processing that combines block interleaving and cyclic shift. The second subsequence 220 first undergoes block interleaving to obtain an intermediate sequence 223, and then cyclic shift interleaves the intermediate sequence based on the first subsequence 210 to obtain a target subsequence 310. The length of the first subsequence in Figure 4(3) is 3, and the corresponding integer value is 3, so the corresponding cyclic shift is 3 bits.

[0191] In S103, bit selection is performed on the third bit sequence to obtain a fourth bit sequence.

[0192] In some embodiments, the length of the fourth bit sequence is greater than the length of the useful information bits. This ensures that the transmission coding rate is a positive real number less than 1, allowing the receiver to correctly decode the raw data (e.g., useful information bits). The transmission coding rate is typically equal to the ratio of the useful information bit length to the length of the fourth bit sequence.

[0193] In some embodiments, the fourth bit sequence does not include the first subsequence, i.e., the first subsequence is transmitted implicitly, which can improve data transmission efficiency and reduce power consumption during transmission.

[0194] In some embodiments 、S 103 is , silly This is realized by performing bit selection on the third bit sequence based on the redundancy version to obtain the fourth bit sequence. For example, the start position for bit selection from the third bit sequence is determined based on the redundancy version. , open The circular selection can be started from the starting position.

[0195] In some examples, the redundancy version includes at least one of a zeroth redundancy version (RV0), a first redundancy version (RV1), a second redundancy version (RV2), and a third redundancy version (RV3). The redundancy version is used to determine a start position for bit selection from the third bit sequence, and bit selection is started from the start position. If the last bit of the third bit sequence is selected, if further bit selection is required, selection is started from the start address of the third bit sequence to obtain a fourth bit sequence.

[0196] In some examples, the starting position corresponding to the zeroth redundancy version (RV0) is 0, the starting position corresponding to the first redundancy version (RV1) is 13×Z, the starting position corresponding to the second redundancy version (RV2) is 25×Z, and the starting position corresponding to the third redundancy version (RV3) is 43×Z, where Z is a lift value and is a positive integer. ExampleAs such, the 0th redundancy version (RV0) may be used for the first transmission of data from the first transmitting node.

[0197] In some examples, a first bit sequence is error-correction coded based on a parity check matrix to obtain a second bit sequence, where the parity check matrix is ​​determined based on the lift value and a basis matrix. The basis matrix is ​​a base graph. Fu It is determined based on the basic graph. Hu is , the first basic graph Fuo and / or the second basic graph Hu Among them, the first basic graph Fu The size of the corresponding basis matrix is ​​46 rows and 68 columns, and it contains eight basis matrices. The index i LS are 0 to 7 respectively. Fu The size of the corresponding basis matrix is ​​42 rows and 52 columns, and it also contains 8 basis matrices, and the index i corresponding to each basis matrix is LS are from 0 to 7 respectively.

[0198] As an example, if at least one of the following conditions 1 to 3 is satisfied, the second basic graph Fu The parity check matrix is ​​determined based on the following: Condition 1, the size of the transmission block is 292 or less; Condition 2, the size of the transmission block is 3824 or less and the coding rate is less than 0.67; Condition 3, the coding rate is less than 0.25. As another example, if none of the above conditions 1 to 3 is satisfied, the first basic graph is determined. Huh? The parity check matrix is ​​determined from the Example So, the first basic graph Fu The corresponding basis matrix and second basis graph Fu The corresponding basis matrices are those defined in 3GPP standard protocol 38.212.

[0199] one Example In Table 1, the lift value of the parity check matrix belongs to one element in the eight lift value subsets, and the index i of the eight lift value subsets is LSare 0 to 7, respectively. Hu If it is determined that the index i is used, it is calculated based on the lift value. LS Determine the first basic graph Fu's i LS Determine the parity check matrix based on the basis matrix and the lift value. For example, if the lift value Z is 120, then the index i LS = 7, and the first basic graph matrix i LS The parity check matrix is ​​determined based on the 7th basis matrix and the lift value Z=120. Hu If it is determined that the index i is used, it is calculated based on the lift value. LS Determine the second basic graph Fu's i LS Determine the parity check matrix based on the basis matrix and the lift value. For example, if the lift value Z is 24, then the index i LS = 1, and the second basic graph Fu's i LS A parity check matrix is ​​determined based on the basis matrix of Z=1 and the lift value Z=24.

[0200] [Table 1]

[0201] In some examples, the starting positions corresponding to the zeroth redundancy version (RV0), the first redundancy version (RV1), the second redundancy version (RV2), and the third redundancy version (RV3) are determined as shown in Table 2, where N cb indicates the length of the third bit sequence in the ring buffer. In one example, the position of the first element of the target subsequence in the third bit sequence is equal to the starting position corresponding to the redundancy version with index 0, i.e., the position of the first element of the target subsequence in the third bit sequence is 0.

[0202] [Table 2]

[0203] one Example Then, as shown in Table 2, the position of the first element of the target subsequence in the third bit sequence is equal to the starting position corresponding to the redundancy version with index 1, that is, the position of the first element of the target subsequence in the third bit sequence is

number

number

[0204] one Example Then, as shown in Table 2, the position of the first element of the target subsequence in the third bit sequence is equal to the starting position corresponding to the redundancy version with index 2, that is, the position of the first element of the target subsequence in the third bit sequence is

number

number

[0205] In one example, as shown in Table 2, the position in the third bit sequence of the first element of the target subsequence is equal to the starting position corresponding to the redundancy version with index 3, i.e., the position in the third bit sequence of the first element of the target subsequence is

number

number

[0206] In S104, the fourth bit sequence is transmitted.

[0207] In some embodiments, the fourth bit sequence does not include the first subsequence, i.e., the first subsequence is transmitted implicitly, which can improve data transmission efficiency and reduce power consumption during transmission.

[0208] In some embodiments, the second transmitting node is a receiver. 、S 104 is , th The fourth bit sequence is transmitted to the second transmitting node.

[0209] In some embodiments, the fourth bit sequence may be frequency modulated before being transmitted, thereby improving the anti-interference capability in the data transmission process and improving the reliability of communication.

[0210] In an embodiment of the present application, redundant information is added to the data to be transmitted by error correction coding the data to be transmitted, and data with the added redundant information (e.g., a second bit sequence) is obtained. Furthermore, by interleaving the subsequences of the data with the added redundant information, the data is more resistant to random interference and noise during transmission, and the error correction performance of communication is improved.

[0211] For ease of understanding, the above data transmission method and its related art will be described below with reference to some examples. fruit Regarding the embodiment The theory Reveal.

[0212] Example 1

[0213] In this example, the second bit sequence does not include the system puncture sequence.

[0214] 5, the third bit sequence may be determined as follows: after determining the first subsequence 210 and the second subsequence 220 from the second bit sequence 200, interleaving the second subsequence 220 based on the first subsequence 210 to obtain a target subsequence 310, and merging the target subsequence 310 and the remaining other bit sequences 230 in the second bit sequence 200 to form the third bit sequence 300 in the ring buffer. Further, bit selection is performed on the third bit sequence 300 to obtain a fourth bit sequence 400.

[0215] Here, the first subsequence 210 consists of one or more consecutive bits in the second bit sequence 200. The second subsequence 220 consists of one or more consecutive bits in the second bit sequence 200. The target subsequence 310 is placed at the beginning of the third bit sequence 300.

[0216] In some examples, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than one.

[0217] In some examples, the length of the first subsequence satisfies the following relationship:

number

[0218] however,

number

[0219] In some examples, the length of the first subsequence satisfies the following relationship:

number

[0220] however,

number

[0221] In some examples, a third bit sequence is determined based on the second bit sequence, where a target subsequence of the third bit sequence is obtained by interleaving the second subsequence based on the first subsequence.

[0222] In some examples, the length of the target subsequence is an integer greater than one, the length of the first subsequence is an integer greater than zero, and the length of the second subsequence is an integer greater than one.

[0223] In some examples, after obtaining the third bit sequence 300 according to the example shown in Figure 5, bit selection may be performed on the third bit sequence to obtain a bit-selected fourth bit sequence 400. Then, the fourth bit sequence 400 is transmitted to a second transmission node.

[0224] In some examples, the bit selection for the third bit sequence may be implemented by selecting bits based on the redundancy version. For example, a starting position for bit selection is determined based on the redundancy version, and bit selection is started from the starting position. When bits are selected up to the last bit of the third bit sequence, selection is performed from the first bit (i.e., the first element of the third bit sequence). The redundancy version is 、S You may refer to the explanation of 103, but the explanation will be omitted here.

[0225] In some instances, the first transmissionWhen a node transmits data for the first time, it transmits using a redundancy version with index 0 (RV0), ensuring that the target subsequence is included in the initially transmitted data and ensuring the performance of the encoding method. Furthermore, implementing incremental redundancy hybrid automatic repeat request (IR-HARQ) allows the receiving side to perform soft bit merging when receiving retransmitted data, thereby reducing the complexity of decoding and improving retransmission performance. Furthermore, if the initially transmitted data is lost (e.g., if the initially transmitted data DCI is lost), the receiving side (e.g., the second transmitting node) can also perform self-decoding if the data retransmitted by the transmitting side (e.g., the first transmitting node) is the initially transmitted data.

[0226] 5, third bit sequence 300 includes target subsequence 310 and other bit sequence 230. Here, target subsequence 310 is located at the beginning of third bit sequence 300. In this way, first, the target subsequence of the third bit sequence can be transmitted preferentially in the initial transmission, improving reception performance for the initial transmission. Second, if reception and decoding of the initially transmitted data fails, decoding performance during retransmission can be improved by merging the initially transmitted data and the retransmitted data for decoding. Third, if the initially transmitted data is lost (when both control signaling and data are not received), self-decoding is possible even in the retransmission, ensuring reception performance for the retransmitted data.

[0227] In this example, the first subsequence is a consecutive subsequence in the second bit sequence, and the second subsequence is a consecutive subsequence in the second bit sequence.

[0228] In this example, the length of the first subsequence is less than the length of the third bit sequence.

[0229] one ExampleIn the example, the length of the effective information bits is 64, and if the first bit sequence includes the effective information bits and a padding bit sequence of length 2, the length of the first bit sequence is K=66 bits. The first bit sequence is error-correction coded to obtain a second bit sequence of length N=192. The length of the first subsequence is L=6, and the indices of the first subsequence in the second bit sequence range from 0 to 5. That is, the indices of the first subsequence in the second bit sequence form A=[0, 1, 2, ..., 5]. The length of the second subsequence is 58, and the indices of the second subsequence in the second bit sequence range from 6 to 63, and the indices of the second subsequence in the second bit sequence form B=[6, 7, 8, ..., 63]. The length of the other bit sequences is 128, and the indices of the other bit sequences in the second bit sequence range from 64 to 191. The indices of the first bit sequence in the second bit sequence range from 0 to 65, respectively.

[0230] Example 2

[0231] In example 2, the third bit sequence includes the first sub-sequence.

[0232] Referring to FIG. 6, the second bit sequence 200 includes a system puncture sequence 240, a first subsequence 210, a padding sequence 250, a second subsequence 220, and an other bit sequence 230. The second subsequence 220 is divided into subsequences 221 and 222 by the padding sequence 250. The second subsequence 220 is interleaved based on the first subsequence 210 to obtain a target subsequence 310. The first subsequence 210, the padding sequence 250, the target subsequence 310, and the other bit sequence 230 together constitute a third bit sequence 300 in the ring buffer. Bit selection is performed on the ring buffer sequence 300 to obtain a fourth bit sequence 400. The fourth bit sequence 400 does not include the first subsequence 210 or the padding sequence 250. The system puncture sequence 240 is composed of system puncture bits in error correction coding. The useful information bits are equal to the contents of the union of the system puncture sequence 240, the first subsequence 210, and the second subsequence 220. The first bit sequence is equal to the contents of the union of the useful information bits and the padding sequence 250.

[0233] In some embodiments, The error correction coding scheme used in Figure 6 is LDPC coding. The length of the system puncture sequence 240 is q*Z bits, where Z is the lift value of the LDPC code.

[0234] In Example 2, the length of the third bit sequence is determined based on the length of the first sub-sequence.

[0235] In some embodiments, 6, the length of the third bit sequence 300 is equal to the length of the second bit sequence 200 minus the length of the system puncture sequence 240. If the length of the third bit sequence is Ncb, Ncb is determined according to the following equation: Ncb=Nq*Z. In some embodiments, q is 0, 1, or 2.

[0236] Assuming that the length of the first subsequence is L, the length of the third bit sequence is Ncb, and if the third bit sequence does not include the system puncture sequence and the first subsequence, Ncb is determined according to the following formula: Ncb=Nq*ZL. Alternatively, if the third bit sequence does not include the system puncture sequence, the first subsequence, and the padding sequence, the length of the third bit sequence Ncb is determined according to Ncb=Nq*ZLF, where F is an integer greater than 0 and is the length of the padding sequence, and N is the length of the second bit sequence.

[0237] In some examples, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than one.

[0238] In some examples, a third bit sequence is obtained based on the second bit sequence, where a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, where the length of the target subsequence is an integer greater than 1, the length of the first subsequence is an integer greater than 0, and the length of the second subsequence is an integer greater than 1. Bit selection is performed on the third bit sequence to obtain a fourth bit sequence.

[0239] In some examples, the length of the third bit sequence is determined based on the length of the second bit sequence.

[0240] In some examples, when the third bit sequence has a length Ncb, the length of the third bit sequence satisfies the relationship Ncb=Nq*Z, where the third bit sequence includes the padding sequence and the first subsequence in the second bit sequence, where q is the number of columns of the system puncture in the corresponding basis matrix, and N is the length of the second bit sequence. In some embodiments , q is 0, 1, or 2.

[0241] Example 3

[0242] In Example 3, the third bit sequence does not include the system puncture sequence and / or the first sub-sequence of the second bit sequence.

[0243] Referring to Figure 7, the second bit sequence 200 includes a system puncture sequence 240, a first subsequence 210, a second subsequence 220, a padding sequence 250, and other bit sequences 230. The second subsequence 220 is interleaved based on the first subsequence 210 to obtain a target subsequence 310. The target subsequence 310, the padding sequence 250, and the other bit sequences 230 are combined together to form a third bit sequence 300 in the ring buffer. Bit selection is performed on the third bit sequence 300 to obtain a fourth bit sequence 400. The union of the system puncture sequence 240, the first subsequence 210, and the second subsequence 220 is a valid bit sequence. information BIT To The first bit sequence is the same as the content of the union of the useful information bits and the padding sequence 250.

[0244] Among these, the fourth bit sequence 400 does not include the first subsequence 210 or the padding sequence 250 .

[0245] As an example, the union of the system puncture sequence 240, the first subsequence 210, the second subsequence 220, and the padding sequence 250 is the same as the content of the first bit sequence, i.e., the system puncture sequence 240, the first subsequence 210, and the second subsequence 220 are each the same as the content of a subsequence of the first bit sequence.

[0246] In this example, the first subsequence is one contiguous subsequence in the first bit sequence, and the second subsequence is one contiguous subsequence in the first bit sequence.

[0247] one ExampleA first bit sequence of length K is error-correction coded to obtain a second bit sequence of length N, where K and N are both integers greater than 1.

[0248] one Example a third bit sequence is determined based on the second bit sequence, where a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, where the length of the target subsequence is an integer greater than 1, the length of the first subsequence is an integer greater than 0, and the length of the second subsequence is an integer greater than 1.

[0249] one Example As such, the length of the second subsequence is determined based on at least one of the length of the first subsequence, the length of the first bit sequence, and the length of the second bit sequence.

[0250] one Example As such, when the error correction coding scheme of FIG. 7 is system coding, the first subsequence is a subset of the first bit sequence, and / or the second subsequence is a subset of the first bit sequence.

[0251] one Example 7 is LDPC coding, the length of the third bit sequence can satisfy the relationship Ncb=NL-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, L represents the length of the first subsequence, and Z is the lift value used in LDPC coding.

[0252] Furthermore, the length of the first subsequence is the largest positive integer not exceeding log2(K-2Z), and / or the length of the second subsequence is determined based on the length of the first bit sequence, the length of the first subsequence, and the lift value. For example, the length of the second subsequence is equal to the length of the first bit sequence minus the length of the first subsequence minus two times the lift value.

[0253] one Example 7 is LDPC coding, if the dimension number of the basis matrix is ​​42 rows and 52 columns, i.e., if the number of systematic columns of the basis matrix is ​​kb=52-42=10, the lift value is Z=16. That is, the indices of the corresponding system bits in the second bit sequence are {0, 1, 2, 3, ..., kb*Z-1}, and the indices of the corresponding check bits in the second bit sequence are {kb*Z, kb*Z+1, kb*Z+2, kb*Z+3, ..., 52*Z-1}.

[0254] In some examples, the useful information bit length is K'=96 bits, the first bit sequence length is K=160, the second bit sequence length is N=832, the fourth bit sequence length is E=200, the system puncture sequence length is 32, the first subsequence length is L=6, the second subsequence length is 58, the padding sequence length is 64, and the other bit sequences length is 672. The index of the first bit sequence in the second bit sequence ranges from 0 to K-1.

[0255] In some examples, the index of the first bit sequence in the second bit sequence ranges from 0 to 95, and the index of the first element of the first subsequence in the second bit sequence is equal to 2Z. For example, if the lift value Z is 16, the index of the first element of the first subsequence in the second bit sequence is equal to 2*16=32. The length of the first subsequence is equal to L=6, and the index of the first subsequence in the second bit sequence ranges from 32 to 37, i.e., the index of the first subsequence in the second bit sequence comprises A={32, 33, 34, 35, 36, 37}. The length of the second subsequence is determined based on the length K of the first bit sequence, the length L of the first subsequence, and the lift value Z. 、K-L-2Z, i.e., 58, and the indices in the second bit sequence of the second subsequence are from 38 to 95, so that the indices in the second bit sequence of the second subsequence constitute B={38, 39, 40, ..., 95}. The length of the other bit sequences is equal to 672, and the indices in the second bit sequence of the other bit sequences are from 160 to 831.

[0256] Example 4

[0257] In Example 4, the third bit sequence does not include the system puncture sequence and / or the first sub-sequence in the second bit sequence.

[0258] Referring to FIG. 8, the second bit sequence 200 includes a system puncture sequence 240, a first subsequence 210, a second subsequence 220, a padding sequence 250, and an other bit sequence 230. The second subsequence 220 is divided into subsequences 221 and 222 by the padding sequence 250. The second subsequence 220 is interleaved based on the first subsequence 210 to obtain a target subsequence 310. The padding sequence 250, the target subsequence 310, and the other bit sequence 230 are combined together to form a third bit sequence 300 for the ring buffer. Bit selection is performed on the ring buffer sequence 300 to obtain a fourth bit sequence 400. The fourth bit sequence 400 does not include the first subsequence 210 or the padding sequence 250. The effective information bits are the same as the contents of the union of the system puncture sequence 240, the first subsequence 210, and the subsequence 221. The first bit sequence is the same as the contents of the union of the useful information bits and the padding sequence 250 .

[0259] one Example As such, when the error correction coding scheme of FIG. 8 is system coding, the first subsequence is a subset of the first bit sequence, and / or the second subsequence is a subset of the first bit sequence.

[0260] one ExampleAlternatively, the error correction coding scheme in FIG. 8 may be LDPC coding.

[0261] one Example The length of second subsequence 220 may be determined based on the coding rate, where R is equal to the maximum target coding rate defined in the MCS table and is a positive real number less than 1. For example, the coding rate may be equal to 948 / 1024, 772 / 1024, or 0.95. Alternatively, the coding rate R may be equal to 948 / 1024 + Δ or 772 / 1024 + Δ, where Δ is a positive real number greater than -0.06 and not greater than 0.06. For example, Δ may be 0.

[0262] one Example where the length of first subsequence 210 is determined based on the length K of the first bit sequence and the coding rate R. The length of second subsequence 220 is determined based on the length K of the first bit sequence and the coding rate R. In one example, the length of first subsequence 210 is the largest positive integer not exceeding log2(K / R), and the length of second subsequence 220 is f(K / R), where K is the length of the first bit sequence, R is the coding rate, and f(K / R) represents an integer obtained by truncating, raising, or rounding the real number K / R.

[0263] one Example where the length of first subsequence 210 is determined based on the effective information bit length K' and the coding rate R. The length of second subsequence 220 is determined based on the effective information bit length K' and the coding rate R. In one example, the length of first subsequence 210 is the largest positive integer not exceeding log2(K' / R), and the length of second subsequence 220 is f(K' / R), where K' is the effective information bit length, R is the coding rate, and f(K' / R) represents an integer obtained by truncating, raising, or rounding off the real number K' / R.

[0264] one Examplewhere K is the length of the first bit sequence, R is the coding rate, Z is the lift value of the parity check matrix, and f(K / R) is an integer obtained by truncating, raising, or rounding the real number K / R.

[0265] one Example where the length of second subsequence 220 is determined based on the length K of the first bit sequence and the coding rate R, and the length of first subsequence 210 is determined based on the length of second subsequence 220. In one example, the length of second subsequence 220 is f(K / R), where f(K / R) represents an integer obtained by truncating, rounding, or rounding the real number K / R. The length of first subsequence 210 is the largest positive integer not exceeding log2(f(K / R)).

[0266] one Example The length of the second subsequence is determined based on the parameters of the coding rate R, the useful information bit length K′, the length of the first subsequence L, and the lift value Z.

[0267] For example, the length of the second subsequence may be equal to f(K' / RL-2Z), where f(x) represents the smallest integer not less than the real number x (i.e., an integer obtained by a rounding operation), the largest integer not greater than the real number x (i.e., an integer obtained by a rounding operation), or an integer obtained by rounding the real number x.

[0268] one Example 8 is LDPC coding, the length of the third bit sequence may satisfy the relationship Ncb=NL-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, L represents the length of the first subsequence, and Z is the lift value used for LDPC coding. In some examples, N may be equal to 52Z or 68Z.

[0269] In some examples, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than one.

[0270] In some examples, the error correction coding uses an LDPC code, and a first bit sequence of length K is error-correction coded based on a parity check matrix to obtain a second bit sequence of length N. Here, the parity check matrix is ​​determined based on a lift value and a basis matrix. The basis matrix includes two types of elements: an element representing a cyclic shift of an identity matrix and an element representing an all-zero square matrix. The lift value is equal to the number of dimensions of the identity matrix and the all-zero square matrix. The lift value is Z, where Z is an integer greater than 0.

[0271] In some examples, the dimension of the basis matrix is ​​42 rows and 52 columns, i.e., the number of systematic columns in the basis matrix is ​​kb = 52 - 42 = 10, and the lift value is Z = 16. The effective information bit length is K' = 96 bits, the length of the first bit sequence is K = 160, the length of the second bit sequence is N = 832, the length of the fourth bit sequence is E = 160, and the coding rate R is equal to 948 / 1024. The length of the system puncture sequence is 32, the length of the first subsequence is L = 6, the length of the second subsequence is 66, the length of the padding sequence is 64, and the lengths of the other bit sequences are 664. The third bit sequence in the ring buffer includes the padding sequence, the target subsequence, and the other bit sequences. That is, the length of the third bit sequence is 794. Bit selection is performed on the third bit sequence in the ring buffer to obtain a fourth bit sequence with a length of E = 160 bits.

[0272] In some examples, the indices in the second bit sequence of the first subsequence are 32 to 37, i.e., the indices in the second bit sequence of the first subsequence comprise a set A = {32, 33, 34, 35, 36, 37}. The indices in the second bit sequence of the second subsequence comprise a set B = {38, 39, 40, ..., 95} & {160, 161, ..., 167}. If the length of the other bit sequence is equal to 664, the indices in the second bit sequence of the other bit sequence are 168 to 831.

[0273] In some examples, the effective information bit length is K'=96, the length of the first bit sequence is K=160, the length of the second bit sequence is N=832, the length of the fourth bit sequence is E=160, and the coding rate R is equal to 948 / 1024. The length of the second subsequence is equal to f(K / R). The length of the second subsequence is equal to 104 where f(x) indicates the real number x is rounded up. Then, the length of the first subsequence is the largest positive integer not exceeding log2(N), i.e., 6. N is the length of the second subsequence, and N=104. The length of the system puncture sequence is 32, the length of the padding sequence is 64, and the length of the other bit sequences is 626. That is, the indices in the second bit sequence of the system puncture sequence comprise {0, 1, 2, ..., 31}, the indices in the second bit sequence of the first subsequence comprise the set A = {32, 33, 34, 35, 36, 37}, and the indices in the second bit sequence of the second subsequence comprise the set B = {38, 39, 40, ..., 95} & {160, 161, ..., 205}. The indices in the second bit sequence of the other bit sequences are 206 to 831.

[0274] Example 5

[0275] In Example 5, the length of the first subsequence is determined based on the parameters of the number of rows m of the core matrix, the lift value Z, and the useful information bit length K′.

[0276] Here, the core matrix may be one submatrix of the base matrix. The number of rows, m, of the core matrix may be equal to the difference between the number of columns with a column weight greater than 1 and the number of systematic columns in the base matrix. In one example, the matrix formed by the test portion of the core matrix has a bidiagonal structure. The core matrix is ​​located in the upper left corner of the base matrix as a submatrix with m rows and m+kb columns, where kb is the number of systematic columns in the base matrix, and both m and kb are integers greater than 0. For example, in the case of a base matrix with 42 rows and 52 columns, the number of systematic columns in the base matrix is ​​52-42=10. If the number of columns with a column weight greater than 1 in the base matrix is ​​equal to 14 and the number of rows, m, of the core matrix is ​​equal to the difference between 14 and 10, i.e., m=4, the core matrix is ​​located in the upper left corner of the base matrix as a submatrix with m rows and m+10 columns, i.e., 4 rows. 14 The number of check columns of the core matrix is ​​equal to the number of rows of the core matrix, i.e., both are equal to m.

[0277] In some examples, the basis matrix is ​​a 42-by-52 matrix, i.e., the number of systematic columns is 52-42=10, and the lift value takes Z=16. The core matrix is ​​located in the upper-left corner of the 42-by-52 basis matrix at the m-by-10+m submatrix (i.e., the upper-left corner at the 4-by-14 submatrix), where m equals 4.

[0278] In some examples, the length of the second subsequence is determined based on the following parameters: length K of the first bit sequence, number m of rows of the core matrix, and lift value Z. The length of the first subsequence is determined based on the length of the second subsequence.

[0279] In some examples, the length of the first subsequence is determined based on the following parameters: the useful information bit length K', the number of rows m of the core matrix, and the lift value Z. for example, The length L of the first subsequence is the maximum positive integer not exceeding log2(K'+m*Z-2Z). The length of the second subsequence is determined based on the following parameters: the length of useful information bits K', the number of rows m of the core matrix, the length L of the first subsequence, and the lift value Z. for example,The length of the second subsequence may be equal to K'+m*ZL-2Z.

[0280] Note that the length of the calculated first subsequence is L, the length of the second subsequence is N, and if L is greater than log2(N), then one of the following operations is performed: 1, L=L-1; 2, N=2 L It is necessary to execute

[0281] In some examples, the length of the third bit sequence is determined based on the following parameters: the length N of the second bit sequence, the length L of the first subsequence, and a lift value Z. The length of the third bit sequence may satisfy the relationship Ncb=NL-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, L represents the length of the first subsequence, and Z is the lift value used for LDPC coding. In some examples, N is 52Z.

[0282] In some other examples, the length of the third bit sequence may satisfy the relationship Ncb=N-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, and Z is the lift value of the parity check matrix used for LDPC coding. In some embodiments, N is 52Z.

[0283] In some examples, the useful information bit length is K' = 96, the first bit sequence has a length K = 160, the second bit sequence has a length N = 832, and the fourth bit sequence has a length E = 180. Also, the system puncture sequence has a length of 32, the first subsequence has a length L = 7, the second subsequence has a length 128, the padding sequence has a length 64, and the other bit sequences have a length 608. The indices of the first subsequences in the second bit sequences form a set A = {32, 33, 34, 35, 36, 37, 38}, the indices of the second subsequences in the second bit sequences form a set B = {39, 40, 41, ..., 94, 95} & {160, 161, ..., 229, 230}, the length of the other bit sequences is equal to 601, and the indices of the other bit sequences in the second bit sequence range from 231 to 831.

[0284] Example 6

[0285] In Example 6, as shown in Figure 8, the length of the first subsequence is determined based on a parameter called the useful information bit length K', and / or the length of the second subsequence is determined based on a parameter called the useful information bit length K'.

[0286] In some examples, the length L of the first subsequence is the largest positive integer that does not exceed the value of log2(K').

[0287] In some embodiments, the basis matrix is ​​a 42-by-52 matrix, ie, the number of systematic columns in the basis matrix is ​​52-42=10, and the lift value takes a value of Z=16.

[0288] In some examples, the length of the third bit sequence may satisfy the relationship Ncb=NL-2Z or Ncb=N-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, L represents the length of the first subsequence, and Z is a lift value used for LDPC coding. In some examples, N is 52Z.

[0289] In some examples, the effective information bit length is K' = 96, the first bit sequence length is K = 160, the second bit sequence length is N = 832, and the fourth bit sequence length is E = 260. Then, the system puncture sequence length is 32, the first subsequence length is L = floor(log2(K')) = 6, where floor(x1) represents the truncation operation of the real number x, the second subsequence length is equal to the effective information bit length K' = 96, the padding sequence length is 64, and the other bit sequences length is 634. The indices in the second bit sequence of the first subsequence constitute A={32,33,34,35,36,37}, the indices in the second bit sequence of the second subsequence constitute B={38,39,40,41,...,94,95}&{160,161,...,196,197}, the length of the other bit sequences is equal to 634, and the indices in the second bit sequence of the other bit sequences are from 198 to 831.

[0290] Example 7

[0291] As shown in FIG. 9 , the second bit sequence 200 includes a system puncture sequence 240, a padding sequence 250, a first subsequence 210, a second subsequence 220, and other bit sequences 230. The second subsequence 220 is interleaved based on the first subsequence 210 to obtain a target subsequence 310, and the padding sequence 250, the target subsequence 310, and the other bit sequences 230 are combined together to form a third bit sequence 300 in the ring buffer. Alternatively, the third bit sequence 300 in the ring buffer may be composed of the padding sequence 250, the first subsequence 210, the target subsequence 310, and the other bit sequences 230 (not shown). Bit selection is performed on the third bit sequence 300 to obtain a fourth bit sequence 400, where the fourth bit sequence 400 does not include the first subsequence 210 or the padding sequence 250. The useful information bits include some or all of the bits in the system puncture sequence 240, the first subsequence 210, and the second subsequence 220. The first bit sequence is the union of the useful information bits and the padding sequence 250.

[0292] In some examples, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than one.

[0293] In some examples, the third bit sequence is determined based on the second bit sequence, where a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, where the length of the target subsequence is an integer greater than 1, the length of the first subsequence is an integer greater than 0, and the length of the second subsequence is an integer greater than 1.

[0294] In some examples, the error correction coding uses an LDPC code, and a first bit sequence of length K is error correction coded based on a parity check matrix to obtain a second bit sequence of length N. Here, the parity check matrix is ​​determined based on a lift value and a basis matrix. The basis matrix includes two types of elements: an element representing a cyclic shift of an identity matrix and an element representing an all-zero square matrix. The lift value is equal to the number of dimensions of the identity matrix and the all-zero square matrix. The lift value is Z, where Z is an integer greater than 0.

[0295] In some embodiments, If the number of bits in the first bit sequence is less than the number of system bits, it may be padded with null bits, where the number of padded bits is equal to the number of system bits minus the number of bits in the first bit sequence.

[0296] In some embodiments, The starting index for NULL bit padding is q*Z, where q is the number of system puncture columns in the basis matrix and Z is the lift value.

[0297] one Example Then, the index positions for NULL bit padding are {q*Z, q*Z+1, q*Z+2, ..., q*Z+p-1}, where q is the number of system puncture sequences in the basis matrix, p is the number of padding NULL bits, and p is a non-negative integer. In this way, the second subsequence to be interleaved is not a combination of two separated subsequences, but is convenient for the interleaving process of the first transmitting node and the decoding process of the receiving side corresponding to the first transmitting node, thereby reducing the complexity of transmission and reception.

[0298] In some embodiments The length of the third bit sequence may satisfy the following relationship: Ncb=NL-2Z, where Ncb represents the length of the third bit sequence, N represents the length of the second bit sequence, L represents the length of the first subsequence, and Z is a lift value used for LDPC coding. In some examples, N is 52Z.

[0299] In some examples, the dimension of the basis matrix is ​​a 42x52 matrix, i.e., the number of systematic columns in the basis matrix is ​​52-42=10, and the lift value takes Z=16. The length of the useful information bits is K'=96, the length of the first bit sequence is K=160, the length of the second bit sequence is N=832, and the length of the fourth bit sequence is E=160. The lengths of the system puncture sequence, the length of the first subsequence, the length of the padding sequence, and the lengths of the other bit sequences are as shown in Examples 1 to 6 above. Fruit It is the same as the embodiment.

[0300] In some embodiments , the index in the second bit sequence of the last bit of the second subsequence is determined based on at least one parameter of the lift value, the number of systematic columns of the basis matrix, the number of columns of the core matrix, the length of the first bit sequence, the length of the first subsequence, and the length of the padding sequence.

[0301] For example, the index in the second bit sequence of the last bit of the second subsequence may be equal to kb*Z, where kb is the number of systematic columns in the basis matrix and Z is the lift value.

[0302] As yet another example, the index in the second bit sequence of the last bit of the second subsequence may be equal to n*Z, where n is the number of columns in the core matrix and Z is the lift value.

[0303] As another example, the index in the second bit sequence of the last bit of the second subsequence may be equal to (n a )*Z, where n is the number of columns in the core matrix, Z is the lift value, and a is equal to 1, 2, 3, or −1.

[0304] As another example, the index in the second bit sequence of the last bit of the second subsequence may be equal to K+q*Z+p+L, where K is the length of the first bit sequence, q is a non-negative integer, Z is the lift value, p is the length of the padding sequence, and L is the length of the first subsequence.

[0305] In some examples, the length of the second subsequence is determined based on at least one parameter of the lift value, the number of systematic columns of the basis matrix, the number of columns of the core matrix, the length of the first bit sequence, the useful information bit length, the length of the first subsequence, and the length of the padding sequence.

[0306] Example 8

[0307] As shown in FIG. 10 , the second bit sequence 200 includes a system puncture sequence 240, a padding sequence 250, a first subsequence 210, a second subsequence 220, and other bit sequences 230. The second subsequence 220 is interleaved based on the first subsequence 210 to obtain a target subsequence 310. The padding sequence 250, the first subsequence 210, the target subsequence 310, and the other bit sequences 230 are combined together to form a third bit sequence 300 for the ring buffer. Bit selection is performed on the third bit sequence 300 to obtain a fourth bit sequence 400, where the fourth bit sequence 400 does not include either the first subsequence 210 or the padding sequence 250. The useful information bits include some or all of the bits of the system puncture sequence 240, the first subsequence 210, and the second subsequence 220. The first bit sequence is the union of the useful information bits and the padding sequence 250 .

[0308] In Example 8, the third bit sequence includes the padding sequence and the first subsequence.

[0309] In some examples, a first bit sequence of length K is error correction encoded to obtain a second bit sequence of length N, where K and N are both integers greater than 1.

[0310] In some embodiments If the number of bits in the first bit sequence is less than the number of system bits, it may be padded with null bits. The number of padded bits is equal to the number of system bits minus the number of bits in the first bit sequence.

[0311] In some embodiments , the third bit sequence satisfies the relationship Ncb=N-2Z, where the third bit sequence includes the padding sequence and the first subsequence of the second bit sequence.

[0312] In some embodiments , the third bit sequence satisfies the relationship Ncb=N-2Z-PL, where Ncb is the length of the third bit sequence, N is the length of the second bit sequence, Z is the lift value, P is the length of the padding sequence, and L is the length of the first subsequence.

[0313] Example 9

[0314] Example 9 illustrates a method for determining the first sub-sequence based on higher layer signaling.

[0315] In some embodiments , one or more of the length of the first subsequence, the useful information bit length, the index of the first subsequence in the second bit sequence, and the index of the first element of the first subsequence in the second bit sequence may be determined based on higher layer signaling.

[0316] In some embodiments , the higher layer signaling may include one or more of Downlink Control Information (DCI) signaling, Radio Resource Control (RRC) signaling, or Medium Access Control (MAC) signaling.

[0317] In some examples, the length of the first subsequence may be configured based on DCI signaling. Furthermore, the length L of the first subsequence may be determined based on the DCI signaling, and the first subsequence may be configured by extracting L bits from the starting position of the first subsequence. Here, the starting position of the first subsequence may be a fixed starting position. The fixed starting position may be predetermined. In some embodiments , the fixed starting position may be any bit index in the second bit sequence. In some embodiments If the error correction coding is LDPC coding, the fixed start position may be a start position determined based on a lift value.

[0318] In some examples, an index in the second bit sequence of the first element of the first subsequence may be configured based on the RRC signaling. Further, after determining the index in the second bit sequence of the first element of the first subsequence based on the RRC signaling, the index may be used as the starting position of the first subsequence, and the first subsequence may be extracted from the second bit sequence based on the length L of the first subsequence determined from the DCI signaling.

[0319] It should be understood that the longer the length of the first subsequence, the better and more accurate the corresponding decoding performance, and the shorter the length of the first subsequence, the simpler the corresponding decoding process. Therefore, different configurations of the length of the first subsequence can meet user needs in various situations. By determining the first subsequence based on higher layer signaling, the first transmitting node can flexibly configure the length of the first subsequence according to the state of the user device.

[0320] For example, if the receiving side of the first transmitting node is a base station, when the current base station is in a low load state, i.e., when it is idle most of the time, the receiving performance of the base station can be improved by setting a longer length for the first subsequence to the user device via upper layer signaling. Conversely, when the base station is in a high load state, the amount of data to be processed is large, so the receiving processing time can be shortened by setting a shorter length for the first subsequence via upper layer signaling.

[0321] It should be understood that the longer the first subsequence, the more decoding attempts are required at the receiving end and the higher the decoding complexity. However, the longer the first subsequence, the better the decoding performance at the receiving end, i.e., the lower the transmission power. Therefore, the advantage of determining the first subsequence based on higher layer signaling is that the transmitting end can flexibly configure the length of the first subsequence according to the current state of the user device. For example, if the receiving end is a power-saving device or the user device is in a low-power state, the first subsequence can be set to a shorter length. If the receiving end is a high-end device (e.g., a device in a high-power state), the first subsequence can be set to a longer length, which can reduce transmission power or improve the decoding performance at the receiving end. In other words, determining the first subsequence based on higher layer signaling can increase the flexibility and reliability of communications. For example, if the current base station is in a low-load state, i.e., is idle most of the time, the base station can increase the length of the first subsequence to the user device via higher layer signaling, thereby improving reception performance. Conversely, when the base station is in a high load state, the amount of data to be processed is large, so the reception processing time can be reduced by setting the length of the first subsequence to a short length via higher layer signaling.

[0322] Example 10

[0323] Example 10 illustrates a method for determining a first sub-sequence based on the type of user device.

[0324] In some examples, the length of the first subsequence may be determined according to the type of user device. Furthermore, the first subsequence may be constructed by extracting L bits from the starting position of the first subsequence based on the length L of the first subsequence. Here, the starting position of the first subsequence may be a fixed starting position. The fixed starting position may be predetermined. In some embodiments , the fixed starting position may be any bit index in the second bit sequence. In some embodiments If the error correction coding is LDPC coding, the fixed start position may be a start position determined based on a lift value.

[0325] Furthermore, the types of user devices may be distinguished according to different transmission data rates, for example, low-end devices with low data transmission capabilities and high-end devices with high data rates. Illustratively, the types of user devices may be classified according to Table 3 below.

[0326] [Table 3]

[0327] Below, several examples are given of how to determine the length of the first subsequence depending on the user device. For example, if the user device type is Type 1 and / or Type 2 in Table 3, the length of the first subsequence is 0. If the user device type is Type 3 and / or Type 4 in Table 3, the length of the first subsequence is 2. If the user device type is Type 5 and / or Type 6 in Table 3, the length of the first subsequence is 4. If the user device type is Type 7 and / or Type 8 in Table 3, the length of the first subsequence is 6.

[0328] The first subsequence may be constructed by consecutively extracting bits corresponding to the length of the first subsequence from a fixed starting position based on the length of the first subsequence. The fixed starting position may be equal to any bit index in the second bit sequence, e.g., an integer from 0 to N-1, where N is the length of the second bit sequence. If the error correction coding is LDPC coding, the fixed starting position may be determined based on a lift value.

[0329] It should be understood that the longer the first subsequence, the more decoding attempts there are at the receiving end, and the higher the decoding complexity. However, the longer the first subsequence, the better the decoding performance at the receiving end. Therefore, the advantage of determining the first subsequence according to the type of user device is that it can flexibly adjust to different user devices and apply a first subsequence length that is highly efficient.

[0330] Example 11

[0331] Example 11 shows how to determine the first subsequence based on the modulation order, the coding rate, and the number of resources.

[0332] Here, the modulation order is an integer greater than 0, the coding rate is a positive real number less than 1, and the number of resources is the number of subcarriers or resource elements carrying data, and is an integer greater than 0. The modulation order, coding rate, and number of resources may be determined by downlink control signaling.

[0333] In some embodiments , the length of the first subsequence may be determined based on the modulation order, the coding rate, the coding and modulation scheme index, or the number of resources.

[0334] In some embodiments , the length of the first subsequence may satisfy the following relationship:

number

[0335] where L represents the length of the first subsequence, Q represents the modulation order, R represents the coding rate, and Re represents the number of resources.

number

[0336] In some embodiments , the length of the first subsequence may satisfy the following relationship:

number

[0337] where L represents the length of the first subsequence, Q represents the modulation order, R represents the coding rate, C represents the number of blocks, and Re represents the number of resources.

number

[0338] Example 12

[0339] Example 12 provides a performance analysis of an embodiment of the present application.

[0340] In Example 12, the first bit sequence is the information sequence and the CRC parity That is, the information sequence is CRC-encoded to generate a CRC parity Get the sequence, information sequence and CRC parity The sequences are merged to obtain a first bit sequence, where the length of the information sequence is an integer greater than 0, and the CRC parity The length of the sequence is an integer greater than 0.

[0341] For example, the effective information bit length is K'=144, the length of the first bit sequence is K=240, and the first bit sequence is LDPC-encoded. Here, the length of the transmission block is 128 bits, and CRC check coding is performed to generate a CRC with a length of 16 bits. parity Obtain the sequence, transmission block and CRC parity The system puncture sequence is 2*Z=48 bits, the second subsequence is 144 bits, the padding sequence is 96 bits, and the other bit sequences are 953 bits. The second subsequence is interleaved based on the first subsequence to obtain a target subsequence. The target subsequence, the padding sequence, and the other bit sequences are combined to form a third bit sequence. Bit selection is performed on the third bit sequence to obtain a fourth bit sequence of length E=172. Here, the fourth bit sequence does not include the first subsequence or the padding sequence.

[0342] 11 shows a performance analysis of an embodiment of the present application. Here, the abscissa is the signal-to-noise ratio (SNR, unit: decibels / dB) of an additive white Gaussian noise (AWGN) channel, and the ordinate is the block error rate (BLER). The closer the performance curve is to the left of the abscissa, the better the performance. The solid line (labeled "New") is the performance curve corresponding to the coding method of this example, and the dashed line (labeled "Old") is the performance curve of conventional LDPC coding.

[0343] Referring to Figure 11, it can be seen that when the target block error rate (BLER) is 0.01, a performance gain of approximately 0.6 dB is achieved. Therefore, the coding method of this example achieves a superior performance gain. That is, because the corresponding signal-to-noise ratio is lower, less energy needs to be transmitted to achieve the same target block error rate. Alternatively, at the same signal-to-noise ratio, the data transmission method of this example has the beneficial effect of achieving a lower block error rate than the conventional method. For example, at a signal-to-noise ratio of 6.0 dB, the block error rate of the coding method of this example reaches or exceeds 0.07, while the block error rate of the conventional method is 0.16.

[0344] Example 13

[0345] In Example 13, a first bit sequence with length K'=144 useful information bits and length K=240 is LDPC-encoded to obtain a second bit sequence with length 1248. When performing LDPC encoding, a lift value Z=24 is used, and the basis matrix is ​​a 42-row, 52-column matrix. A third bit sequence is determined based on the second bit sequence. The target subsequence of the third bit sequence is obtained by interleaving the second subsequence of the second bit sequence based on the first subsequence of the second bit sequence.

[0346] one Example In the example, the length of the second subsequence is equal to Z=24, the length of the first subsequence is equal to 4, and the indices of the first subsequence in the second bit sequence are A={48, 49, 50, 51}, and the indices of the second subsequence in the second bit sequence are B={72, 73, 74, 75, ..., 94, 95}. The interleaving process includes cyclic shift interleaving Z=24 bits in the second subsequence based on the first subsequence. If the non-negative integer corresponding to the first subsequence is S, the second subsequence is cyclically shifted to the left by S bits. Next, bit selection is performed on the third bit sequence to obtain a fourth bit sequence.

[0347] Another Examplethe length of the second subsequence is equal to Z=48, the length of the first subsequence is equal to 5, and the indices of the first subsequence in the second bit sequence are A={48, 49, 50, 51, 52}, and the indices of the second subsequence in the second bit sequence are B={72, 73, 74, 75, ..., 118, 119}. The interleaving process includes cyclically interleaving a plurality of bit groups in the second subsequence based on the first subsequence, where the length of each bit group is equal to Z=24, the length of the first subsequence is equal to 5, and the indices of the first element of the first bit group in the second bit sequence are B={72, 73, 74, 75, ..., 118, 119}. 2 The index of the first element of this bit group in the second bit sequence is 96. If S is a non-negative integer corresponding to the first subsequence, then if S is less than Z=24, then the first bit group in the second subsequence is cyclically shifted to the left by S bits, and the second bit group is left unchanged. If S is greater than or equal to Z=24, then the first bit group in the second subsequence is cyclically shifted to the left by S-24 bits, and the second bit group is left unchanged. 2 The bit group of is cyclically shifted one bit to the left. Next, bit selection is performed on the third bit sequence to obtain a fourth bit sequence.

[0348] The embodiment of the present application also provides a data transmission method performed by a second transmitting node, corresponding to the data transmission method shown in Figure 2. Referring to Figure 12, this method includes the following steps: S 201 and BiS Including 202.

[0349] In S201, a fourth bit sequence is received.

[0350] Here, the fourth bit sequence is obtained by performing bit selection on the third bit sequence stored in the ring buffer, the target subsequence of the third bit sequence is obtained by interleaving the second subsequence of the second bit sequence based on the first subsequence of the second bit sequence, and the second bit sequence is obtained by error correction coding the first bit sequence.

[0351] In some embodiments, the second transmitting node may also perform processing such as demodulation, noise reduction, or amplification on the received fourth bit sequence to obtain more accurate information.

[0352] The related concepts of first subsequence, second subsequence, target subsequence, first bit sequence, second bit sequence, third bit sequence, and fourth bit sequence have already been discussed above. S 101 or et al. It should be understood that the above description is provided in detail in 104, and the description thereof may be referred to, and will not be repeated here.

[0353] In addition, taking the case where a fourth bit sequence is transmitted from a first transmission node to a second transmission node as an example, when considering the fourth bit sequence transmitted from the first transmission node to the second transmission node, the fourth bit sequence may be subjected to some interference during channel transmission. 、S In 201, the fourth bit sequence received by the second transmitting node is 、S The fourth bit sequence in 104 may differ in part. 、S The fourth bit sequence in 201 is 、S The fourth bit sequence of 104 may be understood as a sequence (or a log-likelihood ratio (LLR) sequence) obtained after channel transmission. However, the present application does not particularly limit this.

[0354] In S202, the fourth bit sequence is error-correction decoded based on the information of the first subsequence.

[0355] In some embodiments, the information of the first subsequence includes at least one of: a length of the first subsequence, an index in the second bit sequence of the first subsequence, and an index in the second bit sequence of a first element of the first subsequence.

[0356] In some embodiments 、S 202 is , th This is achieved by performing a bit deselection process on the fourth bit sequence to obtain a third bit sequence. Based on the information of the first subsequence, the target subsequence of the third bit sequence is deinterleaved to obtain a soft bit sequence for decoding. The soft bit sequence is decoded to obtain the first bit sequence.

[0357] In some embodiments, the information of the first subsequence is stored in advance by the second transmitting node. For example, when the fourth bit sequence is transmitted by the first transmitting node, the first transmitting node and the second transmitting node may pre-agree on the length and index of the first subsequence to be used during the encoding and decoding process. The information of the first subsequence may be determined by several parameters. For this, reference may be made to the above description, which will not be repeated here.

[0358] The above describes the solutions of the embodiments of the present application mainly from the viewpoint of the method. ,aboveIt should be understood that the above-described data transmission method includes a hardware structure and / or software modules for performing each function. Those skilled in the art should easily recognize that the present application can be realized in the form of hardware or a combination of hardware and computer software, referring to the exemplary algorithm steps described in the embodiments of the present application. Whether a particular function is performed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for each specific application scenario, but such implementation means should not be considered beyond the scope of the present application.

[0359] In the embodiments of the present application, the functional modules of the data transmission device can be divided according to the above-described method embodiments. For example, each functional module may be divided according to its function, or two or more functions may be integrated into one functional module. The integrated module may be implemented in the form of hardware or software. Note that the module division in the embodiments of the present application is merely an example and merely a logical division of functions. In actual implementation, a different division method may be used. Below, an example of dividing each functional module by function will be described.

[0360] 13 is a structural schematic diagram of a first transmitting node according to an embodiment of the present application. As shown in FIG. 13, the first transmitting node 500 includes: an encoding module 501 and a sending module 502.

[0361] The encoding module 501 is configured to error correction encode a first bit sequence to obtain a second bit sequence, obtain a third bit sequence based on the second bit sequence to be stored in a ring buffer, and perform bit selection on the third bit sequence to obtain a fourth bit sequence, where a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, and a length of the first subsequence is an integer greater than 0.

[0362] The transmitting module 502 is configured to transmit the fourth bit sequence.

[0363] In some embodiments, the first sub-sequence consists of one or more consecutive bits in the second bit sequence and / or the second sub-sequence consists of one or more consecutive bits in the second bit sequence.

[0364] In some embodiments, the index in the second bit sequence of the elements of the first sub-sequence is different from the index in the second bit sequence of the elements of the second sub-sequence.

[0365] In some embodiments, the length of the third bit sequence is determined based on the length of the first sub-sequence.

[0366] In some embodiments, the length of the third bit sequence is no less than the sum of the lengths of the first and second subsequences.

[0367] In some embodiments, the length of the target subsequence is less than the length of the third bit sequence.

[0368] In some embodiments, the target subsequence is located at the beginning of the third bit sequence.

[0369] In some embodiments, the position in the ring buffer of the first element of the target subsequence is equal to the starting position corresponding to the redundant version with index 0.

[0370] In some embodiments, the first subsequence is determined based on one or more of the second bit sequence, the length of the predetermined fourth bit sequence, the length of the first bit sequence, the effective information bit length, the modulation order, the coding rate, the number of resources, higher layer signaling, the type of user device, and the size of the transport block.

[0371] In some embodiments, the first bit sequence includes a first sub-sequence.

[0372] In some embodiments, error correction encoding the first bit sequence to obtain a second bit sequence includes error correction encoding the first bit sequence to obtain the second bit sequence based on a parity check matrix, where the parity check matrix is ​​determined from the lift value and the basis matrix.

[0373] In some embodiments, the index in the second bit sequence of the first element of the first subsequence is equal to a non-negative integer multiple of the lift value.

[0374] In some embodiments, the index in the second bit sequence of the elements of the first subsequence is equal to the index in the systematic column of the parity check matrix.

[0375] In some embodiments, the indices in the second bit sequence of the L elements of the first subsequence are the indices of the L columns in the parity check matrix with the smallest column weights, where L is the length of the first subsequence and is a positive integer.

[0376] In some embodiments, the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth threshold and is used to calculate a lift value, or the lift value is less than or equal to a predetermined threshold value of lift values.

[0377] In some embodiments, the target sub-sequence of the third bit sequence is obtained after interleaving the second sub-sequence of the second bit sequence based on an interleaving index sequence corresponding to the first sub-sequence, where: In the second bit sequence The two interleaving index sequences corresponding to any two different first subsequences are different.

[0378] In some embodiments, the target sub-sequence of the third bit sequence is obtained after interleaving the second sub-sequence of the second bit sequence based on an interleaving index sequence corresponding to the first sub-sequence. Here, in the second bit sequence In two interleaved index sequences corresponding to any two different first subsequences, there are at most T elements having the same value at the same position, where T is a positive integer.

[0379] In some embodiments, the length of the second subsequence is equal to the length of the first bit sequence.

[0380] In some embodiments, the first bit sequence is determined by a transmission block, the size of the transmission block being less than or equal to a third threshold, where the third threshold is an integer greater than or equal to 64.

[0381] In some embodiments, the length of the first bit sequence is less than or equal to a fourth threshold, where the fourth threshold is an integer greater than or equal to 64.

[0382] In some embodiments, the basic graph Fu A parity check matrix is ​​determined based on the parity check matrix, and then the first bit sequence is error-correction-encoded based on the parity check matrix to obtain a second bit sequence. In some embodiments , the basic graph Hu is Second Basic Graph Fu Yes, the second basic graph Fu The size of the corresponding basis matrix is ​​42 rows and 52 columns.

[0383] Furthermore, the embodiment of the present application also provides a structure of a second transmitting node, as shown in Figure 14. The second transmitting node 600 includes: a decoding module 601 and a receiving module 602.

[0384] The receiving module 602 is configured to receive a fourth bit sequence, where the fourth bit sequence is obtained by performing bit selection on the third bit sequence stored in the ring buffer. A target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence. The second bit sequence is obtained by error correction coding the first bit sequence.

[0385] The decoding module 601 is configured to error correction decode the fourth bit sequence based on the information of the first sub-sequence.

[0386] In some embodiments, the relevant contents of the first sub-sequence, the second sub-sequence, the target sub-sequence, the first bit sequence, the second bit sequence, the third bit sequence, and the fourth bit sequence may refer to the description of the above method embodiment or the description of the first transmitting node 500 shown in Fig. 13, and the description thereof will be omitted here.

[0387] When the functions of the above integrated modules are realized in the form of hardware, the embodiment of the present application may be a communication device. The structureThe communication device 700 is configured to perform a data transmission method according to an embodiment of the present application. As shown in FIG. 15 , the communication device 700 includes a communication interface 703, a processor 702, and a bus 704. In some embodiments The communication device may further include a memory 701 .

[0388] The processor 702 may implement or combine and execute various exemplary logic blocks, modules, and circuits described in the embodiments of the present application. The processor 702 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. These may implement or combine and execute various exemplary logic blocks, modules, and circuits described in the embodiments of the present application. The processor 702 may also be a combination that performs computing functions. For example, a combination of one or more microprocessors, Digital signal processor ( DSP ) and a microprocessor combination.

[0389] The communication interface 703 is configured to connect with other devices over a communication network, which may be an Ethernet, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), etc.

[0390] Memory 701 may be, but is not limited to, read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), magnetic disk storage media or other magnetic storage device, or any other medium that carries or stores desired program code in the form of instructions or data structures and that is accessible by a computer.

[0391] fruit In an embodiment, the memory 701 may exist independently of the processor 702, or the memory 701 may be connected to the processor 702 via a bus 704 for storing instructions or program codes. The processor 702 can implement the data transmission method according to the embodiment of the present application by calling and executing the instructions or program codes stored in the memory 701.

[0392] Further Fruit In an embodiment, memory 701 may be integrally integrated with processor 702 .

[0393] The bus 704 may be an Extended Industry Standard Architecture (EISA) bus or the like. The bus 704 can be divided into an address bus, a data bus, a control bus, and the like. For convenience of illustration, a single bold line is used in FIG. 15, but this does not mean that there is only one bus or only one type of bus.

[0394] Some embodiments of the present application provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) having stored thereon computer program instructions that, when executed on a computer, cause the computer to perform the data transmission method described in any of the above-described embodiments.

[0395] In some examples, the computer may be a terminal device or a device having the functionality of a terminal device, or the computer may be a network device or a device having the functionality of a network device. For example, the computer may be the above-mentioned communication device, first transmission node, or second transmission node, and the present application does not limit the specific form of the computer.

[0396] In some examples, the computer-readable storage medium may include, but is not limited to, a magnetic storage device (e.g., a hard disk, a floppy disk, or a magnetic tape), an optical disk (e.g., a Compact Disk (CD), a Digital Versatile Disk (DVD), etc.), a smart card, and a flash memory device (e.g., an Erasable Programmable Read-Only Memory (EPROM), a card, a stick, or a key drive, etc.). The various computer-readable storage media described herein may represent one or more devices and / or other machine-readable storage media used to store information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0397] In an embodiment of the present application, a computer program including instructions Mu The computer program is provided MuWhen executed on a computer, the program causes the computer to perform the data transmission method according to any of the above embodiments.

[0398] The above description is merely a specific embodiment of the present application, and the scope of protection of the present application is not limited thereto. Any modifications or substitutions within the technical scope disclosed in the present application shall be embraced within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. 1. A data transmission method applied to a first transmitting node, the data transmission method comprising: error correction coding the first bit sequence to obtain a second bit sequence; obtaining a third bit sequence based on the second bit sequence, the third bit sequence being stored in a ring buffer, wherein a target subsequence in the third bit sequence is obtained by interleaving a second subsequence in the second bit sequence based on a first subsequence in the second bit sequence, and the length of the first subsequence is an integer greater than zero; performing bit selection on the third bit sequence to obtain a fourth bit sequence; transmitting the fourth bit sequence. Data transmission method.

2. the first sub-sequence is composed of one or more consecutive bits in the second bit sequence, and / or the second sub-sequence is composed of one or more consecutive bits in the second bit sequence.

2. The data transmission method according to claim 1.

3. a corresponding index in the second bit sequence of an element in the first sub-sequence is different from a corresponding index in the second bit sequence of an element in the second sub-sequence; 2. The data transmission method according to claim 1.

4. the length of the third bit sequence is determined by the length of the first subsequence; 2. The data transmission method according to claim 1.

5. a length of the third bit sequence is equal to or greater than the sum of the lengths of the first and second subsequences; 2. The data transmission method according to claim 1.

6. the length of the target subsequence is less than the length of the third bit sequence; 2. The data transmission method according to claim 1.

7. the target subsequence is located at the beginning of the third bit sequence; 2. The data transmission method according to claim 1.

8. the position in the ring buffer of the first element of the target subsequence is equal to the starting position corresponding to the redundancy version with index 0; 2. The data transmission method according to claim 1.

9. The first subsequence comprises: The length is determined based on one or more of the second bit sequence, the predetermined length of the fourth bit sequence, the length of the first bit sequence, an effective information bit length, a modulation order, a coding rate, the number of resources, higher layer signaling, a type of user device, and a size of a transmission block.

2. The data transmission method according to claim 1.

10. the first bit sequence includes the first subsequence; 2. The data transmission method according to claim 1.

11. The step of error correction encoding the first bit sequence to obtain a second bit sequence includes: performing error correction encoding on the first bit sequence based on a parity check matrix to obtain the second bit sequence; the parity check matrix is ​​determined from a lift value and a basis matrix.

2. The data transmission method according to claim 1.

12. an index in the second bit sequence of the first element of the first subsequence is equal to a non-negative integer multiple of the lift value; 12. The data transmission method according to claim 11.

13. an index in the second bit sequence of an element of the first subsequence is equal to an index in a systematic column of the parity check matrix; 12. The data transmission method according to claim 11.

14. indices in the second bit sequence of the L elements of the first subsequence are indices of L columns in the parity check matrix with the smallest column weights, where L is a length of the first subsequence and is a positive integer; 12. The data transmission method according to claim 11.

15. the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold number of rows; or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold number of columns; or the number of systematic columns of the basis matrices is less than or equal to a predetermined threshold number of systematic columns; or the number of coded systematic columns used to calculate the lift value is less than or equal to a fifth threshold, or the lift value is equal to or less than a preset threshold value of the lift value; 12. The data transmission method according to claim 11.

16. a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on an interleaving index sequence corresponding to the first subsequence, and two interleaving index sequences corresponding to any two different first subsequences are different from each other; 2. The data transmission method according to claim 1.

17. a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on an interleaving index sequence corresponding to the first subsequence, and in two interleaving index sequences corresponding to any two different first subsequences, there are at most T elements having the same value at the same position, where T is a positive integer; 2. The data transmission method according to claim 1.

18. the length of the second subsequence is equal to the length of the first bit sequence; 2. The data transmission method according to claim 1.

19. the first bit sequence is determined by a transmission block; the size of the transmission block is equal to or less than a third threshold, and the third threshold is an integer equal to or greater than 64; 2. The data transmission method according to claim 1.

20. the length of the first bit sequence is equal to or less than a fourth threshold, and the fourth threshold is an integer equal to or greater than 64; 2. The data transmission method according to claim 1.

21. The step of error correction encoding the first bit sequence to obtain a second bit sequence includes: determining a parity check matrix based on a base graph matrix, wherein the base graph matrix is ​​a second base graph matrix, and a size of a base matrix corresponding to the second base graph matrix is ​​42 rows and 52 columns; and performing error correction encoding on the first bit sequence based on the parity check matrix to obtain a second bit sequence.

2. The data transmission method according to claim 1.

22. A data transmission method applied to a second transmission node, the data transmission method comprising: receiving a fourth bit sequence, the fourth bit sequence being obtained by performing bit selection on a third bit sequence stored in a ring buffer, a target subsequence of the third bit sequence being obtained by interleaving a second subsequence of the second bit sequence based on a first subsequence of the second bit sequence, and the second bit sequence being obtained by error correction coding the first bit sequence; and error correction decoding the fourth bit sequence based on information of the first subsequence. Data transmission method.

23. the first sub-sequence is composed of one or more consecutive bits in the second bit sequence, and / or the second sub-sequence is composed of one or more consecutive bits in the second bit sequence.

23. The data transmission method according to claim 22.

24. a corresponding index in the second bit sequence of an element of the first sub-sequence is different from a corresponding index in the second bit sequence of an element of the second sub-sequence; 23. The data transmission method according to claim 22.

25. the length of the third bit sequence is determined by the length of the first subsequence; 23. The data transmission method according to claim 22.

26. a length of the third bit sequence is equal to or greater than the sum of the lengths of the first and second subsequences; 23. The data transmission method according to claim 22.

27. the length of the target subsequence is less than the length of the third bit sequence; 23. The data transmission method according to claim 22.

28. the target subsequence is located at the beginning of the third bit sequence; 23. The data transmission method according to claim 22.

29. the position in the ring buffer of the first element of the target subsequence is equal to the starting position corresponding to the redundancy version with index 0; 23. The data transmission method according to claim 22.

30. the first subsequence is determined based on one or more of the second bit sequence, the length of the fourth bit sequence, the length of the first bit sequence, an effective information bit length, a modulation order, a coding rate, a number of resources, higher layer signaling, a type of user device, and a size of a transport block; 23. The data transmission method according to claim 22.

31. the first bit sequence includes the first subsequence; 23. The data transmission method according to claim 22.

32. The second bit sequence is performing error correction encoding on the first bit sequence based on a parity check matrix to obtain the second bit sequence; the parity check matrix is ​​determined based on a lift value and a basis matrix.

23. The data transmission method according to claim 22.

33. an index in the second bit sequence of the first element of the first subsequence is equal to a non-negative integer multiple of the lift value; 33. The data transmission method according to claim 32.

34. an index in the second bit sequence of an element of the first subsequence is equal to an index in a systematic column of the parity check matrix; 33. The data transmission method according to claim 32.

35. indices in the second bit sequence of the L elements of the first subsequence are indices of L columns in the parity check matrix with the smallest column weights, where L is a length of the first subsequence and is a positive integer; 33. The data transmission method according to claim 32.

36. the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold number of rows; or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold number of columns; or the number of systematic columns of the basis matrices is less than or equal to a predetermined threshold number of systematic columns; or the number of coded systematic columns used to calculate the lift value is less than or equal to a fifth threshold, or the lift value is equal to or less than a preset threshold value of the lift value; 33. The data transmission method according to claim 32.

37. a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on an interleaving index sequence corresponding to the first subsequence, and two interleaving index sequences corresponding to any two different first subsequences are different from each other; 23. The data transmission method according to claim 22.

38. a target subsequence of the third bit sequence is obtained by interleaving a second subsequence of the second bit sequence based on an interleaving index sequence corresponding to the first subsequence, and in two interleaving index sequences corresponding to any two different first subsequences, there are at most T elements having the same value at the same position, where T is a positive integer; 23. The data transmission method according to claim 22.

39. the length of the second subsequence is equal to the length of the first bit sequence; 23. The data transmission method according to claim 22.

40. the first bit sequence is determined by a transmission block; the size of the transmission block is equal to or less than a third threshold, and the third threshold is an integer equal to or greater than 64; 23. The data transmission method according to claim 22.

41. the length of the first bit sequence is equal to or less than a fourth threshold, and the fourth threshold is an integer equal to or greater than 64; 23. The data transmission method according to claim 22.

42. The second bit sequence is determining a parity check matrix based on a base graph matrix, wherein the base graph matrix is ​​a second base graph matrix, and a base matrix corresponding to the second base graph matrix has a size of 42 rows and 52 columns; and performing error correction encoding on the first bit sequence based on the parity check matrix to obtain a second bit sequence.

23. The data transmission method according to claim 22.

43. a memory and a processor, the memory and the processor being coupled; The memory is for storing a computer program, and when the processor executes the computer program, the data transmission method according to any one of claims 1 to 42 is realized. Communication equipment.

44. computer instructions stored therein which, when executed on a computer, cause the computer to carry out the data transmission method of any one of claims 1 to 42; A computer-readable storage medium.

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