Method for depositing a dielectric coating on a component of an electrical device

Abstract

A method for depositing a dielectric coating on a structural array of components of an electrical device includes depositing a first layer of a first dielectric material on the structural array by an atomic layer deposition (ALD) process or a spin-on coating process. The structural array has a plurality of features. The method may also include depositing a second layer of a second dielectric material on the first layer by an evaporation process, a physical vapor deposition process (PVD), or a flux-controlled chemical vapor deposition (CVD) process. The first layer has a first thickness, and the second layer has a second thickness greater than the first thickness.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-Provisional Patent Application No. 18 / 498,493, filed October 31, 2023, which both claim priority to U.S. Provisional Patent Application No. 63 / 382,040, filed November 2, 2022, and U.S. Non-Provisional Patent Application No. 18 / 498,479, the entire contents of which are incorporated herein by reference.

[0002] Statement of Federally Funded Research This invention was made under CRADA SC20 / 01973.00.01 / PTS 1973.02.01 between Quantinuum LLC and National Technology & Engineering Solutions of Sandia, LLC, operated for the U.S. Department of Energy. The Government has certain rights in this invention.

[0003] Various embodiments relate to apparatus, systems, and methods relating to dielectric coatings on components of electrical devices. Exemplary embodiments relate to dielectric coatings on structural arrays of integrated optics of ion traps. [Background technology]

[0004] Components of electrical devices, such as integrated optics for ion traps, often include thick dielectric coatings deposited on the component's substrate. Thick dielectric coatings have traditionally been deposited on the component's substrate with a flux-controlled chemical vapor deposition process. Depositing dielectric coatings on surfaces containing features with high aspect ratios can be challenging and can result in defects or imperfections. Through significant effort, ingenuity, and innovation, many of the shortcomings of conventional dielectric coating formation techniques have been overcome by developing structured solutions in accordance with embodiments of the present invention, many examples of which are detailed herein. Summary of the Invention [Means for solving the problem]

[0005] Exemplary embodiments provide methods for depositing a dielectric coating onto a structural array of a component of an electrical device. In various exemplary embodiments, the structural array is formed of a plurality of features formed on a substrate or one or more sublayers formed on a substrate. In various exemplary embodiments, each and / or at least some of the plurality of features have an aspect ratio of at least 1:1. In various exemplary embodiments, the electrical device is an ion trap and the component is an integrated optic of the ion trap.

[0006] According to aspects of the present disclosure, there is provided a method for depositing a dielectric coating on a structural array of components. In various exemplary embodiments, the method for depositing a dielectric coating on a structural array of components includes depositing a first layer of a first dielectric material having a first thickness on the structural array in a spin-on coating process.

[0007] In various exemplary embodiments, the method further includes depositing a second layer of a second dielectric material onto the first layer by an evaporation process, a physical vapor deposition process (PVD), or a flux-controlled chemical vapor deposition (CVD) process.

[0008] In various exemplary embodiments, the method further includes removing at least a portion of the first layer in an etching process.

[0009] In various exemplary embodiments, a second layer of a second dielectric material is deposited on the first layer in a plasma-enhanced chemical vapor deposition (PECVD) process.

[0010] In various exemplary embodiments, the second layer has a second thickness that is greater than the first thickness.

[0011] In various exemplary embodiments, the first thickness is 300 nanometers (nm) or less and the second thickness is 5,000 nm or more.

[0012] In various exemplary embodiments, at least one feature of the plurality of features is spaced a distance from another one of the plurality of features, and a ratio between the first thickness of the first layer and the distance is at least 0.4:1 and up to 0.6:1.

[0013] In various exemplary embodiments, the ratio between the second thickness and the first thickness is at least 100:1 and up to 300:1.

[0014] In various exemplary embodiments, at least one of the first dielectric material or the second dielectric material comprises silicon dioxide (SiO 2 ).

[0015] In various exemplary embodiments, the first dielectric material and the second dielectric material are the same.

[0016] In various exemplary embodiments, the first and second dielectric materials comprise SiO 2 .

[0017] In various exemplary embodiments, the first dielectric material and the second dielectric material are different.

[0018] In various exemplary embodiments, either the first dielectric material or the second dielectric material is SiO 2 , but not both.

[0019] In various exemplary embodiments, neither the first nor the second dielectric material is SiO 2 .

[0020] In various exemplary embodiments, at least one of the first dielectric material or the second dielectric material comprises titanium dioxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ).

[0021] In various exemplary embodiments, the first and second dielectric materials comprise TiO2, Al2O3, or HfO2.

[0022] In various exemplary embodiments, one of the first or second dielectric material comprises SiO 2 , and the other of the first or second dielectric material comprises TiO 2 , Al 2 O 3 , or HfO 2 .

[0023] In various exemplary embodiments, at least one of the substrate or the structural array comprises at least one of aluminum oxide (Al2O3), titanium dioxide (TiO2), silicon (Si), or silicon nitride (Si3N4).

[0024] In various exemplary embodiments, the method further includes performing chemical mechanical planarization on the first layer before depositing a second layer of a second dielectric material on the first layer.

[0025] In various exemplary embodiments, the spin-on coating process is an ion beam spin-on glass process.

[0026] In various exemplary embodiments, the method further includes performing chemical mechanical planarization on the second layer.

[0027] In various exemplary embodiments, the method further includes depositing a first electrode on the first layer and a second electrode on the second layer.

[0028] In various exemplary embodiments, the method further includes depositing a first electrode on the second layer, depositing a third layer of a third dielectric material on the second layer with an evaporation process, a PVD process, or a flux-controlled CVD process, and depositing a second electrode on the third layer.

[0029] In various exemplary embodiments, the first electrode is a ground electrode of the ion trap and the second electrode is a control electrode of the ion trap.

[0030] In various exemplary embodiments, the first electrode is a ground electrode, a radio frequency driven electrode, or a control electrode.

[0031] In various exemplary embodiments, the second electrode is a ground electrode, a radio frequency driven electrode, or a control electrode.

[0032] In various exemplary embodiments, the first distance is defined by at least a first pair of adjacent features of the plurality of features, and the second distance is defined by at least a second pair of adjacent features of the plurality of features, the second distance being greater than the first distance.

[0033] According to aspects of the present disclosure, a method for depositing a dielectric coating on a structural array of components is provided. In various exemplary embodiments, the method for depositing a dielectric coating on a structural array of components includes depositing a first layer of a first dielectric material having a first thickness on the structural array by an atomic layer deposition (ALD) process or a spin-on coating process.

[0034] In various exemplary embodiments, the method further includes depositing a second layer of a second dielectric material over the first layer in a plasma-enhanced chemical vapor deposition (PECVD) process.

[0035] In various exemplary embodiments, the second layer has a second thickness that is greater than the first thickness.

[0036] In various exemplary embodiments, the first thickness is 300 nanometers (nm) or less and the second thickness is 5,000 nm or more.

[0037] In various exemplary embodiments, the method further includes removing at least a portion of the first layer in an etching process.

[0038] In various exemplary embodiments, at least one of the plurality of features is spaced a distance from another one of the plurality of features, and a ratio between the first thickness of the first layer and the distance is at least 0.4:1 and up to 0.6:1.

[0039] In various exemplary embodiments, the first distance is defined by at least a first pair of adjacent features of the plurality of features, and the second distance is defined by at least a second pair of adjacent features of the plurality of features, the second distance being greater than the first distance.

[0040] In various exemplary embodiments, at least one of the first dielectric material or the second dielectric material comprises silicon dioxide (SiO 2 ).

[0041] In various exemplary embodiments, at least one of the first dielectric material or the second dielectric material comprises titanium dioxide (TiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2).

[0042] In various exemplary embodiments, the electrical device is an ion trap and the component is a photonic component of the ion trap.

[0043] In various exemplary embodiments, the first thickness is less than or equal to 300 nanometers (nm) and the second thickness is greater than or equal to 5,000 nm and less than or equal to 25,000 nm.

[0044] In various exemplary embodiments, the ratio between the second thickness and the first thickness is at least 100:1 and up to 300:1.

[0045] According to another aspect, an electrical device is provided. In an exemplary embodiment, the electrical device includes a component. The component includes a structural array and a dielectric coating disposed on the structural array. The structural array includes a plurality of features, each of the plurality of features having an aspect ratio of at least 1:1. The dielectric coating includes a first layer of a first dielectric material having a first thickness and a first refractive index; and a second layer of a second dielectric material having a second thickness and a second refractive index, the second thickness being greater than the thickness of the first layer. The first layer is positioned between the structural array and the second layer, and a percent difference between the first refractive index and the second refractive index is greater than 0 and up to 0.5 percent.

[0046] In various exemplary embodiments, the first refractive index of the first layer is substantially uniform throughout the first layer.

[0047] In various exemplary embodiments, the second refractive index of the second layer is substantially uniform throughout the second layer.

[0048] In various exemplary embodiments, the component further includes a first electrode positioned between the first layer and the second layer.

[0049] In various exemplary embodiments, the component further includes a second electrode positioned on the second layer.

[0050] In various exemplary embodiments, at least one feature of the plurality of features is spaced a distance from another one of the plurality of features, and a ratio between the first thickness of the first layer and the distance is at least 0.4:1 and up to 0.6:1.

[0051] In various exemplary embodiments, the first distance is defined by at least a first pair of adjacent features of the plurality of features, and the second distance is defined by at least a second pair of adjacent features of the plurality of features, the second distance being greater than the first distance.

[0052] In various exemplary embodiments, at least one of the first dielectric material or the second dielectric material comprises silicon dioxide (SiO 2 ).

[0053] In various exemplary embodiments, the first dielectric material and the second dielectric material are the same.

[0054] In various exemplary embodiments, the first dielectric material and the second dielectric material are different.

[0055] In various exemplary embodiments, the component includes a substrate including at least one of aluminum oxide (Al2O3), titanium dioxide (TiO2), silicon (Si), or silicon nitride (Si3N4).

[0056] In various exemplary embodiments, the electrical device is an ion trap and the component is a photonic component of the ion trap.

[0057] In various exemplary embodiments, the first thickness is less than or equal to 300 nanometers (nm) and the second thickness is greater than or equal to 5,000 nm and less than or equal to 20,000 nm.

[0058] Having thus generally described the invention, reference is now made to the accompanying drawings, which are not necessarily drawn to scale. [Brief explanation of the drawings]

[0059] [Figure 1] 1 is a schematic diagram of an electrical device in accordance with an exemplary embodiment. [Figure 2A] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 2B] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 2C] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 3A]1 is a schematic diagram of a portion of a component with a prior art dielectric coating disposed thereon; [Figure 3B] 1 is a schematic diagram of a portion of a component with a prior art dielectric coating disposed thereon; [Figure 4A] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 4B] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 5] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 6] 1 is a schematic diagram of components of an electrical device according to an illustrative embodiment; [Figure 7] 1 is a schematic diagram of an electrical device in accordance with an exemplary embodiment. [Figure 8A] 1 is a flowchart of a method for depositing a dielectric coating on a component in accordance with an illustrative embodiment. [Figure 8B] 1 is a flowchart of a method for depositing a dielectric coating on a component in accordance with an illustrative embodiment. [Figure 9] 1 is a flowchart of a method for depositing a dielectric coating on a component in accordance with an illustrative embodiment. [Figure 10] 1 is a flowchart of a method for depositing a dielectric coating on a component in accordance with an illustrative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0060] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the invention are shown. Indeed, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The word "or" (also indicated as " / ") is used herein in both the alternative and conjunctive sense, unless otherwise indicated. The terms "exemplary" and "specific" are used as examples without indication of a level of quality. The terms "generally," "substantially," and "approximately" refer to being within design and / or manufacturing tolerances and / or the user's measurement capabilities, unless otherwise indicated. Like numbers refer to like elements throughout.

[0061] Referring now to FIG. 1 , a schematic diagram of an electrical device 100 is provided in accordance with an illustrative embodiment. The electrical device 100 defines an X-direction, a Y-direction orthogonal to the X-direction, and a Z-direction (into and out of the page) orthogonal to the X-direction and the Y-direction. As shown, the electrical device 100 includes a component 200. The component 200 can include a structural array 210 formed on or integrally with a substrate 205 of the component 200. In various examples, the component includes a sublayer on which the structural array 210 is formed on or integrally with the substrate 205. The structural array 210 can include a plurality of features 220. Additionally, the component 200 can include a dielectric coating 300 disposed on the structural array 210 of the component 200.

[0062] As discussed further, applying the dielectric coating 300 using traditional methods can result in defects and / or imperfections. For example, applying the dielectric coating 300 using traditional methods can result in the presence of voids or keyholes in the dielectric coating 300. These defects and / or imperfections can cause the refractive index of the dielectric coating 300 to be inconsistent and / or non-uniform throughout the dielectric coating 300, resulting in optical losses for light beams passing therethrough. The methods described herein can result in the reduction and / or elimination of these defects and / or imperfections. As a result, the methods described herein can result in the application of the dielectric coating 300 to the component 200 having a more uniform and / or more consistent refractive index of the dielectric coating 300.

[0063] In the embodiment of FIG. 1 , the electrical device 100 is an ion trap that can be configured to trap at least one atomic ion 150. The electrical device 100 can include a waveguide 160 that can pass light 120 from at least one laser beam to the component 200. In various embodiments, the component 200 is a photonic component or an integrated optical component. For example, the component 200 can be a photonic component such as a photonic coupling element, which can be a device that couples light from a guided mode into a free-space propagation mode. The component 200 can also be a diffraction grating of the ion trap that can be integrated into the ion trap to focus and direct light 120 from at least one laser beam into a trapping zone 170 that traps at least one atomic ion 150. In various embodiments, the grating or photonic component is etched onto a substrate 205 of the component 200 or one or more sublayers formed on the substrate 205 of the component 200.

[0064] Although various embodiments have been and will be provided in which electrical device 100 is an ion trap and component 200 is an integrated optical component for the ion trap (e.g., a photonic component, such as a photonic coupling element), it should be understood that other embodiments of electrical device 100 and component 200 are contemplated. For example, component 200 can be a photonic component, such as a metasurface for an optical device. For example, component 200 can be a lens, a quarter- or half-wave plate metasurface, a spatial beam-shaping metasurface, a beam-steering metasurface, a lens for an image sensor, a camera, a microscope, a laser beam splitter, or a color filter. In various embodiments, component 200 can be a diffractive optical phase array or a hologram (e.g., a lens hologram, a beam-steering grade array, or a spatial beam-shaping hologram). In still other embodiments, component 200 can be a metasurface for an antenna or an acoustic absorption device. In still other embodiments, component 200 may be a ring resonator, a power modulator, a waveguide, an input taper, a splitter (eg, a multi-mode interference (MMI) or y-branch), or a directional coupler.

[0065] In various embodiments, substrate 205 can be formed from a dielectric material. For example, substrate 205 can be formed from at least one of aluminum oxide (Al2O3), titanium dioxide (TiO2), silicon (Si), or silicon nitride (Si3N4). In various embodiments, structural array 210 and / or plurality of features 220 can be formed from a dielectric material. For example, structural array 210 and / or plurality of features 220 can be formed from at least one of Al2O3, TiO2, Si, or Si3N4. Furthermore, dielectric coating 300 can be formed from a dielectric material. For example, dielectric coating 300 can be formed from or include silicon dioxide (SiO2), titanium oxide (TiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2).

[0066] 2A , a schematic diagram of a component 200 of an electrical device 100 is provided in accordance with an exemplary embodiment. As mentioned, the component 200 may include a structural array 210, which may include a plurality of features 220. Each of the plurality of features 220 may define a ridge 226 extending generally in the X-direction. Further, each of the plurality of features 220 may define at least two walls 222, each extending generally in the Y-direction. The structural array 210 may define one or more bases 224 disposed between at least two of the features 220 of the plurality of features 220. Further, the structural array 210 may define at least one trench 230 defined between two adjacent features 220. Each of the plurality of features 220 may have a height H and a width W and may have an aspect ratio (H:W). Additionally, each of the plurality of features 220 may be spaced a distance D from adjacent features of the plurality of features 220 .

[0067] 2B , a schematic diagram of a component 200 of an electrical device 100 is provided in accordance with an exemplary embodiment. In various examples, each of the plurality of features 220 can define at least one wall 222, such as at least two walls 222, that extends at an acute angle relative to the X direction (also referred to herein as a “re-entrant profile”). A trench 230 defined between two adjacent features 220 can generally have a trapezoidal cross-section, such as an isosceles trapezoidal cross-section. A ridge 226 of adjacent features 220 can define a distance D between adjacent features of the plurality of features 220. A bottom 224 disposed between two of the features 220 can define a trench width TW. The trench width TW defined between two of the features 220 can be greater than the distance D defined between those features.

[0068] 2C , a schematic diagram of a component 200 of an electrical device 100 is provided, according to an example embodiment. In various examples, the distance between adjacent features 220 of the plurality of features 220 may vary. For example, a first feature 220a and an adjacent second feature 220b may define a first distance D1, whereas the second feature 220b and an adjacent third feature 220c may define a second distance D2 that is not equal to the first distance D1. In various examples, the third feature 220c and an adjacent fourth feature 220d may define a third distance D3 that is not equal to the first distance D1 and the second distance D2. Similarly, the trench width TW defined between adjacent features 220 of the plurality of features 200 may vary. For example, a first feature 220a and an adjacent second feature 220b can define a first trench width TW1, while the second feature 220b and an adjacent third feature 220c can define a second trench width TW2 that is not equal to the first trench width TW1. In various embodiments, the third feature 220c and an adjacent fourth feature 220d can define a third trench width TW3 that is not equal to the first trench width TW1 and the second trench width TW2.

[0069] 3A and 3B, schematic illustrations of a structural array 210' of components 220' having a prior art dielectric coating 300' disposed thereon are provided. As mentioned, thick prior art dielectric coatings 300' have traditionally been applied to the structural array 210' of components 200' with an evaporation process or a flux-controlled deposition process. For example, thick prior art dielectric coatings 300' have traditionally been applied to the structural array 210' with an evaporation process, a physical vapor deposition (PVD) process (e.g., sputter deposition), or a flux-controlled chemical vapor deposition (CVD) process (e.g., a plasma-enhanced chemical vapor deposition (PECVD) process). However, evaporation processes, PVD processes, and flux-controlled CVD processes may not provide acceptable coverage and / or quality of the thick dielectric coating 300' on the structural array 210' of components 200'.

[0070] For example, PVD and flux-controlled CVD processes rely on local gas flux. Therefore, the flux of reactant molecules may be greater near the entrance of the trench 230′ defined between two adjacent features 220′. The entrance of the trench 230′ may therefore become clogged, making it difficult for the reactant molecules to diffuse deeper within the trench 230′. As a result, PVD and flux-controlled CVD processes may result in a dielectric coating 300′ with a thickness that varies at different locations when applied directly to the structural array 210′. For example, as shown in FIG. 3A , the thickness of the dielectric coating 300′ disposed on the ridges 226′ of the plurality of features 220′ may be greater than the thickness of the dielectric coating 300′ disposed on the walls 222′ and / or bottoms 224′ of the plurality of features 220′ when the dielectric coating 300′ is disposed directly on the structural array 210′ ​​using a PVD or flux-controlled CVD process. Additionally, or alternatively, as shown in FIG. 3B, material of the dielectric coating 300′ may accumulate at the intersections of the ridges 226′ and respective walls 222′ of the plurality of features 220′ when the dielectric coating 300′ is deposited directly on the structural array 210′ ​​in a PVD or flux-controlled CVD process.

[0071] As a result of the buildup of material in the dielectric coating 300′ and / or the varying thickness of the dielectric coating 300′, defects 240′, such as voids or keyholes, may form in the trenches 230′ defined between each of the plurality of features 220′. These defects 240′, the varying thickness of the dielectric coating 300′, and / or the buildup of material in the dielectric coating 300′ may be undesirable. For example, when the component 200′ is a grating of an ion trap, the presence of defects 240′, the varying thickness of the dielectric coating 300′, and / or the buildup of material in the dielectric coating 300′ may cause the diffraction efficiency (DE) and / or refractive index of the grating to be reduced and / or non-uniform throughout the dielectric coating 300′. As another example, when the component 200′ is a grating of an ion trap, the defects 240′, the varying thickness of the dielectric coating 300′, and / or the buildup of material in the dielectric coating 300′ may cause scattering points ( FIG. 1 ) that can distort the light 120 emitted by the grating. Furthermore, these defects 240′, varying thickness of the dielectric coating 300′, and / or accumulation of material in the dielectric coating 300′ may occur more frequently when the aspect ratio (H:W (FIG. 2A)) of the plurality of features 220′ is at least 1:1, for example, at least 1:1 to 10:1.

[0072] Accordingly, an improved method for applying a dielectric coating 300 onto a structural array 210 of components 200 of an electrical device 100 would be welcome in the art. More particularly, a method for applying a dielectric coating 300 onto a structural array 210 of components 200 of an electrical device 100 having a plurality of features 220 each having an aspect ratio (H:W) of at least 1:1 would be welcome in the art. This method, and the resulting components 200, are discussed in further detail below.

[0073] 4A, a schematic diagram of component 200 is provided in accordance with an exemplary embodiment. Component 200 may include a structural array 210 and may be configured the same as or similar to component 200 of FIG. 2A. However, in this example, component 200 includes a dielectric coating 300 disposed on structural array 210.

[0074] 4A , the dielectric coating 300 can include a first layer 310 of a first dielectric material 312. The first layer 310 can have a first thickness T1 and can have a first refractive index. As shown, the first thickness T1 is defined by the thickness of the first layer 310 over one protrusion 226 of the feature 220. In various embodiments, the first refractive index of the first layer 310 is uniform or substantially uniform throughout the first layer 310. For example, the first refractive index of the first layer 310 can vary by less than 0.3 percent throughout the first layer 310, such as by less than 0.2 percent, such as by less than 0.1 percent. In various embodiments, the first dielectric material 312 is or includes SiO2. In various embodiments, the first layer 310 of the dielectric coating 300 is applied onto the structural array 210 in an atomic layer deposition (ALD) process (e.g., plasma-enhanced ALD or thermal ALD). In various other embodiments, the first layer 310 of the dielectric coating 300 is applied onto the structural array 210 in a PVD or high-density plasma chemical vapor deposition (HD-PECVD) process. In various embodiments, the first layer 310 of the dielectric coating 300 is applied onto the structural array 210 in a spin-on coating process.

[0075] The ALD process is a deposition technique that can deposit highly conformal coatings on substrates and / or structural arrays at controlled thicknesses. The ALD process can include adding a first precursor to a reaction chamber containing the substrate and / or structural array to be coated. After the first precursor is absorbed by the substrate and / or structural array, the first precursor can be removed from the reaction chamber, and a second precursor can be added to the chamber to react with the first precursor, creating a layer on the surface of the substrate and / or structural array. The second precursor can then be removed from the reaction chamber, and the process can be repeated until a coating of the desired thickness is achieved. The ALD process is not a "line-of-site" deposition technique, nor is it a flux-controlled deposition technique, and therefore may have the ability to "grow" uniform coatings on substrates and / or structural arrays containing complex shapes and / or high-aspect features.

[0076] In various embodiments, the coating material may include SiO2, polydimethylsiloxane (PDMS), hydrogen silsesquioxane (HSQ), or sol-gel, which may be a solution of metal oxide precursors condensed into a 3D network. In various embodiments, the spin-on coating process is a spin-on-glass process. Spin-on-glass may be a mixture of SiO2 and a dopant, such as boron or phosphorus, suspended in a solvent solution. The spin-on-glass process is a deposition technique that deposits highly conformal coatings on substrates and / or structural arrays with controlled thicknesses. The spin-on-glass process may include spinning the substrate 205 or the structural array 210 formed on one or more sublayers on the substrate 205 at a rotational speed of at least 100 revolutions per minute (rpm) to 2,000 rpm, e.g., up to 1,000 rpm, e.g., up to 400 rpm. Once structural array 210 is rotated, a volume of spin-on-glass material, such as HONEYWELL'S ACCUGLASS spin-on-glass material, can be dispensed onto structural array 210. Once the spin-on-glass material is dispensed onto structural array 210, the rotation speed of structural array 210 can be increased up to 5,000 rpm, such as up to 4,000 rpm, such as up to 3,000 rpm. The spin-on-glass process can include curing the spin-on-glass material at a temperature of at least 375 degrees Celsius (°C) and up to 425°C for about one hour in a nitrogen environment / atmosphere.

[0077] Compared to PVD and / or flux-controlled CVD processes, ALD and / or spin-on coating processes may be capable of depositing more uniform coatings on high-aspect features, such as feature 220. As used herein, the term "high-aspect feature" refers to a feature having an aspect ratio (H:W) of at least 1:1, e.g., at least 1:1 to 10:1, e.g., at least 1:1 to 5:1, respectively. Some examples of high-aspect features are features having an aspect ratio (H:W) of at least 1:1 to 4:1, at least 1:1 to 3:1, at least 1:1 to 2:1, at least 2:1 to 5:1, at least 2:1 to 4:1, at least 3:1 to 5:1, at least 3:1 to 4:1, at least 4:1 to 8:1, or at least 5:1 to 7:1, to name a few.

[0078] 4A , each feature of the plurality of features 220 may be a high-aspect feature having an aspect ratio (H:W) of at least 1:1. Therefore, as previously discussed, it may be beneficial to apply the first layer 310 of the dielectric coating 300 by an ALD process or a spin-on coating process, as opposed to a PVD or flux-controlled CVD process. In the embodiment of FIG. 4A and various other embodiments, the first layer 310 of the dielectric coating 300 is applied by an ALD process or a spin-on coating process.

[0079] 4A , in various embodiments, the thickness T1 of the first layer 310 can be approximately half of the distance D between one of the plurality of features 220 and an adjacent one of the plurality of features 220. Stated another way, the ratio between the thickness T1 of the first layer 310 and the distance D between one of the plurality of features 220 and an adjacent one of the plurality of features 220 (T1:D) is about 0.5:1, such as at least 0.3:1 to 0.7:1, such as at least 0.4:1 to 0.6:1.

[0080] Having a T1:D ratio of about 0.5:1 can be beneficial for several reasons. First, having a T1:D ratio of about 0.5:1 can ensure that the trenches 230 defined between the features 220 are substantially or completely filled with the first layer 310 of the dielectric coating 300. Second, having a T1:D ratio of about 0.5:1 can ensure that the thickness T1 is uniform throughout the component 200. For example, having a T1:D ratio of about 0.5:1 can ensure that the thickness T1 of the first layer 310 of the dielectric coating 300 on the walls 222 of the features 220 is substantially similar (e.g., within 1 percent) to the thickness T1 of the first layer 310 of the dielectric coating 300 on the ridges 226 of the features 220 and / or on the bottoms 224 of the trenches 230.

[0081] In various embodiments, the thickness T1 of the first layer 310 can be greater than the height H of at least one of the features 220. Stated another way, the ratio between the thickness T1 of the first layer 310 and the height H of at least one of the features 220 (T1:H) can be at least 1:1. For example, the T1:H ratio can be at least 1:1 to 5:1, such as at least 1:1 to 3:1, such as at least 1:1 to 2:1. In various embodiments, having a T1:H ratio of at least 1:1 can ensure that the trenches 230 between each of the features 220 are substantially or completely filled with the first layer 310 of the dielectric coating.

[0082] 4B, a schematic diagram of a component 200 is provided in accordance with an example embodiment. The component 200 may include a structural array 210 and may be configured the same as or similar to the component 200 of FIG. 2C. However, in this example, the component 200 includes a dielectric coating 300 disposed on the structural array 210. The dielectric coating 300 may include a first layer 310 of a first dielectric material 312. The first layer 310 may have a first thickness T1 and may have a first refractive index. As shown, the first thickness T1 is defined by the thickness of the first layer 310 on one ridge 226 of the feature 220. In various examples, the thickness T1 of the first layer 310 of the dielectric coating 300 on the wall 222 of the feature 220 is substantially similar (e.g., within 1 percent) to the thickness T1 of the first layer 310 of the dielectric coating 300 on the ridge 226 of the feature 220 and / or on the bottom 224 of the trench 230.

[0083] When the distances D1, D2, and D3 between adjacent features 220 vary such that at least one of the distances D1, D2, and D3 is different from another one of the distances D1, D2, and D3, the trench between each of the features 220 may not be completely filled. Accordingly, one or more gaps 314 may be formed between the first layer 310 of the dielectric coating 330 of adjacent features, such as feature 220c and feature 220d. For example, when the ratio (D:T1) between the distance D between the features and the first thickness T1 of the first layer 310 is greater than 2:1, the gaps 314 may be formed between those features 220. Also, when the ratio (TW:T1) between the trench width TW and the first thickness T1 of the first layer 310 is greater than 2:1, the gaps 314 may be formed between those features 220.

[0084] As will be discussed further, a second layer 320 of a second dielectric material 322 can be applied to the first layer 310 of the first dielectric material 312. Prior to applying the second layer 320 of the second dielectric material 322, an etching process can be performed on the first layer 310. Performing the etching process on the first layer 310 can remove the layer of the first dielectric material 312. In various embodiments, an ion beam etching process can be performed on the first layer 310. The ion beam etching process can include accelerating an ion beam at the first layer 310 in a low-pressure environment. The accelerated ions can transfer their kinetic energy to the first layer 310, causing the layer of first dielectric material 312 to be ejected and removed.

[0085] Performing an etching process on the first layer 310 when gaps 314 are formed in the first layer 310 may widen the gaps 314, which may be beneficial when a second layer 320 is subsequently applied to the first layer 310. For example, performing an etching process to widen the gaps 314 may increase the likelihood that the second layer 320 will be able to completely fill the gaps 314.

[0086] 5, a schematic diagram of a component 200 of the electrical device 100 of FIG. 1 is provided, according to an exemplary embodiment. The component 200 of FIG. 5 may be configured similarly or identically to the component 200 of FIG. 4A. However, in this example, the thickness T3 of the first layer 310 on the wall 222 of the feature 220 is different from the thickness T1 on the ridge 226 of the feature 220. More specifically, the thickness T3 of the first layer 310 on the wall 222 of the feature 220 is less than the thickness T1 on the ridge 226 of the feature 220. In various embodiments, the ratio (T3:D) between the thickness T3 of the first layer 310 on the wall 222 of the feature 220 and the distance D between one of the plurality of features 220 and an adjacent one of the plurality of features 220 is about 0.5:1, such as at least 0.3:1 to 0.7:1, such as at least 0.4:1 to 0.6:1, whereas the ratio (T1:D) between the thickness T1 of the first layer 310 on the ridge 226 of the feature 220 and the distance D between one of the plurality of features 220 and an adjacent one of the plurality of features 220 is greater than 0.5:1, such as greater than 0.5:1 and up to 4:1, such as greater than 0.5:1 and up to 2:1, such as greater than 0.5:1 and up to 1:1.

[0087] Having a T3:D ratio of about 0.5:1 and a T1:D ratio greater than 0.5:1 has several benefits. First, the thickness T3 of the first layer 310 is large enough to substantially or completely fill the trenches 230 between the features 220. Furthermore, once the thickness of the first layer 310 exceeds half of the distance D (as indicated by the sublayer 311), the first dielectric material 312 deposited after the sublayer 311 may no longer be needed to fill the trenches 230, creating a more uniform surface along the plane defined by the X and Z directions.

[0088] 5, each of the plurality of features 220 can have an aspect ratio (H:W) of at least 1:1, such as at least 1:1 to 10:1, as discussed above. In various embodiments, the height H of each of the plurality of features 220 is at least 1000 nanometers (nm) to 500 nm, such as at least 150 nm to 300 nm, such as at least 200 nm to 250 nm.

[0089] Also noted, component 200 can have a T3:D ratio of about 0.5: 1. In various embodiments, thickness T3 can be at least 100 nm to 500 nm, such as at least 150 nm to 300 nm, such as at least 200 nm to 250 nm.

[0090] Furthermore, as previously mentioned, component 200 can have a T1:D ratio of greater than 0.5: 1. In various embodiments, thickness T1 can be at least 100 nm to 1,000 nm, such as at least 100 nm to 800 nm, such as at least 100 nm to 500 nm, such as at least 100 nm to 400 nm, such as at least 200 nm to 400 nm.

[0091] 6, a schematic diagram of a component 200 of the electrical device 100 of FIG. 1 is provided, according to an exemplary embodiment. The component 200 may include a dielectric coating 300 disposed on a structural array 210 and may be configured the same as or similar to the component 200 of FIG. 4A or FIG. 5. However, in this example, the dielectric coating 300 includes a first layer 310 of a first dielectric material 312 as well as a second layer 320 of a second dielectric material 322.

[0092] The second layer 320 has a second thickness T2 and a second refractive index. In various embodiments, the second dielectric material 322 can be or include SiO2. In various embodiments, the second layer 320 of the dielectric coating 300 can be applied to the first layer 310 with a deposition process that is not an ALD process or a spin-on coating process. In various embodiments, the second layer 320 of the dielectric coating 300 can be applied to the first layer 310 with an evaporation process, a PVD process, or a flux-controlled CVD process. For example, the second layer 320 of the dielectric coating 300 can be applied to the first layer 310 with a PECVD process. In various embodiments, the second refractive index of the second layer 320 is uniform or substantially uniform throughout the second layer 320. For example, the second refractive index of the second layer 320 may vary by less than 0.3 percent across the second layer 320, such as by less than 0.2 percent, such as by less than 0.1 percent.

[0093] In various embodiments, the second thickness T2 of the second layer 320 can be greater than the first thickness T1 of the first layer 310. In other words, the ratio between the second thickness T2 and the first thickness T1 (T2:T1) can be greater than 1:1, such as at least 1:1 to 300:1, such as at least 1:1 to 250:1, such as at least 1:1 to 150:1, such as at least 1:1 to 100:1, such as at least 10:1 to 100:1. For example, the T2:T1 ratio can be at least 100:1 to 300:1, at least 100:1 to 300:1, at least 100:1 to 200:1, at least 150:1 to 200:1, or at least 200:1 to 300:1, for example.

[0094] In various embodiments, the second thickness T2 of the second layer 320 can be approximately equal to the first thickness T1 of the first layer 310. For example, the second thickness T2 can be within 10 percent, e.g., within 5 percent, e.g., within 2 percent of the thickness of the first thickness T1.

[0095] In various embodiments, the second thickness T2 of the second layer 320 can be at least 5,000 nm, such as at least 5,000 nm to 30,000 nm. For example, the thickness T2 of the second layer 320 can be at least 5,000 nm to 25,000 nm, at least 10,000 nm to 30,000 nm, or at least 5,000 to 10,000 nm, for example.

[0096] As mentioned, the first layer 310 of the dielectric coating 300 can be applied by an ALD process or a spin-on coating process, while the second layer 320 of the dielectric coating 300 can be applied by an evaporation process, a PVD process, or a flux-controlled CVD process. In various embodiments, the first dielectric material 312 of the first layer 310 can be the same as the second dielectric material 322 of the second layer 320. For example, the first dielectric material 312 of the first layer 310 and the second dielectric material of the second layer 320 can both be or include SiO2. However, even if the first dielectric material 312 of the first layer 310 is the same as the second dielectric material 322 of the second layer 320, the first refractive index (n1) of the first layer 310 may be different from the second refractive index (n2) of the second layer 320 when the first layer 310 is deposited by an ALD process or a spin-on coating process and when the second layer 320 is deposited by an evaporation process, a PVD process, or a flux-controlled CVD process. As will be appreciated, materials deposited by an ALD process or a spin-on coating process may have a different refractive index than materials deposited by an evaporation process, a PVD process, or a flux-controlled CVD process, even when the deposited materials are the same. Thus, the first refractive index (n1) of the first layer 310 may be different from the second refractive index (n2) of the second layer 320. For example, the percent difference between the first refractive index (n1) and the second refractive index (n2) may be greater than 0 and up to 0.5 percent, and the percent difference between the first refractive index (n1) and the second refractive index (n2) is calculated by the formula (|n1-n2|) / ((n1+n2) / 2)×100.

[0097] In various embodiments, the first refractive index (n1) of the first layer 310 may be greater than the second refractive index (n2) of the second layer 320. For example, the first refractive index (n1) may be at least 0.5 to 10 percent greater than the second refractive index (n2). In various embodiments, the second refractive index (n2) of the second layer 320 may be greater than the first refractive index (n1) of the first layer 310. For example, the second refractive index (n2) may be at least 0.5 to 10 percent greater than the first refractive index (n1).

[0098] In various embodiments, the refractive index (n0) of substrate 205 and / or structural array 220 can be different from the first refractive index (n1) of first layer 310 and / or the second refractive index (n2) of second layer 320. For example, the percent difference between the refractive index (n0) of substrate 205 and / or structural array 210 and the first refractive index (n1) and / or second refractive index (n2) can be greater than 5 percent, such as at least 15 percent to 150 percent, such as at least 15 percent to 100 percent, such as at least 20 percent to 30 percent.

[0099] As will be appreciated, applying the first layer 310 of the dielectric coating 300 by an ALD or spin-on coating process and applying the second layer 320 of the dielectric coating 300 by an evaporation, PVD, or flux-controlled CVD process has several benefits. First, as explained, an ALD or spin-on coating process can provide high conformality, especially for high-aspect features. Thus, applying the first layer 310 of the dielectric coating 300 by an ALD or spin-on coating process can deposit the dielectric coating 300 with relatively high conformality compared to when the dielectric coating 300 is deposited solely by an evaporation, PVD, or flux-controlled CVD process. In various embodiments, a spin-on coating process can deposit the dielectric coating 300 with relatively high conformality and substantially or completely fill trenches between features with a re-entry profile.

[0100] Second, evaporation, PVD, and flux-controlled CVD processes can be faster and less expensive than ALD or spin-on coating processes. Thus, depositing the second layer 320 of the dielectric coating 300 with an evaporation, PVD, or flux-controlled CVD process can deposit the dielectric coating 300 more quickly and inexpensively than if only an ALD or spin-on coating process were used. Thus, depositing the first layer 310 of the dielectric coating 300 with an ALD or spin-on coating process and the second layer 320 of the dielectric coating 300 with an evaporation, PVD, or flux-controlled CVD process may result in depositing the dielectric coating 300 on the component 200 more quickly, inexpensively, and / or more flexibly than if only one of an ALD, spin-on coating, evaporation, PVD, or flux-controlled CVD process were used.

[0101] 7, a schematic diagram of an electrical device 100 is provided in accordance with an exemplary embodiment. The electrical device 100 of FIG. 7 may be configured the same as or similar to the electrical device 100 of FIG. 1. In this example, the electrical device 100 is an ion trap and includes a dielectric coating 300 that includes a first layer 310 and a second layer 320. The dielectric coating 300 of FIG. 7 may be configured the same as or similar to the dielectric coating 300 previously described with respect to FIG. 6.

[0102] 7 , the dielectric device 100 can include at least two electrodes 401. For example, the electric device 100 can include a first electrode 401a positioned between the first layer 310 and the second layer 320 of the dielectric coating 300 and a second electrode 401b positioned on the second layer 320 of the dielectric coating 300. In some embodiments, the electric device 100 can include more than two electrodes 401, for example, at least four electrodes 401. For example, the electric device 100 can include a first electrode 401a, a second electrode 401b, a third electrode 401c on the second layer 320 of the dielectric coating 300, and a fourth electrode 401d positioned between the first layer 310 and the second layer 320 of the dielectric coating 300.

[0103] In other embodiments, the electrical device 100 may not include an electrode 401 between the first layer 310 and the second layer 320. For example, the electrical device 100 may include at least one electrode 401, such as a first electrode 401a, positioned on the second layer 320 of the dielectric coating 300, and at least one electrode 401, such as a second electrode 401b, positioned on a third layer (not shown) of the dielectric coating 300.

[0104] When component 200 is an ion trap, for example, electrode 401 can be positioned to form window 410. In the embodiment of Figure 7, first electrode 401a and fourth electrode 401d are spaced apart a sufficient distance on first layer 310 of dielectric coating 300 so that light 120 can be directed from component 200, which in this embodiment is the lattice of an ion trap, into trapping zone 170 to trap at least one atomic ion 150. Additionally, second electrode 401b and third electrode 401c are spaced apart a sufficient distance on second layer 320 of dielectric coating 300 so that light 120 can be directed from component 200 into trapping zone 170.

[0105] In various embodiments, at least one of the electrodes 401 can be configured as a ground electrode, and another of the electrodes 401 can be configured as a control electrode or a radio frequency drive electrode. For example, electrode 401a and / or electrode 401d can be configured as a ground electrode, and electrode 401b and / or electrode 401c can be configured as a control electrode or a radio frequency drive electrode. As will be appreciated, providing sufficient insulation between the ground electrode and the control electrode or radio frequency drive electrode can be beneficial. As will also be appreciated, a dielectric material, such as second dielectric material 322 of second layer 320 of dielectric coating 300, can provide sufficient insulation between the ground electrode and the control electrode. In various embodiments, thickness T2 of second layer 320 of dielectric coating 300 can be adjusted to provide a sufficient amount of insulation between at least one ground electrode, such as electrode 401a and / or 401d, and at least one control electrode, such as electrode 401b or electrode 401c.

[0106] 8A , a flowchart of a method 800 for depositing a dielectric coating 300 on a structural array 210 of components 200 of an electrical device 100, such as the components 200 of FIG. 6 , is provided, according to an illustrative embodiment. In various examples, the structural array 210 can be formed on a substrate 205 or on one or more sublayers, and the structural array 210 can have a plurality of features 220. The method 800 can include depositing 810 a first layer 310 of a first dielectric material 312 on the structural array 210 using an ALD process. The method can also include performing 815 an etching process, such as an ion beam etching process, on the first layer. The method 800 can further include depositing 830 a second layer 320 of a second dielectric material 322 on the first layer 310 using an evaporation process, a PVD process, or a flux-controlled CVD process. In various examples, the second layer 320 has a second thickness greater than the first thickness. In various embodiments, the method 800 may include performing chemical mechanical planarization on the first layer 310 before depositing the second layer 320 of the second dielectric material 322 on the first layer 310. Performing chemical mechanical planarization on the first layer 310 may provide better adhesion of the second layer 320 to the first layer 310. In various embodiments, the method 800 may include performing chemical mechanical planarization on the second layer 320.

[0107] 8B , a flowchart of a method 850 for depositing a dielectric coating 300 on a structural array 210 of a component 200 of an electrical device 100 is provided, according to an illustrative embodiment. In various examples, the structural array 210 can be formed on a substrate 205 or on one or more sublayers formed on the substrate 205, and the structural array 210 can have a plurality of features 220. The method 850 can include step 811 of depositing a first layer 310 of a first dielectric material 312 on the structural array 210 via a spin-on coating process. The method 800 can include step 830 of depositing a second layer 320 of a second dielectric material 322 on the first layer 310 via an evaporation process, a PVD process, or a flux-controlled CVD process. In various examples, the second layer 320 has a second thickness greater than the first thickness. In various embodiments, the method 850 may include performing chemical mechanical planarization on the first layer 310 before depositing the second layer 320 of the second dielectric material 322 on the first layer 310. Performing chemical mechanical planarization on the first layer 310 may provide better adhesion of the second layer 320 to the first layer 310. In various embodiments, the method 850 may include performing chemical mechanical planarization on the second layer 320.

[0108] 9, a flowchart is provided of a method 900 for applying a dielectric coating 300 onto a structural array 210 of a component 200 of an electrical device 100, such as the electrical device 100 of FIG. 7, according to an illustrative embodiment. Method 900 may be the same as or similar to method 800 of FIG. 8A, including step 810 or method 850 of FIG. 8B, and includes step 811. However, method 900 further includes step 820 of depositing a first electrode 401a onto the first layer 310 after step 820. In addition, method 900 further includes step 840 of depositing a second electrode 401b onto the second layer 320 after step 830.

[0109] 10 , a flowchart is provided of a method 900 for depositing a dielectric coating 300 on a structural array 210 of a component 200 of an electrical device 100, such as the electrical device 100 of FIG. 7 , according to an illustrative embodiment. Method 950 may be the same as or similar to method 800 of FIG. 8A and include step 810 or method 850 of FIG. 8B , including step 811. However, method 950 may include step 835 of depositing a first electrode 401 a on the second layer 320. Additionally, method 950 may include step 845 of depositing a third layer of a second dielectric material 322 on the second layer 320 by an evaporation process, a PVD process, or a flux-controlled CVD process. Method 950 may also include step 855 of depositing a second electrode 401 b on the third layer.

[0110] Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. It is to be understood, therefore, that the inventions are not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation. [Explanation of symbols]

[0111] 100 Electrical Devices 200 components 205 Base material 210 Structural Array 220 features 222 Wall 224 Bottom 226 Prominence 230 Trench 300 dielectric coating 310 First Layer 312 first dielectric material 320 Second Layer 401a first electrode 401b Second electrode 401c Third electrode 401d Fourth electrode

Claims

1. 1. A method of depositing a dielectric coating onto a structural array of components of an electrical device, the structural array having a plurality of features, the method comprising: depositing a first layer of a first dielectric material onto the structural array in a spin-on coating process, the first layer having a first thickness; A method comprising:

2. At least one of the substrate or the structural array is aluminum oxide (Al ２ O ３ ), titanium dioxide (TiO ２ ), silicon (Si), or silicon nitride (Si ３ N ４ 2. The method of claim 1, comprising at least one of:

3. The method of claim 1 , wherein the electrical device is an ion trap and the component is a photonic component of the ion trap.

4. 10. The method of claim 1, wherein at least one feature of the plurality of features is spaced a distance from another one of the plurality of features, and wherein a ratio between the first thickness of the first layer and the distance is at least 0.4:1 and up to 0.6:

1.

5. 10. The method of claim 1, further comprising depositing a second layer of a second dielectric material on the first layer by an evaporation process, a physical vapor deposition process (PVD), or a flux-controlled chemical vapor deposition (CVD) process, the second layer having a second thickness greater than the first thickness.

6. At least one of the first dielectric material or the second dielectric material is silicon dioxide (SiO ２ 6. The method of claim 5, comprising:

7. 6. The method of claim 5, wherein the first dielectric material has a first refractive index and the second dielectric material has a second refractive index, and one of the first refractive index or the second refractive index is greater than the other of the first refractive index or the second refractive index.

8. 6. The method of claim 5, wherein the first dielectric material has a first refractive index and the second dielectric material has a second refractive index, and the percent difference between the first refractive index and the second refractive index is less than 0.5 percent.

9. The method of claim 5 , wherein the first dielectric material and the second dielectric material are the same.

10. The method of claim 5 , wherein the first dielectric material and the second dielectric material are different.

11. The method of claim 5 , wherein the spin-on coating process is an ion beam spin-on glass process.

12. 6. The method of claim 5, wherein a ratio (T1:H) between the first thickness of the first layer and a height of at least one of the features is at least 1:

1.

13. depositing a first electrode on the second layer; depositing a third layer of a third dielectric material over the second layer by an evaporation process, a PVD process, or a flux-controlled CVD process; depositing a second electrode on the third layer; The method of claim 5 further comprising:

14. 1. A method of depositing a dielectric coating onto a structural array of components of an electrical device, the structural array having a plurality of features, the method comprising: depositing a first layer of a first dielectric material over the structural array by an atomic layer deposition (ALD) process or a spin-on coating process, the first layer having a first thickness; removing at least a portion of the first layer by an etching process; depositing a second layer of a second dielectric material over the first layer, the second layer having a second thickness greater than the first thickness; A method comprising:

15. 15. The method of claim 14, wherein the second layer is deposited by an evaporation process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a flux-controlled chemical vapor deposition (CVD) process.

16. 15. The method of claim 14, wherein at least one feature of the plurality of features is spaced a distance from another one of the plurality of features, and a ratio between the first thickness of the first layer and the distance is at least 0.4:1 and up to 0.6:

1.

17. At least one of the first dielectric material or the second dielectric material is silicon dioxide (SiO ２ 15. The method of claim 14, comprising:

18. The method of claim 14 , wherein the electrical device is an ion trap and the component is a photonic component of the ion trap.

19. 15. The method of claim 14, wherein a first distance is defined by at least a first pair of adjacent features of the plurality of features and a second distance is defined by at least a second pair of adjacent features of the plurality of features, the second distance being greater than the first distance.

20. 15. The method of claim 14, wherein the ratio between the second thickness and the first thickness is at least 10:1 and up to 300:1.

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