Composite semiconductor substrate and manufacturing process

Abstract

A compound semiconductor wafer comprising a composite layer structure comprising a stack (2) of layers (2a, 2b), the stack comprising a substrate layer of a semiconductor material and a porous layer extending over the substrate layer, the semiconductor material being one of the group consisting of In, GaAs, GaP, or Ge, the porous layer being made of InP and having a volume porosity of 20% or less.

Description

[Technical Field]

[0001] The present invention relates to a composite semiconductor substrate, as well as a process and method for manufacturing such a substrate. [Background technology]

[0002] Porous semiconductors can exhibit new and unexpected mechanical, electrical, and optical properties compared to bulk materials. For example, in III-V semiconductors, porous semiconductors that exhibit optical properties in specific pore morphologies have emerged in recent years. However, known processes used to fabricate porous III-V semiconductor structures are complex and can only be applied when specific layer stacks are obtained or when semiconductor devices are formed within a semiconductor substrate.

[0003] For example, Ukrainian utility model UA 54 800 discloses a method for producing a film of InN, which comprises preparing a porous monocrystalline InP film on an InP substrate, which is prepared in a dark place in a hydrochloric acid solution (5%) at a direct current density of 150 mA / cm. 2 for 10 minutes, or in a hydrofluoric acid solution (HF:H2O:C2H5OH=1:1:1) at a current density of 80 mA / cm 2 This was achieved by electrochemical etching for 5 minutes, followed by radical beam epitaxy (RAE) growth of a 1.2 micron InN film on the porous single-crystalline InP film at 300-400°C for 1.5 hours in an atomic nitrogen flow. This method is specifically tailored to produce InN films, resulting in a layered structure of specific materials with embedded porous InP. Furthermore, because the InN film has a wurtzite structure and InP has a zincblende structure, there is a large mismatch in the crystal lattices.

[0004] In particular, only device-specific processes are known for devices with heterostructures comprising a porous crystalline compound semiconductor layer on a heterocrystalline substrate of another semiconductor material. For example, Chinese Patent Application Publication No. 110299435 describes a method for preparing an InP film as a distributed Bragg reflector. This known method involves electrochemically etching an InP substrate in an electrolyte to obtain porous InP, followed by increasing the voltage to prepare a large-area porous InP film. The etching is performed at an etching rate of 1 μm / min to 4 μm / min for 10 to 15 minutes. The distributed Bragg reflector is formed on an n-GaN / u-GaN periodic structure by electrochemical etching. The porous InP film is then peeled off from the InP substrate and transferred to the distributed Bragg reflector using PDMS (polydimethylsiloxane) transfer technology. Therefore, this process is specialized for fabricating Bragg reflectors on GaN substrates. Furthermore, this process requires a long time.

[0005] Accordingly, the present inventors have discovered that there is a need for engineered substrates with porous semiconductor layers that are not embedded in a particular stack or dedicated to a particular type of device, and processes for making such engineered substrates.

[0006] Yana Suchikova, Valeriy Kidalov, and G.A. Sukach (2013) report "Morphology of porous n-InP (100) obtained by electrochemical etching in HCl solution" (Functional Materials, 17, pp. 1-4), which describes the creation of pores on the entire surface of an InP ingot. Suchikova further discloses that etching rates differ on different surfaces, and that the shape of the pores is determined by the crystallographic orientation of the surface. Pores on single-crystal InP with a (100) orientation have a nearly rectangular cross section, whereas those with a (111) orientation have a triangular cross section. Suchikova also reports that after electrochemical etching in a hydrochloric acid solution, a nanoporous layer of InP with a porosity of approximately 30% appeared on the (100) surface. The pore diameter averaged 40 nm, and the interpore walls were 5-10 nm. The depth of the pore channels was approximately 35 μm. Suchikova further discloses that the smaller the pore size and the wider the porosity range, the more qualitatively porous the structure, and photoluminescence is only observed in nanometer-order structures.

[0007] However, the ingots are not suitable for forming electronic devices thereon using conventional techniques used in the semiconductor industry, such as photolithography, and currently no substrates exist that can subsequently be fabricated with electronic devices using these conventional techniques, nor are there any processes available for fabricating such substrates. Summary of the Invention [Problem to be solved by the invention]

[0008] The high cost of indium phosphide (InP) substrates, coupled with their low mechanical strength and susceptibility to breakage during handling, present significant challenges in production, ultimately resulting in production losses and waste, especially for large-diameter substrates or wafers. Furthermore, indium and phosphorus are critical materials, raising concerns about their long-term supply stability. Therefore, there is an urgent need to develop new production methods that address these challenges while emphasizing material efficiency and high productivity. [Means for solving the problem]

[0009] The present invention provides a compound semiconductor substrate and a process or method for making such a substrate as described in the detailed description and particularly as claimed in the appended claims.

[0010] Such substrates have been found to have porous layers suitable for fabricating electronic devices, since such layers allow the growth of other layers, particularly homo- or heteroepitaxial layers, while preserving the mechanical, electrical, and optical properties of the porous material.

[0011] Specific embodiments of the invention are set out in the dependent claims and in the detailed description.

[0012] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

[0013] Further details, aspects, and embodiments of the present invention are described, by way of example only, with reference to the drawings, in which like reference numbers are used to identify like or functionally similar elements, and in which elements are illustrated for simplicity and clarity and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0014] [Figure 1]1(a)-(c) are diagrams illustrating an example of an embodiment of a semiconductor wafer at various stages of fabricating a device thereon. [Figure 2] 1 illustrates a cross-sectional view of an example embodiment of a semiconductor wafer. [Figure 3] 3(a)-(f) schematically illustrate cross-sectional side views of an example embodiment of a semiconductor wafer at various stages of an example process for fabricating the wafer, such as the example of FIG. 2. [Figure 4] 3A-3C show electron microscope images of an example porous InP stack at different stages of fabricating the porous layer. [Figure 5] 1 shows the etching current and potential applied to a 0.2 cm 2 wafer surface as a function of time in an example process for electrochemically etching pores in an InP wafer. [Figure 6] A scanning electron microscope image of the porous surface of an InP wafer obtained by the process of FIG. 5 is shown. [Figure 7] In another example of a process for electrochemically etching pores in an InP wafer, the etching current and potential applied to a 0.2 cm 2 wafer surface are shown as a function of time. [Figure 8] A scanning electron microscope image of the porous surface of an InP wafer obtained by the process of FIG. 7 is shown. [Figure 9] In another example of a process for electrochemically etching pores in an InP wafer, the etching current and potential applied to a 0.2 cm 2 wafer surface are shown as a function of time. [Figure 10] 10 shows a scanning electron microscope image of the porous surface of an InP wafer obtained by the process of FIG. [Figure 11] 1 shows a scanning electron microscope image of the porous surface of an InP wafer after chemical mechanical polishing to expose the sublayer on the low porosity side. DETAILED DESCRIPTION OF THE INVENTION

[0015] The illustrated embodiments of the present invention can, for the most part, be implemented using electronic components and circuitry known to those skilled in the art, and so will not be described in detail beyond the extent deemed necessary as illustrated for an understanding and appreciation of the concepts underlying the invention and so as not to obscure or distract from the teachings of the present invention.

[0016] FIG. 1(a) illustrates a semiconductor wafer 10 as an example of a semiconductor substrate suitable for forming semiconductor devices using conventional techniques used in the semiconductor industry. The wafer 10 has two generally parallel major surfaces 11, 12, one of which is the front surface 11 of the wafer and the other of which is the back surface 12 of the wafer. A peripheral edge 13 joins the front surface 11 and the back surface 12 of the wafer 10. In FIG. 1(a), the peripheral edge 13 is circular, giving the wafer 10 a disk-like shape. In this example, the edge 13 has a flat or straight portion 14 that is missing a circular segment of the circle, and thus each of the surfaces 11, 12 is, geometrically speaking, a disk segment. Semiconductor wafers are generally prepared from a single crystal ingot (e.g., an InP or GaAs ingot) and sliced ​​into individual wafers. Typically, but not always, prior to slicing, the ingot is trimmed and ground to provide one or more flats or notches for proper orientation of the wafers in subsequent steps. In this example, this results in a straight section 14 .

[0017] Referring to FIG. 1(b), multiple die regions 100 are shown on wafer 1. The die regions are linear and arranged in a matrix array; however, other shapes and arrangements can be used as well. The fabrication of semiconductor devices and electronic circuits typically involves forming multiple independent devices or circuits on a semiconductor wafer, and then, at a later stage in fabrication, singulating (dicing) the semiconductor wafer into individual pieces of semiconductive material (dies), each with a given electronic circuit or device, to allow the devices or circuits to be separated. Forming multiple separate circuits or devices in the die regions typically involves forming various patterned and unpatterned insulating, semiconductive, and conductive device regions and layers on the substrate formed by the unprocessed wafer. Such patterning involves transferring a predetermined pattern, for example, in the case of photolithography, by projecting an image of the desired pattern onto the wafer surface. As part of the patterning, a photoresist layer is typically deposited on the top surface of the wafer and patterned by photolithography or other processes to define exposed and unexposed areas of the wafer. Other layers can be deposited on the photoresist, and then patterns can be formed on the wafer to form semiconductor devices, such as by removing portions of the photoresist and exposing the top surface to, for example, an etchant or other process.

[0018] As shown in FIG. 1(c), after singulation, the semiconductor wafer 10 is separated into individual dies 101 of semiconductive material, each containing an electronic circuit or device, rather than a monolithic block containing multiple independent circuits or devices. The singulated dies 101 can undergo further processing, as needed, such as testing the singulated circuits and packaging them into integrated circuit packages. Die area 100 indicates the area corresponding to an individual die after the circuits are fabricated and singulated. The dies typically have dimensions of less than 1 mm to 5 cm in width and less than 1 mm to 5 cm in length, although other dimensions can be used, and dicing is shown to a simplified scale in FIG. 1.

[0019] Hereinafter, reference will be made to an unpatterned wafer, which is a wafer prior to the formation of device structures thereon. The wafer may be an initial wafer, which is an undiced, disk-shaped sliced ​​portion of an ingot. However, instead of forming circuits and then dicing, the unpatterned slice may be first diced and the unpatterned die or dies may be provided with a blanket porous layer thereon, for example, by subjecting the unpatterned die or dies to a fabrication process as described. In this example, a process is applied to provide the unpatterned wafer with a blanket unpatterned porous layer prior to forming devices in the wafer. However, the wafer may instead be patterned to provide a blanket layer in the die regions and separate the gaps (where the porous layer is absent) between the die regions, which facilitates dicing and defines, for example, scribe lines. The described process may also be used for other applications and may be adapted to other processes, for example, to locally pattern porous structures as part of device formation.

[0020] Referring to FIG. 2, the semiconductor substrate shown is preferably a wafer 10. In this example, the substrate is an unpatterned and / or undiced semiconductor wafer. The substrate comprises a composite layer structure having a stack 2 of layers 2a, 2b, comprising a substrate layer 2a, also called bulk layer, on top of which are provided one or more other layers 2b, which differ in structure from the bulk layer 2a, in particular in porosity. These other layers constitute porous layers of compound semiconductor material. In this example, the stack is a two-layer stack consisting of a substrate layer 2a and a porous layer 2b.

[0021] The stack 2 is shown with the exposed surface of the porous semiconductor layer 2b forming the front side 11 of the wafer 10, and the porous layer 2b forming the surface layer of the wafer. The exposed surface of the substrate layer 2a faces away from the front side 11 and forms the back side 12 of the wafer. Both exposed surfaces 11, 12 may be temporarily covered with a covering layer or film, e.g., for protection during transport or handling, which is removed prior to growing other layers on the exposed surfaces in subsequent processing. The back side 12 may be formed by a layer separate from the substrate layer 2a; for example, the back side of the wafer may be provided with one or more backing layers. The back side of the wafer is shown in FIG. 3 and may preferably consist of a support layer having a thermal coefficient similar to that of the substrate layers 2a and / or 2b. Preferably, a uniform, homogeneous ohmic contact is provided on the back side of the wafer.

[0022] The semiconductor wafer 10 has a midplane between the front surface 11 and the back surface 12, indicated by a dashed line in FIG. 2 . The midplane extends substantially parallel to the front surface 11 and the back surface 12 and through the bulk layer 2a. A top layer, also referred to as the surface layer 2b, extends parallel to the front surface 11. Viewed in the stacking direction from the front surface 11 to the bottom surface 12, the surface layer extends from the front surface 11 to a depth d within the wafer 10. The surface layer 2b is on top of the substrate layer 2a and, in this example, is in direct contact with the substrate layer 2a. In this case, the surface layer 2b is made of the same material as the substrate layer 2a, InP, preferably single-crystal InP. This structure corresponds to the multilayer structure (c) in FIG. 3 . The substrate layer 2a may be made of the same material as the surface layer 2b or a different material. Examples of suitable materials for the substrate layer 2a include InP, Ge, GaN, GaP, or GaAs.

[0023] In this example, the substrate layer 2a is a single-crystalline semiconductor material, but it can also be a polycrystalline or amorphous material. While reference is made here to a semiconductor wafer with an InP or GaAs substrate layer 2a, the bulk layer 2a can be another material, such as germanium, gallium phosphide, and other alloys of group III and group V elements, such as gallium nitride or indium phosphide, or alloys of group II and group IV elements, such as cadmium sulfide or zinc oxide. Furthermore, the substrate layer 2a can be doped or undoped. For example, the substrate layer 2a can be doped with a p-type dopant or an n-type dopant.

[0024] The surface layer 2b is a porous surface layer of a compound semiconductor material (e.g., InP or other III-V semiconductor). The porous layer 2b is suitable for growing other layers thereon, particularly homo- or heteroepitaxial layers 3 (e.g., as shown in FIG. 3(f)), because it has one or more of the following properties: Each of these properties has been found to result in a porous layer that can exhibit new and unexpected mechanical, electrical, and optical properties compared to bulk materials, while maintaining sufficient self-ordering to allow the growth of other layers, particularly homo- or heteroepitaxial layers.

[0025] The first property is that the porous layer 2b has a surface porosity of 50% or less and / or a volume porosity of 10% or less on the porous surface (front surface 11 in this example) facing away from the substrate layer 2a. Preferably, the surface porosity is 30% or less. Currently, it is preferred that the surface porosity is at least 10%, more preferably at least 20%. The volume porosity of the porous semiconductor layer is preferably less than 5%. The charge carrier density is, for example, 1 to 1.7·10 17 / cm 3 It has been found that this results in a porosity that allows for good bonding with another substrate, and therefore allows for particularly easy transfer of the porous layer to a foreign substrate. Furthermore, it has been found that this results in a porosity that allows for good growth of an overlying layer, i.e., an epitaxially grown layer, grown for example via CVD.

[0026] The second characteristic is that the porous layer is made of a compound semiconductor material and is provided with pores having different geometries, namely, tubular geometries in which the tubes are in the direction of current flow during the etching process, and triangular geometries resulting from the crystallographic orientation of the pores. "Tubular pores" and "triangular pores" are also referred to as "current line pores" and "crystallographically oriented pores," respectively. These geometries can also exist in a mixed form, where the pores exhibit both tubular and triangular shapes. This is because the pores combine current line and crystallographic properties, as evidenced by their branched morphology and preferential orientation perpendicular to the wafer surface. In the context of the present invention, pore types consisting of multiple morphologies, specifically "tubular" and "triangular," are referred to as "mixed-type" pores. Compound semiconductor porous layers with "mixed-type" pores are preferred. These pores can include one or more pore types from the group consisting of macropores, mesopores, and micropores. In the field of semiconductor etching and in the context of the present invention, the term "macropore" refers to a pore having a median diameter in the range of 500 nm to 50 μm. The term "mesopore" refers to a pore having a median diameter in the range of 10 nm to 500 nm. The term "nanopore" refers to a pore having a median diameter of less than 10 nm. In this example, all, or at least the majority, of the pores are mesopores. Currently, the median diameter of the mesopores is preferably in the range of 70 nm to 150 nm. As can be seen in FIG. 2, tubular pores can extend from pore inlets located at the porous surface into the porous layer toward the substrate layer. Some or all of the tubular pores can form branching channels, for example, branching channels that branch from the porous surface toward the substrate layer.

[0027] The third characteristic is that the porous layer is provided with pores (etched at approximately 6 V) oriented along the current lines extending from the porous surface. Crystallographically oriented pores can also be used (etched at approximately 4 V). By applying an intermediate voltage (approximately 5 V), mixed pores, even a combination of both pore types, can be used in this approach. In this regard, current-line oriented pores, unlike crystallographically oriented pores, do not follow crystallographic planes. In this regard, see section 4.4 of Foll, H., Langa, S., Carstensen, J., Christophersen, M., and Tiginyanu, I. (2003), Pores in III-V Semiconductors. Adv. Mater., 15:183-198 (https: / / doi.org / 10.1002 / adma.200390043). Current-line pores in the porous layer are less preferred because they require a larger etching current and result in higher porosity. This can reduce the efficiency of the etching process and result in unwanted etching of other areas of the surface. Therefore, the porous layer preferably includes mixed pores as described above. This mixed pore configuration reduces the required etching current and results in a more uniform and controlled etching process.

[0028] The fourth characteristic is that the pores extend from the porous surface to a depth shallower than the thickness of the semiconductor wafer, and the substrate layer is non-porous. The porous layer may have a thickness of, for example, 50 μm or less and / or 5 μm or more. In one example, the ratio of the thickness of the porous layer to the thickness of the substrate layer is 25% or less, preferably 18% or less.

[0029] The fifth characteristic is that the porous layer is a single crystal layer, and / or the substrate layer is a single crystal layer, and / or the substrate layer and the porous layer have the same type of crystal structure. In a preferred example, the crystal structure of at least one of the substrate layer and the porous layer, more preferably both, is zinc blende.

[0030] In this example, the porous layer is a blanket, unpatterned layer, but in other applications the porous layer may be a patterned layer and / or locally formed. The porous layer is particularly suitable for use in the manufacture of semiconductor devices on unpatterned substrates.

[0031] The substrate (wafer 10 in this example) provided with the porous layer 2b is particularly suitable as a starting point for further processing to produce semiconductor devices when the substrate has a compound semiconductor layered structure. In such cases, the layer stack 2 may comprise a porous InP surface layer 2b in direct contact with the substrate layer 2a, e.g., of InP, GaAs, Ge, or GaP. Preferably, the porous InP surface layer 2b has a thickness of 5-50 μm and a volume porosity of 10% or less, as measured by SEM. Most preferably, the porous InP surface layer 2b has a thickness of 5-50 μm and a volume porosity of 5% or less.

[0032] The porous layer 2b can be formed on the exposed surface of the substrate layer 2a, as shown in Figure 2, and can form a single-component structure with the substrate layer. In this case, the substrate layer and the porous layer can form a single crystal. When the porous layer 2b and the substrate layer 2a form a single-component structure, the thickness of the porous layer is determined by the depth to which the pores extend into the substrate.

[0033] Alternatively, the porous layer may be an additive layer, e.g., a layer transferred onto a substrate layer in a layer transfer process. In such cases, the semiconductor substrate layer may have a flat, irregular side facing the porous semiconductor layer 2b, to which the porous semiconductor layer 2b is bonded. Vice versa, the porous semiconductor layer 2b may have a surface facing the substrate layer to which the porous layer is bonded. A bonding interface may extend between the porous semiconductor layer and the substrate layer. For example, this surface may be bonded to the semiconductor substrate by thermal bonding, e.g., a thin, transient thermal bonding layer may extend between the porous layer and the substrate as a result of the thermal bonding. In the case of a transferred layer, the porous semiconductor layer may have an exposed side that bears the remnants of the lift-off process by which the porous semiconductor layer was separated from the initial wafer.

[0034] The porous layer may have been thinned, i.e., its thickness may have been reduced, and traces of this may be present. For example, the top surface may have been removed to a certain depth to remove portions with undesired properties, such as a different porosity. In the illustrated example, traces of the removal process may be present on the porous surface, which is the exposed side facing away from the substrate layer 2a. In the case of a porous layer 2a transferred onto a substrate layer, traces of the removal process of parts of the porous semiconductor layer may be present on the bonding side of the porous semiconductor layer facing the substrate layer. The traces may be, for example, traces of grinding, polishing, e.g., chemical mechanical polishing (CMP), or other wafer thinning processes applied to partially remove the porous layer 2b and reduce its thickness. For example, CMP may leave scratches, particle residue, or debris on the polished surface.

[0035] The porous surface may have a roughly uniform surface porosity, as seen, for example, in FIG. 10, where the porosity is roughly uniform in two dimensions. While the latter is currently preferred, in an alternative example, the porous surface may have a pattern of regions of differing surface porosity. For example, as can be seen more clearly in FIG. 6, linear regions of limited porosity may be present. These regions are defined by non-porous regions extending between two parallel, spaced-apart linear boundaries. In the non-porous regions, there is a pattern of linear pores extending parallel to the parallel boundaries. The pattern is roughly centered between the parallel boundaries. Outside these regions, a uniform two-dimensional pattern extends, thereby separating the linear pattern by the non-porous regions. Surprisingly, it has been found that such regions do not affect the aforementioned suitability. Furthermore, it has been found that even in the case of regions of limited porosity as described, the porous layer can be transferred to another substrate.

[0036] The porous surface of the semiconductor substrate can be provided with an epitaxial layer 3, as shown in FIG. 3(f). In this way, a semiconductor layered structure can be obtained, such as that described above, comprising a composite wafer and an epitaxial layer 3 extending over the porous surface of the composite wafer. The epitaxial layer 3 can, for example, be grown directly on the porous layer 2b, which forms a seed layer for the epitaxial layer. The epitaxial layer can be of the same semiconductor material as the substrate, although other materials are also possible. The epitaxial layer and the substrate can, for example, form a heterostructure, preferably having the same crystal type. Although other materials can be used, it is currently preferred that the epitaxial semiconductor layer constitute an epitaxial compound semiconductor layer, optionally an epitaxial binary semiconductor layer, and optionally also an epitaxial III-V semiconductor layer, preferably an epitaxial indium phosphide (InP) layer. After forming the epitaxial layer, further blanking processing may be performed, for example, to grow additional layers as deemed appropriate for the particular type of semiconductor device to be fabricated in and on the substrate.

[0037] method 3, diagrams (a) to (c) show a first process for producing a porous surface layer on an initial wafer, such as a monocrystalline semiconductor wafer (e.g., a monocrystalline compound semiconductor wafer). Advantageously, the method of the present invention provides a composite substrate having a porous layer suitable for growing other layers, particularly homo- or heteroepitaxial layers, for use in the manufacture of semiconductor devices.

[0038] As shown in Figure 3(a), a first process can begin by providing an initial semiconductor substrate, such as a wafer 10. The initial semiconductor substrate comprises a substrate layer 2a. For example, the substrate can be a slice obtained from an ingot that has been cleaned, polished, etc., into a wafer and has not been further processed or modified, particularly not patterned to form a semiconductor device.

[0039] As shown in FIG. 3(b), the substrate can then be provided with a porous layer of compound semiconductor material comprising a high-porosity sublayer 2c and a low-porosity sublayer 2b. FIG. 3(b) shows that the porous layer extends over the substrate layer 2a, with the low-porosity sublayer 2b extending between the substrate side of the high-porosity sublayer 2c and the substrate layer 2a. The low-porosity sublayer 2b has a lower porosity than the high-porosity sublayer 2c. In one example, the low-porosity sublayer 2b has a higher porosity than the semiconductor substrate layer 2a and a lower porosity than the high-porosity sublayer 2c. For example, the substrate layer 2a can be non-porous. The low-porosity sublayer 2b can have a volume porosity of 10% or less, e.g., 5% or less, as measured by SEM. The high-porosity sublayer 2c can have a volume porosity of 20% or more, as measured by SEM, for example. The exposed top surface of the resulting laminate may be formed by a thin layer of lower porosity than the higher porosity sublayer 2c, as seen in Figure 4. Porous layer 2 comprises a thin layer or membrane of approximately 0.5 µm to 1 µm thickness, which forms the exposed top surface and is in contact with the higher porosity sublayer 2c.

[0040] The porous layer can be provided by any suitable method. For example, the substrate layer of the initial substrate can be etched, for example by electrochemical (EC) etching, or provided with pores by other methods. This results in a substrate layer 2a with a reduced thickness compared to the initial substrate layer. Alternatively, the porous layer can be grown on the initial substrate, for example by homoepitaxy and subsequent etching. As shown, a first surface of the porous layer can face away from the substrate layer 2a, and a second surface faces towards the substrate layer 2a. In this example, the second surface contacts the substrate layer 2a.

[0041] Figure 4 shows an SEM image of the resulting structure. Shown is a porous layer. As can be seen, the porous layer has a high-porosity sublayer 2c at the front, which is covered by a low-porosity membrane or thin layer. The membrane or thin layer is approximately 1 μm thick and forms the front layer. This membrane or thin layer has a relatively low porosity and low self-organization compared to the high-porosity sublayer 2c. In this example, the high-porosity sublayer has a vertically layered structure from the front to the bottom. Beneath the membrane, down to the low-porosity sublayer 2b, are several layers (3-4 in this experiment) of relatively large-diameter, short-length pore cells, also known as neck pores or wide-body pores. The vertical (i.e., from the front to the bottom) arrangement of cavities and bottlenecks formed by these layers is believed to form a nucleation layer, allowing for highly accurate and reproducible control of the formation of the low-porosity layer.

[0042] Furthermore, it was found that the cavities and bottlenecks still allow high etching rates and current densities, and do not extend the duration of the (electrochemical) etching process, as expected. This is especially true for 5-10 16 / cm 3 Over 1.0 10 18 / cm 3 Below 1·10, preferably 17 / cm 3 Over 4·10 17 / cm 3 Less than or equal to 1·10 17 / cm 3 Over 2.0·10 17 / cm 3 Less than or equal to about 1.5 10 17 / cm 3 This is particularly advantageous when combined with doping with a charge carrier density of 0.01 to 0.10, since it allows for the production of porous layers with good homogeneity in a relatively short time, especially on large wafers. For example, as shown in Figures 5, 7, and 9, the etching process takes about 1 minute. In particular, for InP substrates, prior art methods can produce a porous layer in a commercially acceptable time of 2-4·10. 17 / cm 3(and higher) charge carrier densities are believed to be necessary, but on large wafers, the pore distribution may be non-uniform due to, for example, large currents, ohmic losses, and bubbles during electrochemical etching.

[0043] After preparing the porous layer, the low-porosity sublayer 2b is embedded in the substrate between the substrate layer 2a and the high-porosity sublayer 2c. The low-porosity sublayer 2b may be exposed, and the semiconductor wafer may be provided with an exposed low-porosity surface facing away from the substrate layer. Figure 3(c) shows the substrate after exposing the low-porosity sublayer. As can be seen, this exposure may involve partially removing the porous layer from the front surface to a depth shallower than the thickness of the porous layer and deeper than the depth at which the substrate side of the high-porosity sublayer 2c is located. Preferably, the thickness is reduced so that the thickness of the low-porosity sublayer remains intact; the low-porosity sublayer may not be completely removed in this process. For example, in the example of Figure 4, at least 2 μm of the porous layer may be removed from the front surface. After exposure, the sublayer 2c on the high porosity side is removed and the sublayer 2b on the low porosity side becomes the porous surface layer.

[0044] After creating a porous surface layer on the initial wafer, the resulting engineered substrate or composite substrate can be used, for example, to form semiconductor devices thereon. For example, processing may stop. For example, the engineered wafer may be subjected to finishing steps such as cleaning, planarization, end-of-line metrology testing, and final cleaning. These steps may be omitted, and exposing the porous layer is sufficient to complete the engineered wafer.

[0045] In another example, a wafer with a porous surface layer can be used as a donor wafer in the production of a composite wafer having a heterogeneous composition structure of layers of different materials with a porous surface layer. Figures 3(d)-3(f) show a second process for transferring a porous surface layer 2b from a donor wafer to a foreign wafer with a foreign substrate layer 1, also referred to as a bulk layer, of a semiconductor material different from the porous layer. In the example shown, the foreign wafer has a single-layer structure. The foreign wafer can be an engineered wafer with a multilayer stack onto which at least the porous layer, but optionally other layers of the donor wafer, have been transferred, or it can be a single-layer wafer consisting of a single substrate layer. The foreign substrate can be monocrystalline.

[0046] Layer transfer can include bonding a donor substrate to an initial foreign substrate to obtain a bonded stack and separating one or more layers of the donor substrate from the bonded stack. Figure 3(d) shows a bonded stack in which a donor substrate 2 and an initial foreign substrate 1 are bonded together. As can be seen, a porous surface layer 2b is embedded in the bonded stack and is located between the bonded donor substrate layer and the initial foreign substrate layer. The porous surface is in direct contact with the initial front surface of the foreign substrate 1.

[0047] In this example, after bonding, the donor substrate layer 2a is separated from the porous layer 2b. The donor substrate layer 2a can then be reused in a similar process and provided with a porous layer again, as indicated by the arrow from FIG. 3(e) to FIG. 3(b). FIG. 3(e) shows the substrate after separation. As shown, the porous layer remains bonded to the foreign substrate layer 1 and becomes the surface layer of the foreign substrate. The exposed surface is the side of the donor substrate facing the substrate layer, and the side of the porous semiconductor layer 2b facing the foreign substrate layer was previously the front surface of the donor wafer.

[0048] After transfer, the foreign wafer may be used "as is" in the process of forming a semiconductor device thereon, patterned, etc. Alternatively, one or more blanket layers may be grown or deposited on top to increase the number of layers in stack 2, as shown in FIG. 3(f). This results in a non-patterned engineered wafer. For example, one or more epitaxial layers may be grown on the porous surface of the semiconductor substrate. In such cases, a semiconductor layered structure, such as that described above, may be obtained, comprising a composite wafer and an epitaxial layer extending over the porous surface. The epitaxial layer may be grown directly on the porous layer, for example, which forms a seed layer for the epitaxial layer. The epitaxial layer may be of the same semiconductor material as the substrate, although other materials are possible as well. The epitaxial layer and the substrate may form a heterostructure, for example, having the same crystal type, preferably zinc blende. Although other materials may be used, it is currently preferred that the epitaxial semiconductor layer comprises an epitaxial compound semiconductor layer, optionally an epitaxial binary semiconductor layer, and further optionally an epitaxial III-V semiconductor layer, preferably an epitaxial InP layer.

[0049] Each stage of the above process is described in further detail below, and for each stage, the optional aspects described can be combined with one or more optional aspects of the other stages.

[0050] Wafer preparation Any suitable substrate can be used as the initial substrate. The substrate can be a semiconductor material. The semiconductor material can be doped, for example, with a charge carrier density of, for example, 1 to 1.7·10 17 / cm 3 range, e.g., 1.5 10 17 / cm 3 The charge carrier density may be: In this example, a suitable substrate is provided as a wafer as described above with reference to FIG.

[0051] The wafer may have a single layer structure or a multilayer structure. In the described examples and experiments, a single-crystal single-layer wafer of a compound semiconductor material is used. Specifically, the wafer is of a III-V compound having a zinc-blende crystal structure, more specifically, an InP wafer. However, other types of wafers or substrates can be used as well.

[0052] Prior to forming the pores, a blanket layer, e.g., a homoepitaxial layer, can be grown on the front side of the initial substrate, e.g., an InP homoepitaxial layer can be grown on a single crystal InP substrate using, e.g., a molecular beam epitaxy process known in the art.

[0053] In this example, the surface of the substrate was non-porous, and more specifically, the entire substrate layer was non-porous.

[0054] Pore ​​preparation The prepared substrate is subjected to a process to form a porous layer on the front side of the substrate. The described examples and experiments may also be applicable to other processes, for example, to prepare porous layers with a porosity gradient and / or to better control the reproducibility of the preparation of the porous layer.

[0055] In some embodiments, the front side of the semiconductor foreign wafer is treated to form a porous layer. The porous layer can be formed by contacting the front side of a monocrystalline semiconductor handle substrate with an etching solution. The porous layer can form a monocrystalline layer together with the substrate layer, and in the described example, the pores are provided in the exposed surface of the initial monocrystalline substrate.

[0056] Although other processes, such as pure chemical etching, plasma etching, or other methods, can be used, in these examples and experiments, the substrate layer 2a is electrochemically etched to form a porous layer in the front region of the substrate. When InP is used as the substrate layer, electrochemical etching can be performed, for example, in an HCl solution. The electrochemical etching conditions can be set as needed for a specific type of pore. The properties of the porous compound semiconductor, such as porosity, thickness, pore diameter, and microstructure, vary depending on the anodization conditions. These conditions include electrolyte concentration, current density, wafer type and resistivity, anodization time, illuminance, temperature, and drying conditions. The selection of appropriate conditions to obtain the desired porosity and pore size is described in the prior art. In this regard, see Foell, H., Langa, S., Carstensen, J., Christophersen, M. and Tiginyanu, I. (2003), Pores in III-V Semiconductors. Adv. Mater., 15:183-198 (https: / / doi.org / 10.1002 / adma.200390043).

[0057] During electrochemical etching, the difference between the applied voltage and the open-circuit voltage can be maintained constant by periodically applying an offset voltage to the non-porous semiconductor wafer. This voltage control can be applied to other electrochemical etching processes, such as the preparation of porous layers in compound semiconductors. This has been found to improve the reproducibility of etching conditions and allow for more consistent production, especially when creating pores over large areas. In particular, for preparing porous InP, such as InP layers with varying porosity, constant current control is insufficient; very precise constant potential control is required. Such layers can be used, for example, in layer transfer processes.

[0058] The electrochemical process can be controlled to etch the porous layer in successive etching stages. At various stages of electrochemical porosification, the open circuit potential can be measured and an offset voltage can be applied to the open circuit potential to maintain a constant difference between the applied voltage and the open circuit potential. The open circuit potential measurement can further enable monitoring of the state of the etching experiment / system (e.g., electrolyte degradation, wafer doping) and can be used for in-situ feedback to adapt the individual etch profile.

[0059] For example, the etching cell can be briefly disconnected from the power supply and the applied potential between the sense and reference contacts measured (e.g., using a four-probe arrangement). Such measurements are easily applicable to etching systems of all sizes (from small to large InP wafers) and can account for various phenomena affecting the potential with a single measurement. This is particularly advantageous when reproducible etching conditions are difficult to achieve with constant potential control, e.g., for large-area etching. For example, the potentials within the etching cell are serially additive and can vary significantly depending on, e.g., electrolyte composition, temperature, wafer doping, surface defects, ohmic contacts, and etching cell geometry. In such cases, this measurement of the open-circuit potential can take into account all of the potentials in series.

[0060] A potential offset can then be applied to the measured open-circuit potential (after reconnecting the working counter electrode to the cell). This has been found to significantly improve the reproducibility of etching results. In this regard, the offset can be applied intermittently such that the sequence (duration and value) of the potential offset does not change, but the actual applied absolute potential changes to keep the difference constant.

[0061] The electrochemical process can be controlled to etch the porous layer in successive etching steps. The etching steps can include surface preparation, pore nucleation, and subsequent etching of the low-porosity layer, as well as etching of the thin, highly porous zip layer. In this regard, not all steps need to be performed. For example, the zip layer is a mechanically or otherwise weakened membrane between the porous layer and the substrate, reducing adhesion to the substrate layer and facilitating separation of the substrate layer and the porous layer from each other, thereby enabling transfer from a donor substrate to a dissimilar substrate, such as a handle substrate or device substrate. Therefore, if layer transfer is not intended or if such a layer is not required for layer separation (e.g., if the bond between the layers is already inherently weak enough and has been weakened by ion implantation or other methods), the thin, highly porous zip layer can be omitted.

[0062] Surface preparation may include cleaning and surface activation. In the example shown, surface preparation involves exposure to a series of voltage pulses in an electrochemical cell. More specifically, each pulse can have a duration of less than 1 second and a voltage of 10 V or less, for a total time of less than 0.25 minutes. In the preferred example of an InP substrate, preparation involves exposing the substrate to two 4 V pulse trains of 5 pulses, with an interval of at least 1.5 seconds between pulse trains. Surface preparation of wafers or substrates for electrochemical etching is generally known and will not be described in further detail.

[0063] In this example, a pre-treatment can be performed prior to pore nucleation and subsequent etching of the low-porosity layer, which involves reducing the current flowing through the non-porous semiconductor body to 0 mA / cm before preparing the porous layer. 2 up to 125mA / cm 2 The present invention may include electrochemically pretreating the non-porous layer by monotonically increasing the current to 0 mA / cm over a period of less than 3 seconds, and then decreasing the current to its initial level. 2 The current is increased linearly from an initial current level of 50 mA / cm, and is stopped immediately when a predetermined maximum current level is reached.2 It has been found that good results are obtained when the thickness is less than 1 / 2 μm. Such pretreatment has been found to significantly reduce the heterogeneity of pore growth in the layer on the low-porosity side. As comparative examples, Figures 6 and 10 show substrates that have undergone this pretreatment, while Figure 8 shows a substrate that has undergone pore nucleation and subsequent etching of the low-porosity layer without such pretreatment. The examples used for Figures 6 and 8 have the same InP substrate with the same doping and a charge carrier density of 1·10 17 / cm 3 The example in Figure 10 has a different doping than the example in Figure 6, and the charge carrier density is 1.5 10 17 / cm 3 As can be seen, the example in Figure 8 shows broad, limited regions of porosity, and outside of these regions the porous surface is dominated by dotted non-porous regions, whereas in Figures 6 and 10 these non-porous regions are absent.

[0064] Prior to preparing the porous layer, the initial semiconductor wafer may have a non-porous layer of a compound semiconductor material extending over the semiconductor substrate layer. This non-porous layer may be identical to the semiconductor substrate layer and may be a single structure with the semiconductor substrate layer. Then, pore nucleation and subsequent etching of the low-porosity layer may include preparing a nucleation sublayer within the non-porous layer. The nucleation sublayer may be fabricated to extend from a surface of the non-porous layer facing away from the substrate layer to an initial depth, the initial depth being less than the thickness of the non-porous layer. The non-porous layer with the nucleation sublayer may then be exposed to an etchant to form pores in the non-porous layer at depths deeper than the initial depth, resulting in a low-porosity sublayer in the region of the non-porous layer between the substrate side of the nucleation sublayer and the substrate layer. While other processes may be suitable, electrochemical etching is currently preferred. This allows for good control over the shape and type of pores, thereby preparing a nucleation layer particularly suitable for creating a low-porosity layer, as needed.

[0065] In light of the above disclosure and to be interpreted in the above context, the present invention is briefly defined as follows: In a first aspect, the present invention comprises a compound semiconductor multilayer structure comprising: - a substrate layer (2a or 1) comprising a semiconductor material selected from the group consisting of InP, GaAs, GaP and Ge; - a porous layer (2b) extending on a substrate layer (2a or 1), the porous layer (2b) consisting of InP and having a volume porosity of 20% or less as measured by SEM.

[0066] The present invention essentially provides a porous layer of InP having a low volume porosity, e.g., less than 25%, or less than 20%, or less than 15%, or less than 10%, or even less than 5%, as measured by SEM. Specifically, the present invention enables the formation of such a porous surface layer in a controlled manner. A low-porosity layer of InP, either by itself or bonded or connected to a supporting substrate layer, offers the advantage of forming a controlled fracture line for the formation of thin films. Referring to FIG. 3, the structure of the first embodiment of the present invention envisions concept (b) in which one surface of an InP substrate or substrate wafer is porosified to form a porous InP layer (2b) on top of the non-porous InP substrate. The inventors have found that activation or nucleation of the wafer substrate surface forms a first porous layer (2c) with a relatively high porosity, while subsequent porosification results in a denser porous layer (2b) with a relatively low porosity. The highly porous layer (2c) is advantageously removed by polishing, preferably by chemical-mechanical polishing as described above. After removal of the highly porous layer (2c), the structure (c) of FIG. 3 is obtained. Structure (c) provides an InP substrate with a porous layer as described according to the first aspect of the present invention. Structure (c) can then be bonded to a foreign substrate (1) made of GaAs, GaP, or Ge, with the porous layer (2b) oriented towards the foreign substrate (1). This results in a compound semiconductor multilayer structure (d). Controlled fracture of the compound semiconductor multilayer structure (d) separates the porous layer 2b on the foreign substrate 1 and releases the InP substrate 2a. The InP substrate 2a can then be reused for the next porosification step.

[0067] In a preferred embodiment, the present invention provides a compound semiconductor multilayer structure according to the first aspect of the present invention, wherein the porous layer (2b) has a volume porosity, as measured by SEM, of not more than 10%, preferably not more than 5%, and preferably not less than 0.1%, more than 0.5%, or even more than 1.0%.

[0068] In a preferred embodiment, the present invention provides a compound semiconductor multilayer structure according to the first aspect of the present invention, wherein the porous layer (2b) has a thickness of 1 to 50 μm, preferably 5 to 50 μm, as measured by SEM, and more preferably about 5 μm, about 10 μm, about 15 μm, about 20 μm, or about 25 μm, or any thickness therebetween.

[0069] In a preferred embodiment, the present invention provides a compound semiconductor multilayer structure according to the first aspect of the present invention, wherein the porous layer (2b) has mixed pores extending perpendicular to the exposed surface, the mixed pores having a morphology intermediate between current line aligned pores and crystallographically oriented pores.

[0070] In a preferred embodiment, the present invention provides a compound semiconductor multilayer structure according to the first aspect of the present invention, wherein the porous layer (2b) has pores extending into the porous layer (2b) from pore entrances located on the porous surface, the pore entrances having a median diameter in the range of 70 nm to 150 nm. Preferably, the pore entrances have a median diameter in the range of 70 nm, 90 nm, 110 nm, 130 nm, or 150 nm, or any diameter therebetween.

[0071] In a preferred embodiment, the present invention provides a compound semiconductor multi-layer structure according to the first aspect of the present invention, wherein the substrate layer (2a) consists of InP.

[0072] In a preferred embodiment, the present invention provides a compound semiconductor multilayer structure according to the first aspect of the present invention, wherein the substrate layer (1) consists of a material selected from the group consisting of GaAs, GaP and Ge, preferably GaAs and GaP.

[0073] In a second aspect, the present invention provides a method for preparing a compound semiconductor multi-layer structure, comprising the steps of: - electrochemically etching an InP compound semiconductor substrate to form a porous layer (2b) of InP, the porous layer extending over the substrate layer (2a), the porous layer having a volume porosity of 25% or less as measured by SEM.

[0074] In a preferred embodiment, the present invention provides a method according to the first aspect of the invention, wherein prior to forming the porous layer (2b) of InP by electrochemical etching, the exposed surface of the InP substrate is electrochemically pre-treated by electrochemical etching with intermittent voltage pulses, which may be the same or different.

[0075] In a preferred embodiment, the present invention provides a method according to the first aspect of the present invention, wherein the porous layer (2b) is predominantly formed by electrochemical etching for a time of at least 5 seconds, preferably at least 10 seconds, more preferably at least 15 seconds, preferably at most 120 seconds, preferably at most 60 seconds, more preferably at most 45 seconds, most preferably 15 seconds, 20 seconds, 25 seconds, 30 seconds, 35 seconds, 40 seconds, 45 seconds, or any time in between.

[0076] In a preferred embodiment, the present invention provides a method according to the first aspect of the present invention, in which the porous layer (2b) is formed predominantly by electrochemical etching at a voltage of 4V to 6V (excluding 4V and 6V), more preferably 4.25V to 5.75V, more preferably 4.5V to 5.5V, even more preferably 4.75V to 5.25V, and most preferably about 5V. The inventors have found that electrochemical etching at this specific voltage can form optimal pore morphology, i.e., pores with mixed morphology. The inventors have also found that electrochemical etching at a voltage of 4V results in the formation of pores with a crystallographic morphology, i.e., a morphology in the direction of crystal orientation, growing in the 111A direction, specifically, with the pore walls having a 111B surface and the pore tips in the 111A direction. Such pores have a triangular shape. The inventors have also found that electrochemical etching at a voltage of 6 V results in the formation of pores with a current-oriented morphology, i.e., a morphology that grows parallel to the 100 direction in the direction of the current. Such pores are hexagonally packed and rounded. In a preferred embodiment, electrochemical etching at a voltage of approximately 5 V results in mixed-morphology pores that grow randomly in the 100 or 111B direction and have rounded or triangular shapes. The inventors have found that etching under these conditions results in the most efficient pore etching and is the most effective for forming porous layers. These pores have been found to have less transport limitations.

[0077] In a preferred embodiment, the present invention provides a method according to the first aspect of the present invention, wherein the porous layer (2b) is formed by electrochemical etching, and in the final stage of the formation of the porous layer (2b), regions of increased porosity are formed by electrochemical etching at a temporary elevated voltage. By electrochemically etching at a temporary elevated voltage, a controlled structural weakness or controlled fracture line can be formed. The elevated voltage is preferably 7V to 30V, more preferably 10V to 30V. In this case, the temporary etching may take up to 15 seconds, or may be intermittently performed for up to 15 seconds, preferably up to 10 seconds, and preferably for at least 1 second or at least 2 seconds.

[0078] In a preferred embodiment, the present invention provides a method according to the first aspect of the present invention, wherein the porous layer (2b) is formed to have a volume porosity of not more than 20%, preferably not more than 15%, for example less than 10% or even less than 5%, as measured by SEM. Preferably, the porosity is not less than 0.1%, more than 0.5%, or even more than 1.0%.

[0079] In a preferred embodiment, the present invention provides - a substrate is provided having a porous layer (2b, 2c) of InP, the porous layer extending on a substrate layer (2a) and comprising a high-porosity sublayer (2c) and a low-porosity sublayer (2b) having a volume porosity lower than the volume porosity of the high-porosity sublayer (2c), the low-porosity sublayer (2b) extending between the substrate layer (2a) and the substrate side of the high-porosity sublayer (2c); - providing a semiconductor wafer having an exposed low-porosity surface of InP facing away from a substrate layer, said providing comprising removing the sublayer (2c) on the high-porosity side to expose the sublayer (2b) on the low-porosity side.

[0080] In a preferred embodiment, the present invention provides - preparing said porous layer comprises electrochemically etching a substrate layer to obtain an InP homocomposition structure comprising a substrate layer (2a) and porous layers (2b, 2c); and - providing a method according to the first aspect of the invention, wherein removing the sub-layer (2c) on the higher porosity side comprises chemical-mechanical polishing of the porous layers (2b, 2c) to a depth at which the sub-layer (2b) on the lower porosity side is exposed.

[0081] In a preferred embodiment, the present invention provides - contacting the exposed surface of the low porosity side with a surface layer of a foreign substrate comprising a substrate layer of GaAs, GaP or Ge, and thermally bonding the low porosity layer to the surface layer of the foreign layer to form a thermally bonded substrate.

[0082] In a preferred embodiment, the present invention provides - separating the porous layer from one or more layers of the semiconductor substrate, so that at least the substrate layer (2a) is separated from the thermally bonded substrate, thereby obtaining a substrate comprising a layer stack comprising a substrate layer (1) of GaAs or GaP or Ge and a porous InP surface layer (2b).

[0083] In a preferred embodiment, the present invention provides a method according to the first aspect of the invention, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b).

[0084] In a preferred embodiment, the present invention provides a method according to the first aspect of the invention, wherein the porous layer (2b) is formed by electrochemical etching of an InP substrate, and the difference between the applied voltage and the open circuit voltage is kept constant.

[0085] In a preferred embodiment, the present invention relates to a method for electrochemical etching comprising subjecting an InP substrate to an electrochemical pretreatment, wherein the etching current is 0 mA / cm for a time period of less than 3 seconds. 2 up to 125mA / cm 2In accordance with the first aspect of the present invention, the method increases linearly up to

[0086] In a more preferred embodiment, the present invention provides a method for etching a silicon wafer at the end of the time period, wherein the etching current is 0 mA / cm 2 The present invention provides a method according to a first aspect of the present invention, wherein the

[0087] In a preferred embodiment, the present invention provides a method according to the first aspect of the present invention, wherein the highly porous layer (2c) is subjected to chemical mechanical polishing using a slurry comprising an alkaline aqueous solution having a pH of 9 to 12 and silica nanoparticles.

[0088] In a third aspect, the present invention provides a compound semiconductor layered structure obtained by a method according to the second aspect of the present invention. [Example]

[0089] The following examples are intended to further clarify the preparation of the porous layer and are not intended to limit the scope of the invention in any way.

[0090] Experiment 1 N-type sulfur-doped InP wafers were grown by liquid-enclosed Czochralski (LEC) technology and had polished and cleaned epi-ready surfaces on both sides. The wafers were then heated at 1 10 17 / cm 3 The wafers were doped to have a charge carrier density of 100. The wafers were prepared with a diameter of 2 inches, a thickness of approximately 300-500 μm, and a (100) orientation.

[0091] The prepared InP wafers were subjected to electrochemical etching in a hydrochloric acid solution (3.5 wt%) in the absence of light. The etching cell has an O-ring cell design with a high pump rate to maintain a consistent concentration of electrolyte throughout the etching process. The potentials applied to the InP wafers were in the following order, as shown in Figure 5: (1) Surface preparation was performed (from t = 0 to t = 0.18 min in Figure 5). The surface preparation consisted of repeatedly applying pulse sequences of approximately 5 seconds each, with a 1 second interval between successive sequences. The applied voltage was 4 V. The measured current was 0 mA / cm. 2 It was. (2) Pretreatment was performed (from t = 0.18 min to t = 0.22 min in Figure 5). The etching potential was controlled, and the initial current level was 0 mA / cm. 2 to 50mA / cm 2 Increase the current linearly over 2.4 seconds (0.04 minutes) until 50 mA / cm 2 When this was reached, the current was immediately stopped. (3) Pore nucleation and subsequent etching of the low-porosity layer were performed. Pore nucleation (from t = 0.22 min to t = 0.35 min) consisted of applying a sequence of pulses above 10 V. The duration of the sequence was approximately 0.15 min, with a duty cycle of approximately 50%. An initial pulse of the highest voltage (19 V) was followed by a lower voltage pulse (16 V). The measured etching current was 250 mA / cm during the pulse. 2 ~350mA / cm 2 The pulse was followed by a long DC voltage period of just under 0.5 min (from t = 0.35 min to t = 0.86 min). During this period, the potential was about 6 V, and the etching current was about 150 mA / cm. 2 It starts at , decreases monotonically, and finally reaches 50mA / cm 2 This is what happened. (4) A highly porous zip layer was prepared between the low-porosity layer and the substrate layer (from t = 0.86 min to t = 1.0 min). Two 30 V pulses were applied for approximately 0.05 min. The etching current was 500 mA / cm at the beginning of each pulse. 2 The measured value rose sharply above 1100mA / cm 2 and 750mA / cm 2 ), 125mA / cm 2 It decreased monotonically until

[0092] The results are shown in Figures 4 and 6. A compound semiconductor layered structure was obtained consisting of an InP single-crystal substrate with a non-porous substrate layer and a porous surface layer with a porosity gradient, i.e., a porous surface layer with a porosity that varies from the front to the bottom (see Figure 4). A highly porous sublayer is on top, and a low-porosity sublayer is located below the highly porous sublayer and extends to the non-porous substrate layer (not visible in Figure 4). Layer 2b on the low-porosity side is characterized by vertical channels oriented in the direction of the current line applied during electrochemical etching. Layer 2c on the high-porosity side, which is highly porous, is characterized by high porosity and a 3-4 cell layer. As can be seen in Figure 6, there are narrow, linear, and confined porosity regions; outside these regions, the surface porosity is homogeneous.

[0093] Experiment 2 In this experiment, the pretreatment was omitted, but the wafer was the same as in experiment 1, and the same electrochemical etching was otherwise applied. The voltage and current are shown in Figure 7, and the resulting SEM image of the wafer surface is shown in Figure 8.

[0094] As can be seen in Figure 6, there are broad, linear, and confined regions of porosity, and outside of these regions the porosity is not homogeneous. Non-porous regions or spots are observed.

[0095] Experiment 3 In this experiment, the electrochemical etching and wafer were the same as in Experiment 1, except as noted below. Therefore, pretreatment was applied. The voltage and current are shown in Figure 9. An SEM image of the resulting wafer surface is shown in Figure 10.

[0096] This wafer is 1.5·10 17 / cm 3 and had the properties described in Experiment 1. The voltage of the sequence of pulses applied after pretreatment (between t = 0.25 min and t = 0.4 min) was slightly lower than in Experiment 1, with the first pulse at 15 V and the subsequent pulses at 14 V. The etching current in the series was approximately 50 mA / cm. 2Starting with a low first pulse of 175 mA / cm (ignoring overshoot at the beginning and end of the pulse), each subsequent pulse is higher than the previous one, with 2 , 300mA / cm 2 , 350mA / cm 2 and 400mA / cm 2 It was.

[0097] As shown in Figure 10, the porosity is uniform across the surface, with no linear, confined areas of porosity.

[0098] Experimental Considerations Experiments have shown that pretreatment significantly improves the homogeneity of the porous surface, making subsequent processing easier. Surprisingly, increasing the doping also leads to more homogeneous porosity. Most surprisingly, pretreatment at 1–1.7 10 17 / cm 3 It can be seen that when combined with doping in the range of 1000 .mu.m, excellent homogeneity is obtained.

[0099] Removal of the top layer After preparing the porous layer, the high-porosity sublayer is removed to expose the low-porosity sublayer 2b, which can be removed, for example, by chemical-mechanical polishing of the front surface.

[0100] Chemical mechanical polishing can be performed using a slurry containing nanoparticles, such as 250 nm SiO2 particles, and a basic solution with a pH of 9-12, preferably about 11. It has been found that such a solution has good selectivity toward the high-porosity sublayer, removing it without affecting the low-porosity sublayer. In particular, it has been found to be particularly advantageous for selectively etching a porous layer on a non-porous InP substrate layer, since it does not chemically etch the bulk InP. The slurry can contain, for example, potassium hydroxide (KOH) and a solution containing SiO2 nanoparticles. Furthermore, it has been observed that CMP can widen the pore diameter near the surface. This does not affect bonding, but is highly relevant for CVD / MOCVD. Therefore, purely mechanical polishing using 250 nm SiO2 particles is suitable for MOCVD. Alternatively, a water-based diamond suspension, DiaPro Nap 1 / 4 (Struers), and a polishing cloth, MD-Nap (soft synthetic fiber cloth), can be used for mechanical polishing.

[0101] experiment Experiment 4 The following examples are intended to further clarify the removal of the highly porous sublayer and are not intended to limit the scope of the invention in any way.

[0102] The porous wafer obtained in Experiment 1 was subjected to chemical mechanical polishing (CMP) using Nanopure NP6230 slurry. A Suba polishing pad available from DuPont was used as the polishing cloth. Polishing was performed at 100 rpm with a polishing force of 25 N for 15 minutes.

[0103] Figure 11 shows an SEM image of the resulting surface near the axial center of the wafer. The low-porosity sublayer was observed to be exposed and porous. Scars (lines) from the CMP process are visible in Figure 11. Thus, evidence of the process used to remove the highly porous sublayer, e.g., after layer transfer, is still present.

[0104] After exposing the lower-porosity sublayer, the wafer comprises the substrate layer of the initial wafer and the exposed porous surface layer. In this example, the wafer retains all layers of the initial wafer in addition to the porous surface layer. The wafer may undergo further processing, such as cleaning, thinning, and / or planarization to remove particulates and residue from the surface.

[0105] After removing the sublayer on the high-porosity side and exposing the layer on the low-porosity side, the wafer can be used as a composite wafer. The wafer can be used as an initial substrate in the fabrication of semiconductor devices, for example, and can be subjected to processes to form various patterned and unpatterned insulating, semiconducting, and conductive device regions and layers. For example, the finished engineered wafer may undergo end-of-line metrology testing and final cleaning. These steps can be omitted, and exposing the porous layer is sufficient to complete the engineered wafer.

[0106] In the illustrated example, after removing the top layer, the wafer is an intermediate product, and further processing is performed to obtain another type of composite wafer, a compound wafer. In this example, the intermediate product is used as a donor wafer in a layer transfer process in which at least the porous layer is transferred to a foreign wafer.

[0107] Bonding to different wafers In this example, the porous layer is transferred from an initial wafer to a foreign semiconductor wafer. For example, the porous layer can be transferred onto a foreign substrate, thereby forming a substrate layer on the exposed front or back surface (also referred to as the bottom surface) of the foreign wafer after transfer. As part of the layer transfer, the exposed low-porosity surface can be bonded to the exposed surface of the foreign substrate. The result is a bonded wafer having a composite layer structure comprising the initial substrate or wafer (hereinafter referred to as the donor wafer), the porous layer, and the foreign substrate.

[0108] Although other bonding processes may be suitable for forming the bonded wafers, the donor wafer can also be bonded to the foreign substrate by thermally bonding the two. For example, the donor wafer and foreign wafer can be placed with their exposed porous surfaces in contact with the bottom or front surface of the foreign wafer, thereby initiating bonding via van der Waals forces, after which the bond can be strengthened by a thermal treatment. The thermal treatment can transform the bond between the two interfacial materials, thereby strengthening the bond.

[0109] In the illustrated example, the top surfaces of the donor wafer and the foreign wafer are brought into contact with each other and the wafers are pressed together, creating a bond between the donor wafer and the foreign wafer at the interface between the former top layers of the wafers. In such a case, the mechanical bond may be held together by van der Waals forces. The bonded structure is further annealed to solidify the bond between the donor wafer and the foreign wafer.

[0110] In some preferred embodiments, the bonded structure is annealed at a temperature of about 100° C. to about 250° C., about 125° C. to about 200° C., preferably about 150° C. Thermal annealing can be performed for a duration of about several minutes to about 10 hours, preferably about 1 hour. Thermal annealing within these temperature ranges is sufficient to form a thermally bonded interface between the previously exposed surface of the porous layer and the respective surfaces of the dissimilar wafer.

[0111] The foreign wafer may be a single-crystal semiconductor substrate, such as a single-crystal semiconductor wafer. In a preferred example, the semiconductor wafer comprises a semiconductor material selected from the group consisting of germanium, gallium arsenide, gallium phosphide, indium phosphide, and combinations thereof. Preferably, both the foreign substrate and the donor substrate have a zinc-blende crystal lattice (cubic close-packed) or other face-centered cubic lattice. Depending on the desired characteristics of the final integrated circuit device, the single-crystal semiconductor foreign wafer may be doped with n-type or p-type dopants. The single-crystal semiconductor foreign wafer may be an unpatterned wafer, but undergoes standard process steps such as implantation, post-implant cleaning, and surface activation before bonding.

[0112] Separation of the foreign wafer from the donor wafer After bonding the donor wafer to the foreign substrate, a portion of the donor wafer can be separated from the bonded wafer. For example, the substrate layer of the donor wafer can be physically separated from the porous layer. The resulting foreign wafer comprises the foreign substrate and the porous layer forming the front or bottom surface of the foreign wafer. The resulting substrate is suitable for use in the manufacture of semiconductor devices. The wafer can be used as an initial substrate in the manufacture of semiconductor devices, and can be subjected to processes to form, for example, various patterned and unpatterned insulating, semiconducting, and conductive device regions and layers.

[0113] Separation can include mechanically lifting the initial wafer from the porous layer. In this example, after the thermal bonding described above, the bond between the single-crystalline semiconductor donor substrate and the wafer is strong enough to initiate layer transfer by cleaving the bonded structure at the cleavage plane. The donor wafer is then cleaved along the cleavage plane defined by the zip layer, although other separation techniques can be used. For example, a locally mechanically weakened surface can be formed by ion implantation at a depth corresponding to the desired separation plane, or laser lift-off or other separation techniques can be used. Cleaving can be performed by placing the bonded wafers in a fixture and applying a mechanical force perpendicular to both sides of the bonded wafers to separate a portion of the donor wafer from the bonded wafer. According to some methods, a suction cup can be used to apply the mechanical force. Separation of the portion of the donor wafer can be initiated, for example, by applying a mechanical wedge to the cleavage plane at the edge of the bonded wafer to initiate crack propagation along the cleavage plane. A mechanical force applied by the suction cup then pulls a portion of the donor wafer from the bonded wafer, thereby forming a composite wafer. In this example, the composite wafer comprises a compound semiconductor substrate and a porous top layer. Cleaving removes a portion of the donor wafer, leaving one or more layers, including the porous layer, on the foreign substrate. The foreign substrate is then provided with one or more additional layers from the donor substrate, resulting in a composite layer structure.

[0114] The removed non-porous portion of the donor substrate can be reused, for example, to form another porous layer and perform the process shown in Figures 3(a)-3(c) again, optionally followed by the process of Figures 3(d)-3(f) described above.

[0115] Further Processing of Engineered Substrates After separation, the foreign wafer comprises a foreign substrate layer (e.g., a single-crystal Ge wafer or a compound semiconductor wafer such as GaP or GaAs) and a porous surface layer (e.g., InP). The foreign wafer with the transferred layer may undergo further processing, such as annealing or other treatments to further strengthen the bond between the transferred layer and the foreign wafer, cleaning to remove particles from the surface, thinning, or planarization. In one example, after separation, one or more unpatterned epitaxial layers 3 are grown, as described above and shown in FIG. 3(f). The finished engineered wafer may then undergo end-of-line metrology testing and final cleaning. A cover layer may also be applied to cover the exposed low-porosity surface to temporarily protect the finished wafer, for example, during transport.

[0116] In the foregoing specification, the invention has been described with reference to specific examples of embodiments thereof. However, it will be apparent that various modifications and changes thereto are possible, and therefore the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0117] For example, while the illustrated examples show the ideal case in which the layers extend parallel to the front side of the semiconductor wafer and have a constant thickness, in actual implementations the thickness of one or more layers may vary across the substrate and the layers may not be flat. Also, while the wafer is shown as a flat, unbent body with flat front and bottom surfaces, in some cases the wafer may be curved, e.g., planar but curved in one or two directions, resulting in a non-flat front and / or bottom surface.

[0118] Furthermore, in embodiments, the semiconductor wafer is not patterned or diced immediately after performing the method, although in some implementations the wafer is subsequently subjected to the formation of devices therein. However, it is currently contemplated that engineered wafers will be provided by their manufacturer to other parties who will then use them as raw materials for manufacturing semiconductor devices.

[0119] As a "semiconductor," any material can be used that has a non-zero intermediate band gap, behaves as an insulator at T=0 K, but below its melting point, more specifically at the intended operating temperature (e.g., above -20°C, e.g., above 0°C, and / or below 100°C, e.g., below 50°C, e.g., below 30°C), some states in the conduction band are occupied, thereby exhibiting electrical conductivity between that of an insulator and that of most metals. An example of a semiconductor layer is composed of a single semiconductor, such as germanium (Ge), or a compound semiconductor, as described below. The semiconductor can be a doped or undoped semiconductor.

[0120] A "compound semiconductor" can be a semiconductor composed of at least two different types of chemical elements, such as elements from groups III and V, and elements from groups II and VI. These semiconductors are typically formed from elements from groups 13-15 (old III-V) of the periodic table, such as elements from the boron group (old III, boron, aluminum, gallium, indium) and elements from group 15 (old V, nitrogen, phosphorus, arsenic, antimony, bismuth). Compound semiconductors can be, for example, binary (two elements, e.g., indium phosphide (InP), gallium(III) arsenide (GaAs)), ternary (three elements, e.g., indium gallium arsenide (InGaAs)), or quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys. Typical compound semiconductors are as follows: II-VI group: ZnSe Group III-V: GaAs, GaN, InP, InGaAlP, InGaN IV-IV group: SiC, SiGe

[0121] As "substrate" or "semiconductor substrate" can be used any type of body on which deposited layers of material can be formed or applied to form a semiconductor device, such as having a bulk or substrate layer of semiconductor material, preferably a porous top layer of compound semiconductor material. Preferably, the substrate is monocrystalline. The semiconductor substrate can be a wafer, wafer die, or other plate-like type of substrate (for simplicity, all referred to as "wafer") used as a substrate on which microelectronic devices can be built. The semiconductor substrate can be subjected to different processes such as doping, ion implantation, etching, thin film deposition, or lithographic patterning. The substrate can consist of a single substrate layer, or can constitute a stack having a substrate or bulk layer and one or more other layers.

[0122] Exemplary substrates that may be used include: Bulk germanium wafers, bulk InP wafers, bulk GaN wafers, bulk GaAs wafers, bulk Ga wafers, which have a single crystal layer of uniform thickness as the bulk layer; simple semiconductor wafers comprising a substrate or bulk layer of homogeneous thickness of a simple semiconductor (e.g., Ge) that is monocrystalline, polycrystalline, or amorphous; a compound semiconductor wafer comprising a substrate or bulk layer of a homogeneous thickness of a monocrystalline, polycrystalline, or amorphous compound semiconductor; Examples of suitable wafers include, but are not limited to, composite or engineered wafers comprising a stack of layers having a bulk layer of a simple or compound semiconductor and one or more layers on top of the bulk layer. Two or more layers can be of the same material and crystalline structure but with different porosities, such as a non-porous bulk layer and a porous surface layer (preferably both InP), forming a homogeneous composition structure. Alternatively, two or more layers can form a heterogeneous composition structure of layers of different materials and / or crystalline structures, such as an InP-on-x wafer. The InP-on-x wafer comprises a layer of InP disposed on a homogeneous bulk layer of a different simple or compound semiconductor material, which may be monocrystalline, polycrystalline, or amorphous. A homogeneous or heterogeneous composition stack can form a heterostructure. Preferably, the semiconductor substrate comprises a bulk layer comprising a material selected from the group consisting of Ge, InP, GaP, GaAs, and GaN. More preferably, the bulk layer consists essentially of this material, e.g., such a material, and the composite wafer has a porous InP surface layer.

[0123] However, other modifications, variations, and alternatives are also possible.

[0124] Unless otherwise defined, all terms, including technical and scientific terms, have the meanings commonly understood by those skilled in the art of semiconductor processing. By way of further guidance, definitions of terms are included to better understand the teachings of the present invention.

[0125] As used herein, the following terms have the following meanings: As used herein, "a," "an," and "the" mean "one or more," and refer to both singular and plural referents, unless the context clearly dictates otherwise. The use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that the introduction of another claim element with the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to embodiments containing only one such element. This is true even if the same claim contains both an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an."

[0126] As used herein, "about" referring to a measurable value such as a parameter, amount, duration, etc. is considered synonymous with the term "substantially" and is meant to encompass a variation of no more than ±20%, preferably no more than ±10%, more preferably no more than ±5%, even more preferably no more than ±1%, and still more preferably no more than ±0.1% from the particular value, provided such variation is appropriate for the practice of the disclosed invention, with the understanding that the value referred to by the "about" modifier is itself specifically disclosed.

[0127] As used herein, the terms "comprise," "comprising," "comprises," and "comprised of" are synonymous with "include," "including," "includes," or "contain," "containing," or "contains," and are inclusive or open-ended terms that specify the presence of what follows, e.g., a component, and do not exclude or preclude the presence of additional, unlisted components, features, elements, materials, steps that are known in the art or disclosed therein.

[0128] The recitation of numerical ranges by endpoints includes not only the recited endpoints but also all numbers and fractions subsumed within that range. All percentages, unless otherwise defined or unless a different meaning is apparent to one of ordinary skill in the art from their use and the context in which they are used, are understood to be percent by weight, abbreviated as "wt %," or percent by volume, abbreviated as "vol %."

[0129] Terms such as "front," "back," "top," "bottom," "upper," "lower," and the like, used in this specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It is understood that terms so used are interchangeable under appropriate circumstances, and that embodiments of the invention described herein are operable, for example, in orientations other than those shown or otherwise described herein.

[0130] Terms such as "first" and "second" are used to arbitrarily distinguish between elements that such terms describe, and as such, these terms are not necessarily intended to indicate a temporal or other priority of such elements.

[0131] In the context of the present invention, the term "substrate" generally refers to a material having a thickness of at least 1 μm. A semiconductor substrate as used in the context of the present invention is, for example, It can have a wafer size of 1 inch (25 mm) and typically have a thickness of about 275 μm; It can have a wafer size of 2 inches (51 mm) and typically have a thickness of about 275 μm; It can have a wafer size of 3 inches (76 mm) and typically have a thickness of about 375 μm; It can have a 4 inch (100 mm) wafer size and typically have a thickness of about 525 μm; It can have a wafer size of 5 inches (125 mm) and typically have a thickness of about 625 μm; It can have a wafer size of 6 inches (150 mm) and typically have a thickness of about 675 μm; It can have an 8 inch (200 mm) wafer size and typically have a thickness of about 725 μm; The wafer size may be 12 inches (300 mm) and may typically have a thickness of about 775 μm.

[0132] In the context of the present invention, the term "film" or "semiconductor film" refers to a semiconductor material having a substantially uniform thickness of material covering its surface. A film can have a porous or non-porous structure. In the context of the present invention, the term "film" refers to a material having a thickness of 0.01 μm to 1 μm.

[0133] In the context of the present invention, the term "layer" or "semiconductor layer" refers to a semiconductor material having a substantially uniform thickness of material covering a surface. A layer can be either continuous or discontinuous (i.e., having gaps between regions of material). For example, a layer can completely or partially cover a surface, or can be divided into discrete regions that collectively define the layer (i.e., regions formed using selective area epitaxy). Furthermore, a layer can have a porous or non-porous structure. In the context of the present invention, the term "layer" refers to a material having a thickness of at least 1 μm and at most 800 μm.

[0134] A first layer or film described and / or indicated herein as "constituted on," "deposited on," "on top of," "on," or "over" a second layer or film may be directly adjacent to the second layer, i.e., in contact with the second layer or film, or one or more intervening layers may be present between the first and second layers or films. In preferred embodiments of the present invention, the first layer or film is in direct contact with, or bonded to, the second layer or film. In the context of the present invention, the term "disposed on" means "existing on" an underlying material or layer. This underlying layer may include intermediate layers, such as transitional layers, necessary to ensure a suitable surface. For example, when a material is described as "disposed on a substrate," this may mean either that the material is in contact with the substrate or that the material is separated from the substrate by one or more intermediate layers present on the substrate.

[0135] In the context of the present invention, the term "directly contacting" is synonymous with the terms "directly bonded," "directly bonded," and "in direct contact," and should be understood as two separate layers that are distinguishable by a layer boundary, for example, from cross-sectional SEM image analysis. The two separate layers can be connected or bonded to each other with or without a bonding agent, such as an organic or inorganic adhesive. The different layers can have similar properties, such as having the same composition, crystallinity, or porosity. For example, the separate layers may form a single-crystal structure but have different porosities. For example, this applies to a single-crystal wafer comprising a non-porous bulk layer (also called a substrate layer) and a porous top layer with an exposed surface.

[0136] In the context of the present invention, the volumetric porosity of a material is expressed as a volume percentage and is abbreviated as "vol %" or "%". In the context of the present invention, the term "porous" refers to a layer or film comprising pores, wherein the void volume of the layer or film is at least 1% by volume of the total volume of the layer or film. Typically, unless otherwise specified, the void volume of a porous layer is at most 30%, 40%, 50%, 60%, or even at most 70%. In the context of the present invention, the term "non-porous" refers preferably to a layer or film that is free of pores or has a porosity of at most 1%, preferably at most 0.8%, more preferably at most 0.5%, and most preferably 0%.

[0137] In the context of the present invention, the porosity of a layer or film can be measured by SEM analysis of the layer or film at multiple stages of the electrochemical etching process. The porosity is analyzed with the OpenCV image analysis library using noise removal and adaptive Gaussian image thresholding to measure the porosity.

[0138] In the context of the present invention, the term "surface" refers to the two-dimensional outer surface or outer boundary of an object or part of an object, e.g., a layer, and the term "surface area" refers to the size of the surface. Also, the term "surface layer" refers to the exposed three-dimensional outer surface or outer boundary, e.g., a layer, of an object or part of an object. Thus, in the context of the present invention, the term "surface" is distinguished from the terms "surface region" and "surface layer." Surfaces are generally referred to as "front" or "back" simply for convenience and to distinguish them from the surfaces of substrates.

[0139] Any of the structures shown and described herein may be part of a larger structure having additional layers above and / or below that shown. For clarity, the figures herein may omit these additional layers, but these additional layers may be part of the disclosed structure. Furthermore, the structures shown may be repeated in units even if that repetition is not shown in the figures.

[0140] The growth and / or deposition described herein may be carried out using one or more of chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and / or physical vapor deposition (PVD).

[0141] In the claims, any reference signs placed between parentheses shall not be construed as limiting the scope of the claims. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

[0142] In conclusion, a compound semiconductor wafer, in a first aspect, the invention provides a composite layer structure having a stack (2) of layers (2a, 2b), said stack comprising: a substrate layer of a semiconductor material that is one of the group consisting of GaAs, GaP, and Ge; a porous layer extending over the substrate layer, the porous layer being InP and comprising: i. a porous InP layer having a surface porosity of 50% or less, as measured by SEM, on the porous surface facing away from the substrate layer; ii. A porous InP layer having a volume porosity of 10% or less as measured by SEM; iii. a porous InP layer provided with tubular and triangular pores extending from the porous surface towards the substrate layer; More specifically, a compound semiconductor wafer having characteristics ii. and / or iii. is provided.

[0143] In a preferred embodiment, the present invention provides a compound semiconductor wafer as disclosed above, wherein the porous layer (2b) comprises (ii) and has a volume porosity of 5% or less as measured by SEM.

[0144] In a preferred embodiment, the present invention provides a compound semiconductor wafer as disclosed above, wherein the porous surface layer (2b) comprises (iii) tubular, triangular or mixed pores extending perpendicular to the exposed surface.

[0145] In a preferred embodiment, the present invention provides the compound semiconductor wafer disclosed above, wherein the porous surface has (i), the tubular pores extend from pore inlets located on the porous surface into the porous layer, and the pore inlets have a median diameter in the range of 70 nm to 150 nm.

[0146] In a preferred embodiment, the present invention provides the compound semiconductor wafer disclosed above, in which some or all of the tubular pores are branched, and the branched pores branch from the substrate layer toward the porous surface or in the reverse direction.

[0147] In a second aspect, the present invention provides a method for preparing a composite semiconductor structure, comprising the steps of: Providing a semiconductor substrate having an InP substrate layer (2a); providing a substrate having a porous layer (2b, 2c) of InP, the porous layer extending on a substrate layer (2a) and comprising a high-porosity sublayer (2c) and a low-porosity sublayer (2b) having a volume porosity lower than the volume porosity of the high-porosity sublayer (2c), the low-porosity sublayer (2b) extending between the substrate layer (2a) and the substrate side of the high-porosity sublayer (2c); The method includes providing a semiconductor wafer having an exposed low-porosity surface of InP facing away from a substrate layer, the providing including partially removing the porous layer to expose a sublayer on the low-porosity side.

[0148] In a preferred embodiment, the present invention provides preparing the porous layer includes electrochemically etching a substrate layer to obtain an InP homogeneous composition structure comprising a substrate layer (2a) and porous layers (2b, 2c); The method disclosed above is provided, wherein partially removing the porous layer comprises chemically mechanically polishing the porous layer (2b, 2c) to a depth at which the sublayer (2b) on the lower porosity side is exposed.

[0149] In a preferred embodiment, the present invention provides The method disclosed above includes contacting the exposed surface of the low porosity side with a surface layer of a heterogeneous substrate comprising a GaAs or GaP substrate layer, and thermally bonding the low porosity layer to the surface layer of the heterogeneous layer to form a thermally bonded substrate.

[0150] In a preferred embodiment, the present invention provides The method disclosed above includes separating the porous layer from one or more layers of the semiconductor substrate, whereby at least the substrate layer (2a) is separated from the thermally bonded substrate, thereby obtaining a substrate comprising a stack comprising a GaAs or GaP substrate layer (1) and a porous InP surface layer (2b).

[0151] In a preferred embodiment, the present invention provides the method disclosed above, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b).

[0152] In a preferred embodiment, the present invention provides the method disclosed above, wherein the porous layer (2b) is formed by electrochemical etching of an InP substrate, and the difference between the applied voltage and the open circuit voltage is kept constant.

[0153] In a preferred embodiment, the present invention relates to a method for electrochemical etching comprising subjecting an InP substrate to an electrochemical pretreatment, wherein the etching current is 0 mA / cm for a time period of less than 3 seconds. 2up to 125mA / cm 2 The method disclosed above provides a linear increase in the amount of

[0154] In a preferred embodiment, the present invention provides a method for etching a silicon wafer at the end of the time period, where the etching current is 0 mA / cm 2 The present invention provides the method disclosed above, wherein the

[0155] In a preferred embodiment, the present invention provides the method disclosed above, wherein the highly porous layer (2c) is subjected to chemical mechanical polishing using a slurry containing an alkaline aqueous solution having a pH of 9 to 12 and silica nanoparticles.

[0156] In a third aspect of the present invention, there is provided a compound semiconductor layered structure obtained by the method described above.

Claims

1. a substrate layer (2a or 1) made of a semiconductor material selected from the group consisting of InP, GaAs, GaP and Ge; a compound semiconductor multilayer structure comprising a porous layer (2b) extending on said substrate layer (2a or 1), said porous layer (2b) consisting of InP and having a volume porosity of less than or equal to 20% as measured by SEM.

2. 2. The compound semiconductor multilayer structure according to claim 1, wherein said porous layer (2b) has a volume porosity of less than or equal to 10%, preferably less than or equal to 5%, as measured by SEM.

3. Compound semiconductor multilayer structure according to claim 1 or 2, wherein said porous layer (2b) has a thickness of 1 to 50 μm, preferably 5 to 50 μm, as measured by SEM.

4. 2. The compound semiconductor multilayer structure of claim 1, wherein the porous layer (2b) has mixed pores extending perpendicular to the exposed surface, the mixed pores having a morphology intermediate between current line oriented pores and crystallographically oriented pores.

5. 2. The compound semiconductor multilayer structure of claim 1, wherein the porous layer (2b) has pores extending into the porous layer (2b) from pore entrances located on the porous surface, the pore entrances having a median diameter in the range of 70 nm to 150 nm.

6. 2. The compound semiconductor multilayer structure of claim 1, wherein the substrate layer (2a) consists of InP.

7. 2. Compound semiconductor multilayer structure according to claim 1, wherein said substrate layer (1) is made of a material selected from the group consisting of GaAs, GaP and Ge, preferably GaAs and GaP.

8. 1. A method for preparing a compound semiconductor multilayer structure, comprising: - electrochemically etching an InP compound semiconductor substrate to form a porous layer (2b) of InP, said porous layer extending over said substrate layer (2a), said porous layer having a volume porosity of less than or equal to 20% as measured by SEM.

9. The method according to claim 8, wherein said porous layer (2b) is formed by electrochemical etching at a voltage between 4.5V and 5.5V, preferably at a voltage of about 5V.

10. 9. The method of claim 8, wherein the porous layer (2b) is formed to have a volume porosity of 10% or less, preferably 5% or less, as measured by SEM.

11. - a substrate is provided having a porous layer (2b, 2c) of InP, the porous layer extending on the substrate layer (2a) and comprising a high-porosity sublayer (2c) and a low-porosity sublayer (2b) having a volume porosity lower than the volume porosity of the high-porosity sublayer (2c), the low-porosity sublayer (2b) extending between the substrate layer (2a) and the substrate side of the high-porosity sublayer (2c); A method according to any one of claims 8 to 10, comprising providing a semiconductor wafer having an exposed low-porosity surface of InP facing away from the substrate layer, said providing comprising removing the sublayer (2c) on the high-porosity side to expose the sublayer (2b) on the low-porosity side.

12. - preparing said porous layer comprises electrochemically etching said substrate layer to obtain an InP homocomposition structure comprising a substrate layer (2a) and said porous layers (2b, 2c), and The method of claim 11, wherein removing the sub-layer (2c) on the higher porosity side comprises chemical-mechanical polishing of the porous layers (2b, 2c) to a depth at which the sub-layer (2b) on the lower porosity side is exposed.

13. 12. A method according to claim 11, comprising contacting the exposed surface of the low-porosity side with a surface layer of a foreign substrate, the surface layer being a GaAs, GaP or Ge substrate layer, and thermally bonding the low-porosity layer to the surface layer of the foreign layer to form a thermally bonded substrate.

14. - a method according to claim 13, comprising separating the porous layer from one or more layers of the semiconductor substrate, at least the substrate layer (2a) being separated from the thermally bonded substrate, thereby obtaining a substrate comprising a layer stack comprising a substrate layer (1) of GaAs or GaP or Ge and a porous InP surface layer (2b).

15. 15. The method of claim 14, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b).

16. 9. A method according to claim 8, wherein the porous layer (2b) is formed by electrochemical etching of an InP substrate, the difference between the applied voltage and the open circuit voltage being kept constant.

17. The electrochemical etching includes subjecting the InP substrate to an electrochemical pretreatment, wherein the pretreatment provides an etching current of 0 mA / cm for a time period of less than 3 seconds. ２ up to 125mA / cm ２ 9. The method of claim 8, wherein the temperature is increased linearly to

18. At the end of the time, the etching current is 0 mA / cm ２ 18. The method of claim 17, wherein the

19. The method according to claim 11, wherein said highly porous layer (2c) is subjected to said chemical mechanical polishing using a slurry comprising an alkaline aqueous solution with a pH of 9-12 and silica nanoparticles.

20. A compound semiconductor layered structure obtained by the method of claim 8.

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