Systems and methods for adjusting the frequency of an RF amplifier

Abstract

Systems and methods for adjusting the frequency of a radio frequency (RF) amplifier are disclosed. One method includes receiving a coil current measurement signal. The coil current measurement signal is measured at the input of an RF coil of a plasma chamber. The method further includes generating a normalized sawtooth signal based on the coil current measurement signal. The method also includes applying a plurality of direct current (DC) references to the normalized sawtooth signal to determine a tuning frequency, and controlling a frequency generator of a matchless plasma source according to the tuning frequency. The tuning frequency is the frequency of the RF amplifier. The method further includes slow-pass control to optimize the efficiency of the RF amplifier.

Description

[Technical Field]

[0001] The present embodiments relate to a system and method for adjusting the frequency of a radio frequency (RF) amplifier. [Background technology]

[0002] The background art provided herein is intended to provide a general background to the present disclosure, and the work of the inventors named herein, to the extent described in this background art, along with aspects of the description that would not normally be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0003] In a plasma tool, a plasma source is provided. A plasma chamber is also provided, and the plasma chamber is coupled to the plasma source. A substrate is placed in the processing chamber for processing. The plasma source generates a radio frequency (RF) signal and transmits the RF signal to the plasma chamber to process the substrate. However, the substrate is not processed in an efficient and desirable manner. Summary of the Invention

[0004]

[0009] Embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for adjusting the frequency of a radio frequency (RF) amplifier. It should be understood that the present embodiments can be embodied in various forms, such as a process, an apparatus, a system, a device, or a method recorded on a computer-readable medium. Some embodiments are described below.

[0005] In some embodiments, it takes a long time to adjust the power output from the plasma system. For example, in the case of power control using a step-down converter, a direct current (DC) bus voltage is charged. The DC bus voltage drops due to the load until the control system reacts. The control system reacts to the voltage drop and adjusts the power output from the plasma system. In this example, the period from when the DC bus voltage is charged to when the control system reacts is at least 20 microseconds (μs). The long time to react is much longer than the predetermined rise time (e.g., 2.5 μs) of the transition of the amplified signal output from the RF amplifier.

[0006] In one embodiment, an agile DC rail is used to regulate and control the RF power supplied to the plasma load. The agile DC rail includes the output of a DC-DC converter (e.g., a buck converter). Due to the energy storage requirements of the agile DC rail, power control in the agile DC rail is not fast enough to drive the highly dynamic plasma impedance of the plasma load. Furthermore, an additional high-speed frequency regulation loop is preferably implemented to achieve zero-voltage switching (ZVS) of the RF amplifier's switching elements. The two control loops, including the control system for controlling the agile DC rail and the high-speed frequency regulation loop, are operated at different speeds so as not to interfere with each other. Operation at different speeds limits the power regulation and speed control. The buck converter is operated at a predetermined frequency (e.g., 200 kilohertz (kHz)) to achieve a predetermined rise time. However, operation at the predetermined frequency interacts with the frequency of operation of the plasma system's analog frequency regulator.

[0007] In one embodiment, the frequency generator of the matchless plasma source is operated at a tuning frequency higher than the resonant frequency for a given dynamic load. The tuning frequency is limited to be higher than the resonant frequency and is therefore varied to regulate the power output from the RF amplifier. In this embodiment, a step-down converter is not required. Higher efficiency and greater power density are obtained when a step-down converter is not utilized. Once the tuning frequency is achieved, zero voltage switching is achieved. Thus, in this embodiment, a single control is provided for achieving ZVS and regulating power.

[0008] Also, in one embodiment, the set frequency of the frequency generator is adjusted to determine a tuning frequency at half the RF period. In this way, the frequency of the frequency generator is adjusted very quickly to achieve zero voltage switching.

[0009] In one embodiment, a method is described for adjusting a specific plasma power amount by adjusting the switching frequency (e.g., tuning frequency) of an RF amplifier. While doing so, the RF switching frequency range of the RF amplifier is limited to facilitate zero-voltage switching of the RF amplifier's switching elements. By using the switching frequency for both RF power adjustment and zero-voltage switching, the method potentially eliminates a front-end DC-DC converter stage (e.g., a buck converter), contributing to significant improvements in power conversion efficiency, power density, and reliability.

[0010] In one embodiment, the method described herein facilitates plasma power control by adjusting the operating frequency of an RF amplifier. The antenna current is sensed, and a switching signal for the RF amplifier is generated based on a zero detection of the antenna current. The switching signal for the RF amplifier is limited to introduce a phase lag between the switch voltage and current. Delaying the switch current allows zero-voltage switching of each of the switching elements, contributing to improved efficiency. While the method described herein does not require an agile DC rail to control the power output from the RF amplifier, a slow DC bus rail can be utilized to set the DC voltage for a specific amount of power in a feedforward manner. The method described herein extends the operating plasma impedance of the RF amplifier while improving system efficiency.

[0011] In one embodiment, the method described herein provides a faster, more reliable approach to plasma power control by adjusting the operating frequency of an RF amplifier while maintaining zero voltage switching. The method also extends the range of operating plasma impedance by using an optimal feedforward DC bus voltage. The method integrates power control and fast frequency adjustment into a single control, providing simpler, faster, and more reliable plasma power control.

[0012] In one embodiment, the method described herein starts from a preset frequency (e.g., a high operating frequency of the RF amplifier) ​​and then modulates (e.g., increases) the preset frequency to a tuning frequency. The high frequency results in low gain, providing a soft and safe start for the RF amplifier. Transitioning from the high frequency to the tuning frequency achieves a soft switching condition for the RF amplifier. Due to the pulsing, after a few cycles, information about the tuning frequency can be stored and used to have a much faster response in subsequent operating cycles of the RF amplifier.

[0013] In one embodiment, the electric (E) and magnetic (H) modes of the plasma present different types of impedance to the RF amplifier. E mode presents a very high load and transitions to H mode when the plasma is ignited. During fixed-frequency operation of the RF amplifier, specifications indicating high voltage gain during E mode result in sub-resonant operation during H mode. An example of sub-resonant operation is an RF amplifier operating frequency lower than the RF amplifier's resonant operating frequency. Sub-resonant operation is a hard-switching mode that results in large switching transients and subsequent failure of switching elements. The method described herein actively tracks changes in the plasma's impedance and adjusts a preset frequency to operate the RF amplifier above a resonant condition (e.g., above the resonant operating frequency). The tracking is much faster than the E-to-H mode transition, resulting in a safer E-to-H mode transition.

[0014] In one embodiment, RF power pulsing is received as a specification. The RF power pulsing is limited when an agile DC rail is utilized due to charging and discharging of one or more bus capacitors of the buck converter, thereby varying the supplied power. The method described herein varies the gain of the RF amplifier by applying a tuning frequency, where the application of the tuning frequency is much faster than controlling the agile DC rail.

[0015] In one embodiment, the upper and lower operating frequency limits of the RF amplifier provide a safe operating range for the DC-DC converter.

[0016] In one embodiment, variable frequency-based control of the RF amplifier allows higher reactive power to be output from the RF amplifier when the RF amplifier is used to manage a high quality factor (Q) load. For high Q loads, the efficiency of the RF amplifier can be low, especially when operated at low power. Feedforward-based control controls the slow DC bus rail based on a predetermined plasma power, and the RF power amplifier is simultaneously adjusted to operate at a lower reactive power.

[0017] In one embodiment, the agile DC rail can be made much slower because the DC bus link is not used for closed-loop power control. Therefore, the DC bus capacitor of the DC-DC converter can be made much larger to provide high frequency attenuation and low input impedance to the RF amplifier, all of which results in stable and reliable operation.

[0018] In one embodiment, different gain settings of the RF amplifier are utilized during the E and H modes of operation. For example, a different tuning frequency of the RF amplifier is utilized during the E mode than is utilized during the H mode. During the E mode, the gain of the RF amplifier is set lower compared to the H mode, thereby optimizing the response time and overshoot or undershoot in both the E and H modes.

[0019] In one embodiment, a method for adjusting the frequency of an RF amplifier is described. The method includes receiving a coil current measurement signal. The coil current measurement signal is measured at the input of an RF coil of a plasma chamber. The method further includes generating a normalized sawtooth signal based on the coil current measurement signal. The method includes applying a plurality of DC references to the normalized sawtooth signal to determine a tuning frequency, and controlling a frequency generator of a matchless plasma source according to the tuning frequency. The tuning frequency is the frequency of the RF amplifier.

[0020] In one embodiment, a controller for adjusting the frequency of an RF amplifier is described. The controller includes a processor. The processor receives a coil current measurement signal. The coil current measurement signal is measured at the input of an RF coil of a plasma chamber. The processor generates a normalized sawtooth signal based on the coil current measurement signal. The processor applies multiple DC references to the normalized sawtooth signal to determine a tuning frequency. The processor controls a frequency generator of a matchless plasma source according to the tuning frequency. The controller includes a memory device coupled to the processor. The tuning frequency is the frequency of the RF amplifier.

[0021] In one embodiment, a system is described. The system includes a matchless plasma source. The matchless plasma source includes a frequency generator that generates a digital pulse signal. The matchless plasma source further includes a gate driver connected to the frequency generator. The gate driver receives the digital pulse signal and outputs a plurality of gate driver signals. The matchless plasma source includes an RF amplifier connected to the gate driver. The RF amplifier has an output. The RF amplifier receives the plurality of gate driver signals and provides an amplified waveform at the output of the RF amplifier. The system further includes a resonant circuit connected to the RF amplifier. The resonant circuit receives the amplified waveform and outputs a sinusoidal signal. The system includes a plasma chamber having an RF coil. The RF coil has an input connected to the resonant circuit to receive the sinusoidal signal. The system includes a controller connected to the matchless plasma source. The controller receives a coil current measurement signal measured at the input of the RF coil. The controller generates a normalized sawtooth signal based on the coil current measurement signal. The controller applies a plurality of DC references to the normalized sawtooth signal to determine a tuning frequency. The controller controls the frequency generator according to the tuning frequency.

[0022] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0023] The embodiments can be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0024] [Figure 1] FIG. 1 illustrates one embodiment of a system for explaining the determination of a tuning frequency of a radio frequency (RF) amplifier.

[0025] [Figure 2A] FIG. 10 shows an embodiment of a graph illustrating a method for determining a tuning frequency.

[0026] [Figure 2B] FIG. 10 shows an embodiment of a graph illustrating a method for determining a tuning frequency.

[0027] [Figure 2C] FIG. 10 shows an embodiment of a graph illustrating a method for determining a tuning frequency.

[0028] [Figure 2D] FIG. 10 illustrates one embodiment of a graph illustrating changing (e.g., widening) the range of tuning frequencies with an increase in the predetermined upper peak value and a decrease in the predetermined lower peak value.

[0029] [Figure 3A] FIG. 2 is a diagram of an embodiment of a processor for explaining the details of the processor.

[0030] [Figure 3B] FIG. 1 illustrates an embodiment of a system for varying the duty cycle of a pulsed direct current (DC) signal to output a modulated DC signal.

[0031] [Figure 4] FIG. 2 is a diagram of one embodiment of a system illustrating details of an RF amplifier and how a voltage sensor is connected to the output of the RF amplifier.

[0032] [Figure 5A] FIG. 10 shows an embodiment of a graph illustrating the control of power delivered by a matchless plasma source to achieve predetermined rise and fall times.

[0033] [Figure 5B] 1 shows an embodiment of a graph illustrating the occurrence of a transition from an electric mode (E) to a magnetic mode (H) of a plasma formed in a plasma chamber, and a transition from an H mode to an E mode of the plasma. FIG.

[0034] [Figure 5C] FIG. 10 illustrates one embodiment of a graph illustrating the change in DC reference with changing levels of coil current passing through an RF coil.

[0035] [Figure 6] 2 illustrates an embodiment of a graph to illustrate that for different loads, the frequency generator of the system of FIG. 1 is operated at different tuned frequencies to achieve zero voltage switching (ZVS).

[0036] [Figure 7] FIG. 10 illustrates an embodiment of a graph to explain that by controlling tuning frequency, an RF amplifier becomes less reactive and provides the same amount of gain as RF power. DETAILED DESCRIPTION OF THE INVENTION

[0037] The following embodiments describe systems and methods for adjusting the frequency of a radio frequency (RF) amplifier. It will be apparent that the embodiments may be practiced without some or all of these specific details. Additionally, detailed descriptions of well-known process operations have been omitted to avoid unnecessarily obscuring the embodiments.

[0038] FIG. 1 illustrates one embodiment of a system 100 for explaining the determination of the tuning frequency of an RF amplifier. The system 100 includes a frequency generator 102, a gate driver 104, an RF amplifier 106, a resonant circuit 108, an RF coil 110, a voltage / current (V / I) sensor 112, a processor 114, a direct current (DC) voltage source 116, a DC-to-DC (DC-DC) converter 118, a power sensor 120, and a plasma chamber 122. An example of the DC voltage source 116 is a battery or a capacitor. An example of the DC-DC converter 118 is an electronic circuit that converts a voltage received from the DC voltage source 116 from one level to another. An example of the frequency generator 102 is a digital pulse signal generator, such as a clock source. As an example, the resonant circuit 108 includes one or more capacitors connected to each other. As used herein, a processor may be an application specific integrated circuit (ASIC), a digital signal processor (DSP), a programmable logic device (PLD), a central processing unit (CPU), a microprocessor, a field programmable gate array (FPGA), an integrated controller, or a microcontroller. The ASIC, DSP, PLD, CPU, microprocessor, FPGA, integrated controller, and microcontroller are examples of integrated circuits. The RF coil 110 is an example of an electrode of the plasma chamber 122. For example, the RF coil 110 is disposed above a dielectric window of the plasma chamber 122. As another example, the RF coil 110 is a transformer coupled plasma (TCP) coil.

[0039] The frequency generator 102, gate driver 104, and RF amplifier 106 are components of a matchless plasma source (MPS), which does not include an impedance matching circuit and a 50 ohm RF cable.

[0040] The processor 114 is connected to the frequency generator 102, which is connected to the gate driver 104. The gate driver 104 is connected to the RF amplifier 106, which is connected to the resonant circuit 108. The resonant circuit 108 is connected to the RF coil 110. The processor 110 is also connected to the DC-DC converter 118. The RF amplifier 106 is connected to the DC-DC converter 118, which is connected to the DC voltage source 116. The power sensor 120 is connected to the output ODC of the DC-DC converter 118. The output O1 of the RF amplifier 106 is also connected to the resonant circuit 108. The power sensor 120 is connected to the processor 114. The V / I sensor 112 is connected between the RF coil 110 and the resonant circuit 108. For example, the V / I sensor 112 is connected to the input I1 of the RF coil 110 or the output of the resonant circuit 108, or between the input I1 and the output of the resonant circuit 108. Illustratively, the V / I sensor 112 is connected to an RF line 135 (such as an RF communication medium or an RF conductor), which connects the resonant circuit 108 to the RF coil 110. In that example, the input I1 is connected to the RF line 135. The V / I sensor 112 is connected to the processor 114.

[0041] The processor 114 provides a set frequency (such as a high frequency) to the frequency generator 102. The frequency generator 102 generates a digital pulse signal 124 having the set frequency and provides the digital pulse signal 124 to the gate driver 104. An example of a digital pulse signal used herein is a rectangular waveform. The gate driver 104 generates two gate driver signals 126A and 126B based on the digital pulse signal 124. For example, the gate driver 104 generates the gate driver signal 126A by allowing the digital pulse signal 124 to pass and generates the gate driver signal 126B by inverting the digital pulse signal 124. The gate driver signal 126B is inversely synchronized with respect to the gate driver signal 126A. The gate driver 104 transmits the gate driver signals 126A and 126B to the RF amplifier 106.

[0042] Additionally, the DC voltage source 116 generates a DC voltage signal 128 and sends the DC voltage signal 128 to the DC-DC converter 118. The DC-DC converter 118 converts the DC voltage signal 128 to output a DC voltage signal 130. For example, the DC-DC converter 118 changes the voltage level (e.g., amount or amplitude) of the DC-DC voltage signal 128 to another voltage level of the DC voltage signal 130. Illustratively, the DC-DC converter 118 increases or decreases the voltage level of the DC voltage signal 128 to provide the DC voltage signal 130. The DC-DC converter 118 sends the DC voltage signal 130 to the RF amplifier 106.

[0043] Based on the DC voltage signal 130 and the gate driver signals 126A and 126B, the RF amplifier 106 generates an amplified waveform 132 at the output O1. For example, the gate driver signals 126A and 126B include a set frequency that provides the timing at which switches (e.g., transistors) of the RF amplifier 106 are turned on or off, and the DC voltage signal 130 includes an amplitude (e.g., peak-to-peak voltage amplitude) of the amplified waveform 132. As a further example, the peak-to-peak amplitude of the amplified waveform 132 is provided by the voltage level of the DC voltage signal 128. As a further example, the amplified waveform 132 is a digital pulse waveform and not a sinusoidal waveform. Note that the digital pulse signal 124, the gate driver signal 126A, the gate driver signal 126B, and the amplified waveform 132 each have a set frequency.

[0044] The amplified waveform 132 is transmitted from output O1 to resonant circuit 108. Resonant circuit 108 removes higher harmonics from amplified waveform 132 to generate a sinusoidal waveform 134, which is transmitted to RF coil 110. Sinusoidal waveform 134 has a set frequency.

[0045] A substrate, such as a semiconductor wafer, is placed on a substrate support within the plasma chamber 122 for processing. An example of a substrate support is an electrostatic chuck (ESC), which is connected to ground potential, to one or more matchless plasma sources, or to one or more RF generators. When one or more process gases (such as an oxygen-containing gas, a nitrogen-containing gas, a chlorine-containing gas, or a combination thereof) are supplied to the interior space of the plasma chamber 122 along with the sinusoidal waveform 134, a plasma is ignited or maintained within the plasma chamber 122 to process the substrate. Examples of substrate processing include depositing material on the substrate, etching the substrate, or cleaning the substrate.

[0046] The V / I sensor 112 detects the sinusoidal coil current and outputs a coil current measurement signal 136, which it transmits to the processor 114. The processor 114 receives the coil current measurement signal 136 from the processor 114 and processes the coil current measurement signal 136 to determine the tuning frequency fn. For example, the processor 114 identifies zero crossings of the coil current measurement signal 136, and one or more of the zero crossings and a DC reference are used by the processor 114 to determine the tuning frequency fn. The DC reference is described in more detail below. The tuning frequency fn facilitates achieving a phase lag of the RF switch current through each of the switches of the RF amplifier 106 relative to the RF switch voltage across the switch to achieve zero voltage switching (ZVS) of the switch.

[0047] The processor 114 provides the tuning frequency fn to the frequency generator 102 to modulate the set frequency of the frequency generator 102 to the tuning frequency fn. The frequency generator 102 modulates the digital pulse signal 124 based on the tuning frequency fn to output a modulated digital pulse signal. For example, the frequency generator 102 modulates (e.g., raises or lowers) the set frequency of the digital pulse signal to the tuning frequency fn to output a modulated digital pulse signal. As an example, the frequency generator 102 is operated at the set frequency for a predetermined number of RF cycles of the digital pulse signal 124 (half an RF cycle, or one RF cycle, or two RF cycles, or three RF cycles, etc.) before the frequency generator 102 is operated at the tuning frequency fn. The gate driver 104 receives the modulated digital pulse signal and modulates the set frequency of each of the gate driver signals 126A and 126B to output modulated gate driver signals (e.g., a first modulated gate driver signal and a second modulated gate driver signal) having a tuned frequency. The second modulated gate driver signal is synchronized inversely by the gate driver 104 relative to the first modulated gate driver signal in the same way that the gate driver signal 126B is synchronized inversely relative to the gate driver signal 126A.

[0048] The RF amplifier 106 receives the modulated gate driver signal and modulates the set frequency of the RF amplifier signal 132 to a tuning frequency fn to output a modulated amplifier waveform. For example, the RF amplifier 106 generates the modulated amplifier waveform based on the modulated gate driver signal in the same way that the amplifier waveform 132 is generated based on the gate driver signals 126A and 126B. The modulated amplifier waveform having the tuning frequency fn is sent to the resonant circuit 108 to remove high-order harmonics from the modulated amplifier waveform and output a modulated sinusoidal signal. The modulated sinusoidal signal having the tuning frequency fn is sent to the RF coil 110 to process the substrate.

[0049] Further, power control is achieved based on the tuning frequency fn. For example, the V / I sensor 112 measures the power of the sinusoidal signal 134 to generate a value of the measured power. The processor 114 receives the measured power and compares it with the set power of the digital pulse signal 124. The processor 114 modulates the power of the digital pulse signal 124 until the measured power is within a predetermined range of (e.g., equal to) the set power, and outputs a modulated digital pulse signal. The set power is provided by the processor 114 to the frequency generator 102. Upon receiving the set power, the frequency generator 102 generates the digital pulse signal 124 at the set power.

[0050] The processor 114 also determines a measured phase Φ measured based on a DC reference and an optimal phase Φ optimal . Further details of determining the measured phase and the optimal phase will be provided later. The processor 114 controls the voltage level (e.g., amplitude) of the DC voltage signal 130 based on the measured phase and the optimal phase. For example, the processor 114 controls (e.g., increases or decreases) the level of the DC voltage signal 130 via a pulse-width modulator (PWM) described below until the measured phase is within a predetermined range from the optimal phase (e.g., equal to the optimal phase). When the measured phase is within the predetermined range from the optimal phase, the DC-DC converter 118 outputs a modulated DC signal having a voltage level and transmits the modulated DC signal to the RF amplifier 106. The RF amplifier 106 generates a modulated amplified waveform 132 based on the modulated DC signal in the same manner as the RF amplifier 106 generates a modulated amplified waveform 132 based on the DC voltage signal 130.

[0051] In one embodiment, the system 100 does not include a DC-DC converter 118. In that embodiment, the DC voltage source 116 is connected directly to the RF amplifier 106.

[0052] 2A is one embodiment of a graph 200 illustrating a method for determining tuning frequency fn. Graph 200 plots time t on the x-axis, amperes (Amps) on a first y-axis, and voltage (Volts) on a second y-axis. Time t increases from time t0 to time t32. Graph 200 includes a coil current measurement signal 202, which is an example of coil current measurement signal 136 (FIG. 1).

[0053] The processor 114 receives the coil current measurement signal 202 from the V / I sensor 112 (FIG. 1) and generates rectangular pulses 204 of a fixed amplitude (e.g., 1 volt or −1 volt) from the coil current measurement signal 202. For example, in an analog implementation of the processor 114, a comparator in the processor 114 compares each value of the coil current measurement signal 202 to zero to determine whether the value is greater than or less than zero. In this example, if the value of the coil current measurement signal 202 is determined to be greater than zero, the comparator outputs a value of 1 volt, and if the value of the coil current measurement signal 202 is determined to be less than zero, the comparator outputs a value of −1 volt. Thus, in this example, the comparator outputs a voltage value that transitions between 1 volt and −1 volt periodically according to the period of the coil current measurement signal 202. Each transition in the voltage value occurs at a zero crossing of the coil current measurement signal 136. Illustratively, a first transition from 1 volt to −1 volt occurs at time t8, a second transition from −1 volt to 1 volt occurs at time t16, a third transition from 1 volt to −1 volt occurs at time t24, and a fourth transition from −1 volt to 1 volt occurs at time t32. In this example, processor 114 determines that each of the zero crossings occurs at times t0, t8, t16, and t32, when the value of coil current measurement signal 136 is zero. Thus, rectangular pulse 204 extends from time t0 to time t32 so as to span the duration of occurrences of coil current measurement signal 202. Note that time t8 occurs after time t0, time t16 occurs after time t8, time t24 occurs after time t16, and time t32 occurs after time t24. As another example, the function of the comparator that outputs the rectangular pulse 204 may be implemented using an FGPA instead of a comparator to provide a digital implementation of the processor 114 .

[0054] FIG. 2B is an embodiment of a graph 210 illustrating a method for determining tuning frequency fn. Graph 210 plots time t on the x-axis, amperes (amps) on a first y-axis, and voltage on a second y-axis. Graph 210 includes a sawtooth signal 212 generated by processor 114 (FIG. 1). Processor 114 integrates rectangular pulses 204 (FIG. 2A) to generate sawtooth signal 212. For example, processor 114 sums the voltage values ​​of rectangular pulses 204 over time t to generate the voltage values ​​of sawtooth signal 212. For example, the processor 114 generates a sawtooth pulse 217 (having a peak voltage value 214) of the sawtooth signal 212 by adding the first voltage value of the rectangular pulse 204 at time t1 to the second voltage value of the rectangular pulse 204 at time t2, and so on, up to the eighth voltage value of the rectangular pulse 204 at time t8, when a zero crossing occurs in the coil current measurement signal 202. The sawtooth pulse 217 of the sawtooth signal 212 extends from time t0 to time t8. The peak voltage value 214 corresponds to time t8. For example, the peak voltage value 214 occurs at time t8. The processor 114 draws a line from the zero voltage value to the peak voltage value 214 to generate the sawtooth signal 212. Note that the peak voltage value 214 occurs at time Trf / 2, which is half the time Trf of the cycle of the coil current measurement signal 202. As another example, the processor 114 generates a sawtooth pulse 219 (having a peak voltage value 216) of the sawtooth signal 212 by adding the first voltage value of the rectangular pulse 204 at time t8 to the second voltage value of the rectangular pulse 204 at time t9, and so on, up to the eighth voltage value of the rectangular pulse 204 at time t16, when a zero crossing occurs in the coil current measurement signal 202. The sawtooth pulse 219 of the sawtooth signal 212 extends from time t8 to time t16. The peak voltage value 216 corresponds to time t16. For example, the peak voltage value 216 occurs at time t16. The processor 114 draws a line from the zero voltage value at time t8 to the peak voltage value 216 to generate the sawtooth signal 212.

[0055] Note that sawtooth pulses 217 and 219 are generated based on a first cycle of coil current measurement signal 202. The first cycle occurs from time t0 to time t16. In a manner similar to the generation of sawtooth pulse 217, sawtooth pulse 221 of sawtooth signal 212 is generated by processor 114 based on a second cycle of coil current measurement signal 202. The second cycle occurs from time t16 to time t32. Also, in a manner similar to the generation of sawtooth pulse 219, sawtooth pulse 223 of sawtooth signal 212 is generated by processor 114 based on the second cycle of coil current measurement signal 202. The second cycle of coil current measurement signal 202 is consecutive to the first cycle of coil current measurement signal 202.

[0056] The processor 114 normalizes the sawtooth signal 212 to generate a normalized sawtooth signal 218, which is a voltage signal. For example, the processor 114 multiplies each value of the sawtooth pulse 217 by a predetermined constant until an upper peak value 220 of the normalized sawtooth signal 218 at time t8 is determined, thereby generating a normalized sawtooth pulse 225 of the normalized sawtooth signal 218. In this example, the predetermined constant is received by the processor 114 from a user via an input device connected to the processor 114. Examples of input devices include a mouse, a keypad, a keyboard, a touchscreen, and a stylus. In this example, the processor 114 resets the normalized sawtooth signal 218 to zero at time t8. As an example, processor 114 transitions normalized sawtooth signal 218 from upper peak value 220 to a value of zero at time t8. Also in this example, processor 114 multiplies each value of sawtooth pulse 219 by a predetermined constant until lower peak value 222 of normalized sawtooth signal 218 is determined to generate normalized sawtooth pulse 227 of normalized sawtooth signal 218. In this example, processor 114 resets lower peak value 222 to zero at time t16.

[0057] Continuing in this example, during a second cycle of the coil current measurement signal 202, the processor 114 multiplies each value of the sawtooth pulse 221 by a predetermined constant until an upper peak value 231 of the normalized sawtooth signal 218 is determined, and then divides that value by the peak value 220 to generate a normalized sawtooth pulse 229 of the normalized sawtooth signal 218. The upper peak value 230 is determined based on the value of the sawtooth pulse 221 at time t8. By dividing the sawtooth pulse 221 by the upper peak value 220 of cycle 1 of the coil current measurement signal 202, the upper peak value 231 is closer to a predetermined value (such as 1 volt) compared to the upper peak value 220. Illustratively, the upper peak value 231 is 1 volt. In this example, the processor 114 resets the upper peak value 231 to zero at time t24. Additionally, in this example, processor 114 multiplies each value of sawtooth pulse 223 by a predetermined constant until a lower peak value 235 of normalized sawtooth signal 218 is determined, and then divides the value by lower peak value 222 to generate normalized sawtooth pulse 233 of normalized sawtooth signal 218. By dividing sawtooth pulse 223 by lower peak value 222 of cycle 1 of coil current measurement signal 202, lower peak value 235 is closer to a predetermined value (such as −1 volts) compared to lower peak value 222. Illustratively, lower peak value 235 is −1 volts. In this example, processor 114 resets lower peak value 235 to zero at time t32.

[0058] Processor 114 determines DC reference 224 based on an upper peak value (such as upper peak value 220 or 231) of normalized sawtooth signal 218. For example, processor 114 limits DC reference 224 to be between half the upper peak value and the upper peak value of normalized sawtooth signal 218. Illustratively, processor 114 limits DC reference 224 to be between 0.5 volts and 1 volt. In this example, half the upper peak value of normalized sawtooth signal 218 is less than the upper peak value of normalized sawtooth signal 218 by a predetermined increment (e.g., half) of upper peak value 220 of normalized sawtooth signal 218. In this example, the predetermined increment is received from a user via an input device. In this example, a tuning frequency fn that exceeds the resonant frequency of RF amplifier 106 is achieved by limiting DC reference 224 to be less than the upper peak value of normalized sawtooth signal 218 and greater than half the upper peak value of normalized sawtooth signal 218. Similarly, processor 114 determines DC reference 226 based on the lower peak value (such as lower peak value 222 or 235) of normalized sawtooth signal 218. As an example, processor 114 limits DC reference 226 to be between half the lower peak value of normalized sawtooth signal 218 and the lower peak value of normalized sawtooth signal 218. Illustratively, processor 114 limits DC reference 226 to be between −0.5 volts and −1 volt. In this example, the value that is half the lower peak value of normalized sawtooth signal 218 is greater than the lower peak value of normalized sawtooth signal 218 by a predetermined increment (e.g., half) of the lower peak value of normalized sawtooth signal 218. In this example, a tuning frequency f that exceeds the resonant frequency of RF amplifier 106 is achieved by limiting DC reference 226 to be greater than the lower peak value of normalized sawtooth signal 218 and less than half the lower peak value of normalized sawtooth signal 218. In this example, the predetermined increment is received from a user via an input device.

[0059] Note that when DC reference 224 is equal to half the upper peak value of normalized sawtooth signal 218, zero active power is output from RF amplifier 106, and when DC reference 224 is equal to half the upper peak value of normalized sawtooth signal 218, a peak amount of active power is output from RF amplifier 106. Similarly, when DC reference 226 is equal to half the lower peak value of normalized sawtooth signal 218, zero active power is output from RF amplifier 106, and when DC reference 226 is equal to half the lower peak value of normalized sawtooth signal 218, a peak amount of active power is output from RF amplifier 106.

[0060] 2C is one embodiment of a graph 250 for illustrating a method for determining a tuning frequency fn. Graph 250 plots the power of a modulated digital pulse signal output from frequency generator 102 versus time t. The power of the modulated digital pulse signal is plotted on the y-axis of graph 250, and time t is plotted on the x-axis of graph 250. The power values ​​(P0, P1, P2, etc.) of the power of the modulated digital pulse signal are plotted on the y-axis of graph 250. Graph 250 plots a digital pulse signal 252 versus time t.

[0061] After determining DC references 224 and 226 (FIG. 2B), processor 114 further determines tuning frequency fn based on one or more of DC references 224 and 226 and normalized sawtooth signal 218. For example, in an analog implementation of processor 114, for the first cycle of coil current measurement signal 202, a comparator in processor 114 compares each value of normalized sawtooth pulse 225 with DC reference 224 to determine whether the value is greater than or less than DC reference 224. If the comparator determines that the value of normalized sawtooth pulse 225 is less than DC reference 224, it does not output digital pulse 254 of digital pulse signal 252, and if the comparator determines that the value of normalized sawtooth pulse 225 is greater than DC reference 224, it starts outputting digital pulse 254. As an example, from time t0 to time t5.5, the comparator determines that the value of normalized sawtooth pulse 225 is less than DC reference 224 and outputs power value P0 for digital pulse signal 252. In this example, at time t5.5, when normalized sawtooth pulse 225 transitions from less than DC reference 224 to greater than DC reference 224, the comparator transitions digital pulse signal 252 from power value P0 to power value P2 and begins outputting digital pulse 254. In this example, the comparator maintains digital pulse 254 at power value P2 during the period when the value of normalized sawtooth pulse 225 is greater than DC reference 224 (from time t5.5 to time t8) until normalized sawtooth pulse 225 reaches a reset state. In this example, the portion of normalized sawtooth signal 218 from time t5.5 to time t8 is greater than DC reference 224.

[0062] Further, in this example, for the first cycle of the coil current measurement signal 202, the comparator of the processor 114 compares each value of the normalized sawtooth pulse 227 with the DC reference 226 to determine whether the value is greater than or less than the DC reference 226. If the comparator determines that the value of the normalized sawtooth pulse 227 is greater than the DC reference 226, the comparator continues to output the digital pulse 254, and if the comparator determines that the value of the normalized sawtooth pulse 227 is less than the DC reference 226, the comparator stops outputting the digital pulse 254. Illustratively, the comparator continues to output the power value P2 of the digital pulse 254 until the normalized sawtooth pulse 227 transitions from greater than the DC reference 226 to less than the DC reference 226. In this example, at time t16, normalized sawtooth signal 218 is in a reset state, and the value of normalized sawtooth pulse 227 is greater than DC reference 226 during the period from time t8 to time t13.5. In this example, the comparator outputs a power value P2 at time t8 and during the period from time t8 to time t13.5. In this example, the comparator determines that normalized sawtooth pulse 227 transitions from greater than DC reference 226 to less than DC reference 226 at time t13.5, transitions digital pulse signal 252 from power value P2 to power value P0 at time t13.5, and stops outputting digital pulse 254. In this example, the comparator outputs digital pulse signal 252 to have a power value of P0 until normalized sawtooth pulse 227 reaches a reset state at time t16. Thus, the comparator generates digital pulses 254 of the digital pulse signal 252 .

[0063] The digital pulse 254 may be generated at time Trf / 2, which is time t8, so that the tuning frequency fn is determined by the processor 114 at half the period of the high frequency of the coil current measurement signal 202 (see FIG. 2A). Determining the tuning frequency fn at half the period of the high frequency of the coil current measurement signal 202 is a very fast frequency adjustment of the frequency generator 102. Illustratively, the high frequency of the coil current measurement signal 202 is equal to the high frequency of the digital pulse signal 124.

[0064] Further, in this example, for the second cycle of the coil current measurement signal 202, the comparator compares each value of the normalized sawtooth pulse 229 with the DC reference 224 to determine whether the value is greater than or less than the DC reference 224. If the comparator determines that the value of the normalized sawtooth pulse 229 is less than the DC reference 224, the comparator does not output a digital pulse 256 of the digital pulse signal 252, and if the comparator determines that the value of the normalized sawtooth pulse 229 is greater than the DC reference 224, the comparator begins outputting the digital pulse 256. Illustratively, from time t16 to time t23, the comparator determines that the value of the normalized sawtooth pulse 229 is less than the DC reference 224 and outputs a power value P0 of the digital pulse signal 252. In this example, at time t23 when normalized sawtooth pulse 229 transitions from less than DC reference 224 to greater than DC reference 224, the comparator transitions digital pulse signal 252 from power value P0 to power value P2 and begins outputting digital pulse 256. In this example, the comparator maintains digital pulse 256 at power value P2 during the period when the value of normalized sawtooth pulse 229 is greater than DC reference 224 (from time t23 to time t24) until normalized sawtooth pulse 229 reaches its reset state. In this example, the portion of normalized sawtooth signal 218 from time t23 to time t24 is greater than DC reference 224.

[0065] Further, in this example, for the second cycle of the coil current measurement signal 202, the comparator of the processor 114 compares each value of the normalized sawtooth pulse 233 with the DC reference 226 to determine whether the value is greater than or less than the DC reference 226. If the comparator determines that the value of the normalized sawtooth pulse 233 is greater than the DC reference 226, the comparator continues to output the digital pulse 256, and if the comparator determines that the value of the normalized sawtooth pulse 233 is less than the DC reference 226, the comparator stops outputting the digital pulse 256. Illustratively, the comparator continues to output the power value P2 of the digital pulse 256 until the normalized sawtooth pulse 233 transitions from greater than the DC reference 226 to less than the DC reference 226. In this example, at time t32, normalized sawtooth signal 218 is in a reset state, and the value of normalized sawtooth pulse 233 is greater than DC reference 226 during the period from time t24 to time t31. In this example, the comparator outputs a power value P2 at time t24 and during the period from time t24 to time t31. In this example, at time t31, the comparator determines that normalized sawtooth pulse 233 has transitioned from greater than DC reference 226 to less than DC reference 226, stops outputting digital pulse 256, transitions digital pulse signal 252 from power value P2 to power value P0, and stops outputting digital pulse 256. In this example, the comparator outputs digital pulse signal 252 to have a power value of P0 until normalized sawtooth pulse 227 reaches a reset state at time t32. In this manner, the comparator generates digital pulses 256 of digital pulse signal 252. As another example, the functionality of the comparator that outputs digital pulse signal 252 is implemented using an FPGA instead of a comparator to provide a digital implementation of processor 114.

[0066] The digital pulse signal 252 is sometimes referred to herein as a switching signal for switching each of the switches of the RF amplifier 106 (FIG. 1). For example, the tuning frequency fn is the frequency at which each of the switches of the RF amplifier 106 (FIG. 1) operates (e.g., transitions) between an on state and an off state. Illustratively, the tuning frequency fn provides the timing for turning each of the switches of the RF amplifier 106 on and off. As a further illustrative example, the tuning frequency fn is the frequency at which a first one of the transistors of the RF amplifier 106 turns on and off and a second one of the transistors of the RF amplifier 106 turns off and on. In a further illustrative example, the first one of the transistors is turned on at time t5.5 and the second one of the transistors is turned off at time t5.5. In yet another illustrative example, the first one of the transistors is turned off at time t13.5 and the second one of the transistors is turned on at time t13.5. Furthermore, in a further example, a first one of the transistors is turned on at time t23 and a second one of the transistors is turned off at time t23, and a first one of the transistors is turned off at time t31 and a second one of the transistors is turned on at time t31.

[0067] 2D is one embodiment of a graph 260 illustrating a change (e.g., an increase) in the range of tuning frequencies fn with an increase in the upper peak value 231 and a decrease in the lower peak value 235 of the normalized sawtooth signal 218. The change in the range of tuning frequencies fn facilitates processing the substrate using one or more different processes (such as a process using one or more different impedance values ​​of the plasma) compared to another process achieved using the range of tuning frequencies fn without the change. Graph 260 plots voltage on the y-axis and time t on the x-axis.

[0068] Processor 114 (FIG. 1) increases upper peak value 231 of normalized sawtooth signal 218 from 1 volt to a value of 1+ΔV, which is an increment value ΔV, to form upper peak value 262 of normalized sawtooth signal 264. Instead of generating DC reference 224 (FIG. 2B) to be between upper peak value 231 of normalized sawtooth signal 218 and half of upper peak value 231 of normalized sawtooth signal 218, processor 114 generates another DC reference 266 between upper peak value 262 and half of upper peak value 262. The value of half of upper peak value 262 is represented as 0.5(1+ΔV). Note that half is an example of a predetermined increment. Processor 114 determines another tuning frequency fn1 using DC reference 266 and normalized sawtooth signal 264 in the same way that processor 114 determines tuning frequency fn using DC reference 224 and normalized sawtooth signal 218 (FIG. 2B). By using upper peak value 262 instead of upper peak value 231 of normalized sawtooth signal 218, the range of tuning frequencies fn is changed.

[0069] Additionally, processor 114 reduces lower peak value 235 of normalized sawtooth signal 218 (FIG. 2B) from −1 volts to a reduced increment ΔV (−1−ΔV) to generate another lower peak value 268 of normalized sawtooth signal 264. Instead of generating DC reference 226 (FIG. 2B) to be between lower peak value 235 of normalized sawtooth signal 218 and half of lower peak value 235 of normalized sawtooth signal 218, processor 114 generates another DC reference 270 between lower peak value 268 and half of lower peak value 268. Half of lower peak value 268 is represented as 0.5(−1−ΔV). Note that half is an example of a predetermined increment. Processor 114 determines another tuning frequency fn1 using DC reference 270 and normalized sawtooth signal 264 in the same way that processor 114 determines tuning frequency fn using DC reference 226 and normalized sawtooth signal 218. By using lower peak value 268 instead of lower peak value 235 of normalized sawtooth signal 218, the range of tuning frequencies fn is changed.

[0070] 3A is a diagram of one embodiment of processor 114 to explain the details of processor 114. Processor 114 includes a zero current detector (ZCD) 302, a square pulse generator 304, a sawtooth signal integrator 306, a normalizer 310, a voltage controller 312, a comparator 314, a tuning frequency determiner 316, and a comparator 318. By way of example, each of ZCD 302, square pulse generator 304, sawtooth signal integrator 306, normalizer 310, voltage controller 312, comparator 314, tuning frequency determiner 316, and comparator 318 is implemented as an integrated circuit. By way of illustration, ZCD 302 is a first integrated circuit and square pulse generator 304 is a second integrated circuit. As another example, each of ZCD 302, square pulse generator 304, sawtooth signal integrator 306, normalizer 310, voltage controller 312, comparator 314, tuning frequency determiner 316, and comparator 318 is implemented as a computer software program executed by processor 114 or as part of a computer software program executed by processor 114. Illustratively, ZCD 302 is part of a computer software program and square pulse generator 304 is another part of the computer software program.

[0071] ZCD 302 is connected to a rectangular pulse generator 304, which is connected to a sawtooth signal integrator 306. Sawtooth signal integrator 306 is connected to a normalizer 310. Normalizer 310 is connected to a voltage controller 312 and a comparator 314. Each comparator 314 and 318 is also connected to voltage controller 312.

[0072] The ZCD 302 receives the coil current measurement signal 202 (FIG. 2A) from the V / I sensor 112 (FIG. 1) and determines the zero current crossings of the coil current measurement signal 202. For example, the ZCD 302 identifies the times (such as times t0, t8, and t16) at which the value of the coil current measurement signal 202 is zero. Illustratively, the ZCD 302 receives times t0, t8, and t16 from a timer in the V / I sensor 112 and also receives from the V / I sensor 112 a correspondence between each of times t0, t8, and t16 and the zero values ​​of the coil current measurement signal 202. In this example, the ZCD 302 identifies from the correspondence that the value of the coil current measurement signal 202 at times t0, t8, and t16 is zero and determines that the zero current crossings of the coil current measurement signal 202 occur at times t0, t8, and t16. As another example, the processor 114 includes a timer that measures times t0, t8, and t16 when a zero value of the coil current measurement signal 202 is received by the processor 114 from the V / I sensor 112. In this example, the processor 114 determines that a zero current crossing of the coil current measurement signal 202 occurs at each of times t0, t8, and t16.

[0073] The ZCD 302 provides the zero current crossings (e.g., at times t0, t8, and t16) and the zero value of the coil current measurement signal 202 to the rectangular pulse generator 304. The rectangular pulse generator 304 generates rectangular pulses 204 of fixed amplitudes based on the zero crossings of the coil current measurement signal 202. For example, the rectangular pulse generator 304 transitions the rectangular pulse 204 from an amplitude of −1 volt to an amplitude of 1 volt at time t0, when the zero crossing of the coil current measurement signal 202 occurs. Illustratively, the rectangular pulse generator 304 includes the comparator described above that determines that the value of the coil current measurement signal 202 transitions from a negative value to a positive value at time t0, and, if so, transitions the rectangular pulse 204 from −1 volt to 1 volt at time t0. Furthermore, in this example, the rectangular pulse generator 304 transitions the rectangular pulse 204 from an amplitude of 1 volt to an amplitude of −1 volt at time t8, when the zero crossing of the coil current measurement signal 202 occurs. Illustratively, the comparator of the rectangular pulse generator 304 determines that the value of the coil current measurement signal 202 transitions from a positive value to a negative value at time t8, and, in so determining, causes the rectangular pulse 204 to transition from 1 volt to −1 volt at time t8. Note that the functionality of the rectangular pulse generator 304 is the same as that of the comparator or FPGA described above with reference to FIG. 2A.

[0074] The sawtooth signal integrator 306 integrates the rectangular pulse 204 at time t based on the zero crossings of the coil current measurement signal 202 to generate the sawtooth signal 212 ( FIG. 2B ). Examples of how the sawtooth signal 212 is generated based on the zero crossings are described above. Illustratively, the sawtooth signal integrator 306 adds the values ​​of the rectangular pulse 204 from time t0 to time t8 to generate a sawtooth pulse 217 ( FIG. 2B ) having a peak value 214 ( FIG. 2B ), and adds the values ​​of the rectangular pulse 204 from time t8 to time t16 to generate a sawtooth pulse 219 ( FIG. 2B ) having a peak value 216 ( FIG. 2B ). The sawtooth signal integrator 306 also generates sawtooth pulses 221 and 223 of the sawtooth wave 212 in the same manner as described above with reference to FIG. 2B .

[0075] Sawtooth signal integrator 306 provides sawtooth signal 212 to normalizer 310. Normalizer 310 normalizes sawtooth signal 212 and outputs normalized sawtooth signal 218 (FIG. 2B). For example, normalizer 310 generates normalized sawtooth signal 218 from sawtooth signal 212 in the same manner as described above with reference to FIG. 2B.

[0076] Normalizer 310 provides normalized sawtooth signal 218 to voltage controller 312 and comparator 314. Voltage controller 312 determines a first set of upper and lower limits from the upper peak values ​​of normalized sawtooth signal 218, a second set of upper and lower limits from the lower peak values ​​of normalized sawtooth signal 218, a DC reference 224 based on the first set of upper and lower limits, and a DC reference 226 based on the second set of upper and lower limits. For example, voltage controller 312 calculates the first set of upper limits to be the upper peak values ​​of normalized sawtooth signal 218 and calculates the first set of lower limits such that the difference between the first set of upper limits and the first set of lower limits is equal to a predetermined increment. Illustratively, voltage controller 312 calculates the first set of lower limits to be half of the upper peak values ​​of normalized sawtooth signal 218. Continuing, in this example, voltage controller 312 generates DC reference 224 (FIG. 2B) to be between a first set of upper limits and a first set of lower limits.

[0077] In this example, voltage controller 312 calculates the second set of upper limits to be the lower peak values ​​of normalized sawtooth signal 218 (FIG. 2B) and calculates the second set of lower limits such that the difference between the second set of upper limits and the second set of lower limits is equal to a predetermined increment. Illustratively, voltage controller 312 calculates the second set of lower limits to be half the lower peak values ​​of normalized sawtooth signal 218. Subsequently, in this example, voltage controller 312 generates DC reference 226 to be between the second set of upper limits and the second set of lower limits. Voltage controller 312 provides DC references 224 and 226 to comparator 314.

[0078] Comparator 314 compares the voltage value of normalized sawtooth signal 218 with DC references 224 and 226 to output digital pulse signal 252 (FIG. 2C). An example of the function of comparator 314 to generate digital pulse signal 252 is described above. Comparator 314 provides digital pulse signal 252 to frequency determiner 316.

[0079] The frequency determiner 316 determines the tuning frequency fn based on the digital pulse signal 252 and outputs the tuning frequency fn. An example of determining the tuning frequency fn from the digital pulse signal 252 was described above with reference to Figure 2C.

[0080] The comparator 318 receives the set power 320 from the user via the input device. The comparator 318 also receives the measured power 322 from the V / I sensor 112 of FIG. 1. The V / I sensor 112 outputs the measured power 322 by multiplying the voltage and current of the sinusoidal signal 134 (FIG. 1). For example, the V / I sensor 112 includes a processor that averages multiple power values ​​of the sinusoidal signal 134 over a predetermined period to calculate an average power value (which is an example of the measured power 322). In this example, the processor multiplies the value of the voltage measured by the V / I sensor 112 at a certain time by the value of the current measured by the V / I sensor 112 at that time to determine one of the power values. In this manner, a power value is determined for the predetermined period. The current of the sinusoidal signal 134 is the coil current measurement signal 136 (FIG. 1).

[0081] Comparator 318 also receives DC bus power from power sensor 120 (FIG. 1). As an example, DC bus power is determined by a processor of power sensor 120 as the product of the DC bus voltage of DC voltage signal 130 (FIG. 1) and the DC bus current of DC voltage signal 130. In this example, the DC bus voltage and DC bus current are detected by power sensor 120. Comparator 318 also receives a DC set power from a user via an input device.

[0082] Comparator 318 compares measured power 322 with set power 320 to determine whether measured power 322 is within a predetermined range from set power 320. For example, comparator 318 compares measured power 322 with set power 320 and determines that measured power 322 is equal to set power 320, thereby determining that measured power 322 is within the predetermined range from set power 320. In this example, the predetermined range is received by comparator 318 from a user via an input device.

[0083] Comparator 318 compares the DC bus power with the DC set power to determine whether the DC bus power is within a predetermined range from the DC set power. For example, comparator 318 compares the DC bus power with the DC set power and determines that the DC bus power is equal to the DC set power, thereby determining that the DC bus power is within the predetermined range from the DC set power. In this example, the predetermined range is received by comparator 318 from a user via an input device.

[0084] If comparator 318 determines that measured power 322 is within a predetermined range from set power 320 and that DC bus power is within a predetermined range from the DC set power, comparator 318 provides a first indicator to voltage controller 312. The first indicator indicates that measured power 322 is within a predetermined range from set power 320 and that DC bus power is within a predetermined range from the DC set power. On the other hand, if comparator 318 determines that measured power 322 is outside a predetermined range from set power 320, or that DC bus power is outside a predetermined range from the DC set power, or a combination thereof, comparator 318 provides a second indicator to voltage controller 312. The second indicator indicates that measured power 322 is outside a predetermined range from set power 320, or that DC bus power is outside a predetermined range from the DC set power, or a combination thereof.

[0085] In response to receiving the first indicator, voltage controller 312 does not change the DC reference (e.g., DC references 224 and 226 (FIG. 2B)). However, in response to receiving the second indicator, comparator 318 changes the DC reference. For example, comparator 318 increases or decreases the DC reference until measured power 322 is within a predetermined range of set power 320 and DC bus power is within a predetermined range of the DC set power. The DC reference is changed to stay within predetermined limits, such as between upper peak value 231 and half of upper peak value 231 or between lower peak value 235 and half of lower peak value 235 (FIG. 2B).

[0086] 3B is a diagram of one embodiment of a system 360 for modifying the voltage level of the DC voltage signal 130 to output a modulated DC signal. The system 360 includes the processor 114. The processor 114 includes a logic circuit 362, a phase calculator 364, a comparator 366, and a pulse-width modulator (PWM) 368. As an example, the logic circuit 362, the phase calculator 364, the comparator 366, and the PWM 368 are each implemented as an integrated circuit. As an example, the logic circuit 362 is implemented as an integrated circuit and the phase calculator 364 is implemented as another integrated circuit. As another example, the logic circuit 362, the phase calculator 364, the comparator 366, and the PWM 368 are each implemented as a computer software program executed by the processor 114 or as part of a computer software program executed by the processor 114. For example, the logic circuit 362 is part of the computer software program and the phase calculator 364 is another part of the computer software program.

[0087] The voltage controller 312 is connected to a phase calculator 364, which is connected to a comparator 366. The logic circuit 362 is also connected to the comparator 366. The comparator 366 is connected to a PWM 368.

[0088] Phase calculator 364 receives a DC reference (such as DC references 224 and 226 (FIG. 2B)) from voltage controller 322 and determines the measured phase Φ measured based on the DC reference. For example, phase calculator 364 calculates the measured phase Φ measured as the product of π and the difference between 1 and DC reference 224. Phase calculator 364 provides the measured phase Φ measured to comparator 366.

[0089] Further, logic circuit 362 determines the optimal phase Φ optimal based on the DC bus voltage and DC bus current measured by power sensor 120 ( FIG. 1 ). For example, processor 114 receives the DC bus voltage and DC bus current from power sensor 120. Further, in this example, processor 114 generates the optimal phase Φ optimal by calculating the product of a first term and a second term. In this example, the first term is the ratio of the measured power 322 to the product of the DC bus voltage and DC bus current, and this ratio is calculated by processor 114. In this example, the second term is k, which is a constant received from a user via an input device. Logic circuit 362 provides the optimal phase Φ optimal to comparator 366.

[0090] The comparator 366 compares the measured phase Φ measured with the optimal phase Φ optimal and provides the result of the comparison to the PWM 368. Based on the result, the PWM 368 controls (e.g., increases or decreases) the voltage level of the DC voltage signal 130 until the measured phase Φ measured falls within (e.g., is equal to) a predetermined range of the optimal phase Φ optimal. For example, the comparator 366 outputs an indication to the PWM 368 that the measured phase Φ measured is not within the predetermined range of the optimal phase Φ optimal. In this example, the PWM 368 increases or decreases the voltage level of the DC voltage signal 130 by applying pulse-width modulation to the DC-DC converter 116 ( FIG. 1 ) until an indication is received from the comparator 366 that the measured phase Φ measured is within the predetermined range of the optimal phase Φ optimal. Illustratively, the PWM 368 outputs a digital pulse signal having a duty cycle, which determines the voltage level of the modulated DC signal. In this example, as the duty cycle decreases, the voltage level of the modulated DC signal decreases, and as the duty cycle increases, the voltage level of the modulated DC signal increases.

[0091] FIG. 4 shows details of the RF amplifier 106 and how the voltage sensor 120 detects the output O of the DC-DC converter 118. DC 1 is a diagram of an embodiment of a system 400 for illustrating a method for connecting to a host computer 402. The system 400 includes a host computer 402, a frequency generator 102, a gate driver 104, an RF amplifier 106, a plasma chamber 122, a DC voltage source 116, a DC-DC converter 118, a power sensor 120, and a V / I sensor 112. The host computer 402 includes a processor 114 and a memory device 404. The processor 114 is connected to the memory device 404. Examples of memory devices used herein include read-only memory (ROM) and random access memory (RAM). For example, the memory device is a flash memory or a redundant array of independent disks (RAID).

[0092] The gate driver 104 includes a gate 406, such as a buffer, and an inverter 408, such as a NOT gate. The RF amplifier 106 includes a field effect transistor (FET) 410 and another FET 412. The system 400 also includes an inductor 414 and another inductor 416.

[0093] The frequency generator 102 is connected to a gate 406 and an inverter 408. The output of the gate 406 is connected to the gate terminal (G) of a FET 410. The drain terminal (D) of the FET 410 is connected to the output O1, which is connected to the DC-DC converter 118 via an inductor 414. The output O1 is connected to the resonant circuit 108. The source terminal (S) of the FET 410 is connected to a reference potential (such as ground potential). The inductor 414 is connected to the DC-DC converter 118 and the output O1. Furthermore, the source terminal (S) of the FET 412 is connected to the reference potential, and the drain terminal (D) of the FET 412 is connected to an inductor 416 and the resonant circuit 108. The inductor 416 is connected to the output O1 of the DC-DC converter 118. DC and the resonant circuit 108. The output of the inverter 408 is connected to the gate terminal (G) of the FET 412.

[0094] Digital pulse signal 124 is provided from frequency generator 102 to gate 406 and inverter 408. Digital pulse signal 124 is sent to gate 406, where it is buffered and passed through gate 406 to output gate driver signal 126A. Gate driver signal 126A is sent from gate 406 to the gate terminal of FET 410. Digital pulse signal 124 is inverted by inverter 408 to output an inverted digital pulse signal, which is gate driver signal 126B.

[0095] Gate driver signal 126B is inversely pulsed compared to gate driver signal 126A. For example, when gate driver signal 126A is in a logic high state, gate driver signal 126B is in a low state, and vice versa. Gate drive signal 126B is transmitted from inverter 408 to the gate terminal of FET 412.

[0096] FET 410 is turned on during periods when gate driver signal 126A is in a logic high state and turned off during periods when gate driver signal 126A is in a logic low state. Similarly, FET 412 is turned on during periods when gate driver signal 126B is in a logic high state and turned off during periods when gate driver signal 126B is in a logic low state. Thus, gate driver signals 126A and 126B are inversely synchronized, so that during periods when FET 410 is on, FET 412 is off and during periods when FET 410 is off, FET 412 is on. In this manner, FETs 410 and 412 are operated inversely synchronized with each other.

[0097] Additionally, DC voltage signal 130 is provided from DC-DC converter 118 to the drain terminal of FET 410 via inductor 414 and output O1. During periods when FET 410 is on, the voltage of DC voltage signal 130 generates a current flowing from the drain terminal of FET 410 to the source terminal of FET 410, providing a voltage at output O1. During periods when FET 412 is off, the voltage at the drain terminal of FET 412 does not generate a current from the drain terminal of FET 412 to the source terminal of FET 412. During periods when FET 410 is off, the voltage of DC voltage signal 130 does not generate a current from the drain terminal of FET 410 to the source terminal of FET 410. During periods when FET 412 is on, the voltage at the drain terminal of FET 412 generates a current from the drain terminal of FET 412 to the output O1, generating a voltage at output O1. Thus, by operating FETs 410 and 412 in anti-synchronous fashion, the voltage of DC voltage signal 130 and the voltage at the drain terminal of FET 412 generate a current that generates a voltage at output O1, which is the voltage of amplified waveform 132.

[0098] The voltage sensor 120 outputs DC The V / I sensor 112 measures the DC bus current and DC bus voltage of the amplified waveform 132 generated by the V / I sensor 112. The V / I sensor 112 also measures the power of the sinusoidal waveform 134 and outputs measured power 322 (FIG. 3B) to the processor 114. The processor 114 applies a method to determine the tuning frequency fn based on the DC bus current, DC bus voltage, and measured voltage 322.

[0099] 5A is one embodiment of a graph 500 illustrating the control of the power delivered by a matchless plasma source described herein to achieve predetermined rise and fall times. The predetermined rise and fall times are achieved when the frequency generator 102 (FIG. 1) is controlled based on a tuning frequency fn. The graph 500 plots the delivered power from the matchless plasma source on the y-axis and time t on the x-axis. The graph 500 plots the delivered power envelope 502 of the modulated sinusoidal waveform output from the resonant circuit 108 (FIG. 1) to illustrate the delivered power output from the matchless plasma source.

[0100] Envelope 502 begins transitioning from low state S0 to high state S1 at time t4 and from high state S1 back to low state S0 at time t16. As shown in graph 500, the duration of the transition from low state S0 to high state S1 is less than a predetermined rise time, and the duration of the transition from high state S1 to low state S0 is less than a predetermined fall time. For example, the duration of the transition from high state to low state is 0.75 microseconds (μs) or 1 μs, and the duration of the transition from high state to low state is 0.75 μs or 1 μs.

[0101] 5B is one embodiment of a graph 510 illustrating the occurrence of a smooth transition from an electric mode (E) to a magnetic mode (H) of a plasma formed in the plasma chamber 122 (FIG. 1), and a smooth transition from an H mode to an E mode of the plasma. Graph 510 plots the envelope of the RF coil current passing through the RF coil 110 (FIG. 1) versus time t. The RF current passing through the RF coil 110 is represented by the coil current measurement signal 202 (FIG. 2A). The envelope of the RF coil current begins to transition from a low level to a high level at time t4 and from a high level to a low level at time t17. The transition of the plasma from E mode to H mode occurs immediately after the envelope of the RF coil current transitions from a low level to a high level.

[0102] 5C is an embodiment of a graph 224 illustrating the change in DC reference 224 with changes in the level of coil current passing through RF coil 110 (FIG. 1). Graph 520 plots the voltage of DC reference 224 on the y-axis and time t on the x-axis. At time t4, when the coil current passing through RF coil 110 begins to transition from a low level to a high level, DC reference 224 begins to transition from a low value to a high value. At time t17, when the coil current passing through RF coil 110 begins to transition from a high level to a low level, DC reference 224 begins to transition from a high value to a low value.

[0103] 6 is one embodiment of a graph 600 illustrating that the frequency generator 102 (FIG. 1) is operated at different tuning frequencies to achieve zero voltage switching for different loads, and each of the different tuning frequencies is greater than the respective resonant frequency for each of the loads. Graph 600 plots the voltage at input I1 of RF coil 110 (FIG. 1) against the frequency of a sinusoidal signal (e.g., a modulated sinusoidal signal) at input I1 of RF coil 110.

[0104] An example of a load is the impedance of a plasma formed in plasma chamber 122 (FIG. 1). For example, load 1 represents a plasma formed using one gas recipe (e.g., a first combination of two or more process gases), load 2 represents a plasma formed using another gas recipe (e.g., a second combination of two or more process gases), and load 3 represents a plasma formed using yet another gas recipe (e.g., a third combination of two or more process gases). As another example, load 1 represents plasma chamber 122, load 2 represents another plasma chamber, and load 3 represents yet another plasma chamber.

[0105] Graph 600 includes plot 602, which is generated when a modulated sine wave signal is applied to Load 1, plot 604, which is generated when another modulated sine wave signal is applied to Load 2, and plot 606, which is generated when yet another modulated sine wave signal is applied to Load 3. Each plot 602, 606, and 606 has a corresponding resonant frequency (f). For example, plot 602 has a resonant frequency Rf1, plot 604 has a resonant frequency Rf2, and plot 605 has a resonant frequency Rf3.

[0106] When a modulated sine wave signal is applied to load 1, the frequency generator 102 is controlled by the processor 114 to operate at a tuning frequency fn that is higher than the resonant frequency Rf1. Similarly, when another modulated sine wave signal is applied to load 2, the frequency generator 102 is controlled by the processor 114 to operate at a tuning frequency fn1 that is higher than the resonant frequency Rf2. And when yet another modulated sine wave signal is applied to load 3, the frequency generator 102 is controlled by the processor 114 to operate at a tuning frequency fn2 that is higher than the resonant frequency Rf3. By controlling the frequency generator 102 to operate at a tuning frequency higher than the resonant frequencies of the loads, the power output from the RF amplifier 106 (FIG. 1) is adjusted or controlled.

[0107] 7 is one embodiment of a graph 700 illustrating how controlling the tuning frequency fn causes the RF amplifier 106 (FIG. 1) to become less reactive and provide the same amount of gain as RF power. The graph 700 plots the amount of gain in RF power output from the RF amplifier 106 on the y-axis and the tuning frequency fn on the x-axis.

[0108] Graph 700 includes a plot 702 produced when RF amplifier 106 has higher reactive power and a plot 704 produced when RF amplifier 106 has lower reactive power. As the duty cycle output by PWM 368 (FIG. 3B) changes, DC voltage signal 130 changes to a modulated DC signal, changing the amount of gain at output O1 (FIG. 1) of RF amplifier 106. Furthermore, by controlling tuning frequency fn, such as modulating tuning frequency fn from value fna to value fnb, RF amplifier 106 becomes less reactive, as shown by the movement from point 706 on plot 702 to point 708 on plot 704, and the same amount of gain G1 is output by RF amplifier 106.

[0109] The embodiments described herein may be practiced with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. Embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0110] In some embodiments, the controllers described herein are part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling the operation of the systems before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or type of system, the controller may be programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, and wafer movement in and out of load locks connected or coupled to the tool and other moving tools and / or systems.

[0111] Generally, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) to define parameters, factors, variables, etc., for or to a system to perform a particular process on or for a semiconductor wafer. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more process steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0112] In some embodiments, the controller is part of or connected to a computer that is integrated with, connected to, or otherwise networked with the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer that enables remote access of wafer processing. The computer enables remote access to the system to change parameters of a current process, set process steps according to a current process, or initiate a new process, monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, or examine trends or performance indicators from multiple manufacturing operations.

[0113] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network (including a local network or the Internet). The remote computer includes a user interface that allows for entry or programming of parameters and / or settings, which are communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters, factors, and / or variables for each of the process steps performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by having one or more separate controllers that are networked and operate toward a common purpose (such as the process and control described herein). One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (e.g., located at the platform level or remotely as part of a remote computer) that cooperate to control the process at the chamber.

[0114] In various embodiments, examples of systems to which the methods may be applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or utilized in the fabrication and / or manufacturing of semiconductor wafers.

[0115] It should also be noted that in some embodiments, the operations described above apply to several types of plasma chambers, such as plasma chambers with inductively coupled plasma (ICP) reactors, capacitively coupled plasma (CCP) chambers, transformer-coupled plasma chambers, plasma chambers with conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a planar coil, etc.

[0116] As described above, depending on the processing step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to or from tool locations and / or load ports within the semiconductor fabrication factory.

[0117] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0118] Some embodiments further relate to hardware units or apparatus for performing these operations, where the apparatus is specifically configured for a special purpose computer. When defined as a special purpose computer, the computer can operate for a specific purpose while performing other processes, program execution, or routines not included in the specific purpose.

[0119] In some embodiments, operations may be processed on a computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0120] One or more embodiments may be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device) that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a tangible computer-readable medium distributed over network-connected computer systems such that the computer-readable code is stored and executed in a distributed manner.

[0121] Although the method operations described above are presented in a particular order, it should be understood that in various embodiments, other housekeeping processes may be performed between operations, or the method operations may be performed at slightly different times, may be distributed across a system that allows method operations to occur at various intervals, or may be arranged to be performed in an order different from that described above.

[0122] Furthermore, it should be noted that in one embodiment, one or more features of any embodiment described herein may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0123] Although the present embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. 1. A method for adjusting the frequency of a radio frequency (RF) amplifier, comprising: receiving a coil current measurement signal, the coil current measurement signal being measured at the input of an RF coil of a plasma chamber; generating a first sawtooth signal based on the coil current measurement signal; applying a plurality of direct current (DC) references to the first sawtooth signal to determine a tuning frequency; controlling a frequency generator of a matchless plasma source according to the tuning frequency, the tuning frequency being the frequency of the RF amplifier; A method comprising:

2. 2. The method of claim 1, wherein generating the first sawtooth signal based on the coil current measurement signal comprises: generating a rectangular pulse signal across the coil current measurement signal; integrating the rectangular pulse signal to generate a second sawtooth signal; normalizing the second sawtooth wave signal to output a normalized sawtooth wave signal, wherein the first sawtooth wave signal is the normalized sawtooth wave signal; A method comprising:

3. 3. The method of claim 2, further comprising: identifying one or more zero crossings of the coil current measurement signal; The method of claim 1, wherein the rectangular pulse signal is integrated based on the zero crossings.

4. 2. The method of claim 1, wherein the first sawtooth signal has a peak value, and one of the plurality of DC references is limited between an upper predetermined value and a lower predetermined value, the upper predetermined value being determined based on the peak value, and the lower predetermined value being determined based on the upper predetermined value.

5. The method of claim 4 , wherein the upper predetermined value is equal to the peak value.

6. 5. The method of claim 4, wherein the lower predetermined value is a predetermined increment less than the peak value.

7. 10. The method of claim 1 further comprising: determining a measured phase based on said one of said plurality of DC references; determining an optimal phase based on the power measured at the input of the RF coil, the DC bus voltage measured at the output of a DC-DC converter, and the DC bus current measured at the output of the DC-DC converter; comparing the measured phase to the optimum phase to determine a duty cycle; applying a pulse width based on the duty cycle to the DC-DC converter; A method comprising:

8. 2. The method of claim 1, wherein the plurality of DC references includes a first DC reference and a second DC reference, and applying the plurality of DC references to the first sawtooth signal comprises: determining a first time at which the first sawtooth signal transitions from being less than the first DC reference to being greater than the first DC reference; determining a second time at which the first sawtooth signal transitions from being greater than the second DC reference to being less than the second DC reference, the second time occurring after the first time; Including, The method wherein the tuning frequency is determined based on the first and second times.

9. The method of claim 1 , wherein the matchless plasma source does not include a matcher.

10. 1. A controller for adjusting the frequency of a radio frequency (RF) amplifier, comprising: a processor; a memory device coupled to the processor; The processor: receiving a coil current measurement signal, the coil current measurement signal being measured at an input of an RF coil of a plasma chamber; generating a first sawtooth signal based on the coil current measurement signal; applying a plurality of direct current (DC) references to the first sawtooth signal to determine a tuning frequency; controlling a frequency generator of a matchless plasma source according to the tuning frequency, the tuning frequency being the frequency of the RF amplifier; A controller that is configured to run

11. 11. The controller of claim 10, wherein to generate the first sawtooth signal, the processor: generating a rectangular pulse signal across the coil current measurement signal; integrating the rectangular pulse signal to generate a second sawtooth signal; normalizing the second sawtooth wave signal to output a normalized sawtooth wave signal, wherein the first sawtooth wave signal is the normalized sawtooth wave signal; and A controller that is configured to run

12. 12. The controller of claim 11, wherein the processor: Identifying one or more zero crossings of the coil current measurement signal, wherein the rectangular pulse signal is integrated based on the zero crossings. A controller that is configured to run

13. 11. The controller of claim 10, wherein the first sawtooth signal has a peak value, and one of the plurality of DC references is limited between an upper predetermined value and a lower predetermined value, the upper predetermined value being determined based on the peak value, and the lower predetermined value being determined based on the upper predetermined value.

14. 14. The controller of claim 13, wherein the upper predetermined value is equal to the peak value.

15. 14. The controller of claim 13, wherein the lower predetermined value is a predetermined increment less than the peak value.

16. 11. The controller of claim 10, wherein the processor: determining a measurement phase based on one of the plurality of DC references; determining an optimal phase based on the power measured at the input of the RF coil, the DC bus voltage measured at the output of a DC-DC converter, and the DC bus current measured at the output of the DC-DC converter; comparing the measured phase to the optimum phase to determine a duty cycle; applying a pulse width based on the duty cycle to the DC-DC converter; The controller is configured as follows:

17. 11. The controller of claim 10, wherein the plurality of DC references includes a first DC reference and a second DC reference, and to apply the plurality of DC references to the first sawtooth signal, the processor determining a first time at which the first sawtooth signal transitions from being less than the first DC reference to being greater than the first DC reference; determining a second time at which the first sawtooth signal transitions from being greater than the second DC reference to being less than the second DC reference, the second time occurring after the first time; is configured to run The tuning frequency is determined based on the first and second times.

18. The controller of claim 10 , wherein the matchless plasma source does not include a matcher.

19. 1. A system comprising:

1. A matchless plasma source comprising: a frequency generator configured to generate a digital pulse signal; a gate driver connected to the frequency generator, the gate driver configured to receive the digital pulse signal and output a plurality of gate driver signals; a radio frequency (RF) amplifier connected to the gate driver and having an output, the RF amplifier configured to receive the plurality of gate driver signals and provide an amplified waveform at the output of the RF amplifier; a matchless plasma source comprising: a resonant circuit connected to the RF amplifier, the resonant circuit configured to receive the amplified waveform and output a sinusoidal signal; a plasma chamber having an RF coil, the RF coil having an input connected to the resonant circuit for receiving the sinusoidal signal; a controller connected to the matchless plasma source; Equipped with The controller receiving a coil current measurement signal, the coil current measurement signal being measured at the input of the RF coil; generating a first sawtooth signal based on the coil current measurement signal; applying a plurality of direct current (DC) references to the first sawtooth signal to determine a tuning frequency; controlling the frequency generator according to the tuning frequency; A system that is configured to run

20. 20. The system of claim 19, wherein to generate the first sawtooth signal, the processor: generating a rectangular pulse signal across the coil current measurement signal; integrating the rectangular pulse signal to generate a second sawtooth signal; normalizing the second sawtooth wave signal to output a normalized sawtooth wave signal, wherein the first sawtooth wave signal is the normalized sawtooth wave signal; and A system that is configured to run

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