SiC assembly, power semiconductor device and method for manufacturing a SiC assembly for a power semiconductor device

Abstract

An assembly (1) for a power semiconductor device (10) is provided, the assembly (1) comprising a body (1M) based on SiC and a plurality of vias (1V) based on a conductive material. The body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), the second thickness (12T) being less than the first thickness (11T). The first layer (11) and the second layer (12) are formed from SiC, and the first layer (11) has a higher n-doping concentration than the second layer (12). The vias (1V) extend partially into the first layer (11) along a vertical direction from a bottom side (11B) of the first layer (11) toward the second layer (12), but the vias (1V) do not extend into the second layer (12). The assembly further comprises a SiC substrate (5), and the second layer (12) is disposed between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is 1.5 to 250. The SiC substrate (5) is free of any vias formed from a conductive material. Furthermore, a power semiconductor device (10) comprising such an assembly (1), as well as a method and a method for manufacturing such an assembly (1) are provided.

Description

[Technical Field]

[0001] The present disclosure relates to SiC assemblies, power semiconductor devices, and methods for manufacturing SiC assemblies of power semiconductor devices. [Background technology]

[0002] Conventional low-voltage SiC devices offer the very low on-state voltage drop required for certain applications, such as event switching. However, the switches must withstand high current pulses for extended periods ranging from a few microseconds to several seconds. This places high demands on the so-called "single event" turn-off capability due not only to the high turn-off current density and / or long pulse length, but also to the very high temperature swings across the switch, which affect both the chip and the package.

[0003] The current area of ​​SiC technology and material properties is that current die sizes are limited to, for example, 50 mm due to crystalline defect density and their limiting effect on manufacturing yield and therefore die cost. 2 This situation is complicated by the fact that the on-resistance is typically limited to values ​​not exceeding 1000 kJ / s. Therefore, in the current situation, it is desirable to fully optimize the potential of SiC devices, such as SiC switches, in terms of on-resistance. Therefore, in order to keep the SiC die area as low as possible for economic reasons, the current density under normal operating conditions needs to be as high as possible. However, this leads to extremely high current densities during high-current events, resulting in strong self-heating of the semiconductor chip and its package. Summary of the Invention [Problem to be solved by the invention]

[0004] While the semiconductor material SiC is quite capable of operating at temperatures above 600 K under vacuum, current state-of-the-art packages and the materials used to create them do not allow for temperatures significantly exceeding the maximum operating temperatures of silicon devices. Thus, for SiC devices used in event switching applications, for example, there is strong interest in adding as much thermal capacity to the device as possible. The present disclosure intends to achieve this goal by utilizing a highly thermally conductive SiC layer onto which, for example, the voltage-sustaining drift layer of a power semiconductor device, such as a switch device, is deposited or grown. [Means for solving the problem]

[0005] Embodiments of the present disclosure, such as those claimed in the independent claims, address in whole or in part the above-mentioned shortcomings in the art. Further embodiments of the SiC assembly, the power semiconductor device, and the method for manufacturing the SiC assembly of the power semiconductor device are the subject of further claims.

[0006] According to one embodiment of an assembly for a power semiconductor device, it comprises a body based on SiC and a plurality of vias based on a conductive material. The body comprises a first layer having a first thickness and a second layer having a second thickness, the second thickness being less than the first thickness. The first and second layers are formed from SiC. The first layer may have a higher n-doping concentration than the second layer. The vias extend vertically from the bottom side of the first layer toward the second layer and partially into the first layer, but do not extend into the second layer.

[0007] The first and second layers have different n-doping concentrations. However, they may be formed from the same material, such as 4H-SiC. However, it is possible for the second layer to be formed from 4H-SiC and the first layer to be formed from 3C-SiC or poly-SiC. For example, the second layer may be a drift layer. Such a drift layer may be epitaxially grown on the first layer. The first layer may be a substrate that supports the second layer and mechanically stabilizes the assembly.

[0008] The via can be a trench that is completely filled with conductive material. It is also possible that the via can be a trench that is partially filled with conductive material. For example, only the inner walls of the trench are coated with conductive material. In this case, the trench may include a region filled with a gaseous medium, for example, air.

[0009] The goal of the present disclosure is to utilize a thicker first layer that allows for reduced self-heating without simultaneously increasing the overall resistance of the configuration, e.g., a power semiconductor device. This goal is achieved by providing a two- or three-dimensional arrangement of holes or trenches in the first layer filled with a metal having high electrical and thermal conductivity, such as aluminum, copper, or silver due to their high inherent electrical conductivity, or a suitable form of graphite. The number of holes or trenches in each assembly may be at least 4, 6, 8, 10, 16, 20, 50, or at least 100.

[0010] According to a further embodiment of the assembly, the ratio of the first thickness in the vertical direction to the second thickness in the vertical direction is between 1.5 and 250. The first thickness may be between 100 μm and 1000 μm. The second thickness may be between 2 μm and 200 μm.

[0011] The vertical direction is understood to mean a direction perpendicular to the bottom surface of the first layer. The lateral direction is understood to mean a direction parallel to the bottom surface of the first layer. The vertical and lateral directions are perpendicular to each other. The bottom surface of the first layer is an outer surface located on the bottom side of the first layer and can be defined by one vector oriented along the length of the assembly and another vector oriented along the width of the assembly.

[0012] According to a further embodiment of the assembly, the maximum vertical distance between the second layer and the via is 0.6 μm to 250 μm, for example, 1 μm to 250 μm. For example, the first thickness is 300 μm or more or 350 μm or more. The second thickness is, for example, 55 μm or less, 25 μm or less, or 10 μm or less. However, the first thickness and the second thickness are not limited thereto.

[0013] According to a further embodiment of the assembly, the ratio of the average vertical height of the vias to the first thickness of the first layer is at least 0.5, for example at least 0.6, 0.7, 0.8, or at least 0.9. In other words, the vias extend into at least 50%, 60%, 70%, 80%, or at least 90% of the total vertical thickness of the first layer. However, the vias do not extend vertically through the entire first layer. In this sense, the vias extend vertically only partially into the first layer from the bottom side of the first layer toward the second layer.

[0014] According to a further embodiment of the assembly, the vias have an average lateral width of 3 μm to 150 μm, for example 6 μm to 150 μm or 10 μm to 150 μm. The vias have an average lateral length greater than the average lateral width. Along a lateral direction, at least some or all of the vias may be fully or partially sealed by the first layer. However, along one lateral direction, it is possible that at least some or all of the vias may extend from one first side surface of the first layer to another side surface of the first layer, for example, opposite the first side surface of the first layer. In this case, the vias may be exposed not only to the bottom side of the first layer, but also at least partially to one or two side surfaces of the first layer.

[0015] According to a further embodiment of the assembly, the via is completely surrounded by the first layer along the lateral direction, with no via exposed on the side surfaces of the first layer.

[0016] According to a further embodiment of the assembly, the first layer has a first side and a second side. At least one, some, or all of the vias can extend from the first side to the second side of the first layer along the lateral direction. For example, the first side is opposite the second side. In this case, the vias can have a lateral length equal to or greater than the lateral width or lateral length of the first layer. Along the lateral direction, the vias can extend along the width or length of the first layer. It is also possible for the first side to be adjacent to the second side. In this case, the vias can extend from the first side to the adjacent second side along the lateral direction. Along the lateral direction, the vias are not parallel to the width or length of the first layer.

[0017] According to a further embodiment of the assembly, the assembly further comprises a heat sink, for example made of metal, and the body is arranged on, for example directly on, the heat sink, and the heat sink has, for example, a vertical thickness greater than the sum of the first thickness and the second thickness.

[0018] The heat sink can be a thick metal plate, such as a copper plate, that serves as an efficient primary heat sink for the assembly or semiconductor device. The heat sink can have the same width and / or length dimensions as the body. The vertical thickness of the heat sink can be 500 μm, 1000 μm, 2000 μm, 3000 μm, or 4000 μm or more.

[0019] According to a further embodiment of the assembly, the heat sink has a cross section that is larger than the body so that the body completely overlaps the heat sink in a top view of the heat sink. However, it is also possible for the heat sink to have an equal or approximately equal cross section compared to the cross section of the body.

[0020] According to a further embodiment of the assembly, it further comprises a SiC substrate, and the second layer is arranged between the SiC substrate and the first layer. The SiC substrate has a vertical thickness, and the ratio of the thickness of the SiC substrate to the second layer can be 1.5 to 250. The SiC substrate is free of any vias, for example, formed from a conductive material.

[0021] The SiC substrate and the body may be separated by a metal layer, such as an aluminum or copper layer, which may constitute an electrode, e.g., a cathode, of the assembly or power semiconductor device. The SiC substrate acts as a top-side cooler and is not electrically active. For this reason, no vias, holes, or trenches are formed in the SiC to reduce potential resistive voltage drops. For example, a thermal boundary electrode is present on the bottom side of the assembly.

[0022] According to a further embodiment of the assembly, the vias have a cross-section that varies in size along the vertical direction. For example, the cross-sectional size of each via increases as the distance from the bottom side of the first layer decreases. Due to this via geometry, the vias can be filled with conductive material in an efficient and simple manner.

[0023] According to one embodiment of a power semiconductor device, it comprises an assembly, particularly an assembly described herein in this disclosure. The assembly comprises a body based on SiC and a plurality of vias based on a conductive material. The body comprises a first layer having a first thickness and a second layer, the second thickness being less than the first thickness. The first and second layers are formed from SiC, and the first layer has a higher n-doping concentration than the second layer. The vias extend vertically from the bottom side of the first layer toward the second layer and partially into the first layer, but do not extend into the second layer. The second layer comprises a functional region configured to perform a function of the power semiconductor device. The functional region may include, for example, a p-region and an n-region of a transistor. For example, the second layer is formed as a drift layer.

[0024] According to further embodiments of the power semiconductor device, it is formed as a metal-oxide-silicon field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a Schottky diode, a junction barrier Schottky (JBS) diode, or as a SiC power device for event switching. The second layer may include a functional region of such a transistor or diode.

[0025] According to one embodiment of a method for manufacturing an assembly of power semiconductor devices, a wafer is provided. The wafer includes at least one body based on SiC. The wafer or body includes a first layer having a first thickness and a second layer having a second thickness, the second thickness being less than the first thickness. The first and second layers are formed from SiC. The first layer may have a higher n-doping concentration than the second layer. According to the method, a plurality of trenches are formed extending vertically from a bottom side of the first layer toward the second layer, partially into the first layer, but not into the second layer. The trenches are filled with a conductive material to form a plurality of vias, the vias extending vertically from the bottom side of the first layer toward the second layer, partially into the first layer, but not into the second layer.

[0026] According to a further embodiment of the method, the wafer is singulated into a plurality of bodies along singulation lines, at least some of the singulation lines passing through the vias such that at least some of the singulated bodies include sides that include sides of the vias.

[0027] According to a further embodiment of the method, the wafer is singulated into a plurality of bodies along singulation lines, at least some of the singulation lines not passing through vias, such that at least some of the singulated bodies include all sides where no via sides are present.

[0028] The present disclosure includes, based on embodiments and examples thereof, several aspects of assemblies of power semiconductor devices, power semiconductor devices comprising such assemblies, and methods for manufacturing such assemblies of power semiconductor devices. All features described with respect to one of the aspects are also disclosed herein with respect to the other aspects, even if the respective feature is not explicitly mentioned in the context of a particular aspect. For example, the methods described in the present disclosure relate to methods for manufacturing the assemblies described herein, and the power semiconductor devices described in the present disclosure can comprise the assemblies described herein. Thus, features and advantages described with respect to the assemblies can be used for the methods and power semiconductor devices, and vice versa.

[0029] While the present disclosure is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular described embodiments and examples. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the appended claims.

[0030] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be assigned the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0031] [Figure 1A] 1 is a schematic cross-sectional view illustrating a general concept of an assembly for a power semiconductor device according to one embodiment of the present disclosure. [Figure 1B] 10A-10C show different arrangements of vias according to different embodiments of the assembly in a top view relative to the bottom side of the assembly. [Figure 1C]10A-10C show different arrangements of vias according to different embodiments of the assembly in a top view relative to the bottom side of the assembly. [Figure 2] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 3] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 4] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 5] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 6] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 7] 10A and 10B show further examples of assemblies or power semiconductor devices. [Figure 8A] 10A-10C show some simulation results of different embodiments of the assembly. [Figure 8B] 10A-10C show some simulation results of different embodiments of the assembly. [Figure 8C] 10A-10C show some simulation results of different embodiments of the assembly. [Figure 8D] 10A-10C show some simulation results of different embodiments of the assembly. [Figure 9A] 1A-1C illustrate some exemplary method steps of a method for manufacturing at least one assembly for a power semiconductor device. [Figure 9B] 1A-1C illustrate some exemplary method steps of a method for manufacturing at least one assembly for a power semiconductor device. [Figure 9C] 1A-1C illustrate some exemplary method steps of a method for manufacturing at least one assembly for a power semiconductor device. [Figure 10A]3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. [Figure 10B] 3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. [Figure 11A] 3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. [Figure 11B] 3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. [Figure 12] 3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. [Figure 13] 3A to 3C illustrate some exemplary method steps of different embodiments of a method for manufacturing a plurality of assemblies for power semiconductor devices. DETAILED DESCRIPTION OF THE INVENTION

[0032] FIG. 1A illustrates a cross-sectional view of an assembly 1 for a power semiconductor device 10 according to an exemplary embodiment. The assembly 1 includes a body 1M including a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The body 1M is based on SiC. The first layer 11 is formed of SiC, such as 4H-SiC, 3C-SiC, or poly-SiC. The second layer 12 is formed of SiC, such as 4H-SiC. The first layer 11 has a higher n-doping concentration than the second layer 12. As shown in FIG. 1A, the second thickness 12T is less than the first thickness 11T. The second layer 12 can be directly adjacent to the first layer 11.

[0033] The ratio 11T / 12T of the first thickness 11T to the second thickness 12T can be 1.5 to 250, for example, 5 to 250, 5 to 200, 5 to 100, 5 to 50, 5 to 25, or 5 to 25. For example, the ratio 11T / 12T is 5 or more, 10 or more, 30 or more, 50 or more, or 100 or more. For example, the ratio 11T / 12T is 1.5 or more and 5 or more, but can be 10 or less, 15 or less, 20 or less, 30 or less, 50 or less, or 100 or less.

[0034] The first thickness 11T can be 100 μm to 1000 μm, for example, 100 μm to 800 μm, 100 μm to 600 μm, or 100 μm to 400 μm. For example, the first thickness 11T is 600 μm±300 μm, 600 μm±200 μm, or 600 μm±50 μm.

[0035] The second thickness 12T can be 2 μm to 200 μm, for example, 2 μm to 100 μm, 2 μm to 50 μm, or 2 μm to 10 μm. For example, the second thickness 12T is 50 μm±10 μm, 30 μm±10 μm, or 10 μm±5 μm.

[0036] For example, the first thickness 11T is 300 μm or more or 500 μm or more, and the second thickness 12T is 55 μm or less, 35 μm or less, 20 μm or less, or 10 μm or less.

[0037] The assembly 1 includes a plurality of vias 1V based on a conductive material. For example, the vias 1V are trenches filled with, for example, aluminum, copper, or silver. The vias 1V extend vertically from the bottom side 11B of the first layer 11 toward the second layer 12, partially into the first layer 11, but do not extend into the second layer 12, stopping before the second layer 12.

[0038] The maximum vertical distance between the second layer 12 and the via 1V can be between 0.6 μm and 250 μm, for example between 1 μm and 250 μm, for example between 1 μm and 150 μm, 1 μm and 100 μm, 1 μm and 50 μm, 1 μm and 30 μm, or 1 μm and 10 μm.

[0039] 1A, the vias 1V extend only partially into the first layer 11. The ratio of the average vertical height of the vias 1V to the first thickness 11T of the first layer 11 can be at least 0.5, 0.6, 0.7, 0.8, or at least 0.9, for example, between 0.8 and 0.98.

[0040] The via 1V can have an average lateral width of 3 μm to 150 μm, for example, 6 μm to 150 μm, 10 μm to 150 μm, for example, 10 μm to 100 μm, 10 μm to 80 μm, 10 μm to 60 μm, 10 μm to 40 μm, or 10 μm to 20 μm. The via 1V can have an average lateral length that is greater than the average lateral width. The lateral direction of the via 1V can be the lateral length or width of the assembly 1.

[0041] For example, in a top view relative to the bottom side 11B of the first layer 11 as shown in FIGS. 1B and 1C, the vias 1V are strip-shaped. The vias 1V are parallel to one another. The ratio of the lateral length to the lateral width of one via 1V or of the vias 1V can be 1.5 to 50, 1.5 to 30, 1.5 to 10, or 1.5 to 5. It is also possible for the vias 1V to have other shapes, such as square, circular, trapezoidal, or other regular and irregular shapes, in a top view relative to the bottom side 11B of the first layer 11.

[0042] As shown in FIG. 1A, the assembly 1 includes a plurality of vias 1V, e.g., eight vias 1V, which extend laterally from a first side surface 11F to a second side surface 11S of the first layer 11, with the first side surface 11F being opposite the second side surface 11S, as shown in FIG. 1B. Thus, the vias 1V may have a lateral length equal to or approximately equal to the width of the first layer 11. The vias 1V may be partially exposed on the first side surface 11F and / or the second side surface 11S. The eight vias 1V are parallel to one another.

[0043] 1B, it is possible to rotate the via 1V by an angle of 90°. In this case, the via 1V may have a lateral length equal to or approximately equal to the length of the first layer 11. Other orientations of the via 1V are also possible. For example, along the lateral direction, the via 1V may extend from the first side surface 11F or the second side surface 11S to another side surface of the first layer 11, the other side surface of the first layer being adjacent to the first side surface 11F or the second side surface 11S.

[0044] Compared to via 1V in Figure 1B, via 1V in Figure 1C has the same lateral orientation in a top view relative to bottom side 11B of first layer 11. However, via 1V in Figure 1C does not extend to either side of first layer 11. Thus, in the lateral direction, via 1V is completely sealed or completely surrounded by first layer 11.

[0045] Deviating from FIG. 1C, via 1V can have other orientations along the lateral direction, for example, via 1V can be rotated by a 90° angle or another angle.

[0046] Deviating from FIGS. 1A, 1B, and 1C, other arrangements and / or other numbers of vias 1V are possible. For example, the number of vias 1V may be greater or less than 8, e.g., greater than 10, 15, 20, 30, 40, or 50. Combinations of vias 1V as shown in FIGS. 1B and 1C are also possible. In a top view with respect to the bottom side 11B of the first layer 11, the vias 1V may be arranged in a matrix, i.e., in multiple columns and rows. It is also possible for only one or both ends of some vias 1V to be partially exposed on the side surface of the first layer 11, while some other vias 1V may be completely surrounded by the first layer 11 and therefore not exposed on any side surface of the first layer 11.

[0047] The assembly 1 or power semiconductor device 10 shown in FIG. 2 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 1A, except that FIG. 2 shows only four vias 1V.

[0048] The assembly 1 or power semiconductor device 10 shown in FIG. 3 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 1A, except that the vias 1V have cross-sections that vary in size along the vertical direction. The cross-sectional size of each via 1V increases as the distance to the bottom side 11B of the first layer 11 decreases. Here, the inner walls of the vias 1V may be sloped, for example, to facilitate metallization at the end of semiconductor processing. Therefore, at the bottom side 11B, each via 1V has the largest cross-section or largest opening. This simplifies the filling of the vias 1V with material and ensures that the vias 1V can be completely filled with electrical materials such as aluminum, copper, silver, etc.

[0049] The assembly 1 or power semiconductor device 10 shown in FIG. 4 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 1A, except that the substrate 5 is disposed on the body 1M. The substrate 5 and the body 1M may have the same geometric size, e.g., the same length, width, and thickness. It is also possible for the substrate 5 to have a vertical thickness 5T that is smaller or larger than that of the body 1M. The substrate 5 may be formed from SiC. For example, the substrate 5 may be formed from the same material as the first layer 11 of the body 1M.

[0050] As shown in FIG. 4, the second layer 12 is disposed between the SiC substrate 5 and the first layer 11. The substrate 5 has a vertical thickness 5T, and the ratio 5T / 12T of the substrate 5 to the second thickness 12T can be 1.5 to 250, e.g., 5 to 250, 5 to 200, 5 to 100, 5 to 50, 5 to 25, or 5 to 25. For example, the ratio 5T / 12T can be 5 or more, 10 or more, 30 or more, 50 or more, or 100 or more. For example, the ratio 5T / 12T can be 1.5 or more and 5 or more, but can also be 10 or less, 15 or less, 20 or less, 30 or less, 50 or less, or 100 or less.

[0051] The ratio 5T / 11T of the substrate 5 to the first thickness 11T can be 0.3 to 3, for example 0.5 to 3, 1 to 3, 0.5 to 2, 0.5 to 1.5, 0.75 to 1.25, 0.8 to 1.2 or 0.9 to 1.1. However, compared to the body 1M or the first layer 11, the substrate 5 does not have any vias formed from a conductive material.

[0052] The substrate 5 may act as a top-side cooler. The substrate 5 and the body 1M may be separated by a metal layer, e.g., an aluminum or copper layer, which may constitute an electrode, e.g., a cathode, of the assembly 1 or the power semiconductor device 10. The substrate 5 acting as a top-side cooler is not electrically active. For this reason, vias, holes, or trenches are not required to reduce resistive voltage drops. A thermal boundary electrode may be present on the bottom side of the assembly 1 or the power semiconductor device 10, e.g., on the bottom side 11B of the first layer 11 of the body 1M.

[0053] 5 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 1A, except that the main body 1M is disposed on a heat sink 3. The heat sink 3 may be formed of a metal, such as copper. The heat sink 3 has a vertical thickness 3T that is greater than the sum of the first thickness 11T and the second thickness 12T, for example, at least 1.5, 2, 3, or 5 times greater than the sum of the first thickness 11T and the second thickness 12T.

[0054] Here, the heat sink 3 acts as the primary heat sink or cooler for the assembly 1 or the power semiconductor device 10. The presence of the heat sink 3 results in reduced self-heating and improved current density. The use of the heat sink 3 in combination with vias 1V formed in the first layer 11 enhances these effects. As shown in FIG. 5, the body 1M and the heat sink 3 may have substantially the same geometric size in terms of lateral length and / or lateral width.

[0055] The assembly 1 or power semiconductor device 10 shown in FIG. 6 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 5, except that the heat sink 3 has a larger cross section than the main body 1M. In a top view of the heat sink 3, the main body 1M can completely overlap the heat sink 3. For example, the lateral length and width of the heat sink 3 are larger than the lateral length and width of the main body 1M. The heat sink 3 shown in FIG. 5 and the heat sink shown in FIG. 6 may have the same volume. It has been found that, compared to the heat sink 3 shown in FIG. 5, the use of the heat sink 3 shown in FIG. 6 further reduces self-heating and improves current density.

[0056] The assembly 1 or power semiconductor device 10 shown in FIG. 7 is essentially the same as the assembly 1 or power semiconductor device 10 shown in FIG. 4, except that the assembly 1 or power semiconductor device 10 shown in FIG. 7 includes a heat sink 3, as shown in FIG. 6.

[0057] Some simulation results are shown in connection with Figures 8A, 8B, 8C and 8D.

[0058] The procedure for fabricating a SiC power device can begin with a first layer 11, which is a thick, highly doped SiC layer. For example, for SiC unipolar power devices for 600 V and 1.2 kV applications, the second layer 12 is a thin, lightly doped, voltage-sustaining SiC drift layer that can be epitaxially grown on top of the first layer 11. The thickness of the drift layer can range from a few microns to about 10 microns for the voltage classes mentioned above, which is very thin compared to the thick first layer 11, which has a vertical thickness 11T of 100 microns, 200 microns, 300 microns, or even more.

[0059] For example, in such low voltage class devices, the resistive contribution of the first layer 11 cannot be neglected, so that so far the thickness of the first layer 11 is made small in order to be able to reach the minimum on-state voltage drop.

[0060] For the self-heating simulation, the assembly 1 or the power semiconductor device 10, e.g., a resistor, has two electrical contacts that are used to energize the device. The simulated contacts are chosen to be made of aluminum because aluminum is widely used for metal contacts in power semiconductor devices. On the bottom side 11B of the first layer 11 is a metallization that is a thermal electrode, where a thermal boundary condition is implied. The initial temperature is set to 300 K in this example, and the thermal electrode is 10 cm 2 It is characterized by a thermal surface resistance in K / W. This thermal surface resistance value is representative of mounting a power semiconductor device on a small heat sink without forced cooling.

[0061] In the simulations described here, a thermal boundary surface temperature of 300 K is used. In the self-heating simulation, a 3 second long current pulse is subjected to an assembly 1 or power semiconductor device 10 comprising a first layer 11 and a second layer 12. The height of the current density pulse is variable, thus resulting in different maximum device temperatures at the end of the current pulse.

[0062] For comparison, in a 2D numerical simulation, the typical conventional thickness of the first SiC layer 11 is chosen to be 100 μm, and the typical conventional thickness of the second SiC layer 12, which is the drift layer, is chosen to be 8 μm, resulting in a resistivity of 1.4 mΩ cm above the first layer 11. 2 The width of the first layer 11 and the second layer 12 is selected to be 5120 μm, and a variable current is applied through the second layer 12 and the first layer 11, flowing from the top to the bottom of the assembly 1. The top and bottom surfaces are electrical contacts, and there is also a thermal junction at the bottom surface with a thermal boundary condition T=300 K.

[0063] The results of such a conventional assembly 1 or power semiconductor device 10 are shown by curve A1 in FIG. 8A, where dT denotes the average temperature rise in Kelvin and dI denotes the average temperature rise in A / cm 2The unit pulse current density is shown, where there are no vias in the first layer 11.

[0064] Curve A2 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve A1, but the first layer 11 has a thickness 11T of 600 μm and there are no vias 1V.

[0065] Curve A3 corresponds to the same assembly 1 or power semiconductor device 10 configuration as curve A2, but with four vias 1V as shown in FIG. 2. Here, each of the four vias 1V is in the form of a trench with a lateral width of 40 μm and a vertical height of 590 μm, which is assumed to be filled with copper. They provide an electrical bypass from the upper drift layer, second layer 12, to an electrical contact on the bottom side 11B of first layer 11. A thermal boundary / electrode is also located on the bottom side 11B of first layer 11.

[0066] Curve A4 corresponds to the same assembly 1 or power semiconductor device 10 configuration as curve A2, but with eight vias 1V as shown in FIG. 1A. Here, each of the eight vias 1V is in the form of a trench with a lateral width of 20 μm and a vertical height of 590 μm, which is assumed to be filled with copper. They provide an electrical bypass from the upper drift layer, second layer 12, to an electrical contact on the bottom side 11B of first layer 11. A thermal boundary / electrode is also located on the bottom side 11B of first layer 11.

[0067] As shown in FIG. 8A, due to the good thermal properties of silicon carbide, a thicker first layer 11 adds a significant amount of heat capacity. This results in a slower increase in the assembly temperature when a current pulse is applied. However, it has also been observed that a second, opposite effect occurs: as the thickness 11T of the first layer increases, the total resistance of the assembly 1 or power semiconductor device 10 becomes higher. This means that the heat generated by the exact same current pulse will be higher in the second case. Therefore, there is a maximum thickness 11T of the first layer 11, at which the final maximum temperature reached after the current pulse no longer decreases but instead increases again.

[0068] However, the presence of vias 1V can ensure reduced self-heating and improved current density, even with a relatively thick first layer 11. The tops of the vias 1V can be stopped short before the second layer 12, for example, in the range of 1 μm to 50 μm for curves A3 and A4, or 10 μm here, thereby contributing to the maximum path for bypassing the resistance of the first layer 11. The widths of the four vias 1V for curve A3 and the eight vias 1V for curve A4 were intentionally chosen to be different, indicating that the width of the vias 1V and the lateral spacing between them are suitable parameters for optimization. The results of the self-heating simulation for various configurations are provided by curves A1 through A4. Although the density of vias 1V remains low—here, only four or eight vias 1V across a 5120 μm assembly width—the results provided by curves A3 and A4 already indicate the possibility of peak temperature limits exceeding 100 K when measured against the base case provided by curve A1, especially at higher current densities. The peak temperature can be further limited by increasing the number and / or size of the vias 1V in the first layer 11.

[0069] Thus, using two-dimensional simulations, the effectiveness of this approach has been demonstrated for the configurations shown in Figures 1A and 2. It has been shown that a thick first layer 11 with multiple vias 1V can significantly slow thermal runaway. To enhance this effect, the density of vias 1V per area can be much higher than that used in the numerical examples presented herein.

[0070] FIG. 8B shows further curves B1, B2 and B3 as a function of temperature rise as a function of current density after a 3 second current pulse.

[0071] Curve B1 corresponds to the same configuration of assembly 1 or power semiconductor device 10 with a first SiC layer 11 having a thickness 11T of 600 μm without any vias 1V and a second SiC layer 12 that is a drift layer having a thickness of 8 μm, and a further configuration of assembly 1 or power semiconductor device 10 according to curve A2. In addition, assembly 1 or power semiconductor device 10 is placed on a heat sink 3 that is a copper plate with a thickness 3T of 4180 μm. Such an assembly 1 or power semiconductor device 10 is shown in FIG. 5, but without any vias 1V in the first layer 11.

[0072] Curve B2 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B1, but the first SiC layer 11 has a thickness 11T of 600 μm and four vias 1V, as shown in Figure 2. Such an assembly 1 or power semiconductor device 10 is shown in Figure 5, but with four vias 1V in the first layer 11, each in the form of a trench having a lateral width of 40 μm and a vertical height of 590 μm, and filled with copper.

[0073] Curve B3 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B1, but with eight vias 1V. Such an assembly 1 or power semiconductor device 10 is shown in Figure 5, but with eight vias 1V in the first layer 11, each in the form of a trench having a lateral width of 20 μm and a vertical height of 590 μm, and filled with copper.

[0074] As shown in Figure 8B, using a thick first SiC with the highest density of vias 1V provides the most efficient delay of thermal runaway. This effect is enhanced by the presence of a heat sink 3. According to Figure 8B, the maximum temperature is reached after a 3-second current pulse with a given current density. Compared to Figure 8A, it is clear that the presence of a heat sink 3 significantly limits the final temperature reached at the end of the current pulse. Here, for a given allowable temperature rise, the maximum current density can be roughly doubled by adding a thick copper heat sink 3, as used in the numerical example. This can be seen by comparing curve A4 in Figure 8A with curve B3 in Figure 8B, for a temperature rise of, say, 150 K.

[0075] FIG. 8B also shows that the advantage of a thick SiC first layer 11 featuring copper-filled vias 1V is that it can be used at higher current densities, e.g., 300 A / cm 2 It shows that the increase in the current density remains significant even at lower current densities, e.g., 150 A / cm 2 In this case, the maximum allowable current density increases by more than 10%.

[0076] FIG. 8C shows the curves B1, B2 and B3 already shown in FIG. 8B as well as additional curves C4 and C5.

[0077] Curve C4 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B3, but with a heat sink 3 that exceeds the width or cross section of body 1M as shown in Figure 6. Here, the size of heat sink 3 is changed from 5120 μm x 4180 μm to 10240 μm x 2090 μm, while the volume of heat sink 3 remains unchanged.

[0078] 5, the heat sink 3 in FIG. 6 has a larger width or a larger cross section, but a smaller thickness 3T. Therefore, the volume of the heat sink 3 shown in FIG. 5 and the volume of the heat sink 3 shown in FIG. 6 can be the same, which applies to the configuration of the assembly 1 or the power semiconductor device 10 according to curves B3 and C4. In other words, curve B3 corresponds to the assembly 1 or the power semiconductor device 10 shown in FIG. 5, and curve C4 corresponds to the assembly 1 or the power semiconductor device 10 shown in FIG. 5. For a quantitative evaluation of the additional effect on the dimensions of the heat sink 3, it can be seen from curves B3 and C4 that a wider heat sink 3 with the same volume can achieve a current of 300 A / cm. 2 It can be seen that this provides a reduction of about 50K at a current density of 1000kJ / cm.

[0079] Curve C5 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve C4, except that assembly 1 or power semiconductor device 10 includes a SiC substrate 5, i.e., a top-side cooler, as shown in FIG. 7. SiC substrate 5 may have approximately the same size as first layer 11 or body 1M. However, substrate 5 does not have vias 1V. For the simulation, SiC substrate and first SiC layer 11 have the same thickness of 600 μm.

[0080] FIG. 8D is essentially the same as FIG. 8A, except that an additional curve D5 is shown. Curve D5 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve A4 shown in FIG. 1A, except that assembly 1 includes an additional SiC substrate 5 having a thickness 5T as shown in FIG. 4. For numerical simulations, thickness 5T is selected to be 600 μm. Curve D5 shows that the additional substrate 5 can further delay thermal runaway, resulting in a further reduction in self-heating and a further increase in current density.

[0081] The additional SiC substrate 5 is a SiC top cooler that acts as an additional heat sink, further reducing the final maximum temperature after the completion of the 3 second pulse of current. 2 The configuration investigated using a 1.2 kV JFET with an on-resistance of 150-160 A / cm 2 The initial configuration, such as curve A1, can withstand a current pulse of 70-80 A / cm², resulting in a final temperature rise of 150 K. 2 This temperature rise is reached after a current pulse of 1000 . It is clear that the configuration shown in Figure 4 may be extended for top and / or bottom cooling, i.e. for an additional substrate 5 and / or heat sink 3. In this case, the additional substrate 5 may receive a second thermal boundary / electrode.

[0082] 8A-8D illustrate some key concepts of this disclosure for a 1200V device. This can be extended to other voltage classes to achieve similar benefits in reducing device temperature and thereby increasing operating current density. This benefit may be more pronounced in lower voltage classes, such as 600V devices typically used in event switching applications. This is because the contribution to total device resistance from a thicker first layer 11 is greater in this voltage range. The illustration is done using a 600µm thick SiC first layer 11. This can be applied to a standard SiC first layer 11 acting as a substrate with a thickness 11T of approximately 350µm, and similar benefit trends are observed by using metal-filled trenches or vias 1V within the first layer 11 and / or in combination with a heat sink 3 and additional substrate 5.

[0083] 9A, 9B and 9C show some exemplary method steps of a method for manufacturing at least one assembly 1 for a power semiconductor device 10. In FIG.

[0084] 9A , a wafer 100 is provided that includes at least one SiC-based body 1M. The body 1M includes a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The second thickness 12T is smaller than the first thickness 11T, and the first layer 11 and the second layer 12 are formed from SiC. The first layer 11 has a higher n-doping concentration than the second layer 12. For example, the first layer 11 is formed as a substrate, and the second layer 12 is formed as a drift layer of the assembly 1 or the power semiconductor device 10.

[0085] 9B, a plurality of trenches 1H extend vertically from the bottom side 11B of the first layer 11 toward the second layer 12 and partially into the first layer 11, with the trenches 1H not extending into the second layer 12. Some possible arrangements of the trenches 1H are described in relation to FIGS. 10A-13. The trenches 1H can be formed by a drilling and / or etching process.

[0086] 9C , the trench 1H is filled with a conductive material to form a plurality of vias 1V, which extend partially into the first layer 11 along the vertical direction from the bottom side 11B of the first layer 11 toward the second layer 12, but do not extend into the second layer 12. Therefore, the vias 1V do not provide a connection between the bottom side 11B and the top side of the first layer 11. In other words, the trench 1H is not formed as a through hole that extends entirely through the first layer 11 along the vertical direction. Therefore, the vias 1V are not formed as through vias.

[0087] The trench 1H can be completely filled with the conductive material, as shown in FIG. 9C. However, it is also possible for the trench 1H to be partially filled with the conductive material. For example, only the inner walls of the trench 1H are coated with the conductive material. In this case, the trench 1H may include a region filled with a gaseous medium, for example, air.

[0088] 10A shows possible arrangements of trenches 1H or vias 1V relative to an edge 100E of a wafer 100 and relative to a plurality of assemblies 1 or power semiconductor devices 10 to be fabricated. The trenches 1H or vias 1V extend perpendicular to the edge 100E. In a top view relative to the bottom side of the wafer, some of the trenches 1H or vias 1V overlap with a plurality of assemblies 1 or power semiconductor devices 10 to be fabricated. The trenches 1H or vias 1V are parallel to each other. The trenches 1H or vias 1V can also be formed in the regions between the assemblies 1 or power semiconductor devices 10 to be fabricated. The trenches 1H or vias 1V can extend across the entire lateral extent of the wafer 100.

[0089] When the wafer 100 is singulated into a plurality of bodies 1M, assemblies 1 or power semiconductor devices 10 along singulation lines 1S, at least some of the singulation lines 1S pass through the vias 1V so that at least some of the singulated bodies 1M, assemblies 1 or power semiconductor devices 10 include sides that include sides of the vias 1V.

[0090] Figure 10B shows a cross-sectional view of wafer 100 as shown in Figure 10A along line AB. Deviating from Figures 10A and 10B, other lateral orientations of trench 1H or via 1V are possible. For example, trench 1H or via 1V can be parallel to edge 100E of the wafer or form an acute angle with edge 100E.

[0091] The wafer 100 shown in FIG. 11A is essentially the same as the wafer 100 having the trenches 1H or vias 1V shown in FIG. 10A, except that the wafer 100 does not have the trenches 1H or vias 1V located in the regions between the assemblies 1 or power semiconductor devices 10 to be manufactured. Therefore, it can be ensured that a portion of the singulation line does not pass through the trenches 1H or vias 1V. FIG. 11B shows a cross-sectional view of the wafer 100 as shown in FIG. 11A along the line AB.

[0092] The wafer 100 shown in FIG. 12 is essentially the same as the wafer 100 having trenches 1H or vias 1V shown in FIG. 10A, except that the trenches 1H or vias 1V are parallel to the edge 100E of the wafer.

[0093] 13 is essentially the same as the wafer 100 with trenches 1H or vias 1V shown in FIG. 10A, except that the trenches 1H or vias 1V are formed only in the region of the assembly 1 or power semiconductor device 10 to be manufactured. Thus, in the lateral direction, the trenches 1H or vias 1V are completely surrounded by the first layer 11.

[0094] According to Figure 13, when the wafer 100 is singulated into multiple bodies 1M, assemblies 1 or power semiconductor devices 10 along the singulation lines 1S, none of the singulation lines 1S pass through the vias 1V so that no vias 1V are present on all sides of any of the singulated bodies 1M, assemblies 1 or power semiconductor devices 10.

[0095] Deviating from FIG. 13 , it is possible for the via 1V to be rotated by an angle of 90° or another angle, for example, 45°±10°, 45°±15°, 45°±20°, or 45°±30°. As shown in FIG. 13 , in a top view with respect to the bottom side of the first layer 11, the via 1V can extend across the entire lateral width or lateral length of the power semiconductor device 10 to be manufactured. The via 1V can also have a lateral extension that is smaller than the lateral width and smaller than the lateral length of the power semiconductor device 10 to be manufactured. Deviating from FIG. 13 , it is also possible that, prior to singulating the wafer 100 into a plurality of power semiconductor devices 10, the via 1V can have a lateral extension that is larger than the lateral width and / or the lateral length of the power semiconductor device 10 to be manufactured.

[0096] The embodiments shown in the above figures represent exemplary embodiments of the assembly, the power semiconductor device, and the method for manufacturing the assembly for the power semiconductor device. Therefore, they do not constitute an exhaustive list of all embodiments and methods according to improved configurations of the assembly, the power semiconductor device, and the method. The actual configurations of the assembly, the power semiconductor device, and the method may differ from the exemplary embodiments described above.

[0097] This application claims priority from European Patent Application No. 23160696.3, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0098] Reference sign 100 wafers 10 Power Semiconductor Devices 1 Assembly 1M Assembly Body 1V via 1H trench / hole 1S singulation wire 11 First layer of the body 11B bottom side of first layer 11F First layer, first side 11S Second side of first layer 11T first thickness 12 Second layer of the body 12T second thickness 3 Heatsink 3T Heatsink Thickness 5. Substrate 5T board thickness 100E Wafer edge

Claims

1. An assembly (1) for a power semiconductor device (10), comprising: - said assembly (1) comprises a body (1M) based on SiC and a number of vias (1V) based on a conductive material; - said body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), said second thickness (12T) being smaller than said first thickness (11T); - said first layer (11) and said second layer (12) are made of SiC, said first layer (11) having a higher n-doping concentration than said second layer (12); - the vias (1V) extend partly into the first layer (11) along a vertical direction from the bottom side (11B) of the first layer (11) towards the second layer (12), and the vias (1V) do not extend into the second layer (12); - the assembly further comprises a SiC substrate (5), - the second layer (12) is arranged between the SiC substrate (5) and the first layer (11); the SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is between 1.5 and 250; An assembly (1) in which said SiC substrate (5) does not contain any vias made of conductive material.

2. - the ratio (11T / 12T) of the first thickness (11T) to the second thickness (12T) is 1.5 to 250; Assembly (1) according to claim 1, wherein said first thickness (11T) is between 100 μm and 1000 μm and said second thickness (12T) is between 2 μm and 200 μm.

3. - the first thickness (11T) is 300 μm or more, - said second thickness (12T) is less than or equal to 55 μm, An assembly (1) according to any of the preceding claims, wherein the maximum vertical distance between said second layer (12) and said via (1V) is between 0.6 μm and 250 μm.

4. a ratio of the average vertical height of the vias (1V) to the first thickness (11T) of the first layer (11) being at least 0.5; An assembly (1) according to any of the preceding claims, wherein said vias (1V) have an average lateral width of between 10 μm and 150 μm.

5. Assembly (1) according to any of claims 1 to 4, wherein along the lateral direction, said via (1V) is completely surrounded by said first layer (11).

6. 5. The assembly (1) according to claim 1, wherein the first layer (11) has a first side (11F) and a second side (11S), and at least one of the vias (1V) extends from the first side (11F) to the second side (11S) along a lateral direction.

7. 10. The assembly (1) of any preceding claim, further comprising a heat sink (3) made of metal, the body (1M) being arranged on the heat sink (3), the heat sink (3) having a vertical thickness (3T) greater than the sum of the first thickness (11T) and the second thickness (12T).

8. 8. The assembly (1) according to claim 7, wherein the heat sink (3) has a cross section larger than that of the body (1M) such that the body (1M) completely overlaps the heat sink (3) in a plan view of the heat sink (3).

9. - said SiC substrate (5) and said body (1M) are separated by a metal layer constituting an electrode of said assembly (1); An assembly (1) according to any of the preceding claims, wherein the SiC substrate (5) acts as a top cooler and is not electrically active.

10. Assembly (1) according to any of the preceding claims, wherein the vias (1V) have cross-sections whose size varies along the vertical direction, the size of the cross-section of each of the vias (1V) increasing as the distance to the bottom side (11B) of the first layer (11) decreases.

11. A power semiconductor device (10) comprising an assembly (1), - said assembly (1) comprises a body (1M) based on SiC and a number of vias (1V) based on a conductive material; - said body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12), said second thickness (12T) being smaller than said first thickness (11T); - said first layer (11) and said second layer (12) are made of SiC, said first layer (11) having a higher n-doping concentration than said second layer (12); - the vias (1V) extend partly into the first layer (11) along a vertical direction from the bottom side (11B) of the first layer (11) towards the second layer (12), and the vias (1V) do not extend into the second layer (12); - said second layer (12) comprises a functional area configured to perform the function of said power semiconductor device (10); - the assembly further comprises a SiC substrate (5), - the second layer (12) is arranged between the SiC substrate (5) and the first layer (11); the SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is between 1.5 and 250; A power semiconductor device (10) in which the SiC substrate (5) is free of any vias made of conductive material.

12. 12. The power semiconductor device (10) of claim 11, which is a MOSFET, a JFET, an IGBT, a Schottky diode, a junction barrier Schottky diode, or a SiC power device for event switching.

13. A method for manufacturing an assembly (1) for a power semiconductor device (10), comprising: - providing a wafer (100) comprising at least one body (1M) based on SiC, said body (1M) comprising a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), said second thickness (12T) being smaller than said first thickness (11T); - providing a wafer (100) in which the first layer (11) and the second layer (12) are made of SiC, the first layer (11) having a higher n-doping concentration than the second layer (12); - forming a plurality of trenches (1H) extending partly into the first layer (11) along a vertical direction from the bottom side (11B) of the first layer (11) towards the second layer (12), the trenches (1H) not extending into the second layer (12); filling the trenches (1H) with a conductive material to form a plurality of vias (1V), the vias (1V) extending partly into the first layer (11) along the vertical direction from the bottom side (11B) of the first layer (11) towards the second layer (12) and not extending into the second layer (12); The assembly comprises a SiC substrate (5), - the second layer (12) is arranged between the SiC substrate (5) and the first layer (11); the SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is between 1.5 and 250; - the method, wherein said SiC substrate (5) does not contain any vias made of conductive material.

14. - said wafer (100) is singulated along singulation lines (1S) into a plurality of bodies (1M), The method according to claim 13, wherein at least some of the singulation lines (1S) pass through the vias (1V) so that at least some of the singulated bodies (1M) have sides that include sides of the vias (1V).

15. - said wafer (100) is singulated along singulation lines (1S) into a plurality of bodies (1M), - A method according to claim 13, wherein at least some of the singulation lines (1S) do not pass through the vias (1V) so that at least some of the singulated bodies (1M) have all sides on which no sides of the vias (1V) are present.

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