Improved off-state isolation bias circuit for D-mode amplifiers

Abstract

The circuit includes an amplifier (706) and a bias circuit. The amplifier (706) includes an output transistor having a source electrode, a drain electrode, and a gate electrode. The bias circuit includes a first control loop configured to set a first quiescent bias of the output transistor based on a first value of a first control voltage and a second value of a second control voltage, the first quiescent bias being configured to turn the output transistor ON, and a second control loop configured to set a second quiescent bias of the output transistor based on a first value of a first control voltage and a second value of a second control voltage. The second quiescent bias is configured to turn the output transistor OFF and to increase the insertion loss of the amplifier when the output transistor is OFF.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to devices, systems, and methods that provide a circuit for biasing a radio frequency (RF) amplifier.

Background Art

[0002] FIG. 1 is a first circuit diagram 100 of a conventional amplifier (here, a radio frequency (RF) amplifier), including a depletion mode transistor Q1 whose source electrode is coupled to a reference potential (here, ground), a drain electrode coupled to a potential higher than the reference potential (here, +Vdd) via a first inductor as shown, and providing an amplified RF output after passing through a first capacitor as shown, and a gate electrode coupled to an input signal (here, an RF input via a second capacitor) as shown. Note that, as shown, the source electrode of transistor Q1 is connected to ground, and there is a second inductor between the gate of Q1 and the gate voltage Vg.

[0003] This setting of the quiescent drain current (Id) of a field effect transistor (FET) type amplifier as shown in FIG. 1 is typically achieved by adjusting the DC gate voltage Vg supplied to the gate of the transistor (Q1), for example, via a bias circuit / network (as is well known, the bias network / circuit is used to place the FET at the intended quiescent operating point). In principle, the gate voltage Vg can be easily determined from the transfer characteristic of the quiescent drain current Id versus the gate voltage Vg of a typical device, but the inherent sensitivity of the FET characteristics to the manufacturing process and temperature prevents the use of a fixed Vg.

[0004] In analog circuit design, there are various ways to bias an FET amplifier and reach its intended quiescent operating point. For example, one method for biasing a first FET is to use an active bias circuit / network, such as a current mirror circuit. An active bias circuit / network is an analog circuit that uses a second FET to "calculate" the gate bias required for the first FET being biased, and then the second FET supplies the required gate bias to the first FET (corresponding to the active device in the amplifier). This arrangement eliminates the need to manually adjust the Q point of the first FET, but requires a negative supply voltage. For example, a current mirror circuit can be used as an active bias circuit / network. An example of a current mirror used for DC biasing of FETs can be found in "Analysis and Design of Analog Integrated Circuits, 3" by Paul R. Gray and Robert G. Meyer. rd This information is contained in "ed., New York: Wiley, 1993," and is incorporated herein by reference.

[0005] Figure 2 is a second schematic diagram illustrating a prior art current mirror configuration for a depletion-mode gallium arsenide metal semiconductor field-effect transistor (D-mode GaAs MESFET) operational amplifier, similar to those demonstrated by Scheinberg (see N. Scheinberg, Design of high speed operational amplifiers with GaAs MESFETs, procs1987 IEEE ISCAS (Philadelphia), May 1987, pp193-198) and C. Tamazou and D. Haigh, "Gallium Arsenide Analog Integrated Circuit Design Techniques," Chapter 8 in "Analogue IC design: the current-mode approach," Edited by C. Tamazou, F.J. Lidgey & D. G. Haigh, London: Peter Peregrinus Ltd. 1990, each of which is incorporated herein by reference.

[0006] The second circuit diagram 200 in Figure 2 shows a bias circuit, which has a current source Iref and a bias circuit (depletion mode transistors Q1, Q3, Q4, first diode 220, second diode 222) arranged as shown, connected to the current source Iref 204 and includes a current mirror connected between a potential higher than the reference potential (+Vdd) and a potential lower than the reference potential (Vss1, corresponding to a potential lower than Vss). The first diode 220 and the second diode 222 in this example are gallium arsenide (GaAs) diodes. Although only the first diode 220 and the second diode 222 are shown in the second circuit diagram 200, it should be noted that there may be multiple GaAs diodes, for example, n, where n is the number of diodes in series selected according to the voltage used in a given circuit. In the example in Figure 2, +Vdd is 24 volts and Vss1 is -8.0 volts. The circuit in Figure 2 can be easily implemented to control the drain current of a high-efficiency, high-power RF amplifier.

[0007] Figure 3 is a third circuit diagram of a prior art amplifier and current mirror configuration, showing a simplified schematic embodiment with appropriate inductors and capacitors connected to an RF amplifier having FET Q2. For a high-power, high-efficiency RF amplifier, it is essential that the FET source potential be directly connected to ground reference, which is also shown in Figure 3 by Vss being connected to ground potential. Note that Vss1 is lower than ground potential, and the drains of Q1, Q2, and Q3 are at a higher potential than ground potential. The arrangement and function of the first diode 310 and the second diode 312 are the same as those of the first diode 220 and the second diode 222 in Figure 2, and will not be repeated here.

[0008] In circuits like those shown in Figures 1 and 2, if there is no bias circuit to compensate for process variations, some means can be implemented to adjust the gate voltage Vg for each amplifier, preferably, so that the quiescent drain current Id is set close to the nominal target value. Examples of patents relating to these types of circuits are U.S. Patents 5,889,429, 6,304,130, 6,114,901, 5,793,194, 4,896,121, 7,928,804, and 8,854,140, ​​all of which are incorporated herein by reference. [Overview of the project]

[0009] Below is a simplified overview to provide a basic understanding of one or more aspects of the embodiments described herein. This overview is not a comprehensive overview of all possible embodiments, nor is it intended to identify or limit the scope of any key or essential elements of an embodiment. Rather, the main purpose of this overview is to present some of the concepts of the embodiments described herein in a simplified form, serving as an introduction to the more detailed descriptions that will follow.

[0010] One common embodiment is a circuit, the circuit comprising a first amplifier, the first output transistor comprising a first source electrode, a first drain electrode, and a first gate electrode; and a bias circuit operably communicating with the first amplifier, the bias circuit comprising a first control loop configured to set a first quiescent bias of the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, the first quiescent bias being configured to turn the first output transistor on; and a second control loop configured to set a second quiescent bias of the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, the second quiescent bias being configured to turn the first output transistor off and to increase the insertion loss of the first amplifier when the first output transistor is off.

[0011] In some embodiments, the bias circuit provides a first output signal to a first gate electrode based on at least one of a first control loop and a second control loop. In some embodiments, at least one of the first control loop and the second control loop further includes a first level shift network configured to provide a first level shift to the level of the first output signal. In some embodiments, the first level shift network includes at least one of a diode, a resistor, and a short-circuit connection. In some embodiments, the circuit further includes a second level shift network configured to be shared by both the first and second control loops, the second level shift network configured to provide a second level shift to the level of the first output signal. In some embodiments, the second level shift network includes at least one of a diode, a resistor, and a short-circuit connection.

[0012] In some embodiments, a second quiescent bias is configured to set the voltage at the first gate electrode to a positive value relative to the pinch-off voltage of the first output transistor, and to form a resistance between the first drain electrode and the first source electrode that is low enough to allow conduction to ground between the first drain electrode and the first source electrode. In some embodiments, a first control voltage and one of the second control voltages are coupled to the first drain electrode of the first amplifier. In some embodiments, when the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop is configured to set a first quiescent bias to turn on the first output transistor. In some embodiments, when the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop is configured to set a second quiescent bias to turn off the first output transistor. In some embodiments, at least one of the first control loop and the second control loop further includes a diode network including at least one diode, the diode network being configured to isolate at least a portion of the first control loop from the second control loop.

[0013] In some embodiments, the bias circuit further includes a second amplifier comprising a second output transistor, the second output transistor comprising a second source electrode, a second drain electrode, and a second gate electrode, the bias circuit operably communicates with the second amplifier, and a first control loop configured to set a third quiescent bias of the second output transistor based on a first value of a first control voltage and a second value of a second control voltage, the third quiescent bias being configured to turn off the second output transistor and increase the insertion loss of the second amplifier when the second output transistor is off; and a second control loop configured to set a fourth quiescent bias of the second output transistor based on a first value of a first control voltage and a second value of a second control voltage, the fourth quiescent bias being configured to turn on the second output transistor.

[0014] In some embodiments, the first and second control loops are configured such that, when the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop sets a first quiescent bias to turn on the first output transistor, and sets a third quiescent bias to turn off the second output transistor. In some embodiments, the first and second control loops are configured such that, when the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop sets a first quiescent bias to turn off the first output transistor, and sets a fourth quiescent bias to turn on the second output transistor. In some embodiments, the bias circuit provides a second output signal to the second gate electrode based on at least one of the first and second control loops.

[0015] In some embodiments, the bias circuit includes a third control loop configured to set a third quiescent bias of the first output transistor based on a first value of a first control voltage, a second value of a second control voltage, and a third value of a third control voltage, the third quiescent bias being configured to put the first output transistor into one of an on state and an off state. In some embodiments, at least one of the first control loop and the second control loop includes a plurality of control loops. In some embodiments, at least one of the first control voltage and the second control voltage is associated with a range of voltage values.

[0016] One common embodiment is a method, the method comprising the steps of: providing a first amplifier including a first output transistor, the first output transistor comprising a first source electrode, a first drain electrode, and a first gate electrode; and operably coupling a bias circuit to the first amplifier, the bias circuit comprising: a first control loop configured to set a first quiescent bias of the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, the first quiescent bias being configured to turn the first output transistor on; and a second control loop configured to set a second quiescent bias of the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, the second quiescent bias being configured to turn the first output transistor off and to increase the insertion loss of the first amplifier when the first output transistor is off. The method also includes the step of providing a first output signal to a first gate electrode, the first output signal being based on at least one of a first control loop and a second control loop.

[0017] In some embodiments, the method further includes the steps of setting the voltage at the first gate electrode to a positive value relative to the pinch-off voltage of the first output transistor, and forming a resistance between the first drain electrode and the first source electrode that is low enough to allow conduction to ground between the first drain electrode and the first source electrode.

[0018] It should be understood that the individual elements of the different embodiments described herein can be combined to form other embodiments not specifically described above. Various elements described in the context of a single embodiment may be provided separately or in any suitable partial combination. It should also be understood that other embodiments not specifically described herein also fall within the scope of the claims contained herein.

[0019] Details relating to these embodiments and other embodiments will be further described herein.

[0020] The advantages and aspects of the embodiments described, as well as the embodiments themselves, will be better understood in conjunction with the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0021] [Figure 1] This is the first simplified circuit diagram of a conventional amplifier. [Figure 2] This is a second simplified circuit diagram of the conventional current mirror configuration. [Figure 3] This is a third simplified circuit diagram of a conventional amplifier and current mirror configuration. [Figure 4] This is a fourth simplified circuit diagram of a first transmit / receive (TR) front-end element of the prior art, in which a low-noise amplifier (LNA) is enabled, according to one embodiment. [Figure 5]FIG. 5 is a fifth simplified diagram of a circuit representing a second TR front-end element when the LNA is active, in accordance with an exemplary embodiment of the present disclosure, of the RF amplifier bias circuit described herein. [Figure 6] FIG. 6 is a truth table showing how the operating state of the circuit of FIG. 5 is related to the bias states of its LNA and power amplifier (PA), in accordance with an exemplary embodiment of the present disclosure. [Figure 7] FIG. 6 is a sixth simplified circuit diagram of a first amplifier and a first bias circuit, in accordance with a first exemplary embodiment of the present disclosure. [Figure 8] FIG. 7 is a seventh simplified circuit diagram of a diode configuration of a second bias circuit, in accordance with a second exemplary embodiment of the present disclosure. [Figure 9] FIG. 8 is an eighth simplified circuit diagram of a first alternative amplifier that can be used with the exemplary bias circuits of FIGS. 5-8, in accordance with one embodiment. [Figure 10] FIG. 9 is a ninth simplified circuit diagram of a second alternative amplifier that can be used with the exemplary bias circuits of FIGS. 5-8, in accordance with one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] These drawings are not necessarily drawn to scale. Also, in the drawings, like reference numerals denote like elements.

[0023] The following detailed descriptions are provided assuming specific use cases in the front end of radar systems, at least in some examples, but the embodiments described herein are applicable to any system, circuit, or device requiring biasing of transistors in an amplifier, and any system that may be subject to unwanted coupling and / or other types of signal interference. The embodiments described herein are also applicable to several semiconductor technologies, including, but not limited to, gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0024] The following description and drawings illustrate various connections and couplings between elements. These general connections may be direct or indirect unless otherwise specified, and this specification is not intended to limit them in this respect. Any component or element described herein can be formed as a processing circuit that may include application-specific integrated circuits (ASICs), electronic circuits, processors (shared, dedicated, or grouped), and memory, combinational logic circuits, and / or other suitable components that run one or more software or firmware programs.

[0025] Furthermore, the use of the term “signal” in relation to this disclosure is not limited to analog and / or digital signals, but is rather intended to also refer to (1) a mathematical description of any measurable phenomenon in natural or artificial systems, and (2) a mathematically described function of one or more variables that depend on one or more parameters. Examples of the types of signals included in the embodiments described herein include, but are not limited to, light intensity, voltage, pressure, electromagnetic radiation (including radio waves), magnetic field strength, and electric field strength.

[0026] RF amplifiers are used in many applications, such as the front end of radar systems, and may include transmit / receive (TR) amplifier elements that amplify the signal sent to the antenna's radiating element. This is illustrated in Figure 4, which is a fourth simplified circuit diagram of a first TR element 400 of a first system front end when a low-noise amplifier (LNA) 406 is enabled according to one embodiment. The first TR element 400 of the TR system front end includes a TX / RX connection 402 coupled to a radar receiver (not shown) and a radar transmitter (not shown). The TX / RX connection 402 is also connected to a switch 410 configured to switch the TX / RX connection to either a receive path 411 or a transmit path 413.

[0027] When switch 410 is set to receive path 411 (for example, as shown in Figure 4), RF signals (for example, returning from a target) are received by one or more radiating elements 404 of the antenna array, and these received signals are amplified by LNA 406 and provided to a receiver (not shown) as is well known in the art. When switch 410 is set to transmit path 413, signals from a transmitter (not shown) are coupled to a power amplifier (PA) 408 and then provided to one or more radiating elements 404 for transmission.

[0028] The LNA 406 in the first TR element 400 of Figure 4 is an FET amplifier type circuit similar to the circuit in Figure 1 described earlier, and the VD LNA ON signal 412 in the circuit of Figure 4 provides a drain voltage level (for example, +VDD 102 in Figure 1) that is configured to turn on the FET Q1 120 in Figure 1, as shown in the circuit of Figure 4. The PA 408 in Figure 4 is also an FET amplifier circuit similar to the one in Figure 2 described above, and in the circuit of Figure 4, the VD PA OFF signal 414 is set to turn off the PA (because the transmit path 413 (TX path) is not selected). Furthermore, it will be understood that the switching between transmit and receive is very fast during the operation of the circuit of Figure 4.

[0029] However, undesirable effects may occur during the operation of the first TR element 400 in Figure 4. For example, as shown in Figure 4, unwanted coupling may occur between an off-state TR amplifier element and an on-state TR amplifier element (for example, the unwanted coupling between LNA406 and PA408 when one of the two amplifiers is on and the other is off). The factors causing this effect are not limited to high amplifier gain, operating frequency, or narrow circuit spacing, but can be various. This coupling may result in gain ripple, phase ripple, or oscillation, which may affect the operation and / or accuracy of the circuit and / or the system in which the circuit is installed.

[0030] One way to reduce unwanted coupling is to increase the insertion loss of the amplifier when it is off. In one embodiment of the present invention, an RF amplifier bias circuit is provided that is configured to increase the insertion loss of the amplifier when it is off, and further configured to provide two different bias control loops that help reduce unwanted coupling. In other words, in certain embodiments, the insertion loss when the amplifier is in the "off" state is increased compared to when using a conventional RF amplifier bias circuit. In certain embodiments, the insertion loss when the amplifier is in the "off" state is increased compared to when the amplifier is in the "on" state. In some circuit environments, it is desirable to keep the insertion loss low, but as described herein, increasing the insertion loss when the amplifier is in the "off" state can reduce unwanted coupling in the circuit environment.

[0031] The RF amplifier bias circuit provided herein (further described herein in relation to Figures 5-8, and in particular in relation to Figures 7 and 8 showing two embodiments of the bias circuit) provides a first control loop for establishing a first quiescent bias for the ON state of the LNA amplifier and a second control loop for establishing a second quiescent bias for establishing an improved insertion loss in the OFF state of the LNA. Each of these control loops is enabled or disabled by the drain voltage state of the TR element. As further described below, the circuit configuration provided as a bias circuit provides the LNA with an output signal that can bring the LNA into a high-loss state when the LNA is in the "off" state, helping to reduce the possibility of the LNA coupling to other components in the system. The output signal provided to the LNA helps to set the LNA to one of two quiescent bias states, as further described herein. Furthermore, as further described herein, the circuit configuration provided as a bias circuit provides the PA with an output signal that helps to set the PA to one of two bias states ("on" or "off").

[0032] For example, Figure 5 is a fifth simplified diagram of a circuit representing the second TR element 500 of the second TR front end with the LNA 506 enabled, incorporating the RF amplifier bias circuit further described herein, according to one exemplary embodiment of the present disclosure. In Figure 5, the LNA 506 is enabled and in the "on" state, and the PA 508 is in the "off" state. The arrangement in Figure 5 helps to improve the insertion loss of the amplifier in the off state. Figure 6 is a truth table 600 showing how the operating states of the circuit in Figure 5 relate to the bias states of its LNA 506 and PA 508, according to one exemplary embodiment of the present disclosure. As shown in Figure 5, the drain voltage controls (VD) of the power amplifier (PA) (i.e., VD PA514a and VD PA514b) and the drain voltage controls of the low noise amplifier (LNA) (VD LNA512a and VD LNA512b) are configured such that each of the respective amplifiers (i.e., PA508 and LNA506) is operably connected to each of the two drain voltage control signals. In other words, the drain controls for both the PA and LNA are provided to the LNA and PA of the second TR element 500, and they are not controlled separately.

[0033] As will be further described in relation to Figures 7 and 8, the circuit of Figure 5 uses two different drain power supplies, and in at least some embodiments, the drain power supply voltages advantageously utilize two different voltages already present in the system in which the circuit is installed. If necessary, in a given embodiment, the levels of either or both of the voltages already present in the system may be shifted to a level suitable for biasing the FET amplifier, as will be further described herein. The power supply that provides the drain voltage functions as the bias source and control logic (sensor signal) source in the truth table of Figure 6. In certain embodiments, the power supply that provides the drain voltages to LNA706 (i.e., VD LNA712a) and PA708 (i.e., VD PA714a) in Figure 7 also supplies the bias circuit 703, which is used to switch between a first quiescent bias state and a second quiescent bias state in both LNA706 and PA708. This arrangement allows the control function of the truth table 600 in Figure 6 to provide an equivalent OR gate logic function for establishing the first or second quiescent bias state. In other words, the two different drain power supplies form an equivalent OR gate logic function to establish either a first quiescent bias state or a second quiescent bias state.

[0034] Referring to Figures 5 and 6, the "off" state of a given amplifier is given by truth table 600, which shows the states corresponding to the cases where signals VD LNA512a, 512b are "high or low" and signals VD PA514a, 514b are "high or low", where "high" in truth table 600 corresponds to the "on" state and "low" in truth table 600 corresponds to the "off" state. The "off" state of PA is intended to refer to the state where LNA506 is "on" and PA508 is off (in Figure 5, both VD PA514a and VD PA514b are "low" and both VD LNA512a and VD LNA512b are "high"), which corresponds to the reception state of the second TR element 500.

[0035] In the receive state, the TX / RX switch 510 is set to the receive path (for example, as shown in Figure 5), and the signal received by the radiating element(s) 504 is supplied to the LNA, which applies low-noise amplification to the signal and provides it to the receiver's front end via the TX / RX connection. The receive state corresponds to the PA being "off" and the LNA being "on" (as shown in the first row of the truth table in Figure 6). In the transmit state, the TX / RX switch 510 is set to transmit, the TX / RX connection 502 is coupled to the PA 508, and the signal from the transmitter (not shown) is coupled to the PA 508 via the TX / RX connection 502 and the TX / RX switch 510, and the PA 508 provides the amplified transmit signal to the radiating element 504. The transmission conditions correspond to the second row of truth table 600, where both the first VD LNA signal 512a and the second VD LNA signal 512b are at a "low" voltage level, and both the first VD PA signal 514a and the second VD PA signal 514b are at a "high" voltage level. Note that in truth table 600 in Figure 6, the "STBY*" state in the third row refers to a standby state where the radar or TR front-end element is off and a high-loss state is not required. In the STBY* state, the first VD LNA signal 512a, the second VD LNA signal 512b, the first VD PA signal 514a, and the second VD PA signal 514b are all at a "low" level. In certain embodiments, the "low" level in the truth table corresponds to an actual voltage level that is not high enough to turn on the respective amplifier.

[0036] Figure 7 is a sixth simplified circuit diagram 700 of a first amplifier (LNA706) and a first bias circuit 703 according to a first exemplary embodiment of the present disclosure. The LNA706 is similar to the prior art amplifier of Figure 1, but its first bias circuit 703 and the control of its first bias circuit 703 differ from the prior art described herein. This is because the first bias circuit 703 in Figure 7 consists of two control loops: the first control loop is configured to be tuned by a drain voltage VD (VD LNA712a) used as the drain voltage of LNA706, and the second control loop is tuned by the same signal (VD PA714a) applied to the drain voltage of PA708 (although details of PA708 itself are not shown in Figure 7, it should be noted that those skilled in the art will understand that in at least some embodiments PA708 may include one or more FET amplifiers controlled by the bias voltage VD PA714a, each FET amplifier having a drain electrode, a gate electrode, and a source electrode). The control loops and the remainder of Figure 7 will be described in more detail herein. In certain embodiments, the output signal of the first bias circuit 703 is supplied to the gate electrode of Q1 of LNA706 in Figure 7. As shown in Figure 7, the first control loop includes FETs Q6 and Q5, current source I1, a network of diodes D(n+1) to D(2n) (together forming the first level-shift network), and voltage VD LNA712a. As shown in Figure 7, the second control loop includes FETs Q4 and Q3, current source I2, a network of diodes D1 to Dn (together forming the second level-shift network), and voltage VD PA712a.

[0037] Furthermore, Figure 8 is a seventh simplified schematic diagram showing an alternative diode configuration via diode network 800, replacing the diode arrangement shown between nodes A, B, and C in Figure 7, according to a second exemplary embodiment of the present disclosure. The remainder of the bias circuit associated with the schematic of Figure 8 is not shown here because it is substantially the same as that of Figure 7 and operates similarly. Due to the difference in the arrangement of the diode network in Figure 8, the first and second control loops differ between Figure 8 and Figure 7. For example, replacing the diodes connected to nodes A, B, and C in Figure 7 with the diode network 800 in Figure 8 results in the first control loop in Figure 8, which includes a first level-shift network consisting of FETs Q6 and Q5, current source I1, diode D2 and common diodes D3-Dn, and voltage VD LNA712a. If we replace the diodes in Figure 7 with the diode network 800 in Figure 8, the second control loop includes a second level-shift network and voltage VD PA712a formed by FETs Q4 and Q3, current source I, diode D1, and common diodes D3-Dn. Therefore, in the following description, we will refer only to Figure 7, as the circuits in Figures 7 and 8 operate very similarly. We will only discuss differences that mainly relate to the diode network.

[0038] LNA operation and connection

[0039] Referring to Figure 7, in the "on" state, the RF amplifier LNA has a drain VD of Q1 that is enabled at a positive voltage (for example, +20[V] VD LNA712a as shown in Figure 7), and the gate of Q1 has a negative VG potential (for example, -2[V] as shown in Figure 7), providing a suitable quiescent bias for RF amplification (i.e., -2.0[V] for a d-mode GaN FET such as Q1). In some embodiments, a bias circuit similar to that described above in Figure 2 can be used to set a suitable quiescent gate bias voltage for LNA706. However, according to at least some embodiments of this specification, different improved bias circuits are provided, such as the first bias circuit 703 in Figure 7, or a second bias circuit using the diode network 800 in Figure 8 in the circuit of Figure 7, which not only sets a suitable quiescent gate bias voltage Vg for LNA706 but also provides LNA706 with two different RF conditions for LNA amplification, as will be further described below.

[0040] When the LNA706 amplifier is off, the drain voltage VD is set to 0[V], and VG of Q1 maintains a sufficiently negative voltage relative to the process pinch-off voltage, preventing conduction from the drain to the source of Q1 to ground. When the amplifier is off, setting the gate voltage VG to a sufficiently positive value relative to the process pinch-off voltage creates a low resistance between the drain and source of Q1, allowing conduction to ground, which increases the insertion loss per gain stage (RF input to RF output) and reduces the coupling potential to other components integrated into the system architecture. The magnitude of the "low" resistance varies depending on the environment in which the circuit is operating. In certain embodiments, the resistance between the drain and source electrodes is low enough to allow conduction to ground between the drain and source electrodes. This is further described in the details of the first and second control loops, which are further described herein.

[0041] To enable setting the gate voltage Vg of Q1 to a value sufficiently high relative to the process pinch-off voltage, each of the improved first bias circuit 703 in Figure 7 and the improved second bias circuit in Figure 8 (formed by replacing the diode network connected to nodes A, B, and C in Figure 7 with the diode network 800 in Figure 8) provides two control loops. The first control loop corresponds to the "on" state of LNA 706 and is used to set the quiescent bias of the amplifier when the quiescent voltage of VD LNA 712a is high (e.g., 20[V]) and the quiescent voltage of VD PA 714a is low (e.g., 0[V]), which corresponds to the Q1 amplifier in the "on" state of the LNA in truth table 600 (Figure 6). The second control loop, corresponding to the "off" state of the LNA706, is for setting the quiescent bias of the amplifier when the quiescent voltage of VD LNA712a is low (e.g., 0[V]) and the quiescent voltage of VD PA714a is high (e.g., 20[V]), which corresponds to conduction from the drain to the source of Q1 to ground (i.e., a high-loss state) in the "off" state of the LNA706.

[0042] A brief reference to the simplified diagram in Figure 5 and the truth table in Figure 6 shows that two VD control voltages (such as VD LNA512a and VD PA514a) are routed to LNA506 of the RF amplifier, and two VD control voltages (such as VD LNA512b and VD PA514b) are routed to PA508 of the RF amplifier. Note that in certain embodiments, VD LNA512a and VD PA514b are intended to have the same voltage value and be coupled to the same voltage source, such as a voltage source in the system in which the LNA and PA are installed. The same applies to VD PA514a and VD PA514b. As previously stated, the truth tables 600 for VD high / low and VD low / high applied to VD LNA on and VD PA off, respectively, form two different RF states based on this embodiment: LNA amplification and LNA high insertion loss.

[0043] Referring again to Figure 7, LNA706 is an RF amplifier that includes a depletion-mode (d-mode) transistor Q1, which has a source electrode coupled to a reference potential (here, ground) and a drain electrode coupled to VD LNA712a (note that this drain voltage is supplied from the same power source as the voltage signal of VD LNA712a connected to bias circuit 703 (and has the same value)). The drain voltage signal VD LNA712a is also coupled to PA708 as VD LNA712b (again, note that PA708 is not shown in detail in either Figure 7 or Figure 8). Furthermore, the drain voltage signal VD PA714a of PA708 is coupled to bias circuit 703 as VD PA714a and is also coupled to LNA706. The drain voltage signal of PA708 (VD PA714b) is also coupled to PA708. The drain electrode 736 of Q1 is coupled to a potential higher than the reference potential (here, +VD LNA712a) via a first inductor L2, as shown in the figure. The drain electrode of Q1 provides an RF output that is amplified after passing through a first capacitor 738. The gate electrode of Q1 is coupled to the input signal (here, the RF input) via a second capacitor 740, as shown in the figure. As shown in the figure, the source electrode of transistor Q1 is connected to ground, and a second inductor L1 is provided between the drain of Q1 and the gate voltage VG. As shown in Figure 7, the gate voltage VG varies depending on whether LNA706 is "on". For example, in a particular embodiment, when LNA706 is "on", VG is -2[V], and when LNA706 is "off", VG is +1[V] (where "on" and "off" are according to truth table 600 in Figure 6).

[0044] Bias circuits in Figures 7 and 8

[0045] As previously mentioned, the embodiment in Figure 7 provides a first embodiment of the first bias circuit 703, and Figure 8 provides a second embodiment of the second bias circuit via an alternative diode arrangement. These two bias circuits operate very similarly and have similar first and second control loops, but differ in their diode arrangement, which will be described in more detail herein. Each of the bias circuits in Figures 7 and 8 can also be used to bias other circuits other than the LNA 706. For example, in at least some embodiments, the bias circuit 703 can also be used to bias the PA 708. Furthermore, as will be described further herein in relation to Figures 9-10, the bias circuit 703 can be used to bias additional types of LNA amplifiers and many other types of amplifiers, including but not limited to cascode amplifier arrangements such as a common source / common gate (CS / CG) configuration.

[0046] The bias circuit 703 has two control loops to provide two different possible quiescent bias points to the LNA 706, depending on the values ​​of VD LNA 712a and VD PA 714a. Similarly, although not specifically shown in the figures, the two control loops also provide two different possible quiescent bias points to the PA 708, depending on the values ​​of VD LNA 712b and VD PA 714b. Furthermore, as will be further described herein, it is also possible to provide three or more control loops to provide multiple different quiescent bias points to the biased circuit (including, but not limited to, the LNA or PA). Although configurations with three or more control loops are not specifically shown in the figures, those skilled in the art will readily understand how such circuits are implemented based on the figures and description herein.

[0047] In certain embodiments, each bias circuit 703 utilizes existing supply voltages already available in the system, using those voltages not only as control voltages in the truth table 600 but also as voltages used to set the quiescent gate bias voltage. If the existing supply voltages in the system are not at an appropriate level for setting the quiescent bias voltage, a level shift via a network of diodes helps to ensure that the voltage at VG741 is at an appropriate level. Furthermore, although not shown herein, in certain embodiments, the level shift can also be achieved via a network of one or more resistors.

[0048] First control loop of bias circuit 703

[0049] The first control loop of bias circuit 703 is used to set the amplifier quiescent bias when the VD LNA quiescent voltage is high (e.g., 20[V]) and the VD PA quiescent voltage is low (e.g., 0[V]), which corresponds to the Q1 amplifier of LNA706 being in the "on" state. When VD LNA712a is "high", the TR element 500 (Figure 5) enters receive mode, the TX / RX switch 510 is set to the receive path, PA708 (and PA508 in Figure 5 as well) is turned off, and LNA706 (and LNA506 in Figure 5 as well) is turned on. In this state, the first control loop is configured to form a positive non-inverting current mirror with respect to Q1, although the different networks of diodes between the first bias circuit 703 and the second bias circuit in Figure 8 are coupled slightly differently and will be briefly described separately below.

[0050] In the first control loop, current is supplied to the drain electrode of Q5 from the first current source I1. Although not shown in Figure 7, those skilled in the art will understand that components such as resistors or other transistors can be used as constant current sources, and an example of such a constant current source configuration using a saturation resistor is described in U.S. Patent No. 8,854,140 (hereinafter, the "140 Patent"), which is incorporated herein by reference but is not limited thereto. When the VD LNA712a is 20[V], the first current source I1 operates to supply enough current to saturate the FET Q5, and the drain-to-source current (IDS_Q5) is substantially constant with respect to fluctuations in the voltage between the source and drain. Furthermore, in at least some embodiments, the current source may be a linear resistor or off-chip reference as needed.

[0051] In the first control loop, the gate electrode of FET Q5 is operably coupled to the gate electrodes of FET Q3 and FET Q1. However, as can be seen from the truth table in Figure 6, when FET Q5 is saturated (VD LNA712a = 20[V]), the drain of FET Q3 becomes 0[V], and since the second current source I2 does not supply current to the drain electrode of Q3, FET Q3 is not at the quiescent bias point. The current flowing through the drain electrode of Q5 via the connection from the gate electrode of Q5 to the gate electrode of Q1 is at least partially controlled by current I1. The source electrode of Q5 is directly connected to ground, as is the source electrode of Q1, which is advantageous for high-power and high-efficiency RF amplifiers.

[0052] In the first control loop, the drain electrode of Q5 is coupled to its gate electrode via two different follower networks: one for the first control loop and the other for the second control loop (which will be further described below in relation to the second control loop). When Q5 is saturated, the second control loop is not active and will not be described here, but will be described later. For the first control loop, the first drain follower network consists of FET Q6 and a specific diode configuration (which will be further described herein), the diode configurations which differ in Figures 7 and 8.

[0053] In the first control loop, the drain electrode of FET Q6 is coupled to VD LNA712a. The gate electrode of FET Q6 is coupled to the drain electrode of FET Q5 and also to the first current source I1. In Figure 7, the source electrode of Q6 is connected to the first end of the first network of diodes D(n+1)~D(2n), which itself is coupled (via L1) to the gate electrode of Q1, the drain electrode of load Q2, the gate electrode of Q3, and the gate electrode of Q5. In Figure 7, the gate electrode of Q5 is also coupled to the second end of the first network of diodes D(n+1)~D(2n) and also to the second end of the second network of diodes in the second control loop (i.e., diodes D1~Dn).

[0054] In the first control loop in Figure 8, the source electrode of Q6 is coupled to diode D2 at node A, and diode D2 itself is coupled to the first end of the third network of (shared) diodes D3-Dn, the gate electrode of Q3, the drain electrode of Q2, the gate electrode of G5, and the gate electrode of Q1 (via L1).

[0055] Second control loop of bias circuit 703

[0056] The second control loop of the bias circuit 703 is used to set the quiescent bias of the amplifier when VD LNA712a is low (e.g., 0[V]) and the quiescent voltage of VD PA714a is high (e.g., 20[V]), which corresponds to Q1 having drain-to-source (DS) conduction to ground (e.g., a high-loss state) when the LNA is in the "off" state. When VD PA714a is "high", the second TR element 500 (Figure 5) enters transmit mode, the TX / RX switch 510 is set to the transmit path, PA708 (and PA508 in Figure 5) turns on, and LNA706 (and LNA506 in Figure 5) does not turn on. In this state, the second control loop is configured to form a positive non-inverting current mirror with respect to Q1, but the different networks of diodes between the first bias circuit 703 and the second bias circuit in Figure 8 are coupled slightly differently and will be described separately below.

[0057] In the second control loop of the first bias circuit 703 in Figure 7, the combination of FET Q3, FET Q4, diodes D1~Dn, current source I2, FET Q2, and -Vss (lower than ground) forms a positive non-inverting current mirror with respect to FET Q1. In the second control loop of the second bias circuit in Figure 8, the combination of FET Q3, FET Q4, diode D1 and the shared third diode network D3~Dn, current source I2, FET Q2, and -Vss (negative than ground) forms a positive non-inverting current mirror with respect to FET Q1.

[0058] In both Figures 7 and 8, the drain electrode of Q3 is supplied with current from the second current source I2. As described above in relation to the first current source I1, in the case of the second current source I2, a component such as a resistor or another transistor can be used as a constant current source, as described in, for example, the '140 patent, but is not limited to this. When VD PA714a is 20[V], the second current source I2 operates to supply enough current to saturate FET Q3, and the drain-to-source current (IDS_Q3) becomes approximately constant with respect to fluctuations in the voltage between the source and drain. The gate electrode of FET Q3 is operably coupled to the gate electrode of FET Q5, but according to truth table 600 in Figure 6, when VD PA714a is 0[V], VD LNA712a is 0[V], and since the first current source I1 is not supplying current to the drain electrode of Q5, FET Q5 is not at the quiescent bias point.

[0059] The gate electrode of FET Q3 is also operably coupled to the gate electrode of Q1, and the current flowing through the drain electrode of Q3 is regulated, at least partially, by current I2. The source electrode of Q3, like the source electrode of Q1, is directly connected to ground, which is advantageous for high-power and high-efficiency RF amplifiers. Furthermore, the drain electrode of Q3 is coupled to the gate electrode via two different follower networks (one for the first control loop and the other for the second control loop) (the first control loop is not active when Q3 is saturated and will not be described here, but will be described elsewhere).

[0060] Use of diodes in each control loop of each bias circuit

[0061] For the first bias circuit 703 in Figure 7, the diode arrangement of the first control loop includes a network of first diodes, which includes multiple series-connected diodes (e.g., D(n+1) to D(2n)), where "n" corresponds to the number of second diodes in Figure 7, which will be further described below in relation to the second control loop. For example, if the second control loop in Figure 7 has five diodes D1 to D5 (n=5), the first control loop has diodes D6 to D10 (i.e., the same number n diodes). The number n of second diodes in the network of second diodes is proportional to the voltage required to set the quiescent bias of Q1.

[0062] For the first bias circuit 703 in Figure 7, the first control loop in Figure 7 utilizes a first network of diodes D(n+1)~D(2n) to assist in voltage level shifting and isolation. For example, if there is a problem or unexpected / undesirable signal related to Q5 and / or Q6, the first network of diodes D(n+1)~D(2n) helps prevent that undesirable and / or unexpected signal value from having an undesirable effect on Q4 and / or Q3. For the bias circuits in both Figures 7 and 8, in certain embodiments, other electrical components such as resistors may also be used to assist in providing voltage level shifting and / or isolation. Furthermore, depending on the application and / or the voltage present in the circuit, one or more diodes may be replaced with a short-circuit connection.

[0063] Regarding the second control loop of the first bias circuit 703 in Figure 7, the combination of FET Q3, FET Q4, the second network of diodes D1-Dn, current source I2, FET Q2, and -Vss (negative to ground) forms a positive non-inverting current mirror with respect to FET Q1. The second network of diodes D1-Dn provides level shifting and isolation (e.g., level shifting from VD LNA712a to the gate of Q1 and the drain of Q2). In particular, the first network of diodes D1-Dn helps to provide isolation between the first and second control loops. For example, if there is some problem or unexpected / undesirable signal value related to the elements of the second control loop (such as Q4 and / or Q3), the first network of diodes D1-Dn helps to prevent that unexpected / undesirable signal value from having an undesirable effect on Q5 and / or Q6.

[0064] In the first bias circuit 703 of Figure 7, for the second control loop, the second drain follower network includes FET Q4 (as will be further explained below), a network of the aforementioned series-connected second diodes (e.g., D1-Dn), and other series elements, here being the transistor load Q2 as shown. The number n of diodes in the second diode network is proportional to the required voltage. Thus, in Figure 7, when VD LNA712a is 0[V] (LNA706 is "off"), and when VD PA is 20[V] (PA708 is "on"), the gate electrode of FET Q3, together with the above follower network (e.g., follower Q4, the second diode network, and FET Q2), generates an output at node "N" (e.g., approximately +1[V]), which is supplied to the gate electrode of d-mode FET Q1. According to the second control loop in Figure 7, VD LNA712a is 0[V], VD PA714a is a positive voltage (e.g., 20[V]), and the gate electrode of Q1 has a positive potential (e.g., +1[V]). Therefore, Q1 has a suitable quiescent bias for the second state of high insertion loss of LNA706, and when LNA706 is in the "off" state, the conduction from drain to source of Q1 is grounded.

[0065] A bias circuit formed using the alternative diode arrangement in Figure 8 also provides level shifting and isolation through its diode network, but with a different diode configuration. In Figure 8, each of the first and second control loops has its own diodes for level shifting and isolation (for example, diode D2 for the first control loop and diode D1 for the second control loop), and each of the first and second control loops is coupled to a shared third diode network. In Figure 8, the diode arrangement of the first control loop includes diode D2 and a third network of shared diodes D3-Dn, where the number "n" of the third diodes D3 is proportional to the voltage required to set the quiescent bias 836 of Q1. In at least some embodiments, in either the second bias circuit or the first bias circuit 703 in Figure 8, one or more diodes may be replaced by short circuits, depending on the application and the voltages present in the circuit.

[0066] In the second control loop of Figure 8, the second drain follower network includes FET Q4, diode D1, a network including the above-mentioned third network of shared diodes (e.g., D1~Dn), and other series elements, here being the transistor load Q2 as shown. As described above, the number n of diodes in the third network of shared diodes is proportional to the required voltage. Thus, using the diode arrangement of Figure 8, when VD LNA712a is 0[V] (LNA706 is "off") and VD PA is 20[V] (PA708 is "on"), the gate electrode of FET Q3, together with the above-mentioned follower network (e.g., follower Q4, diode D1, the network of shared third diodes D3~Dn, and FET Q2), generates an output at node "N" (e.g., approximately +1[V]), which is supplied to the gate electrode of d-mode FET Q1.

[0067] According to the second control loop in Figure 8, VD LNA712a is 0[V], VD PA714a is a positive voltage (e.g., 20[V]), and the gate electrode of Q1 has a positive potential (e.g., +1[V]), so Q1 has a suitable quiescent bias for the second state of high insertion loss of LNA706, and when the LNA is in the "off" state, the conduction from drain to source of Q1 is grounded. Furthermore, in Figure 8, each of the first and second control loops is coupled to node N2, which is connected to the first end of a third network of shared diodes D3~Dn, which are coupled to node C, which is coupled to the gate of Q1 of LNA706 via inductor L1.

[0068] In the second bias circuit formed using the diode network in Figure 8, diodes D2 and D1 help provide isolation between the first control loop and the second control loop. For example, if there is any problem or unexpected / undesirable signal value related to Q4 and / or D1, diode D2 helps prevent that unexpected signal value from having an undesirable effect on Q5 and / or Q6. Similarly, if there is a problem or unexpected / undesirable signal related to Q6 and / or D2, diode D1 helps prevent that unexpected signal value from having an undesirable effect on Q4 and / or Q3. Thus, diodes D1 and D2 in Figure 8 help provide isolation between the first control loop and the second control loop.

[0069] Referring further to Figure 8, in the second control loop, the corresponding network of diodes formed by Q3, Q4, and D1, as well as the shared network of third diodes D3-Dn, the combination of current sources I2, Q2, and (lower than ground) -Vss, forms a positive non-inverting current mirror with respect to Q1. Diode D1, dedicated to the second control loop (and not shared with the first control loop) in Figure 8, is used for level shifting specific to and / or unique to the second control loop, and is also used to assist in isolation, as described above, together with the bias circuit 703 in Figure 7. In certain embodiments, one or more of the diodes shown in Figures 7 and 8 can be replaced with resistors. In certain embodiments, depending on the application and the voltage in the circuit, one or more of the diodes can be replaced with short circuits. Level shifts specific to and / or particular to the second control loop may relate to, for example, shifting the level of VD PA714a so that the second bias circuit and / or LNA706 in Figure 8 operate reliably according to the truth table 600 in Figure 6. For example, in a given system environment, the "high" and "low" levels of VD PA714a may be slightly too high for the proper operation of the LNA amplifiers 706 and / or PA708, and diode D1 in Figure 8 may be configured to provide a voltage level shift (such as a voltage drop) to help ensure proper operation.

[0070] Transistor loads for both the first and second control loops

[0071] In both Figures 7 and 8, each of the first and second control loops is also coupled to another series element, a transistor load Q2 as shown here. When VD LNA712a is 20[V] (LNa706 is "on") and VD PA is 0[V] (PA708 is "off"), the gate electrode of FET Q5, together with the follower network described above (i.e., follower Q6 and the corresponding diode of the second control loop), generates an output of approximately -2[V] at node N, which is supplied to the gate electrode of d-mode FET Q1. According to the first control loop, VD LNA712a is a positive voltage (e.g., 20[V]) and the gate electrode of Q1 has a negative potential (e.g., -2[V]), so Q1 has a suitable quiescent bias (e.g., -2[V] for a d-mode GaN FET like Q1) for the first condition of LNA amplification.

[0072] Output and insertion loss of a bias network

[0073] In both the bias networks of the exemplary embodiments shown in Figures 7 and 8, the output at node N is approximately +1[V]. However, in this state, the VD LNA712a supplied to the drain electrode of Q1 is 0[V], so the voltage at the gate electrode of Q1 is sufficiently positive with respect to the process pinch-off voltage (e.g., -2.5[V]), forming a low resistance between the drain and source of Q1, allowing conduction to ground, which increases the insertion loss per gain stage (RF input to RF output) and reduces the coupling potential to other components integrated into the system architecture. When the VGS voltage is sufficiently negative with respect to the pinch-off voltage, FET Q1 allows a virtually zero IDS current. This condition generates a very large resistance DS, but does not support a high-loss condition in itself.

[0074] Therefore, as described above, each of the first bias circuit 703 in Figure 7 and the second bias circuit using the alternative diode network 800 in Figure 8 provides a first quiescent bias for the ON state of LNA 706 via a first control loop and a second quiescent bias for the OFF state of LNA 706 via a second control loop to establish improved insertion loss. Thus, the first and second control loops are activated by the state of the drain voltage (VD LNA712a, VD PA714a) of the second TR element 500.

[0075] Although the configurations in Figures 5 to 8 described above are explained in relation to GaN applications, those skilled in the art will understand that these embodiments are also applicable to gallium arsenide (GaAs) applications. Furthermore, FETs are described here as MOS devices. In addition, although the circuits in Figures 5 to 8 are explained using depletion-mode GAN FETs, those skilled in the art will understand that all or part of the circuits in Figures 5 to 8 can be modified to operate using enhancement-mode FETs.

[0076] Furthermore, although not specifically shown in the drawings, those skilled in the art will understand that each of the bias circuits in Figures 7 and 8 can be composed of more control loops than the two control loops shown, and as a result, the truth table 600 in Figure 6 can reflect the control of the circuit state based on other voltages present in a given system, in addition to voltages VD LNA512a and VD PA514a. For example, each of the bias circuits in Figures 7 and 8 can also be modified to provide multiple different “first” and / or “second” control loops to control a system, each of which may be one of three or more states, so that one or more of the four circuit elements (e.g., amplifiers) can be turned “on” or “off” in response to four or more control voltages. For example, in certain embodiments, there may be multiple voltage input loops (control loops based on voltage inputs to the system’s amplifiers). In other words, in at least some embodiments, there can be three or more control loops as described herein.

[0077] The bias circuits in Figures 7 and 8 may, in certain embodiments, be adapted to operate over a range of input voltages different from the “high” and “low” conditions shown in the truth table of Figure 6. For example, in a system that may be in a “transmit” or “receive” state rather than being a radar front-end element, the system may have a range of input voltages that are all configured to switch a given amplifier “on” or “off” based on the output of the bias circuits in Figures 7 and 8.

[0078] Furthermore, as mentioned above, the bias circuits in Figures 7 and 8 can be used to bias many other types of circuits and amplifiers. For example, Figure 9 is an eighth simplified schematic 900 of a first alternative amplifier 907 that can be used with the exemplary bias circuits in Figures 5-8 according to one embodiment. The first alternative amplifier 907 is a cascode common source / common gate (CS / CG) gain stage that can receive Vg out 780 from the current mirror of the bias circuit 703.

[0079] The first alternative amplifier 907 includes a pair of FETs, such as a CS FET Q1 and a CG FET Q2, which are advantageously of equal gate width and are arranged as a cascode amplifier. Q1 and Q2 are connected in series between the first voltage source VD LN and ground potential. The input RF signal RF in is supplied to the gate of the CS FET via the first direct current (DC) blocking capacitor 911 and amplified by amplifier 907 to produce an output RF signal RF out from the drain of the CG FET Q2, which is supplied via a second DC blocking capacitor 938, as shown in Figure 9. Capacitor C1 is a bypass capacitor connected to the gate electrode of Q2. The first inductor L1 connected to the gate electrode of Q1 and the second inductor L2 connected to the drain electrode of Q2 prevent RF connection while allowing a DC connection between one Vg out 780 (bias input) and the other transistor Q. Resistors R2 and R1 form a voltage divider network to the gate electrode of Q2.

[0080] Figure 10 is a simplified circuit diagram 1000 of a second alternative amplifier 1007, usable with the exemplary bias circuits of Figures 5–8, according to one embodiment. The second alternative amplifier 1007 is similar to the first alternative amplifier 907 described above, except that resistors R2 and R1 form a so-called "Millman passive averager" circuit instead of resistors R1 and R2 forming the voltage divider network in Figure 9, which is described in detail in U.S. Patent No. 9,520,836, commonly granted, “Multistage Amplifier with Cascode Stage and DC Bias Regulator,” which is incorporated herein by reference. Thus, in Figure 10, resistor R1 is connected between the gate of Q2 and one end of inductor L1, whereas in Figure 9 R1 is connected to ground. The remainder of the circuit in Figure 10 is the same as the circuit in Figure 9.

[0081] Embodiments described herein are based on the following U.S. patents, published patent applications, and pending patent applications (some of which are commonly assigned): U.S. Patent No. 4,896,121, "Current Mirror For Depletion-mode Field Effect Transistor Technology," issued January 23, 1990; U.S. Patent No. 5,793,194, "Bias Circuit Having Process Variation Compensation And Power Supply Variation Compensation," issued August 11, 1998; U.S. Patent No. 5,889,429, "Semiconductor Integrated Circuit And Semiconductor Integrated Circuit Device," issued March 30, 1999; U.S. Patent No. 6,114,901, "Bias Stabilization Circuit," issued September 5, 2000; U.S. Patent No. 6,304,130, "Bias Circuit For Depletion Mode Field-effect Transistors," issued October 16, 2001; and U.S. Patent No. 7,852,136, "Bias "Network", issued December 14, 2010, U.S. Patent No. 7,928,804 "Power amplifier", issued April 19, 2011, U.S. Patent No. 8,854,140 "Current Mirror With Saturated Semiconductor Resistor", issued October 7, 2014, U.S. Patent No. 9,520,836 "Multi-Stage Amplifier with Cascode Stage and DC Bias Regulator", issued December 13, 2016, U.S. Patent No. 9,584,072 "DC Bias Regulator for Cascode Amplifier", issued February 28, 2017, U.S. Patent No. 9,634,613 "Bias Circuit Having Reduced Power Consumption", issued April 25, 2017, U.S. Patent No. 9,960,U.S. Patent No. 740 "Bias Circuitry for Depletion Mode Amplifiers," published May 1, 2018; U.S. Patent No. 10,277,176 "Bias Circuitry for Depletion Mode Amplifiers," published April 30, 2019; U.S. Patent No. 10,447,208 "Amplifier Having a Switchable Current Bias Circuit," published October 25, 2019; U.S. Patent No. 11,476,154 "Field Effect Transistor Having Improved Gate Structures," published October 18, 2022; U.S. Patent Application Publication No. 2007 / 0125414 "Thermoelectric Bias Voltage Generator," published June 17, 2007; and U.S. Patent Application No. 17 / 646,162 "Amplifier Bias This may be combined with one or more disclosures of "Circuit" filed December 28, 2021, all of which are incorporated herein by reference.

[0082] The terms “comprises,” “comprising,” “includes,” “including,” and “having,” and their variations, mean at least “including, but not limited to.” As used herein, the singular forms “a,” “an,” and “the” include the plural form unless the context clearly indicates otherwise. Various elements described in the context of a single embodiment may be provided separately or in any suitable sub-combination. Various modifications in the details, materials, and arrangement of the parts described and illustrated herein may be made by those skilled in the art without departing from the following claims.

[0083] The embodiments described herein are not limited to the specific terms thus selected, and each specific term includes at least all grammatical, literal, scientific, technical, and functional equivalents, as well as any other equivalents that operate in a similar manner to achieve a similar purpose. Furthermore, in the drawings, figures, and text, specific names may be given to certain features, elements, circuits, modules, etc. However, such terms used herein are for illustrative purposes only and not limiting.

[0084] While embodiments included herein are described and illustrated in a favorable manner with a particular degree of detail, this disclosure is provided merely as examples, and it should be understood that many modifications can be made to the details of the configuration and combination and arrangement of components without departing from the spirit and scope of the embodiments described herein. The technologies and embodiments disclosed herein can be used in combination with other technologies. Furthermore, all publications and references cited herein are expressly incorporated herein by reference in their entirety. Individual elements of different embodiments described herein can be combined to form other embodiments not specifically described herein. Various elements described in the context of a single embodiment may be provided separately or in any suitable partial combination. It should be understood that other embodiments not specifically described herein are also within the scope of the following claims.

Claims

1. A circuit, and said circuit is A first amplifier including a first output transistor, wherein the first output transistor includes a first source electrode, a first drain electrode, and a first gate electrode, A bias circuit that operably communicates with the first amplifier, the bias circuit is A first control loop configured to set a first quiescent bias of a first output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to turn the first output transistor "on", the first control loop A second control loop configured to set a second quiescent bias of the first output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the second quiescent bias is configured to put the first output transistor in an "off" state and increase the insertion loss of the first amplifier when the first output transistor is in the "off" state, The bias circuit includes, A circuit that includes this.

2. The circuit according to claim 1, wherein the bias circuit provides a first output signal based on at least one of the first control loop and the second control loop to the first gate electrode.

3. The circuit according to claim 2, wherein at least one of the first control loop and the second control loop further includes a first level shift network configured to provide a first level shift to the level of the first output signal.

4. The circuit according to claim 3, wherein the first level-shifting network includes at least one of a diode, a resistor, and a short-circuit connection.

5. The circuit according to claim 3, further comprising a second level-shifting network configured to be shared by both the first and second control loops, wherein the second level-shifting network is configured to provide a second level-shift to the level of the first output signal.

6. The circuit according to claim 5, wherein the second level-shifting network includes at least one of a diode, a resistor, and a short-circuit connection.

7. The aforementioned second static bias is, The voltage at the first gate electrode is set to a positive value relative to the pinch-off voltage of the first output transistor. The circuit according to claim 1, configured to form a resistance between the first drain electrode and the first source electrode that is low enough to allow conduction to ground between the first drain electrode and the first source electrode.

8. The circuit according to claim 1, wherein one of the first control voltage and the second control voltage is coupled to the first drain electrode of the first amplifier.

9. The circuit according to claim 1, wherein when the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop is configured to set the first quiescent bias and bring the first output transistor into the "on" state.

10. The circuit according to claim 1, wherein when the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop is configured to set the second quiescent bias to bring the first output transistor to the "off" state.

11. The circuit according to claim 1, wherein at least one of the first control loop and the second control loop further includes a diode network comprising at least one diode, the diode network configured to isolate at least a portion of the first control loop from the second control loop.

12. The second amplifier further includes a second output transistor, the second output transistor includes a second source electrode, a second drain electrode, and a second gate electrode. The bias circuit communicates operably with the second amplifier, The first control loop is configured to set a third quiescent bias of the second output transistor based on a first value of the first control voltage and a second value of the second control voltage, the third quiescent bias is configured to turn the second output transistor "off" and increase the insertion loss of the second amplifier when the second output transistor is in the "off" state. The circuit according to claim 1, wherein the second control loop is configured to set a fourth quiescent bias of the second output transistor based on a first value of the first control voltage and a second value of the second control voltage, the fourth quiescent bias is configured to turn the second output transistor "on".

13. The circuit according to claim 12, wherein the first control loop and the second control loop are configured such that when the first control voltage is at a logic high level and the second control voltage is at a logic low level, the first control loop sets a first quiescent bias to put the first output transistor in the "on" state, and the second control loop sets a third quiescent bias to put the second output transistor in the "off" state.

14. The circuit according to claim 12, wherein the first control loop and the second control loop are configured such that when the first control voltage is at a logic low level and the second control voltage is at a logic high level, the second control loop sets a first quiescent bias to put the first output transistor in the "off" state and sets a fourth quiescent bias to put the second output transistor in the "on" state.

15. The circuit according to claim 12, wherein the bias circuit provides a second output signal based on at least one of the first control loop and the second control loop to the second gate electrode.

16. The bias circuit includes a third control loop configured to set a third quiescent bias of the first output transistor based on a first value of the first control voltage, a second value of the second control voltage, and a third value of the third control voltage, wherein the third quiescent bias is configured to put the first output transistor into one of an "on" state and an "off" state, according to claim 1.

17. The circuit according to claim 1, wherein at least one of the first control loop and the second control loop includes a plurality of control loops.

18. The circuit according to claim 1, wherein at least one of the first control voltage and the second control voltage is associated with a range of voltage values.

19. A method, and said method is A step of providing a first amplifier including a first output transistor, wherein the first output transistor includes a first source electrode, a first drain electrode, and a first gate electrode. A step of operably connecting a bias circuit to the first amplifier, wherein the bias circuit is A first control loop configured to set a first quiescent bias of a first output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to turn the first output transistor "on", the first control loop A second control loop is configured to set a second quiescent bias of the first output transistor based on a first value of the first control voltage and a second value of the second control voltage, wherein the second quiescent bias is configured to put the first output transistor in an "off" state and increase the insertion loss of the first amplifier when the first output transistor is in the "off" state. Steps and A step of providing a first output signal to the first gate electrode, wherein the first output signal is based on at least one of the first control loop and the second control loop, Methods that include...

20. The steps include setting the voltage at the first gate electrode to a positive value relative to the pinch-off voltage of the first output transistor, The steps include forming a resistance between the first drain electrode and the first source electrode that is low enough to allow conduction to ground between the first drain electrode and the first source electrode, The method according to claim 19, further comprising:

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