Push-pull power amplification circuit and radio frequency front-end module

Abstract

The application discloses a push-pull power amplifier circuit and a radio frequency front end module. The push-pull power amplifier circuit comprises a first bias circuit, a second bias circuit, a first push-pull power amplifier branch, a second push-pull power amplifier branch and an impedance adjusting circuit. The output end of the first bias circuit is coupled to the input end of the first push-pull power amplifier branch. The output end of the second bias circuit is coupled to the input end of the second push-pull power amplifier branch. One end of the impedance adjusting circuit is coupled to the output end of the first bias circuit, and the other end of the impedance adjusting circuit is coupled to the output end of the second bias circuit. The technical scheme can improve the linearity of the push-pull power amplifier circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency amplification, and in particular to a push-pull power amplification circuit and a radio frequency front-end module. BACKGROUND

[0002] As a core unit in a communication system, the performance of the push-pull power amplification circuit has a great influence on the overall indicators of the communication system, especially the linearity and bandwidth characteristics of the push-pull power amplification circuit, which affect the overall performance of the entire communication system. In actual application, when the push-pull power amplification circuit amplifies the radio frequency input signal, distortion often occurs, so that the linearity of the push-pull power amplification circuit cannot meet the actual demand. SUMMARY

[0003] Embodiments of the present application provide a push-pull power amplification circuit and a radio frequency front-end module to solve the problem of poor linearity of the differential amplification circuit.

[0004] A push-pull power amplification circuit, comprising a first biasing circuit, a second biasing circuit, a first push-pull power amplification branch, a second push-pull power amplification branch and an impedance adjusting circuit;

[0005] The output end of the first biasing circuit is coupled to the input end of the first push-pull power amplification branch;

[0006] The output end of the second biasing circuit is coupled to the input end of the second push-pull power amplification branch;

[0007] One end of the impedance adjusting circuit is coupled to the output end of the first biasing circuit, and the other end of the impedance adjusting circuit is coupled to the output end of the second biasing circuit.

[0008] Further, the first biasing circuit comprises a first biasing transistor; the second biasing circuit comprises a second biasing transistor;

[0009] The first end of the first biasing transistor is connected to a first biasing signal port, the second end of the first biasing transistor is connected to a first power supply end, and the third end of the first biasing transistor is coupled to the input end of the first push-pull power amplification branch;

[0010] The first end of the second biasing transistor is connected to the second biasing signal port, the second end of the second biasing transistor is connected to the second power supply end, and the third end of the second biasing transistor is coupled to the input end of the second push-pull power amplification branch;

[0011] One end of the impedance adjusting circuit is coupled to the third end of the first biasing transistor, and the other end of the impedance adjusting circuit is coupled to the third end of the second biasing transistor.

[0012] Further, the first bias circuit further comprises a first voltage dividing unit; and the second bias circuit further comprises a second voltage dividing unit.

[0013] The first end of the first voltage dividing unit is connected to a common node of the first bias signal port and the first end of the first bias transistor, and the second end is connected to a ground terminal.

[0014] The first end of the second voltage dividing unit is connected to a common node of the second bias signal port and the first end of the second bias transistor, and the second end is connected to a ground terminal.

[0015] Further, the first bias circuit further comprises a first resistance; and the second bias circuit further comprises a second resistance.

[0016] The first end of the first resistance is connected to the third end of the first bias transistor, and the second end of the first resistance is connected to an input terminal coupled to the first push-pull power amplification branch.

[0017] The first end of the second resistance is connected to the third end of the second bias transistor, and the second end of the second resistance is connected to an input terminal coupled to the second push-pull power amplification branch.

[0018] One end of the impedance adjusting circuit is connected to the second end of the first resistance, and the other end of the impedance adjusting circuit is connected to the second end of the second resistance.

[0019] Further, the first resistance is an adjustable resistance; and the second resistance is an adjustable resistance.

[0020] Further, the impedance adjusting circuit comprises a first inductor or a first capacitor.

[0021] Further, the impedance adjusting circuit comprises a first inductor and a first capacitor, which are connected in parallel or in series.

[0022] Further, the first push-pull power amplification branch comprises a first power amplification transistor and a third resistance; and the second push-pull power amplification branch comprises a second power amplification transistor and a fourth resistance.

[0023] The first end of the third resistance is connected to the output terminal of the first bias circuit, the second end of the third resistance is connected to the first end of the first power amplification transistor, the second end of the first power amplification transistor is connected to a power supply terminal, and the third end of the first power amplification transistor is connected to a ground terminal.

[0024] The first end of the fourth resistor is connected with the output end of the second bias circuit, the second end of the fourth resistor is connected with the first end of the second power amplifier transistor, the second end of the second power amplifier transistor is connected with the power supply end, and the third end of the second power amplifier transistor is connected with the ground end.

[0025] Further, the push-pull power amplifier circuit comprises a conversion balun; a first input end of the conversion balun is connected with the signal input end, a second input end of the conversion balun is connected with the ground end, a first output end of the conversion balun is connected with the input end of the first push-pull power amplifier branch, and a second output end of the conversion balun is connected with the input end of the second push-pull power amplifier branch.

[0026] A radio frequency front-end module comprises the push-pull power amplifier circuit.

[0027] The push-pull power amplifier circuit and the radio frequency front-end module, the push-pull power amplifier circuit comprises a first bias circuit, a second bias circuit, a first push-pull power amplifier branch, a second push-pull power amplifier branch and an impedance adjustment circuit; the output end of the first bias circuit is coupled to the input end of the first push-pull power amplifier branch; the output end of the second bias circuit is coupled to the input end of the second push-pull power amplifier branch; one end of the impedance adjustment circuit is coupled to the output end of the first bias circuit, and the other end of the impedance adjustment circuit is coupled to the output end of the second bias circuit. By connecting the impedance adjustment circuit between the output end of the first bias circuit and the output end of the second bias circuit, the impedance of the bias circuit is substantially equivalent to the parallel impedance of the first bias circuit and the second bias circuit with respect to the first differential signal and the second differential signal, that is, the impedance of the bias circuit is reduced with respect to the first differential signal and the second differential signal. Therefore, as the power of the first differential signal and the power of the second differential signal increase, the signal from the input end of the first push-pull power amplifier branch entering the first bias circuit increases, and the signal from the input end of the second push-pull power amplifier branch entering the second bias circuit increases, so that the bias signal of the first push-pull power amplifier branch and the second push-pull power amplifier branch increases with the increase of the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplifier circuit. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0029] Figure 1 is a circuit schematic diagram of a push-pull power amplifier circuit in an embodiment of the present application;

[0030] Figure 2 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0031] Figure 3 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0032] Figure 4 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0033] Figure 5 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0034] Figure 6 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0035] Figure 7 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application;

[0036] Figure 8 is another circuit schematic diagram of the push-pull power amplification circuit in an embodiment of the present application.

[0037] In the figure: 10, first bias circuit; 11, first voltage dividing unit; 20, second bias circuit; 21, second voltage dividing unit; 30, first push-pull power amplification branch; 40, second push-pull power amplification branch; 50, impedance adjusting circuit; 60, conversion balun. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0039] It should be understood that the present application can be implemented in different forms and should not be interpreted as being limited to the embodiments presented here. On the contrary, these embodiments are provided to make the disclosure complete and full, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity throughout the same reference numerals represent the same elements.

[0040] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0041] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] For a thorough understanding of the present application, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0044] The embodiment provides a push-pull power amplifier circuit, as shown inFigure 1 As shown, the push-pull power amplification circuit includes a first bias circuit 10, a second bias circuit 20, a first push-pull power amplification branch 30, a second push-pull power amplification branch 40, and an impedance adjustment circuit 50. An output terminal of the first bias circuit 10 is coupled to an input terminal of the first push-pull power amplification branch 30. An output terminal of the second bias circuit 20 is coupled to an input terminal of the second push-pull power amplification branch 40. One end of the impedance adjustment circuit 50 is coupled to the output terminal of the first bias circuit 10, and the other end of the impedance adjustment circuit 50 is coupled to the output terminal of the second bias circuit 20.

[0045] In an embodiment, the push-pull power amplification circuit further includes an input conversion circuit configured to receive an unbalanced radio frequency input signal and convert the unbalanced radio frequency input signal into a balanced first differential signal and a balanced second differential signal. Optionally, as shown, the input conversion circuit includes a conversion balun 60. The first differential signal and the second differential signal are two signals of equal magnitude and opposite polarity. Figure 8

[0046] In an embodiment, the push-pull power amplification circuit includes a first push-pull power amplification branch 30 and a second push-pull power amplification branch 40. The first push-pull power amplification branch 30 is configured to receive the first differential signal and amplify the first differential signal. The second push-pull power amplification branch 40 is configured to receive the second differential signal and amplify the second differential signal.

[0047] Optionally, the first push-pull power amplification branch 30 includes a first power amplification transistor M31. The second push-pull power amplification branch 40 includes a second power amplification transistor M41. The first power amplification transistor M31 and the second power amplification transistor M41 can be BJT transistors or field effect transistors (FETs). Optionally, the second power amplification transistor M41 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. Exemplarily, the second power amplification transistor M41 can be a plurality of BJT transistors connected in parallel. The second power amplification transistor M41 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. Exemplarily, the second power amplification transistor M41 can be a plurality of BJT transistors connected in parallel.

[0048] In an embodiment, as shown, the push-pull power amplification circuit further includes a first impedance matching circuit 70 and a second impedance matching circuit 80. The first impedance matching circuit 70 is coupled to the first push-pull power amplification branch 30. The second impedance matching circuit 80 is coupled to the second push-pull power amplification branch 40. Figure 8 ​As shown, the base (gate) of the first power amplification transistor M31 is connected to the first output end of the conversion balun 60 through the first DC blocking capacitor C1, the collector (drain) of the first power amplification transistor M31 is connected to the power supply terminal VCC, and the emitter (source) of the first power amplification transistor M31 is connected to the ground terminal, so as to realize amplification of the first differential signal. The base (gate) of the second power amplification transistor M41 is connected to the second output end of the conversion balun 60 through the second DC blocking capacitor C2, the collector (drain) of the second power amplification transistor M41 is connected to the power supply terminal VCC, and the emitter (source) of the first power amplification transistor M31 is connected to the ground terminal, so as to realize amplification of the second differential signal.

[0049] In an embodiment, the push-pull power amplification circuit further comprises a first bias circuit 10 and a second bias circuit 20. The output end of the first bias circuit 10 is coupled to the input end of the first push-pull power amplification branch 30 and configured to provide a first bias signal to the first push-pull power amplification branch 30. The output end of the second bias circuit 20 is coupled to the input end of the second push-pull power amplification branch 40 and configured to provide a second bias signal to the second push-pull power amplification branch 40.

[0050] Optionally, the first push-pull power amplification circuit further comprises a third resistor R31; and the second push-pull power amplification branch 40 further comprises a fourth resistor R41.

[0051] In an embodiment, as shown in Figure 7 or Figure 8 The first end of the third resistor R31 is connected to the output end of the first bias circuit 10, and the second end of the third resistor R31 is connected to the first end of the first power amplification transistor M31, which is configured to provide overcurrent or overvoltage protection for the first power amplification transistor M31. The first end of the fourth resistor R41 is connected to the output end of the second bias circuit 20, and the second end of the fourth resistor R41 is connected to the first end of the second power amplification transistor M41, which is configured to provide overcurrent or overvoltage protection for the second power amplification transistor M41.

[0052] In an embodiment, the push-pull power amplification circuit further comprises an impedance adjustment circuit 50, which is configured to adjust the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20.

[0053] In a specific embodiment, by coupling the first bias circuit 10 to the input end of the first push-pull power amplification branch 30, coupling the second bias circuit 20 to the input end of the second push-pull power amplification branch 40, and by coupling one end of the impedance adjustment circuit 50 to the output end of the first bias circuit 10 and the other end of the impedance adjustment circuit 50 to the output end of the second bias circuit 20, the impedance adjustment circuit 50 can make the impedance of the bias circuit substantially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20, i.e. the impedance of the bias circuit is reduced with respect to the first differential signal input to the input end of the first push-pull power amplification branch 30 and the second differential signal input to the input end of the second push-pull power amplification branch 40, thus, as the power of the first differential signal and the power of the second differential signal increase, the signal from the input end of the first push-pull power amplification branch 30 into the first bias circuit 10 increases, and the signal from the input end of the second push-pull power amplification branch 40 into the second bias circuit 20 increases, thus resulting in the bias signal of the first push-pull power amplification branch 30 and the second push-pull power amplification branch 40 increasing with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplification circuit. It should be noted that, since the first differential signal and the second differential signal are equal in size and opposite in polarity, the impedance adjustment circuit 50 has a certain impedance with respect to the first differential signal and the second differential signal, and the impedance adjustment circuit 50 not only avoids the mutual cancellation of the first differential signal and the second differential signal, but also reduces the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20, and the impedance of the impedance adjustment circuit 50 is configured according to actual needs.

[0054] In this embodiment, the push-pull power amplifier circuit includes a first bias circuit 10, a second bias circuit 20, a first push-pull power amplifier branch 30, a second push-pull power amplifier branch 40, and an impedance adjustment circuit 50. The output terminal of the first bias circuit 10 is coupled to the input terminal of the first push-pull power amplifier branch 30; the output terminal of the second bias circuit 20 is coupled to the input terminal of the second push-pull power amplifier branch 40; one end of the impedance adjustment circuit 50 is coupled to the output terminal of the first bias circuit 10, and the other end of the impedance adjustment circuit 50 is coupled to the output terminal of the second bias circuit 20. Thus, the first differential signal input to the input terminal of the first push-pull power amplifier branch 30 and the first differential signal input to the second push-pull power amplifier branch 40 are coupled to the first differential signal input to the input terminal of the first push-pull power amplifier branch 30 and the second ..., respectively. The impedance of the bias circuit is essentially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20, which means that the impedance of the bias circuit is reduced relative to the first differential signal and the second differential signal. Therefore, as the power of the first differential signal and the second differential signal increases, the signal entering the first bias circuit 10 from the input terminal of the first push-pull power amplifier branch 30 increases, and the signal entering the second bias circuit 20 from the input terminal of the second push-pull power amplifier branch 40 increases. This causes the bias signals of the first push-pull power amplifier branch 30 and the second push-pull power amplifier branch 40 to increase with the increase of input power, thereby achieving the purpose of improving the linearity of the push-pull power amplifier circuit.

[0055] In one embodiment, such as Figure 3 As shown, the first bias circuit 10 includes a first bias transistor M11; the second bias circuit 20 includes a second bias transistor M21; the first terminal of the first bias transistor M11 is connected to the first bias signal port A, the second terminal of the first bias transistor M11 is connected to the first power supply terminal VCC1, and the third terminal of the first bias transistor M11 is coupled to the input terminal of the first push-pull power amplifier branch 30; the first terminal of the second bias transistor M21 is connected to the second bias signal port B, the second terminal of the second bias transistor M21 is connected to the second power supply terminal VCC2, and the third terminal of the second bias transistor M21 is coupled to the input terminal of the second push-pull power amplifier branch 40; one end of the impedance adjustment circuit 50 is coupled to the third terminal of the first bias transistor M11, and the other end of the impedance adjustment circuit 50 is coupled to the third terminal of the second bias transistor M21.

[0056] The first bias transistor M11 and the second bias transistor M21 can be BJT transistors (e.g., HBT transistors) or field-effect transistors. The first bias signal port A is configured to receive a first initial bias signal. The second bias signal port B is configured to receive a second initial bias signal.

[0057] In an embodiment, the first biasing circuit 10 comprises a first biasing signal source S1, and the second biasing circuit 20 comprises a second biasing signal source S2. Optionally, the first biasing signal source S1 can be a current source or a voltage source. The second biasing signal source S2 can be a current source or a voltage source. As an example, the first biasing signal source S1 is connected to the first biasing signal port A and configured to input a first initial biasing signal to the first biasing signal port A. The second biasing signal source S2 is connected to the second biasing signal port B and configured to input a second initial biasing signal to the second biasing signal port B.

[0058] In an embodiment, the base (gate) of the first biasing transistor M11 is connected to the first biasing signal port A, the collector (drain) of the first biasing transistor M11 is connected to the first power supply terminal VCC1, and the emitter (source) of the first biasing transistor M11 is coupled to the input terminal of the first push-pull power amplification branch 30. The first biasing transistor M11 receives the first initial biasing signal input by the first biasing signal port A, amplifies the first initial biasing signal, and outputs a first biasing signal to the first push-pull power amplification circuit. The base (gate) of the second biasing transistor M21 is connected to the second biasing signal port B, the collector (drain) of the second biasing transistor M21 is connected to the second power supply terminal VCC2, and the emitter (source) of the second biasing transistor M21 is coupled to the input terminal of the second push-pull power amplification branch 40. The second biasing transistor M21 receives the second initial biasing signal input by the second biasing signal port B, amplifies the second initial biasing signal, and outputs a second biasing signal to the second push-pull power amplification circuit.

[0059] In an embodiment, one end of the impedance adjusting circuit 50 is coupled to the emitter (source) of the first biasing transistor M11, and the other end of the impedance adjusting circuit 50 is coupled to the emitter (source) of the second biasing transistor M21. The impedance adjusting circuit 50 can make the impedance of the biasing circuit substantially equivalent to the parallel impedance of the first biasing circuit 10 and the second biasing circuit 20. That is, the impedance of the biasing circuit is reduced with respect to the first differential signal input to the input terminal of the first push-pull power amplification branch 30 and the second differential signal input to the input terminal of the second push-pull power amplification branch 40. Therefore, as the power of the first differential signal and the power of the second differential signal increase, the signal from the input terminal of the first push-pull power amplification branch 30 entering the first biasing circuit 10 increases, and the signal from the input terminal of the second push-pull power amplification branch 40 entering the second biasing circuit 20 increases. As a result, the biasing signal of the first push-pull power amplification branch 30 and the second push-pull power amplification branch 40 increases with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplification circuit.

[0060] In this embodiment, the first bias circuit 10 includes a first bias transistor M11; the second bias circuit 20 includes a second bias transistor M21; the first terminal of the first bias transistor M11 is connected to the first bias signal port A, the second terminal of the first bias transistor M11 is connected to the first power supply terminal VCC1, and the third terminal of the first bias transistor M11 is coupled to the input terminal of the first push-pull power amplifier branch 30; the first terminal of the second bias transistor M21 is connected to the second bias signal port B, the second terminal of the second bias transistor M21 is connected to the second power supply terminal VCC2, and the third terminal of the second bias transistor M21 is coupled to the input terminal of the second push-pull power amplifier branch 40; one end of the impedance adjustment circuit 50 is coupled to the third terminal of the first bias transistor M11, and the other end of the impedance adjustment circuit 50 is coupled to the third terminal of the second bias transistor M21, as shown below. Therefore, relative to the first differential signal and the second differential signal, the impedance of the bias circuit is essentially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20. That is, relative to the first differential signal input to the input terminal of the first push-pull power amplifier branch 30 and the second differential signal input to the input terminal of the second push-pull power amplifier branch 40, the impedance of the bias circuit is reduced. Therefore, as the power of the first differential signal and the power of the second differential signal increase, the signal entering the first bias circuit 10 from the input terminal of the first push-pull power amplifier branch 30 increases, and the signal entering the second bias circuit 20 from the input terminal of the second push-pull power amplifier branch 40 increases. This causes the bias signals of the first push-pull power amplifier branch 30 and the second push-pull power amplifier branch 40 to increase with the increase of input power, thereby achieving the purpose of improving the linearity of the push-pull power amplifier circuit.

[0061] In one embodiment, such as Figure 4 As shown, the first bias circuit 10 further includes a first voltage divider unit 11; the second bias circuit 20 further includes a second voltage divider unit 21; the first end of the first voltage divider unit 11 is connected to the common node of the first bias signal port A and the first end of the first bias transistor M11, and the second end is connected to the ground terminal; the first end of the second voltage divider unit 21 is connected to the common node of the second bias signal port B and the first end of the second bias transistor M21, and the second end is connected to the ground terminal.

[0062] In an embodiment, the first bias circuit 10 further comprises a first voltage dividing unit 11, a first end of the first voltage dividing unit 11 is connected to a common node of the first bias signal port A and a first end of the first bias transistor M11, and a second end of the first voltage dividing unit 11 is connected to a ground terminal. Optionally, the first voltage dividing unit 11 comprises a first voltage dividing transistor D11 and a second voltage dividing transistor D12 connected in series. As an example, a first end of the first voltage dividing transistor D11 is connected to the common node of the first bias signal port A and the first end of the first bias transistor M11, a second end of the first voltage dividing transistor D11 is connected to a first end of the second voltage dividing transistor D12, and a second end of the second voltage dividing transistor D12 is connected to the ground terminal. The first voltage dividing unit 11 can stabilize the static working point of the first bias signal. It should be noted that, in addition to the embodiment, the first voltage dividing transistor D11 and the second voltage dividing transistor D12 can be diodes, and can also be replaced by transistors.

[0063] In an embodiment, the second bias circuit 20 further comprises a second voltage dividing unit 21, a first end of the second voltage dividing unit 21 is connected to a common node of the second bias signal port B and a first end of the second bias transistor M21, and a second end of the second voltage dividing unit 21 is connected to a ground terminal. Optionally, the second voltage dividing unit 21 comprises a third voltage dividing transistor D21 and a fourth voltage dividing transistor D22 connected in series. As an example, a first end of the third voltage dividing transistor D21 is connected to the common node of the first bias signal port A and the first end of the first bias transistor M11, a second end of the third voltage dividing transistor D21 is connected to a first end of the fourth voltage dividing transistor D22, and a second end of the fourth voltage dividing transistor D22 is connected to the ground terminal. The second voltage dividing unit 21 can stabilize the static working point of the second bias signal. It should be noted that, in addition to the embodiment, the third voltage dividing transistor D21 and the fourth voltage dividing transistor D22 can be diodes, and can also be replaced by transistors.

[0064] In the embodiment, the first bias circuit 10 further comprises a first voltage dividing unit 11, the second bias circuit 20 further comprises a second voltage dividing unit 21, a first end of the first voltage dividing unit 11 is connected to a common node of the first bias signal port A and a first end of the first bias transistor M11, and a second end of the first voltage dividing unit 11 is connected to a ground terminal, a first end of the second voltage dividing unit 21 is connected to a common node of the second bias signal port B and a first end of the second bias transistor M21, and a second end of the second voltage dividing unit 21 is connected to a ground terminal, thereby stabilizing the static working points of the first bias signal and the second bias signal.

[0065] In an embodiment, as Figure 3As shown, the first bias circuit 10 further comprises a first resistor R11, and the second bias circuit 20 further comprises a second resistor R21. A first end of the first resistor R11 is connected to a third end of the first bias transistor M11, and a second end of the first resistor R11 is connected to an input end of the first push-pull power amplifier branch 30. A first end of the second resistor R21 is connected to a third end of the second bias transistor M21, and a second end of the second resistor R21 is connected to an input end of the second push-pull power amplifier branch 40. One end of the impedance adjusting circuit 50 is connected to the second end of the first resistor R11, and the other end of the impedance adjusting circuit 50 is connected to the second end of the second resistor R21.

[0066] In an embodiment, the first bias circuit 10 further comprises a first resistor R11, a first end of the first resistor R11 is connected to an emitter (source) of the first bias transistor M11, and a second end of the first resistor R11 is connected to an input end of the first push-pull power amplifier branch 30. The first resistor R11 is configured to couple a first bias signal output by the first bias circuit 10 to the first push-pull power amplifier branch 30.

[0067] In an embodiment, the second bias circuit 20 further comprises a second resistor R21, a second end of the first resistor R11 is connected to an input end of the first push-pull power amplifier branch 30, a first end of the second resistor R21 is connected to an emitter (source) of the second bias transistor M21, and a second end of the second resistor R21 is connected to an input end of the second push-pull power amplifier branch 40. The second resistor R21 is configured to couple a second bias signal output by the second bias circuit 20 to the second push-pull power amplifier branch 40.

[0068] Optionally, the first resistor R11 and the second resistor R21 are adjustable resistors, and the resistance values of the first resistor R11 and the second resistor R21 can be adjusted according to actual requirements.

[0069] In the embodiment, one end of the impedance adjusting circuit 50 is connected to the second end of the first resistor R11, and the other end of the impedance adjusting circuit 50 is connected to the second end of the second resistor R21. In this way, the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20 can be reduced, so that the amplitude of the first bias signal output by the first bias circuit 10 and the amplitude of the second bias signal output by the second bias circuit 20 can be increased, and the linearity of the push-pull power amplifier circuit can be improved.

[0070] In an embodiment, the impedance adjusting circuit 50 comprises a first inductor L51 or a first capacitor C51.

[0071] In an embodiment, as shown in FIG. 2, the impedance adjusting circuit 50 comprises a first inductor L51, and the first inductor L51 is connected in series with the first resistor R11 and the second resistor R21. Figure 3As shown, the impedance adjusting circuit 50 comprises a first inductor L51. By coupling a first end of the first inductor L51 to the output end of the first bias circuit 10 and coupling a second end of the first inductor L51 to the output end of the second bias circuit 20, the impedance of the bias circuit is substantially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20 with respect to the first differential signal input to the input end of the first push-pull power amplification branch 30 and the second differential signal input to the input end of the second push-pull power amplification branch 40, i.e. the impedance of the bias circuit is reduced with respect to the first differential signal and the second differential signal. Therefore, as the power of the first differential signal and the power of the second differential signal increase, the signal from the input end of the first push-pull power amplification branch 30 into the first bias circuit 10 and the signal from the input end of the second push-pull power amplification branch 40 into the second bias circuit 20 increase, so as to cause the bias signal of the first push-pull power amplification branch 30 and the second push-pull power amplification branch 40 to increase with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplification circuit. It should be noted that, since the first inductor L51 has a certain impedance value, the first inductor L51 can avoid the first differential signal and the second differential signal from canceling each other out and can reduce the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20. Alternatively, the impedance value of the first inductor L51 can be adjusted to adjust the impedance value of the first inductor L51. For example, the inductance value of the first inductor L51 is 1.5nH, and the inductance value of the first inductor L51 can be selected according to actual needs.

[0072] In a specific embodiment, as Figure 4As shown, the impedance adjusting circuit 50 includes a first capacitor C51, by coupling a first end of the first capacitor C51 to the output end of the first bias circuit 10 and coupling a second end of the first capacitor C51 to the output end of the second bias circuit 20, the impedance of the bias circuit is substantially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20, i.e. the impedance of the bias circuit is reduced with respect to the first differential signal input to the input end of the first push-pull power amplifier branch 30 and the second differential signal input to the input end of the second push-pull power amplifier branch 40, thus, as the power of the first differential signal and the power of the second differential signal increase, the signal from the input end of the first push-pull power amplifier branch 30 into the first bias circuit 10 increases and the signal from the input end of the second push-pull power amplifier branch 40 into the second bias circuit 20 increases, so as to cause the bias signal of the first push-pull power amplifier branch 30 and the second push-pull power amplifier branch 40 to increase with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplifier circuit. It should be noted that, since the first capacitor C51 has a certain impedance value, the first capacitor C51 can avoid the mutual cancellation of the first differential signal and the second differential signal, and can reduce the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20. Alternatively, the impedance presented by the first inductor L51 can be adjusted by adjusting the capacitance value of the first capacitor C51, and the capacitance value of the first capacitor C51 can be selected according to actual needs.

[0073] In the embodiment, the impedance adjusting circuit 50 includes the first inductor L51 or the first capacitor C51, by coupling one end of the first inductor L51 or the first capacitor C51 to the output end of the first bias circuit 10 and coupling the other end to the output end of the second bias circuit 20, the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20 can be reduced, thereby increasing the amplitude of the first bias signal output by the first bias circuit 10 and the amplitude of the second bias signal output by the second bias circuit 20, to achieve the purpose of improving the linearity of the push-pull power amplifier circuit.

[0074] In an embodiment, the impedance adjusting circuit 50 further includes the first inductor L51 and the first capacitor C51, and the first inductor L51 and the first capacitor C51 are connected in parallel; or, the first inductor L51 and the first capacitor C51 are connected in series.

[0075] In a specific embodiment, as shown in FIG. 2, the impedance adjusting circuit 50 includes the first inductor L51 and the first capacitor C51, and the first inductor L51 and the first capacitor C51 are connected in parallel. Figure 5As shown, the impedance adjusting circuit 50 further comprises a first inductor L51 and a first capacitor C51, which are connected in parallel between the output of the first bias circuit 10 and the output of the second bias circuit 20. By configuring the inductance value of the first inductor L51 and the capacitance value of the first capacitor C51, not only can the first differential signal and the second differential signal be avoided from canceling each other, but also the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20 can be reduced.

[0076] In a specific embodiment, as shown in Figure 6 As shown, the impedance adjusting circuit 50 further comprises a first inductor L51 and a first capacitor C51, which are connected in series between the output of the first bias circuit 10 and the output of the second bias circuit 20. By configuring the inductance value of the first inductor L51 and the capacitance value of the first capacitor C51, not only can the first differential signal and the second differential signal be avoided from canceling each other, but also the impedance of the first bias circuit 10 and the impedance of the second bias circuit 20 can be reduced.

[0077] In the embodiment, the impedance adjusting circuit 50 further comprises a first inductor L51 and a first capacitor C51, which are connected in parallel or in series. Both of them can make the impedance of the bias circuit substantially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20, i.e. the impedance of the bias circuit is reduced with respect to the first differential signal and the second differential signal. Therefore, as the power of the first differential signal and the power of the second differential signal increase, the signal entering the first bias circuit 10 from the input of the first push-pull power amplification branch 30 increases, and the signal entering the second bias circuit 20 from the input of the second push-pull power amplification branch 40 increases, so that the bias signal of the first push-pull power amplification branch 30 and the second push-pull power amplification branch 40 increases with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplification circuit.

[0078] In an embodiment, as shown in Figure 8 The push-pull power amplification circuit comprises a conversion balun 60. The first input of the conversion balun 60 is connected to the signal input, the second input of the conversion balun 60 is connected to the ground, the first output of the conversion balun 60 is connected to the input of the first push-pull power amplification branch 30, and the second output of the conversion balun 60 is connected to the input of the second push-pull power amplification branch 40.

[0079] In the embodiment, the first input terminal of the conversion balun 60 is connected with the signal input terminal, the second input terminal of the conversion balun 60 is connected with the ground terminal, the first output terminal of the conversion balun 60 is connected with the input terminal of the first push-pull power amplifier branch 30, and the second output terminal of the conversion balun 60 is connected with the input terminal of the second push-pull power amplifier branch 40. The input conversion circuit is configured to receive an unbalanced radio frequency input signal and convert the unbalanced radio frequency input signal into a balanced first differential signal and a balanced second differential signal.

[0080] The embodiment provides a radio frequency front-end module, which comprises the push-pull power amplifier circuit in the above embodiment. The push-pull power amplifier circuit comprises a first bias circuit 10, a second bias circuit 20, a first push-pull power amplifier branch 30, a second push-pull power amplifier branch 40 and an impedance adjustment circuit 50. The output terminal of the first bias circuit 10 is coupled to the input terminal of the first push-pull power amplifier branch 30. The output terminal of the second bias circuit 20 is coupled to the input terminal of the second push-pull power amplifier branch 40. One end of the impedance adjustment circuit 50 is coupled to the output terminal of the first bias circuit 10, and the other end of the impedance adjustment circuit 50 is coupled to the output terminal of the second bias circuit 20. Compared with directly coupling the first bias circuit 10 to the first push-pull power amplifier branch 30 and coupling the second bias circuit 20 to the second push-pull power amplifier branch 40, the impedance adjustment circuit 50 can make the impedance of the bias circuit substantially equivalent to the parallel impedance of the first bias circuit 10 and the second bias circuit 20, that is, the impedance of the bias circuit is reduced with respect to the first differential signal and the second differential signal. Therefore, as the first differential signal power and the second differential signal power increase, the signal from the input terminal of the first push-pull power amplifier branch 30 entering the first bias circuit 10 increases, and the signal from the input terminal of the second push-pull power amplifier branch 40 entering the second bias circuit 20 increases, so that the bias signal of the first push-pull power amplifier branch 30 and the second push-pull power amplifier branch 40 increases with the input power, thereby achieving the purpose of improving the linearity of the push-pull power amplifier circuit.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A push-pull power amplifier circuit, characterized in that, It includes a first bias circuit, a second bias circuit, a first push-pull power amplifier branch, a second push-pull power amplifier branch, and an impedance adjustment circuit. The first bias circuit includes a first bias transistor, and the second bias circuit includes a second bias transistor. The first terminal of the first bias transistor is connected to the first bias signal port, the second terminal of the first bias transistor is connected to the first power supply terminal, and the third terminal of the first bias transistor is coupled to the input terminal of the first push-pull power amplifier branch. The first push-pull power amplifier branch is configured to receive the first differential signal and amplify the first differential signal. The first terminal of the second bias transistor is connected to the second bias signal port, the second terminal of the second bias transistor is connected to the second power supply terminal, and the third terminal of the second bias transistor is coupled to the input terminal of the second push-pull power amplifier branch. The second push-pull power amplifier branch is configured to receive the second differential signal and amplify the second differential signal. One end of the impedance adjustment circuit is coupled to the third terminal of the first bias transistor, and the other end of the impedance adjustment circuit is coupled to the third terminal of the second bias transistor. The first differential signal and the second differential signal are two signals of equal magnitude and opposite polarity. The impedance adjustment circuit is configured to prevent the first differential signal and the second differential signal from canceling each other out and to adjust the impedance of the first bias circuit and the second bias circuit so that the impedance of the bias circuit is equivalent to the parallel impedance of the first bias circuit and the second bias circuit.

2. The push-pull power amplifier circuit as described in claim 1, characterized in that, The first bias circuit further includes a first voltage divider unit; the second bias circuit further includes a second voltage divider unit. The first end of the first voltage divider unit is connected to the common node of the first bias signal port and the first end of the first bias transistor, and the second end is connected to the ground terminal. The first end of the second voltage divider unit is connected to the common node of the second bias signal port and the first end of the second bias transistor, and the second end is connected to the ground terminal.

3. The push-pull power amplifier circuit as described in claim 1, characterized in that, The first bias circuit further includes a first resistor; the second bias circuit further includes a second resistor; The first end of the first resistor is connected to the third end of the first bias transistor, and the second end of the first resistor is coupled to the input end of the first push-pull power amplifier branch. The first end of the second resistor is connected to the third end of the second bias transistor, and the second end of the second resistor is coupled to the input end of the second push-pull power amplifier branch. One end of the impedance adjustment circuit is coupled to the second end of the first resistor, and the other end of the impedance adjustment circuit is coupled to the second end of the second resistor.

4. The push-pull power amplifier circuit as described in claim 3, characterized in that, The first resistor is an adjustable resistor; the second resistor is an adjustable resistor.

5. The push-pull power amplifier circuit as described in claim 1, characterized in that, The impedance adjustment circuit includes a first inductor or a first capacitor.

6. The push-pull power amplifier circuit as described in claim 1, characterized in that, The impedance adjustment circuit includes a first inductor and a first capacitor, which are connected in parallel; or, the first inductor and the first capacitor are connected in series.

7. The push-pull power amplifier circuit as described in claim 1, characterized in that, The first push-pull power amplifier branch includes a first power amplifier transistor and a third resistor; the second push-pull power amplifier branch includes a second power amplifier transistor and a fourth resistor; The first end of the third resistor is connected to the output end of the first bias circuit, the second end of the third resistor is connected to the first end of the first power amplifier transistor, the second end of the first power amplifier transistor is connected to the power supply end, and the third end of the first power amplifier transistor is connected to the ground end. The first end of the fourth resistor is connected to the output terminal of the second bias circuit, the second end of the fourth resistor is connected to the first end of the second power amplifier transistor, the second end of the second power amplifier transistor is connected to the power supply terminal, and the third end of the second power amplifier transistor is connected to the ground terminal.

8. The push-pull power amplifier circuit as described in claim 1, characterized in that, The push-pull power amplifier circuit includes a conversion balun; the first input terminal of the conversion balun is connected to the signal input terminal, the second input terminal of the conversion balun is connected to the ground terminal, the first output terminal of the conversion balun is connected to the input terminal of the first push-pull power amplifier branch, and the second output terminal of the conversion balun is connected to the input terminal of the second push-pull power amplifier branch.

9. A radio frequency front-end module, characterized in that, Includes the push-pull power amplifier circuit as described in any one of claims 1 to 8.

Images