Memory devices, memory systems, and methods for data computation using memory devices

Abstract

A memory device, a memory system, and a method for data computation using the memory device are provided. The memory device includes an array of memory cells, and peripheral circuits coupled to the memory cells are provided. The peripheral circuits include a page buffer configured to store first data transmitted from the data interface of the memory device and to sense second data from the array of memory cells. The peripheral circuits further include at least one processing unit coupled to the page buffer via the peripheral circuits' data path bus and configured to perform computations based on the first and second data. The peripheral circuits further include control logic configured to program the second data into the array of memory cells.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a memory system, and a method for data calculation using the memory device.

Background Art

[0002] The inference of generative artificial intelligence (AI) involves AI calculations. For example, a transformer model typically uses a tensor processing unit (TPU) and memory for calculations. Large-scale transformer models require large amounts of data and calculations, which require large amounts of power consumption and sufficient memory. If the memory access speed is slower than the calculation speed of the processor, the memory bottleneck will prevent the effective operation of high-performance processors and become a major constraint on high-performance computing (HPC). This problem is called the memory wall. To further improve the performance of AI systems, it is desirable to break through the memory wall.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a memory device is provided that includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a page buffer configured to store first data transmitted from a data interface of the memory device and to detect second data from the array of memory cells. The peripheral circuits further include at least one processing unit coupled to the page buffer via a data path bus of the peripheral circuits and configured to perform calculations based on the first data and the second data. The peripheral circuits further include control logic configured to program the second data to the array of memory cells.

[0004] In some implementations, the first data includes at least one row. The control logic is further configured to control the page buffer to receive each row of the first data based on the first data pattern.

[0005] In some implementations, the first data pattern contains N first data segments of equal length, where N is a positive integer and N ≥ 2, and the sequence of N first data segments in the first data pattern is the same as the sequence of the first data.

[0006] Furthermore, every two adjacent first data segments of the first data pattern are separated by M first empty segments, where M is a positive integer and M ≥ 2.

[0007] In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

[0008] In some implementations, the second data contains M columns. The control logic is further configured to program each column of the second data into the memory cell based on the second data pattern.

[0009] In some implementations, the control logic is further configured to program a second data into the memory cell in single-level memory cell (SLC) mode.

[0010] In some implementations, the second data pattern contains N data groups, each having M second data segments of equal length from M columns of the second data. Any two adjacent data groups of the N data groups in the second data pattern are separated by a second empty segment, each second empty segment corresponding to a first data segment. The first data segment, the second data segment, the first empty segment, and the second empty segment are configured to have equal data lengths.

[0011] In some implementations, each of the M second data segments in each of the N data groups is assigned an error checking and correcting (ECC) code.

[0012] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0013] In some implementations, the control logic is further configured to control the page buffer to detect a second data from the memory cell to the page buffer based on a second data pattern.

[0014] In some implementations, the control logic is further configured to control the page buffer to generate a third data having a third data pattern by performing an OR or AND operation on the first and second data.

[0015] In some implementations, the third data pattern includes N data groups, each having N first data segments from the first data pattern and M second data segments from the second data pattern. The M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments from the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

[0016] In some implementations, each of at least one processing unit includes M processing elements, each configured to perform a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups.

[0017] In some implementations, the control logic is further configured to control the page buffer to send the i-th first data segment and M second data segments to M processing elements.

[0018] In some implementations, each of at least one processing unit includes a control element configured to assign the i-th first data segment to each of the M processing elements, and to assign the M second data segments one by one to the M processing elements based on a sequence of M second data segments.

[0019] In some implementations, the control logic is further configured to retrieve the calculation result and output it to the data interface.

[0020] In some implementations, the array of memory cells is divided into more than one plane, and the number of processing units is equal to the number of planes in the memory cells. Each processing unit corresponds to one of the corresponding planes in the multiple planes of the memory cell.

[0021] In some implementations, the array of memory cells is divided into more planes than one of the memory cells, and the number of processing units is less than the number of planes of memory cells.

[0022] In some implementations, the number of processing units is half the number of memory cell planes, and each processing unit corresponds to two corresponding planes of the memory cell.

[0023] In some implementations, the number of processing units is one-quarter of the number of memory cell planes, and each processing unit corresponds to one of the four corresponding planes of the memory cell.

[0024] In some implementation forms, the number of at least one processing unit is 1, and one processing unit corresponds to a plurality of planes of memory cells.

[0025] In some implementation forms, the memory device includes a NAND flash memory.

[0026] In another aspect, a method for data calculation using a memory device including an array of memory cells and peripheral circuits coupled to the memory cells is provided. The method includes obtaining first data from a data interface of the memory device by a page buffer of the peripheral circuit, detecting second data from the array of memory cells by the page buffer of the peripheral circuit, and performing a calculation based on the first data and the second data by at least one processing unit of the peripheral circuit.

[0027] In some implementation forms, the method further includes programming the second data to the array of memory cells.

[0028] In some implementation forms, the first data includes at least one row. The step of obtaining the first data from the data interface of the memory device includes receiving each row of the first data based on a first data pattern.

[0029] In some implementation forms, the first data pattern includes N first data segments of equal data length, where N is a positive integer, N≥2, the sequence of the N first data segments of the first data pattern is the same as the sequence of the first data, and any two adjacent first data segments of the first data pattern are separated by M first empty segments, where M is a positive integer, M≥2.

[0030] In some implementation forms, the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

[0031] In some implementations, the second data contains M columns. The step of programming the second data into the array of memory cells includes the step of programming each column of the second data into the memory cells based on the second data pattern.

[0032] In some implementations, the second data is programmed into the memory cell in single-level memory cell (SLC) mode.

[0033] In some implementations, the second data pattern comprises N data groups, each having M second data segments of equal length from M columns of the second data, where any two adjacent data groups of the N data groups of the second data pattern are separated by a second empty segment, each second empty segment corresponding to a first data segment, and the first data segment, second data segment, first empty segment, and second empty segment are configured to have equal data lengths.

[0034] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0035] In some implementations, the step of detecting a second data from an array of memory cells includes the step of detecting the second data from the memory cells based on a second data pattern using a page buffer of peripheral circuitry.

[0036] In some implementations, the method further includes the step of generating a third data having a third data pattern by performing an OR operation on the first and second data using a page buffer before performing the calculation.

[0037] In some implementations, the third data pattern includes N data groups, each having N first data segments from the first data pattern and M second data segments from the second data pattern. The M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments from the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

[0038] In some implementations, the step of performing a calculation based on the first and second data includes the step of performing a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups.

[0039] In some implementations, the step of performing a calculation based on the first and second data includes sending the i-th first data segment to each of the M processing elements, and sending the M second data segments one by one to each of the M processing elements.

[0040] In some implementations, the method further includes the steps of obtaining the calculation result and outputting the calculation result to a data interface.

[0041] In yet another embodiment, a memory device is provided that includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a page buffer configured to store first data transmitted from the data interface of the memory device and to detect second data from the array of memory cells, and at least one processing unit coupled to the page buffer and configured to perform calculations based on the first data and the second data. The peripheral circuits further include control logic configured to control the page buffer to store a first portion of the first data and detect a first portion of the second data, then store a second portion of the first data and detect a second portion of the second data, then store a third portion of the first data and detect a third portion of the second data. The control logic further includes control logic configured to control at least one processing unit to perform a first calculation based on the first portion of the first data and the first portion of the second data while detecting a second portion of the second data, and then perform a second calculation based on the second portion of the first data and the second portion of the second data while detecting a third portion of the second data.

[0042] In some implementations, the control logic is further configured to output to the data interface a first calculation result for the first part of the first data and the first part of the second data while detecting the third part of the second data.

[0043] In some implementations, the control logic is further configured to program a second set of data into the array of memory cells.

[0044] In some implementations, the first data contains at least one row. The control logic is further configured to control the page buffer to receive each row of the first data based on the first data pattern.

[0045] In some implementations, the first data pattern contains N first data segments of equal length, the sequence of N first data segments in the first data pattern is the same as the sequence of the first data, and every two adjacent first data segments in the first data pattern are separated by M first empty segments, where M is a positive integer and M ≥ 2.

[0046] In some implementations, each part of the first data contains one first data segment of the first data pattern.

[0047] In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

[0048] In some implementations, the second data contains M columns. The control logic is further configured to program each column of the second data into the memory cell based on the second data pattern.

[0049] In some implementations, the control logic is further configured to program a second data into the memory cell in single-level memory cell (SLC) mode.

[0050] In some implementations, the second data pattern comprises N data groups, each having M second data segments of equal length from M columns of the second data, where any two adjacent data groups of the N data groups of the second data pattern are separated by a second empty segment, each second empty segment corresponding to a first data segment, and the first data segment, second data segment, first empty segment, and second empty segment are configured to have equal data lengths.

[0051] In some implementations, each part of the second data contains one data group of N data groups of the second data pattern.

[0052] In some implementations, each of the M second data segments in each of the N data groups is assigned an error checking and correcting (ECC) code.

[0053] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0054] In some implementations, the control logic is further configured to control the page buffer to detect a second data from the memory cell to the page buffer based on a second data pattern.

[0055] In some implementations, the control logic is further configured to control the page buffer to generate a third data having a third data pattern by performing an OR or AND operation on the first and second data.

[0056] In some implementations, the third data pattern includes N data groups, each having N first data segments from the first data pattern and M second data segments from the second data pattern. The M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments from the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

[0057] In some implementations, each of at least one processing unit includes M processing elements, each configured to perform a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups.

[0058] In some implementations, each control logic is further configured to control the page buffer to send the i-th first data segment and M second data segments to M processing elements.

[0059] In some implementations, each of at least one processing unit includes a control element configured to assign the i-th first data segment to each of the M processing elements, and to assign the M second data segments one by one to the M processing elements based on a sequence of M second data segments.

[0060] In some implementations, the array of memory cells is divided into more than one plane, and the number of processing units is equal to the number of planes in the memory cells. Each processing unit corresponds to one of the corresponding planes in the multiple planes of the memory cell.

[0061] In some implementations, the array of memory cells is divided into more planes than one of the memory cells, and the number of processing units is less than the number of planes of memory cells.

[0062] In some implementations, the number of processing units is at least half the number of planes in the memory cell. Each processing unit corresponds to two corresponding planes in the memory cell.

[0063] In some implementations, the number of processing units is one-quarter of the number of memory cell planes, and each processing unit corresponds to one of the four corresponding planes of the memory cell.

[0064] In some implementations, there is at least one processing unit, and each processing unit corresponds to multiple planes of memory cells.

[0065] In some implementations, the memory device is NAND flash memory.

[0066] In yet another embodiment, a system is provided that includes a memory device and a controller. The memory device includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a page buffer configured to store first data transmitted from the data interface of the memory device and to sense second data from the array of memory cells, and at least one processing unit coupled to the page buffer via the data path bus of the peripheral circuits and configured to perform calculations based on the first and second data. The controller is coupled to the memory device and configured to transmit first data to the memory device and to receive the results of calculations from the memory device.

[0067] In some implementations, the controller is further configured to send second data to a memory device.

[0068] In some implementations, the memory device is NAND flash memory.

[0069] The accompanying drawings incorporated herein and forming part thereof illustrate aspects of the present disclosure and, along with modes for carrying out the invention, are further useful in describing the present disclosure and enabling those skilled in the art to prepare and use the present disclosure. [Brief explanation of the drawing]

[0070] [Figure 1A] This is a block diagram of a system having a memory device according to some aspects of the present disclosure. [Figure 1B] This is a diagram of a memory card having a memory device according to some aspects of the present disclosure. [Figure 1C] This is a diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. [Figure 1D] This is a schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure. [Figure 1E]This is a block diagram of a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure. [Figure 1F] This is a block diagram of a processing unit according to some aspects of the present disclosure. [Figure 2A] This figure shows first data and second data processed by a memory device according to some aspects of the present disclosure. [Figure 2B] This figure shows the data shapes of the first data and the second data in Figure 2A according to several aspects of this disclosure. [Figure 2C] This figure shows a first data pattern and a second data pattern used to process the first data and the second data in Figure 2A, respectively, according to some aspects of this disclosure. [Figure 2D] This figure shows a storage map of the second data in Figure 2A based on the second data pattern in Figure 2C, according to some aspects of this disclosure. [Figure 2E] This figure shows the data flow in the page buffer of a memory device according to several aspects of this disclosure. [Figure 2F] This figure shows the data flow within a memory cell array, page buffer, and processing unit according to several aspects of the present disclosure. [Figure 3A] This figure shows the data flow in a processing unit of a memory device according to several aspects of this disclosure. [Figure 3B] This figure shows the data flow in a processing unit of a memory device according to several aspects of this disclosure. [Figure 4] This figure shows a process used to process the first and second data in Figure 2A based on the first and second data patterns in Figure 2C, according to some aspects of this disclosure. [Figure 5] This figure shows the operation pipeline of a memory device according to some aspects of the present disclosure. [Figure 6]This is a flowchart of a method for data computation using a memory device according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0071] In general, terms can be understood at least partially from their usage in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, a combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can be understood, at least partially depending on the context, to convey a singular or plural meaning. In addition, the term “based on” may be understood not necessarily as intended to convey an exhaustive set of factors, and instead, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly described.

[0072] Generative artificial intelligence (AI) inference involves AI computation. For example, transformer models, as a common model in AI systems, typically use tensor processing units (TPUs) and memory for computation. Large transformer models require a large amount of data and computation, which necessitates significant power consumption and sufficient memory. If memory access speed is slower than the processor's computation speed, a memory bottleneck hinders the effective operation of high-performance processors and becomes a major constraint on high-performance computing (HPC). This problem is known as the memory wall.

[0073] To address one or more of the aforementioned problems and to overcome the memory wall, this disclosure introduces a strategy that provides a memory device and a method for computation using the memory device. Multiple processing units are provided in the peripheral circuit of the memory device to perform computations under the control of the peripheral circuit's control logic. In this way, some of the computation tasks of the AI ​​system, in particular tasks requiring a large data width, can be distributed to the memory device of the AI ​​system. The computation tasks can be completed within the memory device without transferring large amounts of data from the memory device to the AI ​​system's processor to perform the computations, allowing the processor to handle other computations in the meantime. Thus, the computation speed of the AI ​​system is effectively improved by introducing processing units into the memory device.

[0074] Figure 1A shows a block diagram of a system 10 having a host 20 and a memory system 30, according to some aspects of the present disclosure. System 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, an artificial intelligence (AI) device, or any other suitable electronic device having storage in it. As shown in Figure 1A, system 10 may include a host 20 and a memory system 30 having one or more memory devices 34 and a memory controller 32. The host 20 may be a processor of an electronic device, such as a tensor processing unit (TPU), a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host 20 may be configured to send data to and receive data from the memory system 30.

[0075] The memory device 34 may be any memory device disclosed in this disclosure, such as NAND flash memory, vertical NAND flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM®), magnetoresistive random access memory (MRAM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), or nano random access memory (NRAM).

[0076] In some implementations, the memory controller 32 is coupled to the memory device 34 and the host 20 and configured to control the memory device 34. The memory controller 32 can manage the data stored in the memory device 34 and communicate with the host 20. In some implementations, the memory controller 32 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 32 is designed to operate in high-duty-cycle environments, such as SSDs or eMMCs (embedded multi-media cards) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and as storage arrays for enterprises. The memory controller 32 may be configured to control the operation of the memory device 34, such as read operations, erase operations, and program operations. The memory controller 32 may also be configured to manage various functions related to data stored or to be stored in the memory device 34, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 32 may further be configured to handle error correction codes (ECC) for data read from or written to the memory device 34. Any other appropriate functions, such as formatting the memory device 34, may also be performed by the memory controller 32. The memory controller 32 may communicate with an external device (e.g., host 20) according to a specific communication protocol.For example, the memory controller 32 can communicate with an external device through at least one of various interface protocols, such as the USB protocol, MMC protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (advanced technology attachment) protocol, serial-ATA protocol, parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, IDE (integrated drive electronics) protocol, and Firewire protocol.

[0077] The memory controller 32 and one or more memory devices 34 can be integrated into various types of storage devices contained in the same package, such as a UFS (universal flash storage) package or an eMMC package. In other words, the memory system 30 can be implemented and packaged into various types of final electronic products. In one example, as shown in Figure 1B, the memory controller 32 and a single memory device 34 can be integrated into a memory card 40. The memory card 40 may include PC cards (PCMCIA, personal computer memory card international association), CF cards, SM (smart media) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may further include a memory card connector 42 that connects the memory card 40 to a host (for example, the host 20 in Figure 1A). In another example, as shown in Figure 1C, the memory controller 32 and multiple memory devices 34 can be integrated into an SSD 50. The SSD 50 may further include an SSD connector 52 that connects the SSD 50 to a host (for example, the host 20 in Figure 1A). In some implementations, the storage capacity and / or operating speed of the SSD 50 are higher than those of the memory card 40.

[0078] Figure 1D shows a schematic circuit diagram of a memory device 60 including peripheral circuits according to several embodiments of the present disclosure. The memory device 60 may be an example of the memory device 34 in Figure 1A. The memory device 60 may include a memory cell array 62 and peripheral circuits 64 coupled to the memory cell array 62. The memory cell array 62 may be a NAND flash memory cell array in which memory cells are provided therein in the form of an array of NAND memory strings 66, each extending vertically on a substrate (not shown). In some implementations, each NAND memory string 66 includes a plurality of memory cells coupled in series and stacked vertically. Each memory cell can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the memory cell region. Each memory cell may be either a floating-gate memory cell including a floating-gate transistor or a charge-trap memory cell including a charge-trap transistor.

[0079] In some implementations, each memory cell is a single-level cell (SLC) with two possible memory states, and can store one bit of data. For example, the first memory state "0" may correspond to a first range of voltage, and the second memory state "1" may correspond to a second range of voltage. In some implementations, each memory cell is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to carry a range of possible nominal storage values. For example, if each MLC stores two bits of data, the MLC can be programmed to carry one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0080] As shown in Figure 1D, a schematic circuit diagram of an exemplary memory device 60 includes peripheral circuits according to several embodiments of the present disclosure. The memory device 60 may be an example of the memory device 34 in Figure 1A. The memory device 60 may include a memory cell array 62 and peripheral circuits 64 coupled to the memory cell array 62. The memory cell array 62 may be a NAND flash memory cell array in which memory cells 622 are provided therein in the form of an array of NAND memory strings 621, each extending vertically on a substrate (not shown). In some implementations, each NAND memory string 621 includes a plurality of memory cells 622 coupled in series and stacked vertically. Each memory cell 622 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 622.

[0081] In some implementations, each memory cell 622 is a single-level cell (SLC) with two possible memory states, and can store one bit of data. For example, the first memory state "0" may correspond to a first range of voltage, and the second memory state "1" may correspond to a second range of voltage. In some implementations, each memory cell 622 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to carry a range of possible nominal storage values. For example, if each MLC stores two bits of data, the MLC can be programmed to carry one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0082] As shown in Figure 1D, memory cells 622 of adjacent NAND memory strings 621 may be connected via word lines 629 that select which rows of memory cells 622 are affected by read and program operations. Each NAND memory string 621 may include a source selection gate (SSG) 623 at the source end and a drain selection gate (DSG) 624 at the drain end. The SSG 623 and DSG 624 may be configured to enable a selected NAND memory string 621 (a column in the array) during sense, read, and program operations. In some implementations, the sources of NAND memory strings 621 are connected via the same source line (SL) 625, for example, a common SL. In other words, according to some implementations, all NAND memory strings 621 in the same block have an array common source (ACS). According to some implementations, the DSG 624 of each NAND memory string 621 is connected to a respective bit line 626 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 621 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the DSG 624) or a deselection voltage (e.g., 0V) to each DSG 624 through one or more DSG lines 627, and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the SSG 623) or a deselection voltage (e.g., 0V) to each SSG 623 through one or more SSG lines 628.

[0083] Referring to Figure 1E, the peripheral circuit 64 includes a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, control logic 75, an address register 76, a data register 77, a data interface 79, a processing unit 80, and a data path bus 81. The above peripheral circuit 70 may be the same as the peripheral circuit 64 in Figure 1D, and it should be understood that in some other examples, the peripheral circuit 70 may also include additional peripheral circuits not shown in Figure 1E.

[0084] The page buffer / sense amplifier 71 may be configured to sense, read, and program (write) data to and from the memory cell array 62 according to a control signal from the control logic 75. In one example, the page buffer / sense amplifier 71 may store one page of program data (write data) to be programmed into one page of the memory cell array 62. In another example, the page buffer / sense amplifier 71 may perform a program verification operation to ensure that data is properly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 71 may also sense a low-power signal from a bit line representing data bits stored in the memory cell and amplify a small voltage amplitude to a logic level that is recognizable in a read operation. The column decoder / bit line driver 72 may be controlled by the control logic 75 and configured to select one or more NAND memory strings 66 by applying bit line voltages generated from a voltage generator 74.

[0085] The row decoder / word line driver 73 is controlled by control logic 75 and may be configured to select / deselect blocks of the memory cell array 62 and select / deselect the word lines of the blocks. The row decoder / word line driver 73 may be configured to drive word lines using word line voltages generated from a voltage generator 74. In some implementations, the row decoder / word line driver 73 can also select / deselect and drive SSG lines 628 and DSG lines 627. As will be described in detail below, the row decoder / word line driver 73 is configured to apply a read voltage to the selected word line in a read operation on a memory cell coupled to the selected word line.

[0086] The voltage generator 74 may be controlled by the control logic 75 and configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 62.

[0087] The control logic 75 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The address register 76 and data register 77 may be coupled to the control logic 75 and configured to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The data interface 79 is coupled to the control logic 75 via the data path bus 81 and acts as a control buffer, buffering control commands received from a host (not shown) and relaying them to the control logic 75, and buffering status information received from the control logic 75 and relaying it to the host. The data interface 79 is also coupled to the column decoder / bit line driver 72 and acts as a data input / output (I / O) interface and data buffer, buffering data and relaying it to and from the memory cell array 62. The data interface 79 may also be coupled to the data register 77 and the processing unit 80 to receive the calculation results of the processing unit 80 and transmit the results to the memory controller 32 or the host 20.

[0088] As shown in Figure 1F, a processing unit 80 is shown. The processing unit 80 includes a plurality of processing elements 82, at least one first register 86, a plurality of second registers 88, and control elements coupled to the first registers 86 and the second registers 88. The processing unit 80 may be coupled to the page buffer 71 through a plurality of first registers 86 for receiving first data from latched data in the page buffer 71, and a plurality of second registers 88 for receiving second data from the memory cell array 62. The second data may be detected by the page buffer 71 from the memory cell array 62. The processing unit 80 further includes a plurality of processing elements 82 coupled to the first registers 86 and the second registers 88 and configured to perform a convolution calculation based on the first and second data. Each processing element 82 may include a result register configured to store the calculation result generated by the corresponding processing element. The number of processing elements 82 is equal to the number of second registers 88 and the number of columns of second data. In this implementation, each processing unit includes six processing elements and six second registers 88. The processing unit 80 further includes a control element 84 configured to assign first data and second data to a plurality of processing elements 82 according to a pre-set data pattern. In some implementations, the number of at least one first register 86 is equal to the number of rows of first data. For example, in this implementation, each processing unit 80 includes one first register 86. In some implementations, the first register 86 and the second register 88 are FIFO (first-in-first-out) registers.

[0089] AI systems are primarily used in two aspects: training and inference. This disclosure can be used primarily in AI inference, where data is input to a trained AI module and recognized and analyzed to obtain expected results from the input data. In AI inference, calculations are performed based on the input data and data pre-stored in the AI ​​system to verify one or more properties of the input data. In AI inference, the input data may be one-dimensional data, and the reference data may often be two-dimensional data, as shown in Figure 2A, in which case the first data is a one-dimensional vector and the second data is a two-dimensional matrix. The AI ​​system has three modules for performing data calculations. The first module performs calculations near the memory device, and the calculations are performed outside the memory device. The second module performs calculations within the memory cell, and the calculations are performed by the memory cell of the memory device. The third module processes within the memory cell, and the calculations are performed by an additional processing unit of the memory device. The third module, i.e., the module processing within the memory cell, is used in the implementation of this disclosure.

[0090] Figure 2B shows equivalent shapes of the first and second data in Figure 2A. In some implementations, the one-dimensional first data can be considered equivalent to rows of data of length a, and the two-dimensional second data, i.e., an a×b matrix, can be considered equivalent to columns b, each column having length a. In some implementations, the first data may also be a two-dimensional matrix containing more than one row of equal data length, and dimensionality reduction may be performed on more than one row of the first data to decompose the first data into multiple single rows to which this disclosure should be applied.

[0091] In some implementations, the first and second data can be preprocessed before being processed to perform convolution on the memory device. In some implementations, the first and second data can be preprocessed based on the first and second data patterns, as shown in Figure 2C.

[0092] In some implementations, the first data consists of a single row, and the control logic 75 is configured to control the page buffer 71 to retrieve a row of the first data based on the first data pattern and send it to at least one processing unit 80, as shown in Figures 2C and 2D. The first data pattern consists of N first data segments of equal length, where N is a positive integer and N ≥ 2. In some implementations, referring to Figure 2D, any two adjacent first data segments of the first data pattern are separated by M first empty segments. For example, if N=4 is used as an example to illustrate the present disclosure, referring to Figure 2D, the first data consists of four first data segments based on the first data pattern, namely, first data segment S1-0, first data segment S1-1, first data segment S1-2, and first data segment S1-3. Six first empty segments are placed between the first data S1-0 and the first data segment S1-1, six first empty segments are placed between the first data segment S1-1 and the first data segment S1-2, six first empty segments are placed between the first data segment S1-2 and the first data segment S1-3, and six first empty segments are placed between the first data segment S1-3 and the first first data segment that is adjacent to it. In some implementations, the first empty segments may be filled with "1" instead of being empty. In some implementations, the first empty segments may be filled with "0" instead of being empty.

[0093] The sequence of the four first data segments of the first data pattern is the same as the sequence of the first data. In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the data path bus. The first data segments and the first empty segment are configured to have equal data lengths. In some implementations, an error checking and correcting (ECC) code is assigned to each first data segment to verify it. The ECC code may also be used as an identifier to recognize each first data segment of the first data pattern.

[0094] In some implementations, the second data contains M columns, where M is a positive integer and M ≥ 2. As shown in Figures 2C and 2E, the control logic 75 is configured to program each column of the second data into the memory cells of the memory cell array 62 based on the second data pattern. The second data pattern contains N data groups, each having M second data segments of equal data length from the M columns of the second data, and the first and second data segments are configured to share equal data lengths. Any two adjacent data groups in the N data groups of the second data pattern are separated by a second empty segment, each second empty segment corresponding to a first data segment. For example, N=4 and M=6 are used as examples to illustrate this disclosure. As shown in Figure 2C, the second data contains 6 columns, i.e., column 1, column 2, column 3, column 4, column 5, and column 6. Each of the six columns contains four second data segments, namely, second data segment S2-0, second data segment S2-1, second data segment S2-2, and second data segment S2-3. Referring to Figure 2C, the six second data segments S2-0 are regrouped as the first data group of the second data pattern, the six second data segments S2-1 are regrouped as the second data group of the second data pattern, the six second data segments S2-2 are regrouped as the third data group of the second data pattern, and the six second data segments S2-3 are regrouped as the fourth data group of the second data pattern.Referring to Figure 2E, the first data group of the second data is separated from the preceding data group of the second data by the second empty segment S2-0, the second data group of the second data is separated from the first data group of the second data by the second empty segment S2-1, the third data group of the second data is separated from the second data group of the second data by the second empty segment S2-2, and the fourth data group of the second data is separated from the third data group of the second data by the second empty segment S2-3. In some implementations, the second empty segment may be filled with "1" instead of being empty. In some implementations, the first empty segment may be filled with "0" instead of being empty.

[0095] In some implementations, referring to Figures 2C and 2E, each data group of the four data groups of the second data pattern is programmed sequentially into the memory cell array 62, that is, the logical addresses of the data in each data group are continuous, so that data from the same data group can be detected simultaneously into the page buffer 71. For example, in some implementations, the six second data segments S2-0 and one second empty segment S2-B of the first data group are programmed sequentially in block 0 of the memory cell array 62, the six second data segments S2-1 and one second empty segment S2-B of the second data group are programmed sequentially in block 1 of the memory cell array 62, the six second data segments S2-2 and one second empty segment S2-B of the third data group are programmed sequentially in block 2 of the memory cell array 62, and the six second data segments S2-3 and one second empty segment S2-B of the first data group are programmed sequentially in block 3 of the memory cell array 62.

[0096] In some implementations, the capacity of each block in the memory cell array 62 is greater than at least twice the data length of each data group, and two or more data groups can be programmed consecutively within the same array of the memory cell array 62. In some implementations, the capacity of each block in the memory cell array 62 is shorter than the data length of each data group, so that each data group can be programmed in two consecutive blocks of the memory cell array 62. The sequence of the second data segments of the second data pattern is the same as the sequence of the second data. In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus. The first data segment, the first empty segment, the second data segment, and the second empty segment are configured to have equal data lengths. In some implementations, an error checking and correcting (ECC) code is assigned to each second data segment to verify it. The ECC code can also be used as an identifier to recognize each second data segment of the second data pattern.

[0097] In some implementations, referring to Figure 2F, the control logic 75 is further configured to control the page buffer 71 to acquire first and second data and send them to at least one processing unit 80 based on the data sequences of the first and second data patterns in Figure 2C.

[0098] In some implementations, as shown in Figures 2D and 2F, the first data is transmitted from the data interface 79 to the second latch of the page buffer 71 based on a first data pattern, with any two adjacent first data segments separated by M first empty segments. As shown in Figures 2E and 2F, the second data from the memory cell array 62 to the first latch of the page buffer 71 is detected based on a second data pattern, with any two adjacent data groups of the second data separated by one second empty segment.

[0099] The control logic 75 is further configured to control the page buffer 71 to generate a third data having a third data pattern by performing an OR or AND operation on the first data and the second data. The third data pattern includes N data groups, each having N first data segments from the first data pattern and M second data segments from the second data pattern. The M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1. In some implementations, the first and second empty segments are filled with "1" and replaced by the corresponding second and first data segments after the AND operation. In some implementations, the first and second empty segments are filled with "0" and replaced by the corresponding second and first data segments after the OR operation.

[0100] The control logic 75 is configured to control the page buffer to transmit the i-th first data segment and M second data segments to M processing elements. Referring to Figure 2F, at least one processing unit 80 includes M processing elements 82 configured to perform a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups. Each of the at least one processing unit 80 further includes a control element 84 configured to assign the i-th first data segment to each of the M processing elements and to assign the M second data segments to the M processing elements accordingly based on the sequence of M second data segments.

[0101] For example, as shown in Figure 3A, the first data segment S1-0 is first sent to the processing unit 80, and as shown in Figure 3B, the first data segment S1-1 is sent to the processing unit 80 following the first data segment S1-0. The first data segments S1-2 and S1-3 are sent to the processing unit 80 following the first data segment S1-1 (not shown). Using the first data segment S1-0 as an example, in some implementations, the first data segment S1-0 is sent to a first register 86 where it is buffered. In some implementations, as shown in Figure 3A, each processing unit includes a control element configured to assign the first data segment S1-1 to each processing element 82.

[0102] In some implementations, the control logic 75 is further configured to control the page buffer 71 to detect data groups of the second data pattern based on the data sequence of the second data pattern in Figure 2C and send them to at least one processing unit 80. For example, as shown in Figure 3A, the six second data segments S2-0 of the first data group are first sent to the processing unit 80, and as shown in Figure 3B, the six second data segments S2-1 of the second data group are sent to the processing unit 80 following the first data group. Following the second data group, the six second data segments S2-2 of the third data group of the second data are sent to the processing unit 80, and following the third data group, the six second data segments S2-3 of the four data groups of the second data are sent to the processing unit 80 (not shown). Using the six second data segments S2-0 as an example, in some implementations, the six second data segments S2-1 are sent to six second registers 88 where they are buffered. In some implementations, as shown in Figure 3A, each processing unit includes a control element configured to assign the six second data segments S2-1 to six processing elements in proportion to the sequence of the six second data segments S2-1.

[0103] In some implementations, the M processing elements 82 of each processing unit 80 are configured to perform a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups, where i is a positive integer and N≧i≧1. Referring to Figures 3A and 3B, in this implementation, the first data segment S1-0 is sent to each of the six processing elements 82, and the six second data segments S2-0 of the first data group of the second data are sent one by one to the six processing elements 82, and the six processing elements 82 perform a convolution operation based on the first data segment S1-0 and the six second data segments S2-0 to obtain a first calculation result. In some implementations, the first calculation result is then sent to the corresponding result register of each processing element 82 for storage in order to perform further calculations. In some implementations, the first calculation result may then be sent to the data interface 79 for storage under the control of the control logic 75. In some implementations, the first calculation result is then transmitted to the memory cell array 62 for storage under the control of the control logic 75. The first data segment S1-1 and six second data segments S2-1 are then transmitted to the six processing elements 82 to perform a convolution operation and generate a second calculation result. Subsequently, the second calculation result is then transmitted to the corresponding result register, data interface 79, or memory cell array 62 by the control logic 75.

[0104] The calculation principle of at least one processing unit is provided in Figure 4, where the i-th first data segment is multiplied by M second data segments of the i-th data group of N data groups to obtain the i-th result. The N i-th results are accumulated to obtain the convolution result. In some implementations, the peripheral circuit 70 includes one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are performed sequentially by one processing unit 80. In some implementations, the peripheral circuit 70 includes more than one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are performed simultaneously by different processing units 80.

[0105] At least one processing unit 80 is independently configured within the peripheral circuit 70 and is a separate module. While increasing the number of at least one processing unit 80 within the peripheral circuit 70 improves the computation speed of the peripheral circuit 70, it requires a larger area of ​​the peripheral circuit 70, resulting in a trade-off between computation speed and the area of ​​the peripheral circuit 70. In some implementations, the memory cell array 62 is divided into more than one plane of memory cells, with each plane containing multiple memory cells. The number of at least one processing unit 80 is equal to the number of planes of memory cells, meaning that at least one processing unit 80 corresponds to one of each of the multiple planes of memory cells. For example, the memory cell array 62 is divided into 128 planes of memory cells, and the number of at least one processing unit 80 is also 128. In some implementations, the number of at least one processing unit 80 is less than the number of planes of memory cells. For example, the memory cell array 62 is divided into 128 planes of memory cells, and the number of at least one processing unit 80 could be 100, 64, 50, or any other number less than 128. In some implementations, the number of at least one processing unit 80 is half the number of memory cell planes, with each processing unit corresponding to two planes of memory cells. For example, if the memory cell array 62 is divided into 128 planes of memory cells, the number of at least one processing unit 80 is 64. In some implementations, the number of at least one processing unit 80 is one-quarter the number of memory cell planes, with each processing unit corresponding to four planes of memory cells. For example, if the memory cell array 62 is divided into 128 planes of memory cells, the number of at least one processing unit 80 is 32. The number of at least one processing unit 80 may be set and adjusted based on the needs of the AI ​​system, and the implementations of this disclosure are intended to illustrate the disclosure and should not be described as limitations.

[0106] In another aspect of this disclosure, the control logic 75 of the peripheral circuit 70 is configured to control the page buffer 71 to successively acquire a first portion of the first data, a second portion of the first data, and a third portion of the first data. The control logic 75 of the peripheral circuit 70 is further configured to control the page buffer 71 to successively detect a first portion of the second data, a second portion of the second data, and a third portion of the second data. The control logic 75 of the peripheral circuit 70 is further configured to perform a first calculation based on the first portion of the first data and the first portion of the second data while detecting the second portion of the second data, and subsequently perform a second calculation based on the second portion of the first data and the second portion of the second data while detecting the third portion of the second data. The control logic 75 of the peripheral circuit 70 is further configured to output the first calculation result of the first portion of the first data and the first portion of the second data to the data interface while detecting the third portion of the second data.

[0107] In some implementations, as shown in Figure 5, the operational pipeline of a single processing unit 80 is illustrated. As described above, the first data consists of at least one row, and the control logic 75 is configured to control the page buffer 71 to receive each row of the first data based on the first data pattern.

[0108] The first data pattern contains N first data segments of equal data length, where N is a positive integer and N ≥ 2, and the sequence of N first data segments in the first data pattern is the same as the sequence of the first data. The data length of each first data segment is less than or equal to the bandwidth of the data path bus 81. In this implementation, as shown in Figure 2C, each part of the first data contains a first data segment, for example, the first part of the first data may be the first data segment S1-0, the second part of the first data may be the first data segment S1-1, the third part of the first data may be the first data segment S1-2, and the fourth part of the first data may be the first data segment S1-3. In some implementations, the Nth part of the first data may be the first data segment S1-(N-1). In some implementations, each part of the first data may contain data segments that are longer or shorter than the first data segment, based on the bandwidth of the data path bus 81 and the other data widths of the peripheral circuitry 70.

[0109] The second data consists of M columns, where M is a positive integer and M ≥ 2. The control logic 75 is configured to program each column of the second data into a memory cell based on the second data pattern. In some implementations, the control logic 75 is configured to program the second data into a memory cell as a single-level memory cell (SLC). The second data pattern consists of N data groups, each having M second data segments of equal data length from the M columns of the second data, and the first and second data segments are configured to share equal data lengths. In some implementations, each part of the second data corresponds to a part of the first data to be multiplied by. For example, the first part of the second data may be the six second data segments S2-0 of the first data group of the second data that are multiplied by the first data segment S1-0; the second part of the second data may be the six second data segments S2-1 of the second data group of the second data that are multiplied by the first data segment S1-1; the third part of the second data may be the six second data segments S2-2 of the third data group of the second data that are multiplied by the first data segment S1-2; and the fourth part of the second data may be the six second data segments S2-0 of the fourth data group of the second data that are multiplied by the first data segment S1-3. In some implementations, the Nth part of the second data may be the six second data segments S2-(N-1) of the Nth data group of the second data that are multiplied by the first data segment S1-(N-1).

[0110] In some implementations, the operational pipeline shown in Figure 5 is performed by at least one processing element 82 of each processing unit 80. The control logic 75 is configured to control the control page buffer 71 to send the i-th first data segment to each processing element 82, and to control the page buffer 71 to send M second data segments to the M processing elements 82. Each of at least one processing unit 80 includes a control element 84 configured to assign the M second data segments one by one to the M processing elements based on a sequence of M second data segments.

[0111] Referring to Figure 5, an initial cycle C0 is configured to prepare the processing unit 80. The operation pipeline starts with a first cycle C1, where a first portion of the first data is obtained by the page buffer 71 and sent to the processing element 82 of the processing unit 80, while a first portion of the second data is detected by the page buffer 71 and sent to the processing element 82 of the processing unit 80.

[0112] In the second cycle C2, which is continuous with the first cycle C1, the first calculation is performed by the processing element 82, and the first result is generated based on the first part of the first data and the first part of the second data. The first result is copied by the control logic 75 at the end of the second cycle C2. At the same time, the second part of the first data is detected by the page buffer 71 and sent to the processing element 82, while the second part of the second data is detected by the page buffer 71 and sent to the processing element 82.

[0113] Next, in the third cycle C3, the first result is sent to the data interface 79, which can be output at any point during the third cycle C3, as this takes much less time than the detection or calculation of the data. During the third cycle C3, the second calculation is performed by the processing element 82, and the second result is generated based on the second part of the first data and the second part of the second data. The second result is copied by the control logic 75 at the end of the second cycle C2. Simultaneously, the third part of the first data is detected by the page buffer 71 and sent to the processing element 82, while the third part of the second data is detected by the page buffer 71 and sent to the processing element 82.

[0114] Next, in the fourth cycle C4, the second result is transmitted to the data interface 79, while the third calculation is performed by the processing element 82, generating the third result based on the third portion of the first data and the third portion of the second data. Simultaneously, the fourth portion of the first data is acquired by the page buffer 71 and transmitted to the processing element 82, while the fourth portion of the second data is detected by the page buffer 71 and transmitted to the processing element 82. Similarly, in the i-th cycle Ci, the (i-2)th result is transmitted to the data interface 79, while the (i-1)th calculation is performed by the processing element 82, generating the (i-1)th result based on the (i-1)th portion of the first data and the (i-1)th portion of the second data. Simultaneously, the i-th portion of the first data is acquired by the page buffer 71 and transmitted to the processing element 82, while the i-th portion of the second data is detected by the page buffer 71 and transmitted to the processing element 82. By applying the operational pipeline shown in Figure 5, the detection of the first and second data, the execution of the convolution calculation, and the output of the calculation results can be completed within a single cycle, effectively improving the computation. In some implementations, only the detection of the first and second data and the execution of the convolution calculation are performed.

[0115] A system including a memory device and a memory controller is provided according to aspects of this disclosure. The memory device includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a page buffer configured to acquire first data from a data interface and to sense second data from the array of memory cells, and at least one processing unit coupled to the page buffer via the peripheral circuits' data path bus and configured to perform calculations based on the first and second data. The controller is coupled to the memory device and is configured to transmit first data to the memory device and to receive the results of calculations from the memory device.

[0116] In some implementations, the system can be any electronic system to which an AI system is applied, such as computers, digital cameras, mobile phones, smart home appliances, IoT (Internet of Things), servers, and base stations. In this disclosure, data processing and computation of the AI ​​system may be performed by processing units 80 of peripheral circuits of a memory device. In some implementations, resource-intensive computational tasks can be distributed to the memory device rather than a TPU or graphics processing unit (GPU) by adding at least one processing unit to the memory device to improve the performance of the AI ​​system. The number of processing units may be designed based on the needs of the AI ​​system. The more processing units integrated into the memory device, the more effective the AI ​​system becomes.

[0117] Referring to Figure 6, Figure 6 shows a flowchart of Method 600 for data computation using a memory device including an array of memory cell arrays 62 and peripheral circuits 70 coupled to the memory cell arrays 62, the memory device may be the same as those described above and are not repeated here. The operations shown in Method 600 are not exhaustive, and it should be understood that other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than that shown in Figure 6.

[0118] As shown in Figure 6, method 600 can be initiated in operation 602, where first data is acquired from the data interface of the memory device by the page buffer of the peripheral circuit. Method 600 can be initiated in operation 604, where second data is detected from the array of memory cells by the page buffer. Note that there are no performance constraints on operations 602 and 604. Operation 602 may be performed before, after, or concurrently with operation 604. In some implementations, operations 602 and 604 may be performed at the same time to improve the computational efficiency of the memory device. The order of operations 602 and 604 should not limit the scope of this disclosure.

[0119] In some implementations, as shown in Figure 2A, the first data may be one-dimensional data and the second data may often be two-dimensional data, in which case the first data is a one-dimensional vector and the second data is a two-dimensional matrix. In some implementations, the one-dimensional first data can be considered equivalent to a row of data of length a, and the two-dimensional second data, i.e., an a×b matrix, can be considered equivalent to a column b, where each column has length a. In some implementations, the first data may be a two-dimensional matrix containing more than one row of equal data length, and dimensionality reduction may be performed on more than one row of the first data in order to decompose the first data into multiple single rows to which this disclosure should be applied.

[0120] In some implementations, the first and second data may be preprocessed before operations 602 and 604. In some implementations, as shown in Figure 2C, the first and second data may be preprocessed based on the first and second data patterns.

[0121] In some implementations, the first data consists of one row. The first data is acquired by the page buffer 71 from the data interface 79 and sent to at least one processing unit 80 based on a first data pattern, as shown in Figures 2C and 2D. The first data pattern consists of N first data segments of equal length, where N is a positive integer and N ≥ 2. In some implementations, referring to Figure 2D, any two adjacent first data segments of the first data pattern are separated by M first empty segments. For example, if N=4 is used as an example to illustrate the present disclosure, referring to Figure 2D, the first data consists of four first data segments based on the first data pattern, namely, first data segment S1-0, first data segment S1-1, first data segment S1-2, and first data segment S1-3. Six first empty segments are placed between the first data S1-0 and the first data segment S1-1, six first empty segments are placed between the first data segment S1-1 and the first data segment S1-2, six first empty segments are placed between the first data segment S1-2 and the first data segment S1-3, and six first empty segments are placed between the first data segment S1-3 and the first data segment that is adjacent to it.

[0122] The sequence of the four first data segments of the first data pattern is the same as the sequence of the first data. In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the data path bus. The first data segments and the first empty segment are configured to have equal data lengths. In some implementations, an error detection and correction (ECC) code is assigned to each first data segment to verify it. The ECC code may also be used as an identifier to recognize each first data segment of the first data pattern.

[0123] In some implementations, the second data contains M columns, where M is a positive integer and M ≥ 2. As shown in Figures 2C and 2E, the second data is programmed into the memory cells of the memory cell array 62 based on the second data pattern. The second data pattern contains N data groups, each having M second data segments of equal data length from the M columns of the second data, and the first and second data segments are configured to share equal data lengths. Any two adjacent data groups in the N data groups of the second data pattern are separated by a second empty segment, each second empty segment corresponding to a first data segment. For example, N=4 and M=6 are used as examples to illustrate this disclosure. As shown in Figure 2C, the second data contains 6 columns, i.e., column 1, column 2, column 3, column 4, column 5, and column 6. Each of the six columns contains four second data segments, namely, second data segment S2-0, second data segment S2-1, second data segment S2-2, and second data segment S2-3. Referring to Figure 2C, the six second data segments S2-0 are regrouped as the first data group of the second data pattern, the six second data segments S2-1 are regrouped as the second data group of the second data pattern, the six second data segments S2-2 are regrouped as the third data group of the second data pattern, and the six second data segments S2-3 are regrouped as the fourth data group of the second data pattern. Referring to Figure 2E, the first data group of the second data is separated from the processing data group of the second data by the second empty segment S2-0, the second data group of the second data is separated from the first data group of the second data by the second empty segment S2-1, the third data group of the second data is separated from the second data group of the second data by the second empty segment S2-2, and the fourth data group of the second data is separated from the third data group of the second data by the second empty segment S2-3.

[0124] In some implementations, referring to Figures 2C and 2E, each of the four data groups of the second data pattern is programmed sequentially into the memory cell array 62, that is, the logical addresses of the data in each data group are continuous, so that data from the same data group can be detected simultaneously into the page buffer 71. For example, in some implementations, the six second data segments S2-0 and one second empty segment S2-B of the first data group are programmed sequentially in block 0 of the memory cell array 62, the six second data segments S2-1 and one second empty segment S2-B of the second data group are programmed sequentially in block 1 of the memory cell array 62, the six second data segments S2-2 and one second empty segment S2-B of the third data group are programmed sequentially in block 2 of the memory cell array 62, and the six second data segments S2-3 and one second empty segment S2-B of the first data group are programmed sequentially in block 3 of the memory cell array 62.

[0125] In some implementations, the capacity of each block in the memory cell array 62 is greater than at least twice the data length of each data group, so that two or more data groups can be programmed consecutively within the same block of the memory cell array 62. In some implementations, the capacity of each block in the memory cell array 62 is less than the data length of each data group, so that each data group can be programmed in two consecutive blocks of the memory cell array 62. The sequence of the second data segments of the second data pattern is the same as the sequence of the second data. In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus. The first data segment, the first empty segment, the second data segment, and the second empty segment are configured to have equal data lengths. In some implementations, an error detection and correction (ECC) code is assigned to each second data segment to verify it. The ECC code can also be used as an identifier to recognize each second data segment of the second data pattern.

[0126] In some implementations, referring to Figure 2F, the first data and the second data are sent to at least one processing unit 80 based on the data sequences of the first and second data patterns in Figure 2C.

[0127] In some implementations, as shown in Figures 2D and 2F, first data is acquired from the data interface 79 to the second latch of the page buffer 71 based on a first data pattern, and any two adjacent first data segments are separated by M first empty segments. As shown in Figures 2E and 2F, second data is acquired from the memory cell array 62 to the first latch of the page buffer 71 based on a second data pattern, and any two adjacent data groups of the second data are separated by one second empty segment.

[0128] In some implementations, the third data has a third data pattern obtained by performing an OR operation on the first and second data, meaning that the empty segments of the first and second data are replaced by the corresponding second and first data segments after the OR or AND operation. The third data may be stored in a third data latch of the page buffer 71, or it may be stored back in the first or second data latch. The third data pattern includes N data groups, each having N first data segments from the first data pattern and M second data segments from the second data pattern. The M empty first segments between the i-th and (i+1)th first data segments of the N first data segments are replaced by the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

[0129] As shown in Figure 6, method 600 can be initiated in operation 606, at which time the calculation is performed by at least one processing unit of the peripheral circuit based on the first data and the second data.

[0130] In some implementations, operation 606 involves each processing unit 80 having M processing elements 82 perform a convolution operation based on the i-th first data segment of N first data segments and the M second data segments of the i-th data group of N data groups, where i is a positive integer and N≧i≧1. Referring to Figures 3A and 3B, in this implementation, the first data segment S1-0 is sent to each of the six processing elements 82, and the six second data segments S2-0 of the first data group of second data are sent one by one to the six processing elements 82, and the six processing elements 82 perform a convolution operation based on the first data segment S1-0 and the six second data segments S2-0 to obtain a first calculation result. The first calculation result is then sent to the data interface 79 by the control logic 75. Next, the first data segment S1-1 and the six second data segments S2-1 are sent to the six processing elements 82 in order to perform a convolution operation and generate a second calculation result. The second calculation result is then subsequently sent to the data interface 79 by the control logic 75.

[0131] The calculation principle of at least one processing unit is provided in Figure 4, where the i-th first data segment is multiplied by M second data segments of the i-th data group of N data groups to obtain the i-th result. The N i-th results are accumulated to obtain the convolution result. In some implementations, the peripheral circuit 70 includes one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are performed sequentially by one processing unit 80. In some implementations, the peripheral circuit 70 includes more than one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are performed simultaneously by different processing units 80.

[0132] The above description of specific implementation forms can be readily modified and / or adapted for various applications. Such adaptations and modifications are therefore intended to be within the meaning and scope of the equivalents of the disclosed implementation forms, based on the teachings and guidance presented herein.

[0133] The scope and width of this disclosure should not be limited by any of the implementations described above, but should be defined solely in accordance with the appended claims and their equivalents.

[0134] While specific configurations and arrangements are discussed, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may also be used in various other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with each other and the scope of this disclosure. [Explanation of Symbols]

[0135] 10 Systems 20 hosts 30 memory systems 32 memory controllers 34 Memory Devices 40 memory cards 42 Memory card connector 50 SSD 52 SSD connectors 60 memory devices 62 memory cell array 64 Peripheral Circuits 70 Peripheral Circuits 71 Page Buffer / Sense Amplifier 72-row decoder / BL driver 73-line decoder / WL driver 74 Voltage Generator 75 Control Logic 76 Address Registers 77 Data Registers 79 Data Interface 80 processing units 82 processing elements 84 control elements 86 First Register 621 NAND memory string 622 memory cells 623 Source Selection Gate 624 Drain Selection Gate 625 Source Line 626-bit line 627 DSG line 628 SSG Line 629 Word lines

Claims

1. A memory cell array and A memory device comprising a peripheral circuit coupled to the array of memory cells, wherein the peripheral circuit is A page buffer configured to store first data transmitted from the data interface of the memory device and to detect second data from the array of memory cells, At least one processing unit is configured to be coupled to the page buffer via the data path bus of the peripheral circuit and to perform calculations based on the first data and the second data, Control logic configured to program the second data into the array of memory cells A memory device comprising the above features.

2. The first data comprises at least one row, The memory device according to claim 1, wherein the control logic is further configured to control the page buffer to receive each row of the first data based on a first data pattern.

3. The first data pattern comprises N first data segments of equal data length, where N is a positive integer and N ≥ 2. The sequence of the N first data segments of the first data pattern is the same as the sequence of the first data, The memory device according to claim 2, wherein any two adjacent first data segments of the first data pattern are separated by M first empty segments, where M is a positive integer and M ≥ 2.

4. The memory device according to claim 3, wherein the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

5. The second data set described above has M columns, The memory device according to claim 3, wherein the control logic is further configured to program each column of the second data into the memory cell based on a second data pattern.

6. The memory device according to claim 5, wherein the control logic is further configured to program the second data into the memory cell in single-level memory cell (SLC) mode.

7. The second data pattern comprises N data groups, each having M second data segments of equal length from the M columns of the second data, Any two adjacent data groups of the N data groups in the second data pattern are separated by a second empty segment, and each second empty segment is associated with the first data segment. The memory device according to claim 5, wherein the first data segment, the second data segment, the first empty segment, and the second empty segment are configured to have equal data lengths.

8. The memory device according to claim 7, wherein each of the M second data segments of each of the N data groups is assigned an error detection and correction (ECC) code.

9. The memory device according to claim 7, wherein the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

10. The memory device according to claim 7, wherein the control logic is further configured to control the page buffer to detect the second data from the memory cell to the page buffer based on the second data pattern.

11. The memory device according to claim 7, wherein the control logic is further configured to control the page buffer to generate a third data having a third data pattern by performing an OR or AND operation on the first data and the second data.

12. The third data pattern is, The N first data segments from the first data pattern, The system comprises N data groups, each having M second data segments from the second data pattern, The memory device according to claim 11, wherein the M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

13. Each of the at least one processing unit is A convolution operation is performed based on the i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups. The memory device according to claim 12, comprising M processing elements configured as follows.

14. The control logic further, The memory device according to claim 12, configured to control the page buffer to transmit the i-th first data segment and the M second data segments to the M processing elements.

15. Each of the at least one processing unit is The i-th first data segment is assigned to each of the M processing elements, Based on the sequence of the M second data segments, each of the M second data segments is assigned to one of the M processing elements. The memory device according to claim 14, comprising a control element configured as follows.

16. The control logic further, Obtain the calculation result, The memory device according to claim 14, configured to output the calculation result to the data interface.

17. The array of memory cells is divided into more than one plane of memory cells, The number of the at least one processing unit is equal to the number of planes of the memory cell, The memory device according to claim 14, wherein each processing unit corresponds to one of the corresponding planes of more than one of the memory cells.

18. The array of memory cells is divided into more than one plane of memory cells, The memory device according to claim 14, wherein the number of the at least one processing unit is less than the number of planes of the memory cell.

19. The number of the at least one processing unit is half the number of the planes of the memory cell, The memory device according to claim 18, wherein each processing unit corresponds to two corresponding planes of a memory cell.

20. The number of the at least one processing unit is one-quarter of the number of planes of the memory cell, The memory device according to claim 18, wherein each processing unit corresponds to one of the four corresponding planes of a memory cell.

21. The number of the aforementioned at least one processing unit is 1, The memory device according to claim 18, wherein the one processing unit corresponds to more than one plane of the memory cell.

22. The memory device according to claim 1, wherein the memory device comprises NAND flash memory.

23. A method for data computation using a memory device comprising an array of memory cells and peripheral circuits coupled to the memory cells, The steps include: obtaining first data from the data interface of the memory device using the page buffer of the peripheral circuit; The step of detecting a second data from the array of memory cells using the page buffer of the peripheral circuit, A method comprising the step of performing a calculation based on the first data and the second data using at least one processing unit of the peripheral circuit.

24. The method according to claim 23, further comprising the step of programming the second data into the array of memory cells.

25. The first data comprises at least one row, The method according to claim 24, wherein the step of obtaining the first data from the data interface of the memory device comprises the step of receiving each row of the first data based on a first data pattern.

26. The first data pattern comprises N first data segments of equal data length, where N is a positive integer and N ≥ 2. The sequence of the N first data segments of the first data pattern is the same as the sequence of the first data. The method according to claim 25, wherein any two adjacent first data segments of the first data pattern are separated by M first empty segments, where M is a positive integer and M ≥ 2.

27. The method according to claim 26, wherein the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

28. The second data set described above has M columns, The method according to claim 26, wherein the step of programming the second data into the array of memory cells comprises the step of programming each column of the second data into the memory cells based on a second data pattern.

29. The method according to claim 28, wherein the second data is programmed into the memory cell in single-level memory cell (SLC) mode.

30. The second data pattern comprises N data groups, each having M second data segments of equal length from the M columns of the second data, Any two adjacent data groups of the N data groups in the second data pattern are separated by a second empty segment, and each second empty segment is associated with the first data segment. The method according to claim 28, wherein the first data segment, the second data segment, the first empty segment, and the second empty segment are configured to have equal data lengths.

31. The method according to claim 30, wherein the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

32. The step of detecting the second data from the array of memory cells is: The method according to claim 30, further comprising the step of detecting the second data from the memory cell based on the second data pattern using the page buffer of the peripheral circuit.

33. Before performing the calculation, The method according to claim 30, further comprising the step of generating a third data having a third data pattern by performing an OR operation on the first data and the second data using the page buffer.

34. The third data pattern is, The N first data segments from the first data pattern, The system comprises N data groups, each having M second data segments from the second data pattern, The method according to claim 33, wherein the M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

35. The step of performing calculations based on the first data and the second data is: The method according to claim 34, further comprising the step of performing a convolution operation on the i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups using M processing elements of each of the at least one processing unit.

36. The step of performing calculations based on the first data and the second data is: The steps include transmitting the i-th first data segment to each of the M processing elements, The method according to claim 35, further comprising the step of transmitting the M second data segments one by one to the M processing elements.

37. Steps to obtain the calculation result, The method according to claim 36, further comprising the step of outputting the calculation result to the data interface.

38. A memory cell array and A memory device comprising peripheral circuits coupled to the array of memory cells, wherein the peripheral circuits are A page buffer configured to store first data transmitted from the data interface of the memory device via a data path bus and to detect second data from the array of memory cells, At least one processing unit, which is coupled to the page buffer and configured to perform calculations based on the first data and the second data, The first portion of the first data is stored, and the first portion of the second data is detected. Next, the second portion of the first data is stored, and the second portion of the second data is detected. Next, the third portion of the first data is stored, and the third portion of the second data is detected. It comprises control logic configured to control the page buffer, The control logic further, While detecting the second portion of the second data, a first calculation is performed based on the first portion of the first data and the first portion of the second data. Next, while detecting the third portion of the second data, a second calculation is performed based on the second portion of the first data and the second portion of the second data. A memory device configured to control the at least one processing unit.

39. The memory device according to claim 38, wherein the control logic is further configured to output to the data interface a first calculation result for the first portion of the first data and the first portion of the second data while detecting the third portion of the second data.

40. The memory device according to claim 38, wherein the control logic is further configured to program the second data into the array of memory cells.

41. The first data comprises at least one row, The memory device according to claim 40, wherein the control logic is further configured to control the page buffer to receive each row of the first data based on a first data pattern.

42. The first data pattern comprises N first data segments with equal data lengths, The sequence of the N first data segments of the first data pattern is the same as the sequence of the first data, The memory device according to claim 41, wherein any two adjacent first data segments of the first data pattern are separated by M first empty segments, where M is a positive integer and M ≥ 2.

43. The memory device according to claim 42, wherein each portion of the first data comprises a first data segment of the first data pattern.

44. The memory device according to claim 42, wherein the data length of each first data segment is less than or equal to the bandwidth of the data path bus.

45. The second data set described above has M columns, The memory device according to claim 42, wherein the control logic is further configured to program each column of the second data into the memory cell based on the second data pattern.

46. The memory device according to claim 45, wherein the control logic is further configured to program the second data into the memory cell in single-level memory cell (SLC) mode.

47. The second data pattern comprises N data groups, each having M second data segments of equal length from the M columns of the second data, Any two adjacent data groups of the N data groups in the second data pattern are separated by a second empty segment, and each second empty segment is associated with the first data segment. The memory device according to claim 46, wherein the first data segment, the second data segment, the first empty segment, and the second empty segment are configured to have equal data lengths.

48. The memory device according to claim 47, wherein each of the second plurality of data comprises one data group of the N data groups of the second data pattern.

49. The memory device according to claim 47, wherein each of the M second data segments of each of the N data groups is assigned an error detection and correction (ECC) code.

50. The memory device according to claim 47, wherein the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

51. The memory device according to claim 47, wherein the control logic is further configured to control the page buffer to detect the second data from the memory cell to the page buffer based on the second data pattern.

52. The memory device according to claim 47, wherein the control logic is further configured to control the page buffer to generate a third data having a third data pattern by performing an OR or AND operation on the first data and the second data.

53. The third data pattern is, The N first data segments from the first data pattern, The system comprises N data groups, each having M second data segments from the second data pattern, The memory device according to claim 52, wherein the M first empty segments between the i-th first data segment and the (i+1)th first data segment of the N first data segments are replaced by the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

54. Each of the at least one processing unit is A convolution operation is performed based on the i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups. The memory device according to claim 53, comprising M processing elements configured as follows.

55. Each of the above control logics further, The memory device according to claim 53, configured to control the page buffer to transmit the i-th first data segment and the M second data segments to the M processing elements.

56. Each of the at least one processing unit is The i-th first data segment is assigned to each of the M processing elements, Based on the sequence of the M second data segments, the M second data segments are assigned one by one to the M processing elements. The memory device according to claim 55, comprising a control element configured as follows.

57. The array of memory cells is divided into more than one plane of memory cells, The number of the at least one processing unit is equal to the number of planes of the memory cell, The memory device according to claim 54, wherein each processing unit corresponds to one of the corresponding planes of more than one of the memory cells.

58. The array of memory cells is divided into more than one plane of memory cells, The memory device according to claim 54, wherein the number of the at least one processing unit is less than the number of planes of the memory cell.

59. The number of the at least one processing unit is half the number of the planes of the memory cell, The memory device according to claim 58, wherein each processing unit corresponds to two corresponding planes of a memory cell.

60. The number of the at least one processing unit is one-quarter of the number of planes of the memory cell, The memory device according to claim 58, wherein each processing unit corresponds to one of the four corresponding planes of the memory cell.

61. The number of the aforementioned at least one processing unit is 1, The memory device according to claim 58, wherein the one processing unit corresponds to more than one plane of the memory cell.

62. The memory device according to claim 38, wherein the memory device is a NAND flash memory.

63. A memory cell array and A memory device comprising a peripheral circuit coupled to the memory cell, wherein the peripheral circuit is A page buffer configured to store first data transmitted from the data interface of the memory device and to detect second data from the array of memory cells, At least one processing unit configured to be coupled to the page buffer via the data path bus of the peripheral circuit and to perform calculations based on the first data and the second data, A memory device comprising, A controller is coupled to the memory device and configured to transmit the first data to the memory device and to receive the results of the calculation from the memory device. A system that includes these features.

64. The system according to claim 63, wherein the controller is further configured to transmit the second data to the memory device.

65. The system according to claim 63, wherein the memory device is a NAND flash memory.

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