Switching modeling system and related methods for power semiconductor devices

Abstract

An implementation of a product system model file generation system may include one or more hardware processors and a first interface generated by a computing device to receive from a user a selection of a product SPICE model for a product including at least one switch; a second interface to receive from a user a selection of at least partial soft-switching process conditions; a third interface to receive from a user a selection of one or more system characteristics and one or more operating characteristics; a fourth interface to receive from a user a selection of one or more circuit parameters including a simulation circuit including at least two switches; and generating a SPICE model output using a SPICE model simulation module and formatting the SPICE model output into a product system model file using a formatting module.

Description

Technical Field

[0001] Aspects of the present document generally relate to the simulation of electronic systems. More specific implementations include systems and methods for simulating a system that includes a semiconductor die.

Background Art

[0002] Semiconductor dies are incorporated into larger electronic systems, such as motherboards or circuit boards, by being directly attached or attached via a packaging system attached to the semiconductor die. The motherboard or circuit board is designed to supply / receive specific electronic signals from the semiconductor die during operation.

Summary of the Invention

[0003] An implementation of a method for generating a product system model file may include selecting a product SPICE model for a product including at least one switch using a first interface generated by a processor and computing device, and selecting at least partial soft-switching process conditions using a second interface generated by a processor and computing device. The method may also include receiving one or more system characteristics and one or more operating characteristics from a user using a third interface generated by a computing device, and receiving one or more circuit parameters from a user using a fourth interface generated by a computing device, wherein the one or more circuit parameters include a simulation circuit including at least one switch. The method may also include generating a SPICE model output having a product SPICE model, at least partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters using a processor and a formatting module, and formatting the SPICE model output into a product system model file using a processor and a formatting module.

[0004] The implementation of the method for generating the product system model file may include one, all, or any of the following:

[0005] Product system model files can be configured to be used to perform system-level simulations of the system containing the product.

[0006] The simulation circuit may further include a resonant inductor coupled to at least one switch.

[0007] The simulation circuit may further include a shunt resistor coupled to at least one switch.

[0008] One or more circuit parameters may further include gate resistance, gate inductance, gate loop inductance, source inductance, loop inductance, diode voltage, and any combination thereof.

[0009] One or more circuit parameters may further include one of the following: shunt resistor, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic elements in the switching loop, and any combination thereof.

[0010] One or more system characteristics may include the output capacitance of at least one switch's output capacitor.

[0011] One or more operating characteristics may include the bus voltage.

[0012] One or more system characteristics may include the inductance value of the resonant inductor.

[0013] One or more operating characteristics may include the maximum transition time for switching at least one switch.

[0014] Generating a SPICE model output may further involve using the current of the resonant inductor prior to the switching event of at least one switch, and using the rate of change of the current of the resonant inductor prior to the switching event of at least one switch.

[0015] An implementation of the product system model file generation system may include one or more hardware processors configured with machine-readable instructions to receive from a user a selection of a product SPICE model for a product including at least one switch, using a first interface generated by a computing device, and to receive from a user a selection of at least partial soft-switching process conditions, using a second interface generated by a computing device. The system may also include receiving from a user a selection of one or more system characteristics and one or more operating characteristics, using a third interface generated by a computing device, and receiving from a user a selection of one or more circuit parameters, including a simulation circuit including at least two switches, using a fourth interface generated by a computing device. The system may also include generating a SPICE model output having a product SPICE model, at least partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters, using a SPICE model simulation module, and formatting the SPICE model output into a product system model file, using a formatting module.

[0016] The implementation of the product system model file generation system may include one, all, or any of the following:

[0017] Product system model files can be configured to be used to perform system-level simulations of the system containing the product.

[0018] The simulation circuit may further include a resonant inductor coupled to at least one switch.

[0019] The simulation circuit may further include a shunt resistor coupled to at least one switch.

[0020] One or more circuit parameters may further include one of the following: shunt resistor, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic elements in the switching loop, and any combination thereof.

[0021] One or more system characteristics may include the output capacitance of at least one switch's output capacitor.

[0022] One or more system characteristics may include the inductance value of the resonant inductor.

[0023] One or more operating characteristics may include the maximum transition time and bus voltage for switching at least one switch.

[0024] Using the SPICE model simulation module to generate SPICE model output in a product SPICE model may further include using the current of the resonant inductor before the switching event of at least one switch, and using the rate of change of the current of the resonant inductor before the switching event of at least one switch.

[0025] Implementations of a method for generating a product system model file may include using one or more processors and one or more interfaces generated by a computing device associated with a user. The method may include selecting a product SPICE model for a product having at least one switch, selecting partial soft-switching process conditions, and receiving one or more system characteristics and one or more operating characteristics. The method may include receiving one or more circuit parameters for a simulation circuit including at least one switch, and using a SPICE model simulation module to generate a SPICE model output having the product SPICE model, the partial soft-switching process conditions, the one or more system characteristics, the one or more operating characteristics, and the one or more circuit parameters. The method may include formatting the SPICE model output into a product system model file using a formatting module.

[0026] The above and other aspects, features, and advantages will be apparent to those skilled in the art from the "Detailed Description of the Invention" and the "Drawings" and from the "Claims".

Brief Description of the Drawings

[0027] Embodiments will be described below with reference to the accompanying drawings. In the drawings, like reference numerals indicate like elements. [Figure 1] It is a schematic diagram of an RLC equivalent circuit of a circuit including at least two semiconductor switches. [Figure 2] It is a graph of the current flowing through the resonant inductor and a graph showing the rate of change of the voltage VSwt at the position shown in FIG. 1. [Figure 3] It is a schematic timing diagram of one implementation of a half-bridge circuit operating in boost mode during the hard-switching operation of a double-pulse test. [Figure 4] It is a schematic timing diagram of one implementation of a half-bridge circuit operating in buck mode during the hard-switching operation of a double-pulse test. [Figure 5] This is a schematic timing diagram of one implementation of a half-bridge circuit operating in boost mode during soft switching operation. [Figure 6] This is a schematic timing diagram of one implementation of a half-bridge circuit operating in buck mode during soft switching operation. [Figure 7] Figures 3 to 6 show the four quadrants of the operation of the half-bridge circuit during hard and soft switching. [Figure 8] This is a schematic diagram of a simulation circuit for two semiconductor switches. [Figure 9] This is a block diagram of one implementation configuration of a switching modeling system. [Figure 10] This is a flowchart illustrating one implementation of a method for generating a product system model. [Modes for carrying out the invention]

[0028] The present disclosure, its embodiments, and implementations are not limited to any specific components, assembly procedures, or method elements disclosed herein. Many additional components, assembly procedures, and / or method elements known in the art, consistent with the intended switching modeling system and associated method, will become apparent for use with any particular implementation from the present disclosure. For example, while a particular implementation is disclosed, such implementations and implementation components may include any shape, size, style, type, model, version, dimension, concentration, material, quantity, method element, step, and others known in the art with respect to such switching modeling system, and implementation components and methods, consistent with the intended operation and method.

[0029] Various implementations of a system and method for creating product system model files are disclosed in U.S. Patent Application No. 18 / 058,382 by Xiao et al., filed November 23, 2022, entitled "Automated Power Discrete and Module Model Generation for System Level Simulators," the entire disclosure of which is incorporated herein by reference (Application 382). The product system model files are then used by various system-level simulators used by circuit designers during circuit design. The product SPICE models of semiconductor products disclosed herein are derived through modeling performed using either or both of the modeling processes disclosed in Victory et al.'s U.S. Patent No. 1,1481532, “Systems and Methods for Designing a Discrete Device Product” ('522 patent), issued on 25 October 2022, and Victory et al.'s U.S. Patent No. 1,1481533, “Systems and Methods for Designing a Module Semiconductor Product” ('533 patent), issued on 25 October 2022, similar to those disclosed in the '382 application, the respective disclosures being incorporated herein in their entirety by reference. Accordingly, the term “product SPICE model” as used herein means the same as the corresponding “product SPICE model” as used in the '532 patent and the '533 patent, respectively. These product SPICE models are the result of significant simulations that take into account the electrical / thermal properties of one or more semiconductor dies, and the electrical / thermal properties of the corresponding packages used to bond the one or more semiconductor dies and provide electrical / thermal connections to the circuit or motherboard to which the semiconductor products are bonded. Implementations of the various systems and methods disclosed herein utilize product SPICE models, such as those disclosed in patents 532 and 533, to create product system model files that can be used by various system-level simulators used by circuit designers during circuit design.These product system model files can take the form of structured text files, plain text files, or delimited text files in various implementations. In some implementations, the product system model file may be a structured text file in XML format, structured for use with the Piecewise Linear Electrical Circuit Simulation (PLECS) system-level simulator (PLECS model) commercially available from Plexim (Zurich, Switzerland). In other implementations, the product system file may be a structured text, plain text, or delimited text file that can be used with other system-level simulator types, such as those commercially available from Powersim, Inc. (Rockville, MD) under the trademark PSIM, or any other system-level simulator.

[0030] For semiconductor packages and modules including switching semiconductor devices (switches), various system simulators, such as those disclosed herein and in Patent Application 382, ​​utilize hard-switching double-pulse testing to model energy loss and operation. In hard switching, the energy stored in the switch's output capacitor is lost within the switch primarily during the turn-on period of the test; therefore, during the turn-off portion of the test, the output capacitor must be refilled to cause a switch transition. However, under certain operating conditions, a semiconductor switch can operate using soft switching / soft-switching operation. In soft switching, some or all of the energy stored in the switch's output capacitor is recycled back to the output capacitor with the help of a resonant tank generated by an inductor coupled to the switch. The ability to recycle some or all of the energy in the switch's output capacitor helps reduce switching power loss and can improve the overall power efficiency of the switching semiconductor package / system.

[0031] Double-pulse testing works well for developing product system model files for semiconductor packages containing semiconductor switches operating in hard-switching mode / operation. However, double-pulse testing does not accurately predict / measure the lower losses experienced by semiconductor switches operating with / in soft-switching mode. This is partly because soft-switching mode operates continuously from some soft-switching to all soft-switching. Also, double-pulse testing ignores the effects of circuits that generate resonant tanks. This can lead to significant errors in simulations performed using product system model files obtained by system-level simulators during circuit design. The ability to accurately develop product system model files that capture the operation of a given semiconductor package containing switches may be particularly important for circuit designs where operation is, or is capable of, operating in at least partial soft-switching mode. Non-limiting examples of such applications and circuit designs where at least partial soft-switching may occur include resonant half-bridge converters, DC-DC LLC designs, CLLC resonant designs, dual active-bridge designs, and phase-shifted full-bridge designs.

[0032] Soft switching, or partial zero-volt transition (ZVT), or partial zero-volt switching (ZVS), occurs when a resonant inductor and the output capacitor of a semiconductor switch resonate, causing a transition during a voltage swing from one rail to the other during the delay between the turn-off and turn-on events. During the transition delay, both switches (in the case of a half-bridge device) are off during this transition. At the end of the transition, electrical conduction begins at the switch's body diode, and Eon is negative. Also, the voltage reaches the other rail in time or during the delay period, resulting in a partial transition with a positive Eon but with smaller switching losses than Eon in a hard-switching system. To initiate a soft-switching transition, the resonant inductor current in the inductor electrically coupled to the semiconductor switch moves in the opposite direction to the energy transfer or turn-off body diode forward current. The total amount of energy in the resonant tank formed by the inductor is important in determining whether a soft-switching transition can occur. This total energy within the resonant tank is, as an unrestricted example, proportional to the current in the inductor (resonant inductor), the rate of change of the current in the resonant inductor, the voltage stored in the output capacitor of the semiconductor switch, the bus voltage, and the load reflection voltage by the isolation transformer. The energy within the resonant tank may also, as an unrestricted example, depend on the structure of the inductor-capacitor-resistor network within a particular semiconductor switch / semiconductor package, and the delay between the timings in which each of the two switches changes state. For example, the amount of delay between when the high-side switch turns off and the low-side switch turns on can affect whether the two switches operate partially or fully in soft-switching mode.

[0033] Referring to Figure 1, an equivalent circuit 2 of a semiconductor package containing a semiconductor switch for use in the simulation is shown. Here, the voltage monitored during the switching transition is the VSwt point 4 adjacent to the capacitor Cr6. Figure 2 shows a graph of the rate of change of the voltage VSwt against a set of delay values ​​between the current through the resonant inductor Lr8 adjacent to the shunt resistor Rs10 and the time when one switch turns off and the other switches turn on (X axis of the voltage graph). The shaded region 12 of the voltage graph indicates the maximum possible region where partial soft switching of the semiconductor package is observed at lower energies within the resonant tank formed by the resonant inductor Lr8. The shaded region 12 corresponds to a delay value of approximately 250–300 nanoseconds (ns). The simulation shown in Figure 2 was performed with a bus voltage VBus of 400V, I0 of -1A, shunt resistor (Rs) of 1 megaohm, inductance of Lr of 10 microhenries, and capacitance of Cr of 1 nanofarad. The di / dt variable was varied stepwise from dt of 10ns, 20ns, 23ns, 25ns, 27ns, 50ns, and 100ns, and the resulting current and voltage values ​​were plotted in Figure 2 for simulation. The graph shows the effect of the rate of change of current in the resonant inductor Lr8. Figures 1 and 2 show that, in the case of a given semiconductor switching system, the system can operate in soft-switching mode at least partially under specific operating conditions.

[0034] Figures 3-6 show the operation of a half-bridge circuit with two semiconductor switches during hard switching operation and soft switching operation during a double-pulse test. In Figure 3, a half-bridge circuit 14 having a low-side switch 16 and a high-side switch 18 is shown coupled to an inductor 22. Here, during the double-pulse test, the switches 16 and 18 are driven on the low side, similar to the boost mode. When the high-side switch 18 is turned off, current continues to flow through the body diode represented by diode 24, allowing the output capacitor of the high-side switch 18, represented by capacitor 26, to discharge to the low-side switch via the inductor 22, resulting in a charge loss. Similarly, referring to Figure 4, when the half-bridge circuit 14 is driven by the high-side switch 18 as in the back mode, when the low-side switch 16 is turned off, current continues to flow through the body diode of the low-side switch, represented by diode 28. This similarly causes the charge of the output capacitor of the low-side switch 16, represented by capacitor 30, to flow to the high-side switch 18 and be lost. Therefore, the double pulse test of the half-bridge circuit assumes that the inductor 22 does not store any energy in the capacitor, and thus the charge on the output capacitors of the low-side switch 16 and the high-side switch 18 is completely lost.

[0035] However, different operating conditions exist for soft switching, and referring to Figure 5, the half-bridge circuit 14 in boost mode when the low-side switch is turned off is shown. Here, as shown in the figure, due to the energy stored in the inductor 22, current cannot flow through the body diode represented by diode 28, and the discharge of the charge of the output capacitor of the low-side switch 16 represented by capacitor 30 is prevented. This means that in back mode, at least a portion of the original charge of the output capacitor of the low-side switch 16 is still present in the output capacitor when the low-side switch is turned on. As shown in Figure 6, a similar operation is observed in soft switching operation during back mode operation, and when the high-side switch 18 is turned off, the energy stored in the inductor 22 again prevents current from flowing through the body diode represented by diode 24. This prevents at least a portion of the charge of the output capacitor of the high-side switch 28 represented by capacitor 26 from discharging, and the charge is retained for recycling when the high-side switch 18 is turned on again. Since the energy is temporarily stored in the inductor 22 with appropriate energy and delay timing, this soft switching operation occurs with appropriate energy values ​​and current change rates.

[0036] In soft switching, energy completes the soft transition, depending on the current and the rate of change of current (di / dt). In double-pulse testing, di / dt always increases, but in soft switching, di / dt can decrease, reducing the amount of resonant energy available for the transition. In soft switching, the goal is to maintain current in the opposite direction to the forward direction of the turn-off switch (high-side or low-side) body diode in all transitions. This allows for the recycling of charge in the switch's output capacitor. Achieving and measuring the soft switching operation of a given circuit requires a more complex test setup than that used for double-pulse (back or boost) testing because it involves changing the rate of change of current (di / dt). This is because double-pulse testing is a specific switching case where di / dt = 0. Achieving partial ZVT depends on the resonant energy (energy in the resonant tank), which is related to the current, di / dt, and voltage bus value, as well as the maximum delay between the high-side and low-side switching events.

[0037] The process described above can be summarized using the chart in Figure 7, which shows the four quadrants of the operation of each switch in the half-bridge circuit 14 in Figures 3 to 6. Hard switching operation is shown in the upper left quadrant 32 and the lower right quadrant 34, respectively, during on and off operation. In the upper left quadrant 32, current from the output capacitor is shown flowing from drain to source, and in the lower right quadrant 34, current from the output capacitor is shown flowing from source to drain. Soft switching operation is shown in the upper right quadrant 36 and the lower left quadrant 38. In the upper right quadrant 36, current flows from drain to source but is blocked by the body diode. In the lower left quadrant 38, current flows from source to drain but is again blocked by the body diode. Figure 7 shows that when using only hard switching in a double-pulse test, the tester can only characterize half of the possible operating states of a given circuit including a semiconductor switch.

[0038] Although the principle described above is explained in relation to a half-bridge circuit involving two switches, the principle disclosed herein can also be applied to the process of testing a semiconductor package containing only one semiconductor switch internally. Those skilled in the art will understand how this can be done using an inductor coupled to a single switch to achieve soft switching conditions under appropriate operating conditions.

[0039] Referring to Figure 8, an implementation of the test setup 40 for a half-bridge circuit showing low-side switch 42 and high-side switch 44 coupled to inductor 44 is shown. During the operation of the test simulation, components of the first measurement module 46 and the second measurement module 48 are used to measure circuit components necessary to calculate Eon and Eoff as various operating and system parameters of the half-bridge circuit change, the operating and system parameters include, in non-limiting examples, bus voltage, current of resonant inductor 44 before a switching event, di / dt of resonant inductor 44 before a switching event, output capacitor capacitance of each switch 42, 44, transition / delay time between switching events, and, in non-limiting examples, any parasitic elements in the switching loop and any combination thereof, including shunt resistor, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic elements in the switching loop, and any combination thereof, or any other operating or system parameters of the electrical circuit. Next, the measurements taken during the simulation using the test setup 40 are used in a product system model file generation system, as disclosed herein, to generate a product system model file for use in a system-level simulator, as disclosed herein. Specific implementations of the product system model file may include, as non-limiting examples, various model parameters such as bus voltage, current of the resonant inductor before a switching event, rate of change of current of the resonant inductor before a switching event (di / dt), resonant inductor value, or other parameters that enable the product system model file to perform soft switching mode modeling by the system-level simulator.

[0040] Referring to Figure 9, a block diagram of an implementation of system 100 for generating a product system model file for use in system-level simulation is shown. In some implementations, system 100 may include one or more computing platforms 102. One or more computing platforms 102 may be configured to communicate with one or more remote platforms 104 according to a client / server architecture, a peer-to-peer architecture, and / or other architecture. One or more remote platforms 104 may be configured to communicate with other remote platforms via one or more computing platforms 102 and / or according to a client / server architecture, a peer-to-peer architecture, and / or other architecture. Users may access system 100 via one or more remote platforms 104. Examples of remote platforms 104 that may be used by users include, as non-biological examples, desktop computers, server computers, laptop computers, smartphones, tablets, or any other portable electronic devices.

[0041] A computing platform (one or more) 102 may consist of machine-readable instructions 106. The machine-readable instructions 106 may include one or more instruction modules. An instruction module may include a computer program module. An instruction module may include one or more of the following: an interface generation module 108, a SPICE model simulation module 110, and a formatting module 112. The interface generation module 108 operates to generate various computing interfaces as shown in Figures 1-4 of the '382 application. The SPICE model simulation module 110 performs a series of simulations using a user-selected product SPICE model stored in a database 114 containing a set of product SPICE models, such as those disclosed in the '382 application and the '532 and '533 patents. The results of these simulations, including the processing of soft-switching operating conditions as disclosed herein, are then processed by the formatting module 112 to form a product system model file. In various implementations, the product system model file may be stored in the database 114 for retrieval by a user or others who wish to access the file.

[0042] In some implementations, the computing platform(s) 102, the remote platform(s) 104, and / or external resources 118 may be operationally linked via one or more electronic communication links. For example, such electronic communication links may be established at least in part via a network such as the Internet and / or other networks. It is not intended to be limiting, and it will be understood that the scope of this disclosure includes implementations in which the computing platform(s) 102, the remote platform(s) 104, and / or external resources 130 may be operationally linked via some other medium of communication.

[0043] A given remote platform 104 may include one or more processors configured to run a computer program module. The computer program module may be configured to enable a professional or user involved with the given remote platform 104 to interface with system 100 and / or external resources 118 and / or to provide other functions attributed herein to the remote platform(s) 104. As a non-limiting example, a given remote platform 104 and / or a given computing platform 102 may include one or more of the following: a server, a desktop computer, a laptop computer, a handheld computer, a tablet computing platform, a netbook, a smartphone, a game console, and / or other computing platforms.

[0044] External resources 118 may include information sources outside of system 100, external entities participating in system 100, and / or other resources. In some implementations, some or all of the functions attributed herein to external resources 130 may be provided by resources included in system 100. As shown in Figure 9, computing platform(s) 102 may include electronic storage / databases 114, one or more processors 116, and / or other components. Computing platform(s) 102 may include communication lines or ports that enable the exchange of information with networks and / or other computing platforms. The illustration of computing platform(s) 102 in Figure 9 is not intended to limit it. Computing platform(s) 102 may include multiple hardware, software, and / or firmware components that work together to provide the functions attributed herein to computing platform(s) 102. For example, a computing platform(s) 102 may be implemented by a cloud of computing platforms that operate together as a computing platform(s) 102.

[0045] A processor(s) 116 may be configured to provide information processing capabilities in a computing platform(s) 102. Thus, a processor(s) 116 may include one or more of the following: a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information. Although the processor(s) 116 is shown as a single entity in Figure 9, this is for illustrative purposes only. In some implementations, a processor(s) 116 may include multiple processing units. These processing units may be physically located within the same device, or the processor(s) 116 may represent the processing capabilities of multiple devices working together. A processor(s) 116 may be configured to run modules 108, 110, and / or 112, and / or other modules. A processor(s) 116 may be configured to run modules 108, 110, and / or 112, and / or other modules by software, hardware, firmware, any combination of software, hardware, and / or firmware, and / or other mechanisms for configuring the processing capabilities on the processor(s) 116. As used herein, the term “module” may refer to any component or set of components that perform the functions attributed to a module. This may include one or more physical processors, processor-readable instructions, circuits, hardware, storage media, or any other components in the process of executing processor-readable instructions.

[0046] Although modules 108, 110, and / or 112 are shown in Figure 9 as being implemented within a single processing unit, please note that in implementations where the processor(s) 116 include multiple processing units, one or more of modules 108, 110, and / or 112 may be implemented remotely from other modules. The descriptions of the functions provided by the different modules 108, 110, and / or 112 described below are for illustrative purposes only and are not intended to limit the functions of any of modules 108, 110, and / or 112, as they may provide more or fewer functions than those described. For example, one or more of modules 108, 110, and / or 112 may be removed, and some or all of their functions may be provided by other modules among modules 108, 110, and / or 112. As another example, processor(s) 116 may be configured to run one or more additional modules that can perform some or all of the functions belonging to one of modules 108, 110, and / or 112.

[0047] Referring to Figure 10, a flowchart of an implementation of a method for generating a product system file 50 is shown. Various method implementations may be performed using any of the system implementations disclosed herein. As shown, the method includes receiving from a user a selection of a product SPICE model for a product including at least one switch (a semiconductor switch, step 52) using a first interface generated by a computing device. In various implementation embodiments, the product may be any of those disclosed in this document or in application 382. The first interface may be an interface having a design as shown in Figure 1 of application 382 in various implementation embodiments. The method further includes receiving from a user a selection of at least partial soft-switching processing conditions / modes which may be any of those disclosed herein using a second interface generated by a computing device (step 54). Application 382 shows a selection of various process conditions, and in various implementations of the method, any of the process conditions disclosed herein may also be selected. In some implementations, the process conditions themselves may actually include at least a partial soft-switching processing condition / mode within a range of process parameters that are modified / tested for a particular selected process condition. In other implementations, the soft-switching selection may be made explicitly. The second interface may have a design as shown in Figure 2 of the 382 application.

[0048] The method also includes receiving one or more system characteristics and one or more operating characteristics from a user using a third interface generated by a computing device (step 56). The third interface may have a design as illustrated in Figure 3 of Application 382 in various implementations. In various implementations of the system and method, one or more system characteristics and one or more operating characteristics may be any of those disclosed in Application 382. In various implementations, one or more system characteristics and one or more operating characteristics may include any of the system characteristics and operating characteristics specified herein that affect soft switching (delay, bus voltage, etc.). The method also includes receiving one or more circuit parameters from a user using a fourth interface generated by a computing device, the one or more circuit parameters may include a simulation circuit including at least one switch (step 58). In some implementations, the simulation circuit may be a circuit as shown in Figure 8. Various implementations of the simulation circuit may include a schematic design of the internal electrical connections of a semiconductor package including switching components for use in identifying specific circuit parameters of components of the circuit to be modified / tested for the user. A fourth interface may be similar to the interface design shown in Figure 4 of the 382 application in various implementations. Specific circuit parameters for a circuit including at least one switch include any of the identified component values ​​(inductance, capacitance, etc.) that affect the soft switching disclosed herein.

[0049] The method also includes using a SPICE simulation module to generate a SPICE model output having a product SPICE model, at least partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters (step 60). The method also includes using a formatting module to format the SPICE model output into a product system model file, which may be formatted in any format disclosed herein or in application 382 (step 62). Here, the method acquires information and uses a product SPICE model (which may be any of those disclosed herein or in application 382) to model at least partial soft-switching operation of the circuit being simulated, and then generates a corresponding product system model file. The resulting product system model file can then be used with a system-level simulator to generate a system simulation that fully captures the effect of soft switching on performance characteristics such as energy consumption, switching timing, or any other desired system characteristics. Because soft-switching operation is captured here, the system simulation may be more accurate than if only double-pulse and / or hard-switching analysis were used on the same circuit design.

[0050] In various methods and system implementations, the simulation circuit may include a resonant inductor coupled to at least one switch, which may be of the inductor type disclosed herein. The method may also include a shunt resistor coupled to at least one switch. In various method implementations, one or more circuit characteristics may further include, as non-limiting examples, gate resistance, gate loop resistance, source inductance, loop inductance, diode voltage, any combination thereof, or any other circuit or device parameter. The method may also include, as non-limiting examples, a shunt resistor, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic elements in the switching loop, any combination thereof, or any other circuit or device parameter affecting the soft switching operation of the product. The method may also include, as one or more system characteristics, the output capacitance of the output capacitor of at least one switch. In various method implementations, one or more operating characteristics may include the inductance value of the resonant inductor. In various method implementations, one or more operating characteristics may include the maximum transition time of switching at least one switch (or the delay between switching of two or more switches). The method may also include, when generating the SPICE model output, using the current of the resonant inductor prior to the switching event of at least one switch, and / or using the rate of change of the current of the resonant inductor prior to the switching event of at least one switch.

[0051] Where the above explanation refers to specific implementation forms of the product system model file generation system and its implementation components, sub-components, methods, and sub-methods, it will be readily apparent that some modifications may be made without deviating from their intent, and that these implementation forms, implementation components, sub-components, methods, and sub-methods may be applicable to other product system model file generation systems and related methods.

Claims

1. A method for generating a product system model file, A step of selecting a product SPICE model for a product including at least one switch using a first interface generated by a processor and computing device, A step of selecting at least partial soft-switching process conditions using a second interface generated by the processor and the computing device, The steps include receiving one or more system characteristics and one or more operational characteristics from the user using a third interface generated by the computing device, A step of receiving one or more circuit parameters from the user using a fourth interface generated by the computing device, wherein the one or more circuit parameters comprise a simulation circuit including at least one switch. The steps of generating a SPICE model output having the product SPICE model, at least partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters using the processor and SPICE model simulation module, The steps include: using the aforementioned processor and formatting module to format the SPICE model output into a product system model file; Methods that include...

2. The method according to claim 1, wherein the product system model file is configured to be used to perform a system-level simulation of a system including the product.

3. The method according to claim 1, wherein the simulation circuit further includes a resonant inductor coupled to the at least one switch.

4. The method according to claim 1, wherein the simulation circuit further includes a shunt resistor coupled to the at least one switch.

5. The method according to claim 1, wherein the one or more circuit parameters further include one of a shunt resistor, a printed circuit board leakage inductance, a decoupling capacitor series resistor, one or more parasitic elements in a switching loop, and any combination thereof.

6. The method according to claim 1, wherein one or more of the system characteristics include the output capacitance of the output capacitor of the at least one switch.

7. The method according to claim 1, wherein one or more of the operating characteristics include a bus voltage.

8. The method according to claim 3, wherein one or more of the system characteristics include the inductance value of the resonant inductor.

9. The method according to claim 1, wherein one or more of the operating characteristics include the maximum switching transition time of at least one switch.

10. The method according to claim 3, wherein generating the SPICE model output further comprises using the current of the resonant inductor prior to the switching event of the at least one switch and using the rate of change of the current of the resonant inductor prior to the switching event of the at least one switch.

11. A method for generating a product system model file, A step of using one or more processors and one or more interfaces generated by a computing device associated with the user, A step of selecting a product SPICE model for a product that includes at least one switch, The steps include selecting partial soft switching process conditions, The steps include receiving one or more system characteristics and one or more operating characteristics, A step of receiving one or more circuit parameters, wherein the one or more circuit parameters include a simulation circuit that includes at least one switch, A step of generating a SPICE model output having the product SPICE model, the partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters using a SPICE model simulation module, The steps include: using a formatting module to format the SPICE model output into a product system model file; Methods that include...

12. A product system model file generation system, It includes one or more hardware processors, and the hardware processors are Using a first interface generated by a computing device, the system receives a selection of a product SPICE model from the user for a product that includes at least one switch. Using a second interface generated by the computing device, the selection of at least partial soft-switching process conditions is received from the user. Using a third interface generated by the computing device, the selection of one or more system characteristics and one or more operational characteristics is received from the user. Using a fourth interface generated by the computing device, the selection of one or more circuit parameters is received from the user, and the one or more circuit parameters include a simulation circuit that includes at least two switches. Using the SPICE model simulation module, a SPICE model output is generated having the product SPICE model, the at least partial soft-switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters. The formatting module is used to format the SPICE model output into a product system model file. A system composed of machine-readable instructions.

13. The system according to claim 12, wherein the product system model file is configured to be used to perform a system-level simulation of a system including the product.

14. The system according to claim 12, wherein the simulation circuit further includes a resonant inductor coupled to the at least one switch.

15. The system according to claim 12, wherein the simulation circuit further includes a shunt resistor coupled to the at least one switch.

16. The system according to claim 12, wherein the one or more circuit parameters further include one of a shunt resistor, a printed circuit board leakage inductance, a decoupling capacitor series resistor, one or more parasitic elements in a switching loop, and any combination thereof.

17. The system according to claim 12, wherein one or more of the system characteristics include the output capacitance of the output capacitor of the at least one switch.

18. The system according to claim 14, wherein one or more of the system characteristics include the inductance value of the resonant inductor.

19. The system according to claim 12, wherein one or more of the operating characteristics include the maximum transition time of switching of at least one switch and the bus voltage.

20. The system according to claim 14, wherein generating a SPICE model output in the product SPICE model using the SPICE model simulation module further comprises using the current of the resonant inductor prior to the switching event of the at least one switch, and using the rate of change of the current of the resonant inductor prior to the switching event of the at least one switch.

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