Carbon-containing cap layer for doped semiconductor epitaxial layers

Abstract

The semiconductor structure includes an alternating stack of doped semiconductor epitaxial layers and capped epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer contains silicon with a carrier dopant, and each capped epitaxial layer contains silicon and carbon that are not doped with a carrier dopant.

Description

[Technical Field]

[0001]

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically to systems and methods for forming doped semiconductor layers and capping layers within a semiconductor structure. [Background technology]

[0002] Explanation of related technologies

[0002] Selective epitaxial technology with phosphorus doping has attracted attention as a method for reducing external transistor resistance at the source / drain of n-type metal oxide semiconductor (MOS) devices. High phosphorus doping is required to ensure low contact resistance when forming metal contacts. However, high concentrations of phosphorus dopant tend to diffuse, hindering control of the doping profile of phosphorus-doped epitaxial layers.

[0003]

[0003] Therefore, there is a need for a method and system that can epitaxially form a doped semiconductor layer that can prevent the diffusion of dopants. [Overview of the Initiative]

[0004]

[0004] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes an alternating stack of doped semiconductor epitaxial layers and capped epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer contains silicon having a carrier dopant, and each capped epitaxial layer contains silicon and carbon that are not doped with a carrier dopant.

[0005]

[0005] Embodiments of the present disclosure also provide a method for forming a doped semiconductor layer within a semiconductor structure. The method comprises performing a plurality of cycles of a first deposition process, a second deposition process following the first deposition process, and an etching process. The first deposition process forms a doped semiconductor layer on the exposed surface of a substrate. The second deposition process forms an undoped cap layer on the doped semiconductor layer. The etching process selectively removes amorphous portions of the undoped cap layer and the amorphous portions of the doped semiconductor layer, leaving the epitaxial portions of the undoped cap layer and the epitaxial portions of the doped semiconductor layer. The doped semiconductor layer contains silicon having a carrier dopant, and the undoped cap layer contains carbon.

[0006]

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a processing chamber and a system controller configured to cause the processing system to perform a plurality of cycles of a first deposition process, a second deposition process following the first deposition process, and an etching process. The first deposition process forms a doped semiconductor layer on the exposed surface of a substrate. The second deposition process forms an undoped cap layer on the doped semiconductor layer. The etching process selectively removes amorphous portions of the undoped cap layer and the amorphous portions of the doped semiconductor layer, leaving the epitaxial portions of the undoped cap layer and the epitaxial portions of the doped semiconductor layer. The doped semiconductor layer contains silicon having a carrier dopant, and the undoped cap layer contains carbon.

[0007]

[0007] To allow for a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] This is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2]

[0009] This is a cross-sectional view of a processing chamber according to one or more embodiments. [Figure 3]

[0010] This is a cross-sectional view of a semiconductor structure including a doped semiconductor layer and a capping layer according to one or more embodiments. [Figure 4]

[0011] This is a process flow diagram of a method for forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure. [Figures 5A-5D]

[0012] Figure 4 shows a cross-sectional view of a portion of the semiconductor structure corresponding to various states of the method. [Figure 5E-5F] Figure 4 shows a cross-sectional view of a portion of the semiconductor structure corresponding to various states of the method. [Modes for carrying out the invention]

[0009]

[0013] For ease of understanding, the same reference numerals were used to indicate identical elements common to multiple figures where possible. It is assumed that elements and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0010]

[0014] Embodiments described herein provide a method and system for forming doped semiconductor epitaxial layers in which dopant diffusion is prevented by adjacent capped epitaxial layers. The doped semiconductor epitaxial layer contains a high concentration of silicon and a carrier dopant. The capped epitaxial layer contains silicon and carbon and is not doped with a carrier dopant. Multiple pairs of doped semiconductor epitaxial layers and capped epitaxial layers interposed within the doped semiconductor epitaxial layer are formed and can be used as source / drain in n-type metal oxide semiconductor (NMOS) devices. Because dopant diffusion is prevented, a sharper doping profile can be achieved. Furthermore, tensile strain induced in the capped epitaxial layer can improve electron mobility, resulting in high conductivity in device applications.

[0011]

[0015] This method includes periodic deposition and etching processes that enable the selective epitaxial growth of doped semiconductor layers and capped layers.

[0012]

[0016] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having transfer robots 112, 114 respectively, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., the atmospheric environment that may be present in the factory). For example, substrates can be processed in various chambers and transferred between various chambers during various processes performed on the substrates in the processing system 100, without disrupting the low-pressure or vacuum environment, while being maintained in a low-pressure (e.g., about 300 Torr or less) or vacuum environment. Therefore, the processing system 100 can provide an integrated solution for processing a portion of the substrate.

[0013]

[0017] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integration processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California, or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, can be adapted to benefit from the aspects described herein.

[0014]

[0018] In the example shown in FIG. 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of each factory interface robot 134 adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0015]

[0019] The load lock chambers 104 and 106 each have ports 140 and 142 connected to the factory interface 102, and ports 144 and 146 connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150 connected to the holding chambers 116 and 118, and ports 152 and 154 connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158 connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166 connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be slit valve openings having slit valves for sealing the spaces between chambers to prevent gas from passing between them, for example, when substrates are passed through by transfer robots 112 and 114. Generally, any port is open for the transfer of substrates. Otherwise, the port is closed.

[0016]

[0020] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidly connected to a gas and pressure control system (not particularly shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), a gas source, various valves, and conduits fluidly connected to the various chambers. During operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via the port 140 or 142. Next, the gas and pressure control system pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, the pumping down of the load lock chamber 104 or 106 facilitates passing the substrate between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0017]

[0021] With the substrate in the load lock chamber 104 or 106 pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 via port 144 or 146. The transfer robot 112 can then transfer the substrate to either the processing chambers 120 or 122 via their respective processing ports 152 or 154, and / or to the holding chambers 116 or 118 via their respective ports 148 or 150 to hold it awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 via port 156 or 158, and transfer the substrate to either the processing chambers 124, 126, 128 or 130 via their respective ports 160, 162, 164 or 166, and / or to the holding chambers 116 or 118 via their respective ports 156 or 158 to hold it awaiting further transfer. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0018]

[0022] Processing chambers 120, 122, 124, 126, 128, and 130 may be any suitable chamber for processing the substrate. In some embodiments, processing chamber 120 may perform an etching process, processing chamber 122 may perform a cleaning process, processing chamber 124 may perform a selective removal process, and processing chambers 126, 128, and 130 may perform their respective epitaxial growth processes. Processing chamber 120 may be a Selectra® etching chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 122 may be a SiCoNi® pre-cleaning chamber available from Applied Materials, Inc., Santa Clara, California. Processing chambers 126, 128, or 130 may be Centura® epi chambers available from Applied Materials, Inc., Santa Clara, California.

[0019]

[0023] The system controller 168 is connected to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. During operation, the system controller 168 enables data acquisition and feedback from each chamber to adjust the performance of the processing system 100.

[0020]

[0024] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor available for use in an industrial setting. Memory 172, or non-temporary computer-readable media, is accessible by the CPU 170 and may be one or more of the following types of memory: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or other forms of local or remote digital storage. Support circuitry 174 is connected to the CPU 170 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein can generally be implemented by the CPU 170 executing computer instruction code stored, for example, as software routines in memory 172 (or memory of a particular process chamber) under the control of the CPU 170. Once the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to execute a process according to various methods.

[0021]

[0025] Other processing systems can be implemented in other configurations. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0022]

[0026] Figure 2 is a cross-sectional view of a processing chamber 200 adapted to perform an epitaxial (Epi) deposition process, as described in detail below, according to one or more embodiments. The processing chamber 200 may be the processing chambers 126, 128, or 130 shown in Figure 1.

[0023]

[0027] The processing chamber 200 includes a housing structure 202 made of a process-resistant material such as aluminum or stainless steel (e.g., 216L stainless steel). The housing structure 202 encompasses various functional elements of the processing chamber 200, such as a quartz chamber 204 containing an upper quartz chamber 206, and a lower quartz chamber 208 containing the processing space 210. Reactant species are supplied to the quartz chamber 204 by a gas distribution assembly 212, and processing byproducts are removed from the processing space 210 by an outlet port 214, which typically communicates with a vacuum source (not shown).

[0024]

[0028] A substrate support 216 is adapted to receive a substrate 218 to be transferred to a processing space 210. The substrate support 216 is positioned along the longitudinal axis 220 of the processing chamber 200. The substrate support 216 may be made of a ceramic material, or a graphite material coated with a silicon material such as silicon carbide, or other process-resistant material. Reactant species from precursor reaction materials are applied to the surface 222 of the substrate 218, and by-products can then be removed from the surface 222 of the substrate 218. Heating of the substrate 218 and / or the processing space 210 may be provided by radiation sources such as an upper lamp module 224A and a lower lamp module 224B.

[0025]

[0029] In one embodiment, the upper lamp module 224A and the lower lamp module 224B are infrared (IR) lamps. Non-thermal energy or radiation from lamp modules 224A and 224B passes through the upper quartz window 226 of the upper quartz chamber 206 and through the lower quartz window 228 of the lower quartz chamber 208. Cooling gas for the upper quartz chamber 206 enters through the inlet 230 and exits through the outlet 232, if necessary. Precursor reaction materials, as well as diluents, purge gases, and vent gases for the processing chamber 200, enter through the gas distribution assembly 212 and exit through the outlet port 214. Although the upper quartz window 226 is shown as curved or convex, the upper quartz window 226 may be flat or concave, since the pressure on both sides of the upper quartz window 226 is substantially the same (i.e., atmospheric pressure).

[0026]

[0030] The low-wavelength radiation in the processing space 210, used to excite the reactants and assist in the adsorption of reactants and the desorption of process by-products from the surface 222 of the substrate 218, is typically in the range of about 0.8 μm to about 1.2 μm, for example, in the range of about 0.95 μm to about 1.05 μm, and various wavelength combinations are provided depending on the composition of the epitaxially grown film, for example.

[0027]

[0031] The component gases enter the processing space 210 via a gas distribution assembly 212. The gases flow out of the gas distribution assembly 212 and exit through the outlet port 214, as generally indicated by the flow path 234. The combination of component gases used for cleaning / passivating the substrate surface or for forming an epitaxially grown silicon and / or germanium-containing film is typically mixed before entering the processing space 210. The overall pressure within the processing space 210 can be regulated by a valve (not shown) at the outlet port 214. At least a portion of the inner surface of the processing space 210 is covered by a liner 236. In one embodiment, the liner 236 comprises an opaque quartz material. In this way, the chamber wall is insulated from the heat within the processing space 210.

[0028]

[0032] The surface temperature within the processing space 210 can be controlled within a temperature range of approximately 200°C to approximately 600°C or higher by the flow of cooling gas passing through the inlet 230 and exiting through the outlet 232, in combination with radiation from the upper lamp module 224A located above the upper quartz window 226. The temperature within the lower quartz chamber 208 can be controlled within a temperature range of approximately 200°C to approximately 600°C or higher by adjusting the speed of a blower unit (not shown) and by radiation from the lower lamp module 224B located below the lower quartz chamber 208. The pressure within the processing space 210 can be approximately 0.1 Torr to approximately 600 Torr, for example, approximately 5 Torr to approximately 30 Torr.

[0029]

[0033] The temperature of the surface 222 of the substrate 218 can be controlled by power adjustment for the lower lamp module 224B in the lower quartz chamber 208, or by power adjustment for both the upper lamp module 224A overlapping the upper quartz window 226 and the lower lamp module 224B in the lower quartz chamber 208. The power density in the processing space 210 is approximately 40 W / cm². 2 ~about 400W / cm 2 For example, approximately 80 W / cm² 2 ~Approx. 120W / cm 2 It is possible.

[0030]

[0034] In one embodiment, the gas distribution assembly 212 is positioned perpendicular or radially 238 to the longitudinal axis 220 of the processing chamber 200 or the substrate 218. In this orientation, the gas distribution assembly 212 is adapted to flow the process gas radially 238 across the surface 222 of the substrate 218, or parallel to the surface 222 of the substrate 218. In some processing applications, the process gas is preheated when introduced into the processing chamber 200, initiating preheating of the gas before it is introduced into the processing space 210, and / or breaking specific bonds in the gas. In this way, the surface reaction kinetics can be modified independently of the thermal temperature of the substrate 218.

[0031]

[0035] During operation, precursors used to form silicon (Si) and silicon-germanium (SiGe) blanket films or selective epitaxial films are supplied to the gas distribution assembly 212 from one or more gas sources 240A and 240B. An IR lamp 242 (only one is shown in Figure 2) may be used to heat the precursors within the gas distribution assembly 212 and along the flow path 234. The gas sources 240A and 240B may be connected to the gas distribution assembly 212 in a manner adapted to facilitate introduction zones within the gas distribution assembly 212, such as radially outer zones and radially inner zones between the outer zones, as viewed from a top view. The gas sources 240A and 240B may include valves (not shown) for controlling the introduction rate into the zones.

[0032]

[0036] Gas sources 240A and 240B may contain silicon precursors such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher silanes, their derivatives, and combinations thereof. Gas sources 240A and 240B may also contain germanium-containing precursors such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), their derivatives, and combinations thereof. Silicon and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. Gas sources 240A and 240B may contain one or more silicon and germanium-containing precursors in one or both of gas sources 340A and 340B.

[0033]

[0037] In this excited state, the precursor material enters the processing space 210 through the opening or hole 244 (only one is shown in Figure 2) of the perforating plate 246. In one embodiment, the perforating plate 246 is made of quartz material and has holes 244 formed therein. The perforating plate 246 may be transparent to IR energy and may be made of clear quartz material. In other embodiments, the perforating plate 246 may be any material that is transparent to IR energy and resistant to process chemicals and other processing chemicals. The energized precursor material flows through the hole 244 of the perforating plate 246 toward the processing space 210 and through the channel 248 (only one is shown in Figure 2). Photons and a portion of the non-thermal energy from the IR lamp 242 also pass through the hole 244, perforating plate 246, and channel 248, facilitated by reflective material and / or surfaces placed on the inner surface of the gas distribution assembly 212, thereby illuminating the flow path 234 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained from the moment it is introduced into the processing space 210 along the flow path.

[0034]

[0038] Figure 3 is a cross-sectional view of a semiconductor structure 300 including a doped semiconductor layer and a capping layer according to one or more embodiments of the present disclosure. A doped semiconductor layer doped with an n-type carrier dopant such as phosphorus can be used as a source / drain in an n-type metal oxide semiconductor (NMOS) device.

[0035]

[0039] The semiconductor structure 300 includes a substrate 302 and an alternating stack of doped semiconductor epitaxial layers 304E and capped epitaxial layers 306E interposed between the doped semiconductor epitaxial layers 304E, formed on the substrate 302.

[0036]

[0040] As used herein, the term "substrate" refers to a layer of material that functions as a base for subsequent processing operations and includes a surface to be cleaned. The substrate can be a silicon-based material, any suitable insulating material, or a conductive material as needed. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0037]

[0041] The doped semiconductor epitaxial layer 304E is formed of silicon (Si) or silicon germanium (SiGe) with a germanium (Ge) ratio in the range of 20% to 100%. The doped semiconductor epitaxial layer 304E can be doped with an n-type carrier dopant such as phosphorus (P) or antimony (Sb) at a concentration of about 10 19 cm -3 ~5×10 21 cm -3 depending on the desired conductive characteristics of the semiconductor structure 300. The doped semiconductor epitaxial layer 304E can be doped with a p-type carrier dopant such as boron (B), gallium (Ga), aluminum (Al), or indium (In) at a concentration of about 10 20 cm -3 ~5×10 21 cm -3 depending on the desired conductive characteristics of the semiconductor structure 300.

[0038]

[0042] The capped epitaxial layer 306E can be formed from undoped carbon (C), carbon-doped silicon (Si:C), or carbon-doped silicon germanium (SiGe:C). The capped epitaxial layer 306E does not need to be doped with carrier dopants. In the capped epitaxial layer 306E, strain is induced by substitution doping, where carbon atoms replace silicon atoms or germanium atoms in the crystal structure. For example, substituting silicon (Si) atoms with carbon (C) induces tensile strain due to the difference in lattice constants between silicon (Si) (e.g., 5.431 Å in crystalline silicon (Si)) and carbon (C) (e.g., 3.567 Å in diamond carbon), and the difference in lattice constants between germanium (Ge) and carbon (C). Furthermore, substituting germanium (Ge) atoms with carbon (C) induces tensile strain due to the difference in lattice constants between germanium (Ge) (e.g., 5.65 Å for crystalline germanium (Ge)) and carbon (C). The strain-induced capped epitaxial layer 306 prevents the migration of carrier dopants (e.g., phosphorus (P)) from the adjacent doped semiconductor epitaxial layer 304E, thus providing a sharp doping profile. In addition, the strain-induced capped epitaxial layer 306 increases electron mobility, thus resulting in high conductivity in potential device applications.

[0039]

[0043] Each doped semiconductor epitaxial layer 304E may have a thickness of approximately 15 Å to approximately 20 Å. Each capped epitaxial layer 306E may have a thickness of approximately 5 Å to approximately 15 Å. The semiconductor structure 300 may have approximately 30 pairs of doped semiconductor epitaxial layers 304E and capped epitaxial layers 306E, with a total thickness of approximately 500 Å to approximately 700 Å, for example, approximately 600 Å.

[0040]

[0044] Figure 4 shows a process flow diagram of a method 400 for forming a doped semiconductor layer within a semiconductor structure 300 according to one or more embodiments of the present disclosure. Figures 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of portions of the semiconductor structure 300 corresponding to various states of the method 400. It should be understood that Figures 5A, 5B, 5C, 5D, 5E, and 5F show only partial schematic diagrams of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor sections, dielectric layers, and additional materials not shown in the figures. It should also be noted that although the method shown in Figure 4 is described in order, other process sequences including one or more steps that are omitted and / or added, and / or rearranged in a different preferred order are also included within the scope of the embodiments of the disclosure provided herein.

[0041]

[0045] Method 400 begins with block 410, and a first deposition process is performed to form a doped semiconductor layer 304 on the exposed surface of the substrate 302, as shown in Figure 5A. The first deposition process may include any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) by flowing a deposition gas in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1, or processing chamber 200 shown in Figure 2.

[0042]

[0046] The doped semiconductor layer 304 is formed of silicon (Si) or silicon germanium (SiGe) with a germanium (Ge) ratio in the range of 20% to 100%. The doped semiconductor layer 304 is formed of approximately 10 depending on the desired conductivity characteristics of the semiconductor structure 300. 19 cm -3 ~5×10 21 cm -3 At concentrations of , n-type carrier dopants such as phosphorus (P) or antimony (Sb) can be doped. The doped semiconductor layer 304 can be doped at about 10 depending on the desired conductivity characteristics of the semiconductor structure 300. 20 cm -3 ~5×10 21 cm -3At concentrations of , p-type carrier dopants such as boron (B), gallium (Ga), aluminum (Al), or indium (In) can be doped.

[0043]

[0047] In some embodiments, the deposition gas used in the first deposition process includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or combinations thereof. Germanium-containing precursors may include germanium (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). n-type dopant sources may include phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), antimony trichloride (SbCl3), Sb(C2H5)5, arsine (AsH3), arsenic trichloride (AsCl3), or tert-butylarsine (AsC4H11). p-type dopant sources may include diborane (B2H6) or boron trichloride (BCl3).

[0044]

[0048] In the first deposition process of block 410, the deposited doped semiconductor layer 304 may include an epitaxial portion 304E and an amorphous portion 304A due to the different nucleation rates of the doped semiconductor layer 304 on the surface of the semiconductor region of the substrate 302 (e.g., silicon (Si) or silicon germanium (SiGe)) and the surface of the dielectric region of the substrate 302 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). Since nucleation can occur at a faster rate on the surface of the semiconductor region than on the surface of the dielectric region, the epitaxial portion 304E of the doped semiconductor layer 304 may be selectively formed on the surface of the semiconductor region, while the amorphous portion 304A of the doped semiconductor layer 304 may be formed on the surface of the dielectric region. The amorphous portion 304A of the doped semiconductor layer 304 may be removed in a subsequent etching process of block 430.

[0045]

[0049] The first deposition can be carried out at low temperatures below approximately 450°C and pressures of 5 Torr to 600 Torr.

[0046]

[0050] In block 420, a second deposition process is performed after the first deposition process to form a cap layer 306 on the doped semiconductor layer 304, as shown in Figure 5B. The cap layer 306 may be formed from undoped carbon (C), carbon-doped silicon (Si:C), or carbon-doped silicon germanium (SiGe:C). The cap layer 306 may not be doped with a carrier dopant. The second deposition process may include any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) by flowing a deposition gas through a processing chamber.

[0047]

[0051] In some embodiments, the deposition gas used in the second deposition process includes a silicon-containing precursor, a germanium-containing precursor, and a carbon source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or combinations thereof. Germanium-containing precursors may include germanium (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). Carbon sources may include silyl alkanes such as monosilylmethane, disilylmethane, trisilmethane, and tetrasilylmethane, as well as alkylsilanes such as monomethylsilane (MMS) and dimethylsilane.

[0048]

[0052] In the second deposition process of block 420, the cap layer 306 may include an epitaxial portion 306E and an amorphous portion 306A due to the different nucleation rates of the cap layer 306 on the surface of the epitaxial portion 304E of the doped semiconductor layer 304 and on the surface of the amorphous portion 304A of the doped semiconductor layer 304. Since nucleation may occur at a faster rate on the surface of the epitaxial portion 304E of the doped semiconductor layer 304 than on the surface of the amorphous portion 304A of the doped semiconductor layer 304, the epitaxial portion 306E of the cap layer 306 may be selectively formed on the surface of the epitaxial portion 304E of the doped semiconductor layer 304, while the amorphous portion 306A of the cap layer 306 may be formed on the surface of the amorphous portion 304A of the doped semiconductor layer 304. The amorphous portion 306A of the cap layer 306 can be removed in a subsequent etching process of block 430.

[0049]

[0053] The second deposition can be carried out at low temperatures below approximately 450°C and pressures of 5 Torr to 600 Torr.

[0050]

[0054] In block 430, as shown in Figures 5C and 5D, an etching process is performed to remove the amorphous portion 306A of the cap layer 306 and the amorphous portion 304A of the underlying doped semiconductor layer 304. The etching process in block 430 may be performed by flowing an etching gas through a processing chamber, following the second deposition process in block 420, or simultaneously with the first deposition process in block 410 and the second deposition process in block 420.

[0051]

[0055] In the etching process, the amorphous portion 306A of the cap layer 306 can be etched faster than the epitaxial portion 306E of the cap layer 306 by a suitable etching gas, leaving the epitaxial portion 306E unetched, as shown in Figure 5C. Since the cap layer 306 is not doped with carrier dopant, the etching selectivity between the amorphous portion 306A and the epitaxial portion 306E is greater than that between the amorphous and epitaxial portions of a silicon and carbon-doped cap layer. As shown in Figure 5D, by using the epitaxial portion 306E of the cap layer 306 as a mask, the amorphous portion 304A of the underlying doped semiconductor layer 304 can be further etched, leaving the epitaxial portion 304E of the doped semiconductor layer 304 unetched. Therefore, the overall result of combining the epitaxial deposition process and the etching process is the growth of the epitaxial portion 304E of the doped semiconductor layer 304 (also referred to as the "doped semiconductor epitaxial layer") and the epitaxial portion 306E of the capped layer 306 (also referred to as the "capped epitaxial layer") on the substrate 302.

[0052]

[0056] The etching gas used in the etching process of block 430 includes an etchant gas and a carrier gas. The etchant gas may include halogen-containing gases such as hydrogen chloride (HCl), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0053]

[0057] The cycles of the first deposition process on block 410, the second deposition process on block 420, and the etching process on block 430 may be repeated as needed to obtain the desired combined thickness of the doped semiconductor epitaxial layer 304E and the capped epitaxial layer 306E of approximately 500 Å to approximately 700 Å, for example, approximately 600 Å, as shown in Figures 5E and 5F. The cycles may be repeated, for example, about 30 times.

[0054]

[0058] Embodiments described herein provide a method and system for forming a contact epitaxial layer in a trench on a selected portion of a transistor structure, and a method and system for forming a capping layer on the contact epitaxial layer to protect the contact epitaxial layer from oxidation and contamination. The contact trench structure includes a metal contact plug formed in a trench between adjacent device modules, and contacts that interlock between the contact plug and a silicon-based channel within the device module. The contacts are formed by selective deposition to reduce parasitic resistance. The metal contact plugs are formed void-free by a deposition-etching-deposition process to reduce contact resistance. The contact epitaxial layer may be p-type silicon-germanium formed on the exposed surface of a p-type MOS device (e.g., silicon-germanium), while an epitaxial layer may not be formed on an n-type MOS (e.g., silicon), or it may be a dielectric layer formed on both the p-type and n-type MOS devices. The capping layer reduces damage to the fabricated contact epitaxial layer.

[0055]

[0059] Embodiments described herein provide a method and system for forming a doped semiconductor epitaxial layer in which dopant diffusion is prevented by an adjacent capped epitaxial layer. The doped semiconductor epitaxial layer contains a high concentration of silicon and a carrier dopant. The capped epitaxial layer contains silicon and carbon and is not doped with a carrier dopant. The method includes periodic deposition and etching processes that enable selective epitaxial growth of the doped semiconductor layer and the capped layer.

[0056]

[0060] Multiple pairs of doped semiconductor epitaxial layers and capped epitaxial layers interposed within the doped semiconductor epitaxial layers are formed and can be used as source / drain in NMOS devices. Because dopant diffusion is prevented, a sharper doping profile can be achieved. Furthermore, the tensile strain induced in the capped epitaxial layers improves electron mobility, resulting in high conductivity in device applications.

[0057]

[0061] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. It is a semiconductor structure, An alternating stack of doped semiconductor epitaxial layers and capped epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer comprises silicon having a carrier dopant. A semiconductor structure in which each capped epitaxial layer contains silicon and carbon that are not doped with carrier dopants.

2. The semiconductor structure according to claim 1, wherein the carrier dopant contains phosphorus.

3. Each doped semiconductor epitaxial layer has a thickness of 15 Å to 20 Å. The semiconductor structure according to claim 1, wherein each cap epitaxial layer has a thickness of 5 Å to 15 Å.

4. The semiconductor structure according to claim 1, wherein the stack of alternating doped semiconductor epitaxial layers and capped epitaxial layers has a thickness of 500 Å to 700 Å.

5. A method for forming a doped semiconductor layer within a semiconductor structure, The method involves performing a first deposition process, a second deposition process following the first deposition process, and a plurality of cycles of the etching process, The first deposition process forms a doped semiconductor layer on the exposed surface of the substrate. The second deposition process forms an undoped cap layer on the doped semiconductor layer. The etching process includes performing a number of cycles that selectively remove the amorphous portion of the undoped cap layer and the amorphous portion of the doped semiconductor layer, leaving the epitaxial portion of the undoped cap layer and the epitaxial portion of the doped semiconductor layer. The doped semiconductor layer includes silicon having a carrier dopant, A method wherein the undoped cap layer contains carbon.

6. The method according to claim 5, wherein the carrier dopant contains phosphorus.

7. The doped semiconductor layer has a thickness of 15 Å to 20 Å. The method according to claim 5, wherein the undoped cap layer has a thickness of 5 Å to 15 Å.

8. The method according to claim 5, wherein the first deposition process includes flowing a silicon-containing precursor and a dopant source in a processing chamber.

9. The method according to claim 8, wherein the second deposition process includes flowing a silicon-containing precursor and a carbon source in the processing chamber.

10. The method according to claim 9, wherein the etching process includes flowing an etchant gas and a carrier gas in a processing gas after the second deposition process.

11. The method according to claim 9, wherein the etching process includes flowing an etchant gas and a carrier gas in the processing gas simultaneously with the first deposition process and the second deposition process.

12. The method according to claim 9, wherein the first deposition process and the second deposition process are carried out at a low temperature of less than about 450°C and a pressure of 5 Torr to 600 Torr.

13. A processing system, Processing chamber and System controller and The system controller provides the processing system A plurality of cycles comprising a first deposition process, a second deposition process following the first deposition process, and an etching process, The first deposition process forms a doped semiconductor layer on the exposed surface of the substrate. The second deposition process forms an undoped cap layer on the doped semiconductor layer. The etching process is configured to perform multiple cycles that selectively remove the amorphous portion of the undoped cap layer and the amorphous portion of the doped semiconductor layer, leaving the epitaxial portion of the undoped cap layer and the epitaxial portion of the doped semiconductor layer. The doped semiconductor layer includes silicon having a carrier dopant, A processing system in which the undoped cap layer contains carbon.

14. The processing system according to claim 13, wherein the carrier dopant contains phosphorus.

15. The doped semiconductor layer has a thickness of 15 Å to 20 Å. The processing system according to claim 13, wherein the undoped cap layer has a thickness of 5 Å to 15 Å.

16. The processing system according to claim 13, wherein the first deposition process includes flowing a silicon-containing precursor and a dopant source in the processing chamber.

17. The processing system according to claim 16, wherein the second deposition process includes flowing a silicon-containing precursor and a carbon source within the processing chamber.

18. The processing system according to claim 17, wherein the etching process includes flowing an etchant gas and a carrier gas in a processing gas after the second deposition process.

19. The processing system according to claim 17, wherein the etching process includes flowing an etchant gas and a carrier gas in the processing gas simultaneously with the first deposition process and the second deposition process.

20. The processing system according to claim 19, wherein the first deposition process and the second deposition process are carried out at a low temperature of less than about 450°C and a pressure of 5 Torr to 600 Torr.

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