Method and apparatus for controlling the temperature of a transducer

Abstract

The exemplary apparatus includes machine-readable instructions and a programmable circuit element configured to instantiate or execute at least one of the machine-readable instructions. The programmable circuit element receives burst excitation information (BURST510) which includes a burst start frequency (FSTART) and a burst stop frequency (FSTOP) that define a frequency range for burst excitation information, and a burst duration (DUR). Based on the burst excitation information (510), it generates first and second sub-burst excitation information (520, 530) which includes a sub-burst duration (DURSUB_BURST) based on the burst duration, a temperature sensing interval (TEMP_INT) which is the time between temperature measurements, and a temperature sensing duration (DURTEMP) which is the time for temperature measurement. It generates excitation signals in response to the first and second sub-burst excitation information and temperature measurements, wherein the excitation signals have a frequency range.

Description

[Technical Field]

[0001] This description generally relates to temperature control, and more specifically, to methods and apparatus for controlling the temperature of a transducer. [Background technology]

[0002] A transducer is an electrical component capable of converting electrical energy into mechanical energy and vice versa. In some applications, a regulator circuit element supplies an electrical signal with a frequency and amplitude that excites a transducer, causing it to vibrate and generate heat. For example, a transducer may be coupled to a camera lens cover to vibrate the lens cover to remove contaminants obstructing the camera's view. In another example, a transducer may be coupled to a camera lens cover to act as a heat source to melt ice obstructing the camera's view. [Overview of the project]

[0003] For a method and apparatus for controlling the temperature of a transducer, the exemplary apparatus includes a machine-readable instruction and a programmable circuit element configured to instantiate or execute at least one of the machine-readable instructions. The programmable circuit element receives burst excitation information, which includes a burst start frequency, a burst stop frequency, and a burst duration, the burst start frequency and burst stop frequency defining a frequency range of the burst excitation information; generates first and second sub-burst excitation information based on the burst excitation information, which includes a burst duration, a temperature sensing interval, and a sub-burst duration based on the temperature sensing duration, the temperature sensing interval being the time between temperature measurements, and the temperature sensing duration being the time of the temperature measurement; and is configured to generate an excitation signal having the frequency range of the burst excitation information in response to the first and second sub-burst excitation information and the temperature measurement. [Brief explanation of the drawing]

[0004] [Figure 1] A block diagram of an exemplary lens cleaning system including an exemplary regulator circuit element having an exemplary controller circuit element, an exemplary amplifier circuit element, an exemplary filter circuit element, and an exemplary sensing circuit element, and an exemplary lens cover system having a transducer.

[0005] [Figure 2] A schematic diagram of examples of the amplifier circuit element, the filter circuit element, and the sensing circuit element of FIG. 1.

[0006] [Figure 3] A block diagram of an example of the controller circuit element of FIG. 1 including an exemplary sweep circuit element for adjusting the temperature of the transducer of FIG. 1.

[0007] [Figure 4] A block diagram of an example of the sweep circuit element of FIG. 3 including an exemplary sequence circuit element, an exemplary temperature adjustment circuit element, and an exemplary signal generation circuit element, the sweep circuit element being for generating an excitation signal using burst excitation information and temperature excitation information.

[0008] [Figure 5] A timing diagram of an example of the operation of the sweep circuit elements of FIGS. 3 and 4 for adjusting the temperature of the transducer of FIG. 1.

[0009] [Figure 6] A timing diagram of an example of the operation of the controller circuit elements of FIGS. 1 and 3, the amplifier circuit elements of FIGS. 1 and 2, and the filter circuit elements of FIGS. 1 and 2.

[0010] [Figure 7A]Using the sweep circuit elements of FIGS. 3 and 4, and / or more generally the exemplary programmable circuit element implementations of the controller circuit elements of FIGS. 1 and 3, form a flowchart representing exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or implemented. [Figure 7B] Using the sweep circuit elements of FIGS. 3 and 4, and / or more generally the exemplary programmable circuit element implementations of the controller circuit elements of FIGS. 1 and 3, form a flowchart representing exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or implemented.

[0011] [Figure 8] A flowchart representing exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or implemented using the exemplary programmable circuit element implementation of the sweep circuit elements of FIGS. 3 and 4.

[0012] [Figure 9] A block diagram of an exemplary processing platform including programmable circuit elements configured to execute, instantiate, and / or implement exemplary machine-readable instructions and / or the exemplary operations of FIGS. 7A, 7B, and 8 for implementing the controller circuit elements of FIGS. 1, 3, and 4.

[0013] [Figure 10] A block diagram of an exemplary implementation of the programmable circuit element of FIG. 9.

[0014] [Figure 11] A block diagram of another exemplary implementation of the programmable circuit element of FIG. 9.

[0015] The same reference numerals or other reference indicators are used to refer to (functionally and / or structurally) identical or similar features.

Best Mode for Carrying Out the Invention

[0016] The drawings described herein are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and in this description refer to the same or similar parts. While the drawings use complete lines and boundaries to indicate areas, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0017] A transducer is a component capable of converting electrical energy into mechanical energy and vice versa. In some applications, a regulator circuit element supplies an electrical signal of a certain frequency and amplitude to the transducer. The frequency and amplitude of the electrical signal are selected to supply power to the transducer. The transducer oscillates in response to the electrical signal, generating heat. Such an electrical signal is called an excitation signal.

[0018] A transducer can be mechanically coupled to a medium (e.g., a plastic cover, a glass panel, etc.) to transmit physical vibration and / or heat to that medium. As transducer technology and manufacturing methods evolve, transducer technology is becoming more complex. For example, a transducer may be coupled to a camera lens or camera lens cover to vibrate the lens cover in order to remove contaminants that obstruct the camera's field of view. In another example, a transducer may be coupled to a camera lens or camera lens cover as a heat source to melt ice that obstructs the camera's field of view.

[0019] Manufacturers fabricate piezoelectric transducers by heating the material to a temperature approximately equal to or higher than the Curie temperature of the piezoelectric material. The Curie temperature of a material is the temperature at which any magnetic charge in the material can be replaced by an induced magnetic charge. At the Curie temperature, the manufacturer exposes the material to an induced magnetic charge. The induced magnetic charge polarizes the material, thereby fabricating a transducer. Some manufacturers use materials with relatively low Curie temperatures to reduce the complexity of the manufacturing process. Other manufacturers use materials with known piezoelectric properties to reduce the complexity of the manufacturing process.

[0020] However, the transducer material may begin to depolarize in response to heating the transducer to an excessive temperature (e.g., a temperature close to and / or greater than half the Curie temperature). Once the material begins to depolarize, the transducer ceases to vibrate in response to an electrical signal. In some examples, supplying an excitation signal to the transducer for a relatively long period of time (e.g., one second or several seconds) can generate excess heat. Such excess heat can depolarize the transducer material. In such examples, environmental conditions may reduce the time required to generate such excess heat.

[0021] Methods and apparatus for controlling the temperature of a transducer are described herein, including a regulator circuit element. The regulator circuit element sequences the supply of an excitation signal to the transducer, including temperature measurement. In some examples described, the regulator circuit element generates an excitation signal in response to excitation information generated by a controller circuit element. The excitation information includes data specifying amplitude, one or more frequencies, phase, and duration of the desired excitation signal. Some circuit elements generate burst excitation information to perform various functions. For example, a controller circuit element generates an excitation signal specific to a cleaning operation in response to burst excitation information from a cleaning circuit element. The burst excitation information includes data specifying amplitude, burst start frequency, burst stop frequency, step size, phase, and burst duration. The controller circuit element includes a sweep circuit element for generating a sinusoidal waveform representing the excitation signal in response to the burst excitation information. In such an example, the sweep circuit element varies the frequency of the excitation signal from the start frequency to the stop frequency in increments of the step size over the burst duration.

[0022] The sweep circuit element includes a sequencing circuit element and a temperature control circuit element that regulates the transducer temperature. In some examples, the sequencing circuit element divides burst excitation information into multiple sub-burst excitation information. The temperature control circuit element performs temperature measurements between each of the multiple sub-burst excitation information supplies. In response to detecting an excessive transducer temperature, the temperature control circuit element prevents the supply of one of the subsequent sub-burst excitation information supplies. An excessive transducer temperature is a temperature approaching the temperature that depolarizes the transducer, such as approximately half the Curie temperature. Advantageously, the sequencing circuit element and the temperature control circuit element regulate the generation of excitation signals to reduce the possibility of transducer depolarization.

[0023] Figure 1 is a block diagram of an exemplary lens cleaning system 100, which includes an exemplary regulator circuit element 105 and an exemplary lens cover system 110. In the example of Figure 1, the regulator circuit element 105 includes an exemplary controller circuit element 115, an exemplary amplifier circuit element 120, an exemplary filter circuit element 125, an exemplary sensing resistor 130, and an exemplary current and voltage (I / V) sensing circuit element 135. In the example of Figure 1, the lens cover system 110 includes an exemplary printed circuit board (PCB) 140, an exemplary camera lens 145, an exemplary transducer 150, an exemplary lens cover 155, an exemplary contaminant 160, an exemplary housing 165, and an exemplary seal 170.

[0024] The regulator circuit element 105 has first and second terminals coupled to the lens cover system 110. The regulator circuit element 105 supplies power to the lens cover system 110 by generating an excitation signal. The regulator circuit element 105 monitors the power supplied to the lens cover system 110 in response to the characteristics of the excitation signal. In some examples, the regulator circuit element 105 determines the characteristics of the lens cover system 110 based on the characteristics of the excitation signal. Such examples are described in more detail later. The regulator circuit element 105 may modify the frequency, phase, and / or amplitude of the excitation signal to modify the power supplied to the lens cover system 110. The regulator circuit element 105 may modify the excitation signal to increase power efficiency, determine the impedance of the transducer 150, respond to variations in the impedance of the lens cover system 110, modify the power consumed by the lens cover system 110, determine the temperature of the lens cover system 110, and so on.

[0025] The lens cover system 110 has first and second terminals coupled to the regulator circuit element 105. The lens cover system 110 receives an excitation signal from the regulator circuit element 105. In response to supplying an excitation signal to the transducer 150, the lens cover system 110 removes the contaminant 160. In the exemplary operation, the regulator circuit element 105 vibrates the lens cover 155 in response to supplying an excitation signal to the transducer 150. In such an example, the lens cover system 110 uses vibration to remove the contaminant 160, thereby providing a clear view to the camera lens 145. Advantageously, the lens cover system 110 prevents the contaminant 160 from obstructing the view of the camera lens 145.

[0026] The controller circuit element 115 has first and second inputs coupled to the I / V sensing circuit element 135 and first and second outputs coupled to the amplifier circuit element 120. The controller circuit element 115 generates a preamplifier signal representing a desired excitation signal. In some examples, the preamplifier signal is a pulse-width modulation (PWM) signal. In such examples, the controller circuit element 115 uses modulation techniques to generate a PWM signal based on a sinusoidal waveform representing a relatively low-power version of the excitation signal. In some other examples, the controller circuit element 115 generates the preamplifier signal as a relatively low-power version of the excitation signal. In such examples, the frequency of the preamplifier signal is approximately equal to the frequency of the excitation signal, while the amplitude of the preamplifier signal is proportional to the amplitude of the excitation signal. The controller circuit element 115 supplies the preamplifier signal to the amplifier circuit element 120.

[0027] In response to the controller circuit element 115 supplying a preamplifier signal to the amplifier circuit element 120, the I / V sensing circuit element 135 provides a sensing current (I SENSE ) and sensing voltage (V SENSEThe controller circuit element 115 receives the following: The controller circuit element 115 determines multiple sensing currents and voltages over the duration that the excitation signal is supplied to the lens cover system 110. In response to the multiple sensing currents and voltages, the controller circuit element 115 determines the impedance of the lens cover system 110. Based on the determined impedance and the characteristics of the supplied excitation signal, the controller circuit element 115 determines the characteristics of the lens cover system. In some examples, the controller circuit element 115 detects a change in the contaminant 160 in response to a change in the determined impedance. In other examples, the controller circuit element 115 determines the temperature of the transducer 150 in response to the determined impedance. Such operation of the controller circuit element 115 will be described further below in relation to Figure 3.

[0028] In some examples, the controller circuit element 115 modifies the characteristics of the excitation signal in response to the determined impedance. In such examples, the controller circuit element 115 can increase power efficiency by modifying the excitation signal to be specific to the impedance of the lens cover system 110. In other examples, the controller circuit element 115 modifies the characteristics of the excitation signal to perform various operations. For example, the excitation signal may have a specific amplitude, frequency, phase, and duration in response to the controller circuit element 115 performing a cleaning operation. Advantageously, the controller circuit element 115 can determine the characteristics of the lens cover system 110, such as impedance, using the sensed current and voltage from the I / V sensing circuit element 135. Advantageously, the controller circuit element 115 can modify the characteristics of the preamplifier signal to modify the characteristics of the excitation signal in response to the determined impedance.

[0029] The amplifier circuit element 120 has first and second inputs coupled to the controller circuit element 115 and first and second outputs coupled to the filter circuit element 125. The amplifier circuit element 120 receives the preamplifier signal from the controller circuit element 115. The amplifier circuit element 120 amplifies the preamplifier signal to produce a relatively high power signal. In some examples, when the preamplifier signal is a PWM signal, the relatively high power signal is a PWM signal with a relatively high voltage level. For example, logic 1 of the preamplifier signal is 3 volts (V), while logic 1 of the relatively high power signal is 50 volts. In other examples, when the preamplifier signal is a sine wave, the relatively high power signal is a sine wave with approximately the same frequency and phase as the preamplifier signal. However, the amplitude of the relatively high power signal is an amplified version of the preamplifier signal. For example, the preamplifier signal may have an amplitude of 2 volts, while the relatively higher power signal may have an amplitude of 100 volts.

[0030] In the example operation, the controller circuit element 115 may operate in a first power domain, while the amplifier circuit element 120 may operate in a second power domain. Such power domain differentiation can reduce the cost of the controller circuit element 115 while the amplifier circuit element 120 can still supply a relatively high power signal. The amplifier circuit element 120 supplies a relatively high power signal to the filter circuit element 125. Advantageously, the amplifier circuit element 120 can generate an excitation signal with a voltage higher than that of the controller circuit element 115.

[0031] The filter circuit element 125 has first and second inputs coupled to the amplifier circuit element 120, and first and second outputs coupled to the lens cover system 110 and the I / V sensing circuit element 135. The filter circuit element 125 receives a relatively high power signal from the amplifier circuit element 120. The filter circuit element 125 filters the relatively high power signal to generate an excitation signal. In some examples, such as when the preamplifier signal is a PWM signal, the filter circuit element 125 averages the relatively fast duty cycle of the relatively high power signal to generate the excitation signal as a sinusoidal waveform. Such exemplary operation is illustrated in Figure 6 and described further thereafter. In other examples, such as when the preamplifier signal is a sinusoidal wave, the filter circuit element 125 removes frequencies higher than the cutoff frequency from the relatively high power signal. The filter circuit element 125 supplies the excitation signal to the lens cover system 110. Alternatively, the filter circuit element 125 may be modified and / or removed from the regulator circuit element 105 based on the amplifier circuit element 120. For example, if the amplifier circuit element 120 is a Class D amplifier, the regulator circuit element 105 needs the filter circuit element 125 to convert the PWM signal into a sinusoidal excitation signal. However, if the amplifier circuit element 120 is a linear amplifier and the preamplifier signal is a sinusoidal signal, the filter circuit element 125 may be unnecessary.

[0032] The I / V sensing circuit element 135 has first, second, and third inputs coupled to the lens cover system 110, the filter circuit element 125, and the sensing resistor 130. The I / V sensing circuit element 135 has first and second outputs coupled to the controller circuit element 115. The I / V sensing circuit element 135 receives a reference voltage as a voltage difference across the sensing resistor 130. The I / V sensing circuit element 135 receives an excitation voltage from the filter circuit element 125 as the excitation signal voltage. The I / V sensing circuit element 135 converts the reference voltage and the excitation voltage from the power domain of the amplifier circuit element 120 into the power domain of the controller circuit element 115. In some examples, the I / V sensing circuit element 135 divides the reference voltage and / or excitation voltage to step down the voltage into the power domain of the controller circuit element 115.

[0033] The I / V sensing circuit element 135 generates the sensing current and sensing voltage as single-ended versions of the differentially sensed reference voltage and excitation voltage. The I / V sensing circuit element generates the single-ended voltage in the power domain of the controller circuit element 115. In some examples, the I / V sensing circuit element 135 generates the sensing current and voltage with reference to a common potential (e.g., ground). The sensing current voltage is proportional to the voltage difference across the sensing resistor 130. Advantageously, the sensing current voltage represents the excitation signal current. The sensing voltage voltage is proportional to the excitation signal voltage. Advantageously, the sensing voltage voltage represents the excitation signal voltage. The I / V sensing circuit element 135 supplies the sensing current and voltage to the controller circuit element 115.

[0034] PCB 140 is coupled to the regulator circuit element 105 and the transducer 150. PCB 140 includes a photodiode (PD) that converts the optical input into an electrical signal. The photodiode 175 can capture an image of the view of the camera lens 145. PCB 140 couples the transducer 150 to the output of the filter circuit element 125. Alternatively, the transducer 150 can be directly coupled to the output of the filter circuit element 125 or the amplifier circuit element 120.

[0035] The camera lens 145 is coupled to the photodiode 175. The camera lens 145 supplies optical light to the photodiode 175. In some examples, the camera lens 145 uses optical techniques to increase the field of view of the camera lens 175. The camera lens 145 may include multiple lenses to focus and / or modulate the light toward the photodiode 175. In some examples, the camera lens 145 and the photodiode 175 form a camera system.

[0036] The transducer 150 is coupled to the lens cover 155, housing 165, and seal 170. Alternatively, the transducer 150 may be directly coupled to the lens cover 145, housing 165, and seal 170. The transducer 150 receives an excitation signal from the regulator circuit element 105. The transducer 150 converts the power supplied by the excitation signal into mechanical motion in the form of physical vibration. The lens cover 155 and / or camera lens 145 vibrate in response to the mechanical motion of the transducer 150. The contaminant 160 moves in response to the physical vibration of the transducer 150. In some examples, the transducer 150 is a piezoelectric component.

[0037] By modifying the characteristics of the excitation signal, the regulator circuit element 150 can control the mechanical movement of the transducer 150. The regulator circuit element 105 can generate an excitation signal with a wide range of characteristics for removing contaminants 160 from the lens cover 155. During the exemplary operation, the impedance of the transducer 150 may fluctuate as contaminants 160 are removed from the lens cover 155 and / or as additional contaminants are added to the lens cover 155. For example, a lens cover system 110 mounted on a vehicle may cause the lens cover 115 to be exposed to additional contaminants as the vehicle moves. In such an example, the regulator circuit element 105 may modify the power supplied to the lens cover system 110 each time the impedance of the transducer 150 fluctuates. The regulator circuit element 105 determines the change in impedance in response to the sensed current and voltage of the excitation signal.

[0038] In the example operation, excessive heat accumulation is responsive to the power consumption of transducer 150. In such an example, heat accumulation causes the temperature of transducer 150 to rise. The impedance of transducer 150 fluctuates as the temperature of transducer 150 changes. Advantageously, the change in impedance of transducer 150 is temperature-dependent. The regulator circuit element 105 can detect the rise in temperature of transducer 150 in response to the impedance fluctuation.

[0039] The housing 165 is coupled to the seal 170. The housing 165 houses the transducer 150 and the lens cover 155, protecting the PCB 140, camera lens 145, and photodiode 175 from exposure to contaminants 160. The seal 170 is coupled between the housing 165 and the transducer 150, and between the housing 165 and the lens cover 155. The seal 170 prevents the contaminants 160 from reaching the camera lens 145 and / or photodiode 175.

[0040] Figure 2 is a schematic diagram of an example of the amplifier circuit element 120, the filter circuit element 125, the sensing resistor 130, and the I / V sensing circuit element 135 of Figure 1. The amplifier circuit element 120 and the I / V sensing circuit element 135 may be coupled to the controller circuit element 115 of Figure 1. The filter circuit element 125, the sensing resistor 130, and the I / V sensing circuit element 135 may be coupled to the lens cover system 110 of Figure 1.

[0041] The amplifier 120 has first and second inputs coupled to the controller circuit element 115 and first and second outputs coupled to the filter circuit element 125. In the example in Figure 2, the amplifier circuit element 120 includes an exemplary supply terminal 200, a first exemplary transistor 204, a second exemplary transistor 208, a first exemplary inverter 212, a third exemplary transistor 216, a fourth exemplary transistor 220, and a second exemplary inverter 224. The amplifier circuit element 120 receives a differential pair of preamplifier signals representing a preamplifier signal. In the example in Figure 2, the differential pair of preamplifier signals is a PWM signal with a fluctuating duty cycle representing a sinusoidal excitation signal. In such an example, the amplifier circuit element 120 amplifies the voltage of the differential pair of preamplifier signals to generate a differential pair of relatively high-power signals representing the excitation signal as a PWM signal. The amplifier circuit element 120 supplies the differential pair of relatively high-power signals to the filter circuit element 125. In the example shown in Figure 2, the amplifier circuit element 120 is a Class D amplifier. However, with some modifications, the amplifier circuit element 120 can be an amplifier circuit element of an alternative class, such as a Class A amplifier or a Class AB amplifier.

[0042] The filter circuit element 125 has first and second inputs coupled to the amplifier circuit element 120, and first and second outputs coupled to the I / V sensing circuit element 135, the sensing resistor 130, and potentially coupled to the lens cover system 110. In the example of Figure 2, the filter circuit element 125 includes a first exemplary inductor 228, a first exemplary capacitor 232, and a second exemplary inductor 236. The filter circuit element 125 receives a differential pair of relatively high power signals. The filter circuit element 125 generates an excitation signal differential pair based on the differential pair of relatively high power signals. In the example of Figure 2, the filter circuit element 125 generates the excitation signal differential pair by averaging the currents through the inductors 228 and 236 based on the fluctuating duty cycle of the differential pair of relatively high power signals. In such an example, the filter circuit element 125 filters the differential pair of relatively high power signals to generate the excitation signal differential pair as a sinusoidal signal. In an example where the amplifier circuit element 120 is not a Class D amplifier circuit element, the filter circuit element 125 may filter the frequency of the differential pair of a relatively high power signal to reduce noise and / or improve noise immunity. In such an example, the preamplifier signal and the relatively high power signal are sinusoidal signals.

[0043] The I / V sensing circuit element 135 has first, second, and third inputs which can be coupled to the filter circuit element 125, the sensing resistor 130, and the lens cover system 110. The I / V sensing circuit element 135 also has first and second outputs which can be coupled to the controller circuit element 115. In the example in Figure 2, the I / V sensing circuit element 135 includes a supply terminal 200, a second exemplary capacitor 240, a first exemplary resistor 244, a second exemplary resistor 248, a third exemplary resistor 252, a third exemplary capacitor 256, a fourth exemplary resistor 260, a fifth exemplary resistor 264, a sixth exemplary resistor 268, a first exemplary amplifier 272, a fourth exemplary capacitor 276, a seventh exemplary resistor 280, an eighth exemplary resistor 284, a ninth exemplary resistor 288, a fifth exemplary capacitor 290, a tenth exemplary resistor 292, an eleventh exemplary resistor 294, a twelfth exemplary resistor 296, and a second exemplary amplifier 298.

[0044] The I / V sensing circuit element 135 receives the differential pair of the excitation signal and the reference voltage of the sensing resistor 130. The I / V sensing circuit element 135 steps down the reference voltage to the logic level of the controller circuit element 115 to generate a single-ended voltage representing the sensing current. The voltage of the sensing current is proportional to the current of the differential pair of the excitation signal. The I / V sensing circuit element 135 steps down the voltage of the differential pair of the excitation signal to the logic level of the controller circuit element 115 to generate a single-ended voltage representing the sensing voltage. The voltage of the sensing voltage is proportional to the voltage of the differential pair of the excitation signal. The I / V sensing circuit element 135 supplies the sensing current and voltage to the controller circuit element 115.

[0045] The supply terminal 200 is coupled to transistors 204 and 216 and resistors 248 and 264. The supply terminal 200 receives a supply voltage (V) from the power supply circuit elements. DD) is supplied. In some examples, the power supply circuit element is inside the regulator circuit element 105. In other examples, the power supply circuit element is outside the regulator circuit element 105. The supply voltage is a fixed reference voltage that supplies power to the amplifier circuit element 120 and the I / V sensing circuit element 135.

[0046] The first transistor 204 has a first terminal coupled to the supply terminal 200 and a second terminal coupled to the second transistor 208 and the first inductor 228. The first transistor 204 has a control terminal coupled to the first inverter 212 and may be coupled to the controller circuit element 115. The first transistor 204 receives a first preamplifier signal, which is a differential pair of preamplifier signals. The first preamplifier signal is a PWM signal that controls the first transistor 204. When the first transistor 204 is enabled (e.g., turned on, conducting), it supplies current from the supply terminal 200 to the first inductor 228, thereby setting the voltage of the first inductor to approximately equal to the supply voltage. When the first transistor 204 is disabled (e.g., turned off, not conducting), it prevents current from the supply terminal 200 from being supplied to the first inductor 228.

[0047] The second transistor 208 has a first terminal coupled to the first transistor 204 and the first inductor 228, and a second terminal coupled to a common terminal that supplies a common potential (e.g., ground). The second transistor 208 has a control terminal coupled to the first inverter 212. The second transistor 208 receives a first inverted preamplifier signal from the first inverter 212. The first inverted preamplifier signal is a PWM signal that controls the second transistor 208. In the example in Figure 2, the first inverted preamplifier signal is approximately an inverted version of the first preamplifier signal. When enabled, the second transistor 208 supplies current from the first inductor 228 to the common terminal, thereby setting the voltage across the first inductor 228 to approximately equal to the common potential. When disabled, the second transistor 208 prevents the supply of current from the first inductor 228 to the common terminal.

[0048] The first inverter 212 has a first terminal that is coupled to the first transistor 204 and can be coupled to the controller circuit element 115, and a second terminal 208 that is coupled to the second transistor. The first inverter 212 receives the first preamplifier signal. The first inverter 212 generates a first inverted preamplifier signal by inverting the first preamplifier signal. The first inverter 212 supplies the first inverted preamplifier signal to the second transistor 208.

[0049] Transistors 204 and 208 generate a first relatively high power signal of a differential pair of high-power signals based on the first preamplifier signal and the first inverted preamplifier signal. In exemplary operation, the first relatively high power signal is approximately equal to the supply voltage at supply terminal 200 in response to the first preamplifier signal being in a first logic state (e.g., logic 1 / logic high, or logic zero / logic low). In such exemplary operation, the first relatively high power signal is approximately equal to the common potential at common terminal in response to the first preamplifier signal being in a second logic state (e.g., logic zero / logic low, or logic 1 / logic high). Transistors 204 and 208 supply the first relatively high power signal to the first inductor 228. Advantageously, transistors 204 and 208 generate the first relatively high power signal by increasing the voltage of the first preamplifier signal. The first preamplifier signal fully enables / deactivates transistors 204 and 208. Advantageously, using the PWM signal as the first preamplifier signal increases the power efficiency of transistors 204 and 208 by reducing their linear operation.

[0050] The third transistor 216 has a first terminal coupled to the supply terminal 200 and a second terminal coupled to the fourth transistor 220 and the second inductor 236. The third transistor 216 has a control terminal coupled to the second inverter 224 and may be coupled to the controller circuit element 115. The third transistor 216 receives a second preamplifier signal, which is the differential pair of the preamplifier signals. The second preamplifier signal is a PWM signal that controls the third transistor 216. In some examples, the second preamplifier signal is approximately equal to the inverted version of the first preamplifier signal. In such examples, the preamplifier signal is approximately equal to the difference between the first preamplifier signal and the second preamplifier signal. Such preamplifier signals form the differential pair of the preamplifier signals. When activated, the third transistor 216 supplies current from the supply terminal 200 to the second inductor 236, thereby setting the voltage across the second inductor 236 to approximately equal the supply voltage. When the third transistor 216 is disabled, it prevents the supply of current from the supply terminal 200 to the second inductor 236.

[0051] The fourth transistor 220 has a first terminal coupled to the third transistor 216 and the second inductor 236, and a second terminal coupled to the common terminal. The fourth transistor 220 has a control terminal coupled to the second inverter 224. The fourth transistor 220 receives a second inverted preamplifier signal from the second inverter 224. The second inverted preamplifier signal is a PWM signal that controls the fourth transistor 220. When the fourth transistor 220 is enabled, it supplies current from the second inductor 236 to the common terminal, thereby setting the voltage across the second inductor 236 to approximately equal to the common potential. When the fourth transistor 220 is disabled, it prevents the supply of current from the second inductor 236 to the common terminal.

[0052] The second inverter 224 has a first terminal that is coupled to the third transistor 216 and can be coupled to the controller circuit element 115, and a second terminal that is coupled to the fourth transistor 220. The second inverter 224 receives the second preamplifier signal from the controller circuit element 115. The second inverter 224 generates the second inverted preamplifier signal by inverting the second preamplifier signal. The second inverter 224 supplies the second inverted preamplifier signal to the fourth transistor 220.

[0053] Transistors 216 and 220 generate a second relatively high power signal of the differential pair of high-power signals based on the second preamplifier signal and the second inverted preamplifier signal. In exemplary operation, the second relatively high power signal is approximately equal to the supply voltage of the supply terminal 200 in response to the second preamplifier signal being in a first logic state (e.g., logic 1 / logic high, or logic zero / logic low). In such exemplary operation, the second relatively high power signal is approximately equal to the common potential of the common terminal in response to the second preamplifier signal being in a second logic state (e.g., logic zero / logic low, or logic 1 / logic high). Transistors 216 and 220 supply the second relatively high power signal to the second inductor 236. Advantageously, transistors 216 and 220 generate the second relatively high power signal by increasing the voltage of the second preamplifier signal. The second preamplifier signal fully enables / deactivates transistors 216 and 220. Advantageously, using the PWM signal as a second preamplifier signal improves the power efficiency of transistors 216 and 220 by reducing their linear operation.

[0054] In the example in Figure 2, the internal body diodes of transistors 204, 208, 216, and 220 are illustrated. However, in other examples, the internal body diodes of transistors 204, 208, 216, and 220 may not be illustrated. In the example in Figure 2, transistors 204, 208, 216, and 220 are n-channel metal oxide semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 204, 208, 216, and 220 may be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), and / or, with some modification, p-type equivalent devices. Transistors 204, 208, 216, and 220 may be depletion-mode devices, drain-extension devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, transistors 204, 208, 216, and 220 can be mounted in / on a silicon substrate (Si), silicon carbide substrate (SiC), gallium nitride substrate (GaN), or gallium arsenide substrate (GaAs).

[0055] The first inductor 228 has a first terminal coupled to transistors 204 and 208, and a second terminal coupled to sensing resistor 130 and capacitors 232 and 240. The first inductor 228 receives a first relatively high power signal from transistors 204 and 208. The first inductor 228 generates a first excitation signal for the differential pair of excitation signals by averaging the current of the first relatively high power signal. The first inductor 228 converts the first relatively high power signal, which has PWM characteristics and a fluctuating duty cycle, into a first excitation signal that is sinusoidal. The first inductor 228 sets the amplitude of the first relatively high power signal by averaging the current of the fluctuating duty cycle of the first relatively high power signal. The first inductor 228 supplies the first excitation signal to sensing resistor 130 and capacitors 232 and 240.

[0056] The first capacitor 232 has a first terminal coupled to the first inductor 228, the sensing resistor 130, and the second capacitor 240, and a second terminal coupled to the second inductor 236, the fifth capacitor 290, and potentially coupled to the lens cover system 110. The first capacitor 232 receives the differential pair of excitation signals from the inductors 228 and 236. The first capacitor 232 filters relatively high-frequency noise in the differential pair of excitation signals. The first capacitor 232 resists relatively high-frequency changes in the difference between signals in the differential pair of excitation signals.

[0057] The second inductor 236 has a first terminal coupled to transistors 216 and 220, and a second terminal coupled to sensing resistor 130, capacitors 232 and 290, and potentially coupled to lens cover system 110. The second inductor 236 receives a second relatively high power signal from transistors 216 and 220. The second inductor 236 generates a second excitation signal for the differential pair of the excitation signals by averaging the current of the second relatively high power signal. The second inductor 236 converts the second relatively high power signal, which has PWM characteristics and a fluctuating duty cycle, into a second excitation signal that is sinusoidal. The second inductor 236 sets the amplitude of the second relatively high power signal by averaging the current of the fluctuating duty cycle of the second relatively high power signal. The second inductor 236 supplies the second excitation signal to lens cover system 110 and fifth capacitor 290.

[0058] The second capacitor 240 has a first terminal coupled to the sensing resistor 130, the first inductor 228, and the first capacitor 232, and a second terminal coupled to the first resistor 244. The second capacitor 240 receives the first excitation signal of the differential pair of excitation signals from the first inductor 228. The second capacitor 240 removes direct current (DC) offset and / or relatively low frequency noise from the first excitation signal. The second capacitor 240 may be called a blocking capacitor. The second capacitor 240 supplies the first excitation signal to the first resistor 244.

[0059] The first resistor 244 has a first terminal coupled to the second capacitor 240 and a second terminal coupled to resistors 248, 252 and the first amplifier 272. The first resistor 244 receives the first excitation signal from the second capacitor 240. The first resistor 244 reduces the current of the first excitation signal. The first resistor 244 may be called a current-limiting resistor. In some examples, the first resistor 244 stabilizes the timing of the resistor-capacitor (RC) circuit formed by resistors 248, 252 and the second capacitor 240. The first resistor 244 supplies the first excitation signal to resistors 248, 252 and the first amplifier 272.

[0060] The second resistor 248 has a first terminal connected to the supply terminal 200 and a second terminal connected to resistors 248, 252, and the first amplifier 272. The second resistor 248 receives the supply voltage from the supply terminal 200 and receives the first excitation signal from the first resistor 244. The second resistor 248 generates a voltage difference approximately equal to the supply voltage minus the voltage of the first excitation signal. In some examples, the second resistor 248 is part of a voltage divider circuit element. In such examples, the resistance of the second resistor 248 can step down the voltage of the first excitation signal.

[0061] The third resistor 252 has a first terminal connected to resistors 244, 248 and the first amplifier 272, and a second terminal connected to a common terminal. The third resistor 252 receives the first excitation signal from the first resistor 244 and the common potential from the common terminal. The third resistor 252 generates a voltage difference approximately equal to the voltage of the first excitation signal minus the voltage of the common potential. In some examples, the third resistor 252 is part of a voltage divider circuit element. In such examples, the resistance of the third resistor 252 can step down the voltage of the first excitation signal.

[0062] The third conductor 256 has a first terminal that can be coupled to the sensing resistor 130 and to the lens cover system 110, and a second terminal that can be coupled to the resistor 260. The third conductor 256 receives the modified first excitation signal from the sensing resistor 130. The modified first excitation signal is approximately equal to the first excitation signal minus the voltage difference across the sensing resistor 130. The third capacitor 256 removes DC offset and / or relatively low frequency noise from the modified first excitation signal. The third capacitor 256 may be called a blocking capacitor. The third capacitor 256 supplies the modified first excitation signal to the fourth resistor 260.

[0063] The fourth resistor 260 has a first terminal coupled to the third capacitor 256, resistors 264 and 268, and the first amplifier 272. The fourth resistor 260 receives the modified first excitation signal from the third resistor 256. The fourth resistor 260 reduces the current of the modified first excitation signal. The fourth resistor 260 may be called a current-limiting resistor. In some examples, the fourth resistor 260 stabilizes the timing of the RC circuit formed by resistors 264 and 268 and the third capacitor 256. The fourth resistor 260 supplies the modified first excitation signal to resistors 264 and 268 and the first amplifier 272.

[0064] The fifth resistor 264 has a first terminal connected to the supply terminal 200 and a second terminal connected to resistors 260, 268, and the first amplifier 272. The fifth resistor 264 receives the supply voltage from the supply terminal 200 and the modified first excitation signal from the fourth resistor 260. The fifth resistor 264 generates a voltage difference approximately equal to the supply voltage minus the voltage of the modified first excitation signal. In some examples, the fifth resistor 264 is part of a voltage divider circuit element. In such examples, the resistance of the fifth resistor 264 can step down the voltage of the modified first excitation signal.

[0065] The sixth resistor 268 has a first terminal coupled to resistors 260, 264, and the first amplifier 272, and a second terminal coupled to a common potential. The sixth resistor 268 receives the modified first excitation signal from the fourth resistor 260 and the common potential from its common terminal. The sixth resistor 268 generates a voltage difference approximately equal to the voltage of the modified first excitation signal minus the voltage of the common potential. In some examples, the sixth resistor 268 is part of a voltage divider circuit element. In such examples, the resistance of the sixth resistor 268 can step down the voltage of the modified first excitation signal.

[0066] The first amplifier 272 has first inputs coupled to resistors 244, 248, and 252, and second inputs coupled to resistors 260, 264, and 268. The first amplifier 272 has an output that can be coupled to the controller circuit element 115. Resistors 244, 248, and 252 set the voltage of the first input of the first amplifier 272 in proportion to the first excitation signal. Resistors 260, 264, and 268 set the voltage of the second input of the first amplifier 272 in proportion to the modified first excitation signal. The first amplifier 272 sets the sensing current voltage based on the difference between the voltages of the first and second inputs. In the exemplary operation, the sensing current voltage is proportional to the voltage difference across the sensing resistor 130. In such an example, the current of the first excitation signal is approximately equal to the sensing current voltage divided by the resistance of the sensing resistor 130. Resistors 244, 248, 252, 260, 264, and 268 can step down the voltage at the input of the first amplifier 272 in order to reduce the magnitude of the voltage difference across the sensing resistor 130. In such an example, the controller circuit element 115 can determine the voltage of the sensing current in response to the voltage being stepped down. The first amplifier 272 supplies the sensing current to the controller circuit element 115.

[0067] The fourth capacitor 276 has a first terminal which can be coupled to the sensing resistor 130 and to the lens cover system 110, and a second terminal which can be coupled to the seventh resistor 280. The fourth capacitor 276 receives the modified first excitation signal from the sensing resistor 130. The fourth capacitor 276 removes DC offset and / or relatively low frequency noise from the modified first excitation signal. The fourth capacitor 276 may be called a blocking capacitor. The fourth capacitor 276 supplies the modified first excitation signal to the seventh resistor 280.

[0068] The seventh resistor 280 has a first terminal connected to the fourth capacitor 276 and a second terminal connected to resistors 284 and 288. The seventh resistor 280 receives the modified first excitation signal from the fourth capacitor 276. The seventh resistor 280 reduces the current of the modified first excitation signal. The seventh resistor 280 may be called a current-limiting resistor. In some examples, the seventh resistor 280 stabilizes the timing of the RC circuit formed by resistors 284 and 288 and the fourth capacitor 276. In some examples, the seventh resistor 280 is part of a voltage divider circuit element. In such examples, the resistance of the seventh resistor 280 may step down the voltage of the modified first excitation signal. The seventh capacitor 280 supplies the modified first excitation signal to resistors 284 and 288.

[0069] The eighth resistor 284 has a first terminal connected to resistors 280 and 288 and a second terminal connected to a common potential. The eighth resistor 284 receives the modified first excitation signal from the seventh resistor 280 and the common potential from its common terminal. The eighth resistor 284 generates a voltage difference approximately equal to the voltage of the modified first excitation signal minus the voltage of the common potential. In some examples, the eighth resistor 284 is part of a voltage divider circuit. In such examples, the resistance of the eighth resistor 284 can step down the voltage of the modified first excitation signal.

[0070] The ninth resistor 288 has a first terminal connected to resistors 280 and 284 and a second terminal connected to the second amplifier 298. The ninth resistor 288 receives the modified first excitation signal from resistors 280 and 284. The ninth resistor 288 can reduce the current of the modified first excitation signal. In some examples, the ninth resistor 288 is part of a voltage divider circuit element. In such examples, the resistance of the ninth resistor 288 can step down the voltage of the modified first excitation signal.

[0071] The fifth capacitor 290 has a first terminal which can be coupled to the first capacitor 232, the second inductor 236, and the lens cover system 110, and a second terminal which can be coupled to the tenth resistor 292. The fifth capacitor 290 receives the second excitation signal of the differential pair of excitation signals from the second inductor 236. The fifth capacitor 290 removes DC offset and / or relatively low frequency noise from the second excitation signal. The fifth capacitor 290 may be called a blocking capacitor. The fifth capacitor 290 supplies the second excitation signal to the tenth resistor 292.

[0072] The tenth resistor 292 has a first terminal connected to the fifth capacitor 290 and a second terminal connected to resistors 294 and 296. The tenth resistor 292 receives the second excitation signal from the fifth capacitor 290. The tenth resistor 292 reduces the current of the second excitation signal. The tenth resistor 292 may be called a current-limiting resistor. In some examples, the tenth resistor 292 stabilizes the timing of the RC circuit formed by resistors 294 and 296 and the fifth capacitor 290. In some examples, the tenth resistor 292 is part of a voltage divider circuit element. In such examples, the resistance of the tenth resistor 292 may step down the voltage of the second excitation signal. The tenth resistor 292 supplies the second excitation signal to resistors 294 and 296.

[0073] The eleventh resistor 294 has a first terminal connected to resistors 292 and 296 and a second terminal connected to a common terminal. The eleventh resistor 294 receives the second excitation signal from the tenth resistor 292 and the common potential from the common terminal. The eleventh resistor 294 generates a voltage difference approximately equal to the voltage of the second excitation signal minus the voltage of the common potential. In some examples, the eleventh resistor 294 is part of a voltage divider circuit element. In such examples, the resistance of the eleventh resistor 294 can step down the voltage of the second excitation signal.

[0074] The twelfth resistor 296 has a first terminal connected to resistors 292 and 294 and a second terminal connected to the second amplifier 298. The twelfth resistor 296 receives the second excitation signal from resistors 292 and 294. The twelfth resistor 296 can reduce the current of the second excitation signal. In some examples, the twelfth resistor 296 is part of a voltage divider circuit element. In such examples, the resistance of the twelfth resistor 296 can step down the voltage of the second excitation signal.

[0075] The second amplifier 298 has a first input coupled to a ninth resistor 288 and a second input coupled to a twelfth resistor 296. The second amplifier 298 has an output that can be coupled to the controller circuit element 115. The ninth resistor 288 sets the voltage of the first input of the second amplifier 298 in proportion to the modified first excitation signal. The twelfth resistor 296 sets the voltage of the second input of the second amplifier 298 in proportion to the second excitation signal. The second amplifier 298 sets the sensing voltage based on the difference between the voltages of the first and second inputs. In the exemplary operation, the sensing voltage is proportional to the voltage difference of the differential pair of excitation signals. In such an example, the sensing voltage is proportional to the voltage supplied to the lens cover system 110. Resistors 280, 284, 288, 292, 294, and 296 can step down the voltage at the input of the second amplifier 298 to reduce the magnitude of the differential voltage difference of the excitation signal pair. In such an example, the controller circuit element 115 can determine the sensing voltage in response to the voltage step-down. The second amplifier 298 supplies the sensing voltage to the controller circuit element 115.

[0076] Figure 3 is a block diagram of an illustrative implementation of the controller circuit element 115 of Figure 1. The controller circuit element 115 of Figure 3 can be instantiated (e.g., create an instance, give it an arbitrary duration, materialize it, implement it, etc.) by a programmable circuit element such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, the controller circuit element 115 of Figure 3 can be instantiated (e.g., create an instance, give it an arbitrary duration, materialize it, implement it, etc.) by (1) an application-specific integrated circuit (ASIC) and / or (2) a field-programmable gate array (FPGA) structured and / or configured in response to the execution of a second instruction to perform an operation corresponding to the first instruction. Therefore, some or all of the circuit elements of Figure 3 can be instantiated together or together. Some or all of the circuit elements of Figure 3 can be instantiated, for example, in one or more threads running simultaneously and / or sequentially on hardware. Furthermore, in some examples, some or all of the circuit elements in Figure 3 may be implemented by microprocessor circuit elements that execute instructions for implementing one or more virtual machines and / or containers, and / or FPGA circuit elements that perform operations for implementing one or more virtual machines and / or containers.

[0077] The controller circuit element 115 has first and second outputs that can be coupled to the I / V sensing circuit element 135 in Figures 1 and 2. The controller circuit element 115 also has first and second outputs that can be coupled to the amplifier circuit element 120 in Figures 1 and 2. In the example in Figure 3, the controller circuit element 115 includes an exemplary impedance determination circuit element 300, an exemplary windowing (WIN) circuit element 305, an exemplary discrete Fourier transform (DFT) circuit element 310, an exemplary sweep circuit element 315, an exemplary sequencing circuit element 320, an exemplary temperature control circuit element 325, an exemplary signal generation circuit element 330, an exemplary storage 335, an exemplary temperature lookup table (LUT) 340, an exemplary driver library 345, an exemplary hardware interface circuit element 350, an exemplary PWM generation circuit element 355, an exemplary pre-driver circuit element 360, an exemplary power control circuit element 365, an exemplary system fault circuit element 370, an exemplary calibration circuit element 375, an exemplary mass detection circuit element 380, and an exemplary cleaning circuit element 385. The controller circuit element 115 receives the sensed current (I) from the I / V sensing circuit element 135. SENSE [n]) and sensing voltage (V SENSE [n]) is received. The controller circuit element 115 generates a differential pair of preamplifier signals based on the sensed current and sensed voltage. The regulator circuit element 105 in Figure 1 supplies an excitation signal to the lens cover system 110 in Figure 1 in response to the differential pair of preamplifier signals from the controller circuit element 115.

[0078] The impedance determination circuit element 300 has first and second inputs that can be coupled to the I / V sensing circuit element 135. The impedance determination circuit element 300 has an output coupled to a sweep circuit element 315, a temperature adjustment circuit element 325, a power regulator circuit element 365, a system fault circuit element 370, a calibration circuit element 375, and a mass detection circuit element 380. In the example of FIG. 3, the impedance determination circuit element 300 includes a window winding circuit element 305 and a DFT circuit element 310. In some examples, the impedance determination circuit element 300 is instantiated by a programmable circuit element executing impedance determination instructions and / or is configured to perform operations such as those represented by the flowchart of FIG. 7A.

[0079] The window winding circuit element 305 has first and second inputs that can be coupled to the I / V sensing circuit element 135 and first and second outputs coupled to the DFT circuit element 310. The window winding circuit element 305 receives sensed current and voltage from the I / V sensing circuit element 135. In some examples, the window winding circuit element 305 includes an analog-to-digital converter (ADC) that converts the sensed current and voltage analog voltages to digital values. In such examples, the digital output of the ADC is at discrete times representing a sampling operation. The window winding circuit element 305 determines a plurality of values (I SENSE [n,n - 1,…n - k] and V SENSE [n,n - 1,…n - k]) of the sensed current and voltage. In some examples, the window winding circuit element 305 periodically samples the sensed current and voltage (I SENSE [n] and V SENSE [n]). In such examples, the window winding circuit element 305 has the sensed current and voltage (I SENSE [n - 1,…n - k] and V SENSEThe windowing circuit element 305 stores multiple previous values ​​(n-1, ...nk) for multiple previous samples (k) before overwriting the sampled values. The windowing circuit element 305 supplies the multiple values ​​of the sensed current and voltage to the DFT circuit element 310. In some examples, the windowing circuit element 305 is instantiated by a programmable circuit element executing a windowing instruction and / or is configured to perform an action such as that represented by the flowchart in Figure 7A.

[0080] The DFT circuit element 310 has first and second inputs coupled to the winding circuit element 305, and outputs coupled to the sweep circuit element 315, the temperature control circuit element 325, the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, and the mass detection circuit element 380. The DFT circuit element 310 receives multiple values ​​of sensed current and voltage from the winding circuit element 305. The DFT circuit element 310 generates a first DFT value that approximately represents the sensed current at a given frequency and a second DFT value that approximately represents the sensed voltage at a given frequency. In some examples, the DFT circuit element 310 transforms multiple values ​​of sensed current and voltage from the discrete-time domain ([n]) to the complex-frequency domain ([k]). Such operation may be called the discrete Fourier transform. In the complex-frequency domain, the DFT circuit element 310 represents the sensed current and voltage using phase and magnitude. In the example shown in Figure 3, the DFT circuit element 310 determines that the frequency response representing the impedance (Z[k]) of the lens cover system 110 is approximately equal to the second DFT value divided by the first DFT value. For example, the impedance of the lens cover system 110 is approximately equal to the sensed voltage divided by the sensed current over a predetermined time. The DFT circuit element 310 supplies the determined impedance (Z[k]) to the temperature control circuit element 325, the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, and the mass detection circuit element 380. In some examples, the DFT circuit element 310 is instantiated by a programmable circuit element executing a DFT instruction and / or is configured to perform operations such as those represented by the flowchart in Figure 7A.

[0081] The sweep circuit element 315 has a first input coupled to the DFT circuit element 310 and a second input coupled to the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, the mass detection circuit element 385, and the cleaning circuit element 385. The sweep circuit element 315 has a third input coupled to the storage 335 and the hardware interface circuit element and an output coupled to the hardware interface circuit element 350 and the PWM generation circuit element 355. In the example in Figure 3, the sweep circuit element 315 includes a sequencing circuit element 320, a temperature control circuit element 325, and a signal generation circuit element 330. The sweep circuit element 315 generates a chirp signal (V) based on burst excitation information from one or more of the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, the mass detection circuit element 380, and / or the cleaning circuit element 385. D [n]) is generated. The sweep circuit element 315 orders the generation of chirp signals to regulate the temperature of transducer 150 in Figure 1. In some examples, the sweep circuit element 315 generates subburst excitation information so that temperature control circuit element 325 determines the temperature of transducer 150. The sweep circuit element 315 supplies chirp signals to hardware interface circuit element 350. An example of the sweep circuit element 315 is described further below in relation to Figure 4. In some examples, the sweep circuit element 315 is instantiated by a programmable circuit element executing a sweep instruction and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A, 7B and 8.

[0082] The sequencing circuit element 320 has a first input coupled to the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, and the mass detection circuit element 380, and a second input coupled to the temperature control circuit element 325. The sequencing circuit element 320 has a first output coupled to the signal generation circuit element 330 and a second output coupled to the temperature control circuit element 325. The sequencing circuit element 320 receives burst excitation information (BURST(A)) from one or more of the power regulator circuit element 365, the system fault circuit element 370, the calibration circuit element 375, the mass detection circuit element 385, and / or the cleaning circuit element 385. D [n], F START F STOP F STEP Φ[n], DUR BURST ) receives. In some examples, the sequencing circuit element 320 is instantiated by the programmable circuit element executing sequence instructions and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A, 7B, and 8.

[0083] In the example in Figure 3, the burst excitation information is the amplitude (A D [n]), starting frequency (F START ), stop frequency (F STOP ), frequency step (F STEP ), offset (Φ[n]), and burst duration (DUR BURST This includes information that identifies the burst excitation information. The amplitude of the burst excitation information identifies the amplitude of the excitation signal, which is represented by the differential pair of excitation signals. The start frequency of the burst excitation information identifies the minimum frequency of the excitation signal. The stop frequency of the burst excitation information identifies the maximum frequency of the excitation signal. The start and stop frequencies form the frequency range of the excitation signal.

[0084] The frequency step of the burst excitation information specifies the interval between frequencies of the excitation signal. The excitation signal of a given instance of burst excitation information may be a sinusoidal signal with a fluctuating frequency. During the exemplary operation, the excitation signal may have a first frequency approximately equal to the start frequency for a first duration, and a second frequency approximately equal to the start frequency plus the frequency step for a second duration. In such exemplary operation, the final duration of the excitation signal corresponding to the burst excitation information will have a frequency approximately equal to the stop frequency.

[0085] The burst excitation information offset identifies a phase shift in the excitation signal. In some examples, the burst excitation information offset optimizes power transmission in the lens cover system 110. In such examples, the burst excitation information offset can alter the phase difference between the power supplied to the lens cover system 110 and the power consumed by the lens cover system 110. Advantageously, reducing the phase difference between the power supplied to the lens cover system 110 and the power consumed by the lens cover system 110 increases the power efficiency of the regulator circuit element 105.

[0086] The burst duration of burst excitation information determines the duration of the excitation signal. In some examples, the sweep circuit element 315 determines the duration of each frequency step of the excitation signal based on the burst duration. In such examples, the sweep circuit element 315 determines that the duration at each frequency is approximately equal to the duration obtained by dividing the burst duration by the number of frequencies in the frequency range across the frequency steps.

[0087] The sequencing circuit element 320 initiates temperature measurement by displaying a temperature sensing indicator (TEMP SENSE) generates. Temperature measurement includes interrupting the supply of burst excitation information and causing the temperature control circuit element 325 to generate temperature excitation information for determining the temperature of the transducer 150. In some examples, the sequencing circuit element 320 periodically sets the temperature sensing display to measure the temperature after a temperature sensing interval. In such examples, the sequencing circuit element 320 may need to separate the supply of burst excitation information in order to enable temperature measurement.

[0088] The sequencing circuit element 320 divides the burst excitation information into multiple sub-burst excitation pieces. These sub-burst excitation pieces represent information about the burst excitation over a series of relatively short operations. The sequencing circuit element 320 supplies one of the sub-burst excitation pieces to the signal generation circuit element 330 during the temperature measurement of the temperature control circuit element 325. Advantageously, the sequencing circuit element 320 allows the temperature control circuit element 325 to adjust the temperature of the transducer 150 while the excitation signal corresponding to the burst excitation information is being generated. An example of the generation of sub-burst excitation pieces is described further below in relation to Figure 4.

[0089] The sequencing circuit element 320 receives a temperature OK indicator (TEMP_OK) from the temperature control circuit element 325 in response to the temperature sensing indicator. The temperature OK indicator indicates whether the temperature of the transducer 150 is low enough to continue generating an excitation signal. If the temperature of the transducer 150 is not low enough to continue generating an excitation signal, the sequencing circuit element 320 causes the transducer 150 to cool down. During the cool-down, the sequencing circuit element 320 prevents the supply of sub-burst excitation information to the signal generation circuit element 330. During the cool-down, the sequencing circuit element 320 continues to set the temperature sensing indicator to initiate further temperature measurements. When the temperature OK indicator indicates that the temperature of the transducer 150 is low enough to continue generating an excitation signal, the sequencing circuit element 320 begins supplying sub-burst excitation information to the signal generation circuit element 330.

[0090] The temperature control circuit element 325 has a first output coupled to the sequencing circuit element 320, a second output coupled to the DFT circuit element 310, and a third output coupled to the storage 335. The temperature control circuit element 325 has a first output coupled to the sequencing circuit element 320 and a second output coupled to the sequencing circuit element 320 and the signal generation circuit element 330. The temperature control circuit element 325 receives the impedance of the transducer 150 and a temperature sensing indicator. In response to the temperature sensing indicator, the temperature control circuit element 325 determines the temperature of the lens cover system 110.

[0091] In some examples, the temperature control circuit element 325 supplies temperature burst excitation information to the signal generation circuit element 330. The regulator circuit element 105 supplies a temperature-sensing excitation signal to the lens cover system 110 in response to the temperature control circuit element 325 supplying temperature burst excitation information to the signal generation circuit element 330. The temperature control circuit element 325 receives the impedance of the lens cover system 110 in response to the temperature-sensing excitation signal from the DFT circuit element 310. The temperature control circuit element 325 determines the temperature of the lens cover system 110 in response to comparing the impedance with the value of the temperature LUT 340.

[0092] The temperature control circuit element 325 compares the determined temperature of the lens cover system 110 with a threshold temperature and generates a temperature OK indicator. When the determined temperature is lower than the threshold temperature, the temperature control circuit element 325 determines that the lens cover system 110 is operating at a safe temperature (e.g., a temperature lower than half the Curie temperature of the transducer 150). When the determined temperature is higher than the threshold temperature, the temperature control circuit element 325 determines that the lens cover system 110 is not operating at a safe temperature (e.g., a temperature higher than half the Curie temperature of the transducer 150). The temperature control circuit element 325 supplies a temperature OK indicator to the sequencing circuit element 320. An example of the temperature control circuit element 325 is shown below in Figure 4. In some examples, the temperature control circuit element 325 is instantiated by a programmable circuit element executing a temperature control command and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A and 7B.

[0093] The signal generation circuit element 330 has inputs coupled to the sequencing circuit element 320 and the temperature control circuit element 325. The signal generation circuit element 330 receives excitation information from the sequencing circuit element 320 and / or the temperature control circuit element 325. In response to the excitation information, the signal generation circuit element 330 generates a chirp signal. The chirp signal is a discrete representation of a sinusoidal waveform having characteristics corresponding to the excitation information. In some examples, the signal generation circuit element 330 varies the frequency of the chirp signal based on the excitation information specifying a range of frequencies. The signal generation circuit element 330 supplies the chirp signal to the hardware interface circuit element 355 and the PWM generation circuit 355. In some examples, the signal generation circuit element 330 is instantiated by a programmable circuit element executing a signal generation instruction and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A and 7B.

[0094] The storage 335 is coupled to the sweep circuit element 315, the temperature control circuit element 325, and the hardware interface circuit element 350. In the example in Figure 3, the storage 335 includes a temperature LUT 340 and a driver library 345. The temperature LUT 340 contains data that identifies the temperature of the lens cover system 110 based on impedance. The temperature control circuit element 325 determines the temperature of the lens cover system 110 based on the value of the temperature LUT 340. The driver library 345 includes instructions and / or operations that constitute and / or use the hardware of the regulator circuit element 105. In some examples, the instructions and / or operations of the driver library 345 are performed using programmable circuit elements. In such examples, executing and / or performing the instructions and / or operations of the driver library 345 may instantiate a circuit element configured to perform one or more operations of the controller circuit element 115.

[0095] The hardware interface circuit element 350 has a first input coupled to the sweep circuit element 315 and the signal generation circuit element 330, and a second input coupled to the storage 335. The hardware interface circuit element 350 has first and second outputs that can be coupled to the amplifier circuit element 120. In the example in Figure 3, the hardware interface circuit element 350 includes a PWM circuit element 355 and a pre-driver circuit element 360. The hardware interface circuit element 350 receives a chirp signal. The hardware interface circuit element 350 modulates the chirp signal to generate a differential pair of pre-amplifier signals. In some examples, the hardware interface circuit element 350 accesses the driver library 345 to interface with the circuit elements of the regulator circuit element 105. For example, the hardware interface circuit element 350 may instantiate the PWM circuit element 355 and / or the pre-driver circuit element 345 depending on the instructions and / or actions of the driver library 345. The hardware interface circuit element 350 supplies the differential pair of preamplifier signals to the amplifier circuit element 120.

[0096] The PWM generation circuit element 355 has an input coupled to the sweep circuit element 315 and the signal generation circuit element 330, and an output coupled to the pre-driver circuit element 360. The PWM generation circuit element 355 receives a chirp signal. The PWM generation circuit element 355 generates a PWM chirp signal (D[n]) by modulating the chirp signal. The PWM generation circuit element 355 varies the duty cycle of the PWM chirp signal to represent different amplitudes of the chirp signal. In some examples, the PWM generation circuit element 355 generates a PWM chirp signal by comparing the chirp signal with a triangular waveform. In such examples, the PWM generation circuit element 355 increases the duty cycle of the PWM chirp signal to represent an increase in the amplitude of the chirp signal, and decreases the duty cycle of the PWM chirp signal to represent a decrease in the amplitude of the chirp signal. Such examples are illustrated in Figure 6 and described further thereafter. The PWM generation circuit element 355 supplies the PWM chirp signal to the pre-driver circuit element 360. In some examples, the PWM circuit element 355 is instantiated by a programmable circuit element executing a PWM generation instruction and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A and 7B.

[0097] The pre-driver circuit element 360 has an input coupled to the PWM generation circuit element 355 and first and second outputs that can be coupled to the amplifier circuit element 120. The pre-driver circuit element 360 receives a PWM chirp signal from the PWM generation circuit element 355. The pre-driver circuit element 360 converts the single-ended PWM chirp signal into a differential pair of pre-amplifier signals. In some examples, the pre-driver circuit element 360 increases the signal strength (e.g., magnitude, drive strength) of the differential pair of pre-amplifier signals. In such examples, the pre-driver circuit element 360 is configured to control the differential pair of pre-amplifier signals shown in Figure 2. The pre-driver circuit element 360 supplies the differential pair of pre-amplifier signals to the amplifier circuit element 120. In some examples, the pre-driver circuit element 360 is instantiated by the programmable circuit element executing pre-driver instructions and / or is configured to perform operations such as those represented by the flowcharts in Figures 7A and 7B.

[0098] The power control circuit element 365 has an input coupled to the DFT circuit element 310 and an output coupled to the sequencing circuit element 320. The power control circuit element 365 receives the impedance of the lens cover system 110 from the DFT circuit element 310. The power control circuit element 365 supplies power control excitation information to the sequencing circuit element 320. The power control excitation information is burst excitation information specific to the operation of determining the power supplied to the lens cover system 110. The regulator circuit element 105 generates a power control excitation signal in response to the power control excitation information. The power control circuit element 365 receives the impedance of the lens cover system 110 in response to generating the power control excitation signal. The power control circuit element 365 determines the power efficiency of the power supply to the lens cover system 110 based on the impedance and the characteristics of the power control excitation signal. In some examples, the power control circuit element 365 modifies the power efficiency by varying the phase and / or frequency of the subsequent excitation information. In such examples, the power control circuit element 365 modifies the power efficiency to improve the performance of the lens cover system 110. In some examples, the power control circuit element 365 is instantiated by a programmable circuit element executing a power control instruction.

[0099] The system fault circuit element 370 has an input coupled to the DFT circuit element 310 and an output coupled to the sequencing circuit element 320. The system fault circuit element 370 receives the impedance of the lens cover system 110 from the DFT circuit element 310. The system fault circuit element 370 supplies fault detection excitation information to the sequencing circuit element 320. The fault detection excitation information is burst excitation information specific to the operation of detecting faults in the system 100. The regulator circuit element 105 generates a fault detection excitation signal in response to the fault detection excitation information. The system fault circuit element 370 receives the impedance of the lens cover system 110 in response to generating the fault detection excitation signal. Based on the impedance and the characteristics of the power regulation excitation signal, the system fault circuit element 370 detects a fault (e.g., mechanical failure, electrical short circuit, malfunction) in the power supply to the lens cover system 110. In some examples, the system failure circuit element 370 prevents the supply of subsequent excitation information in response to detecting a failure in the power supply to the lens cover system 110. In some examples, the system failure circuit element 370 is instantiated by a programmable circuit element executing a system failure instruction.

[0100] Calibration circuit element 375 has an input coupled to DFT circuit element 310 and an output coupled to sequencing circuit element 320. Calibration circuit element 375 receives the impedance of the lens cover system 110 from DFT circuit element 310. Calibration circuit element 375 supplies calibration excitation information to sequencing circuit element 320. Calibration excitation information is burst excitation information specific to the operation of calibrating regulator circuit element 105. Regulator circuit element 105 generates a calibration excitation signal in response to the calibration excitation information. Calibration circuit element 375 receives the impedance of the lens cover system 110 in response to generating the calibration excitation signal. Calibration circuit element 375 determines the characteristics of the generated excitation signal based on the impedance and the information from the calibration excitation information. In some examples, calibration circuit element 375 calibrates controller circuit element 115 by varying the amplitude, phase, and / or frequency of subsequent excitation information. In such examples, the calibration circuit element 375 modifies the generation of the subsequent excitation signal to improve cleaning performance. In some examples, the calibration circuit element 375 is instantiated by a programmable circuit element executing a calibration instruction.

[0101] The mass detection circuit element 380 has an input coupled to the DFT circuit element 310 and an output coupled to the sequencing circuit element 320. The mass detection circuit element 380 receives the impedance of the lens cover system 110 from the DFT circuit element 310. The mass detection circuit element 380 supplies mass detection excitation information to the sequencing circuit element 320. The mass detection excitation information is burst excitation information specific to the operation of detecting a change in mass on the lens cover 155 in Figure 1, such as the addition of contaminant 160 in Figure 1. The regulator circuit element 105 generates a mass detection excitation signal in response to the mass detection excitation information. The mass detection circuit element 380 receives the impedance of the lens cover system 110 in response to generating the mass detection excitation signal. The mass detection circuit element 380 detects a change in mass on the lens cover system 110 based on the impedance and the mass detection excitation information. In some examples, the mass detection circuit element 380 initiates a cleaning sequence in response to detecting an increase in the mass of the lens cover system 110. In some examples, the mass detection circuit element 380 is instantiated by a programmable circuit element executing a mass detection instruction.

[0102] The cleaning circuit element 385 has an output coupled to the sequencing circuit element 320. The cleaning circuit element 385 supplies cleaning excitation information to the sequencing circuit element 320. The cleaning excitation information is burst excitation information specific to the operation of exciting the lens cover system 110 to remove contaminants 160. The regulator circuit element 105 generates a cleaning excitation signal in response to the cleaning excitation information. In some examples, the cleaning circuit element 385 periodically cleans the lens cover system 110. In other examples, the cleaning circuit element 385 cleans the lens cover system 110 in response to indications from the mass detection circuit element 380 and / or indications from alternative circuit elements. In some examples, the cleaning circuit element 385 is instantiated by a programmable circuit element executing a cleaning command.

[0103] Figure 4 is a block diagram of an implementation of an example sweep circuit element in Figure 3 for regulating the temperature of transducer 150 in Figure 1. The sweep circuit element 315 in Figure 2 may be instantiated (e.g., create an instance, give it an arbitrary duration, materialize it, implement it, etc.) by a programmable circuit element such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, the sweep circuit element 315 in Figure 4 may be instantiated (e.g., create an instance, give it an arbitrary duration, materialize it, implement it, etc.) by (1) an application-specific integrated circuit (ASIC) and / or (2) a field-programmable gate array (FPGA) structured and / or configured in response to the execution of a second instruction to perform an operation corresponding to the first instruction. Some or all of the circuit elements in Figure 4 may therefore be instantiated at the same or different times. Some or all of the circuit elements in Figure 4 may be instantiated, for example, in one or more threads running simultaneously and / or sequentially on hardware. Furthermore, in some examples, some or all of the circuit elements in Figure 4 may be implemented by microprocessor circuit elements and / or FPGA circuit elements that execute instructions to perform operations for implementing one or more virtual machines and / or containers.

[0104] Figure 4 is a block diagram of an example of the sweep circuit element, the sequencing circuit element 320, and the temperature control circuit element 325 of Figure 3. In the example of Figure 4, the sequencing circuit element 320 includes an exemplary sub-burst duration circuit element 405, an exemplary sub-burst frequency circuit element 410, an exemplary sub-burst tracker circuit element 415, an exemplary sub-burst generation circuit element 420, an exemplary temperature sensing sequencing circuit element 425, an exemplary temperature sensing timer circuit element 430, an exemplary cool-down timer circuit element 435, an exemplary sensing interval value 440, and an exemplary sensing duration value 445. In the example of Figure 4, the temperature control circuit element 325 includes an exemplary temperature burst generation circuit element 450, an exemplary multiplication circuit element 455, an exemplary temperature selection circuit element 460, and an exemplary temperature comparison circuit element 465.

[0105] The sub-burst duration circuit element 405 has a first input which can be coupled to one or more of the circuit elements 365, 370, 375, 380, and 385 in Figure 3, a second input which is coupled to the sensing interval value 440, and a third input which is coupled to the sensing duration value 445. The sub-burst duration circuit element 405 has first and second outputs which are coupled to the sub-burst tracker circuit element 415 and the sub-burst generation circuit element 420. The sub-burst duration circuit element 405 sets the burst duration (DUR) of the burst excitation information. BURST The subburst duration circuit element 405 receives a sensing interval value of 440 and a sensing duration value of 445. The interval between temperature measurements (TEMP) is based on the sensing interval value of 440. INT ) and the duration of temperature measurement based on the sensing duration value 445 (DUR TEMP The subburst duration circuit element 405 determines that the maximum subburst duration is approximately equal to the interval between temperature measurements minus the duration of the temperature measurement.

[0106] The subburst duration circuit element 405 responds to a comparison of the maximum subburst duration with the burst duration by determining the subburst duration (DUR SUB_BURST The subburst duration circuit element 405 determines that the subburst duration is approximately equal to the maximum burst duration. If the maximum subburst duration exceeds the burst duration, the subburst duration circuit element 405 determines that the subburst duration is approximately equal to the burst duration. The subburst duration circuit element 405 supplies the subburst duration to the subburst tracker circuit element 415 and the subburst generation circuit element 420.

[0107] The subburst duration circuit element 405, in response to determining the subburst duration, calculates the total number of subburst values ​​(SUB_BURST TOTALThe subburst value is determined by the number of instances of subburst excitation information required to represent the burst duration of the burst excitation information. In some examples, the subburst duration circuit element 405 determines the number of subburst values ​​by dividing the burst duration by the subburst duration. The subburst duration circuit element 405 supplies the total number of subburst values ​​to the subburst frequency circuit element 410 and the subburst tracker circuit element 415.

[0108] The sub-burst frequency circuit element 410 has a first input which can be coupled to one or more of the circuit elements 365, 370, 375, 380, and 385, a second input which is coupled to the sub-burst duration circuit element 405, and a third input which is coupled to the sub-burst tracker circuit element 415. The sub-burst frequency circuit element 410 has an output which is coupled to the sub-burst generation circuit element 420. The sub-burst frequency circuit element 410 sets the start frequency (F) of the burst excitation information. START ), stop frequency (F STOP ), and frequency step (F STEP The subburst frequency circuit element 410 receives the total number of subburst values ​​and the subburst exponent (SUB_BURST). NUM The subburst tracker circuit element 415 receives the subburst index. The subburst index is an index value that indicates which of the total number of subbursts is supplied to the signal generation circuit element 330. In some examples, the subburst index is the number between the initial value of the subburst and the total number.

[0109] The sub-burst frequency circuit element 410 determines that the frequency range of the burst excitation information is the frequency between the start frequency and the stop frequency of the burst excitation information. The sub-burst frequency circuit element 410 determines the total number of steps between the start frequency and the stop frequency by dividing the difference between the start frequency and the stop frequency by the frequency step. For each sub-burst in the total number of sub-bursts, the sub-burst start frequency (F START_SUB ) and sub-burst stop frequency (FSTOP_SUB The circuit element 410 generates the subburst frequency. The subburst start frequency is determined by adding a frequency step to the previous subburst stop frequency. In some examples, the subburst start frequency corresponding to the first subburst excitation information is approximately equal to the start frequency. The circuit element 410 determines the subburst stop frequency by adding the difference between the start frequency and the stop frequency divided by the total number of subburst values ​​to the subburst start frequency. In some examples, the subburst stop frequency of the final subburst is approximately equal to the subburst stop frequency of the subburst excitation information.

[0110] The sub-burst frequency circuit element 410 supplies the sub-burst start frequency, sub-burst stop frequency, and frequency step to the sub-burst generation circuit element 420 for each sub-burst. In some examples, the sub-burst frequency circuit element 410 re-determines the sub-burst start frequency and sub-burst stop frequency in response to a change in the sub-burst exponent. In such examples, the change in the sub-burst exponent indicates a transition to a subsequent sub-burst. Advantageously, the sub-burst frequency circuit element 410 divides the frequency range of the burst excitation information into a sub-burst start frequency and a sub-burst stop frequency for each of the total number of sub-bursts.

[0111] The subburst tracker circuit element 415 has a first input coupled to the subburst duration circuit element 405 and the subburst generation circuit element 420, a second input coupled to the cooldown timer circuit element 435, and a third input coupled to the sensed duration value 445. The subburst tracker circuit element 415 has an output coupled to the subburst frequency circuit element 410 and the subburst generation circuit element 420. The subburst tracker circuit element 415 receives the subburst duration, the cooldown indicator (COOL_DIS), and the sensed duration value 445. The cooldown indicator represents the time the transducer 150 in Figure 1 needs to cool down. For example, the cooldown indicator is set in response to the detection that the temperature of the lens cover system 110 is higher than a threshold temperature.

[0112] The subburst tracker circuit element 415 generates a subburst index to index the subburst excitation information of the burst excitation information. The subburst tracker circuit element 415 sets the subburst index to an initial value in response to receiving new burst excitation information. The subburst tracker circuit element 415 modifies the subburst index based on the subburst duration, cooldown indicator, and sensing duration value 445. The subburst tracker circuit element 415 supplies the subburst index to the subburst frequency circuit element 410 and the subburst generation circuit element 420.

[0113] In the exemplary operation, the subburst tracker circuit element 415 determines the time elapsed since the previous modification of the subburst index. In such exemplary operation, the subburst tracker circuit element 415 modifies the subburst index in response to the time being approximately equal to the subburst duration plus the sensing duration value 445. However, when the cooldown indicator indicates that a cooldown is needed, the subburst tracker circuit element 415 maintains the subburst index at its current value. In such operation, the subburst tracker circuit element 415 may modify the subburst index after another subburst duration and sensing duration have occurred. During such operation, the sequencing circuit element 320 does not provide subburst excitation information to the signal generation circuit element 330.

[0114] Advantageously, the cool-down indicator prevents the supply of subsequent sub-burst excitation information to the signal generation circuit element 330. Advantageously, the sub-burst tracker circuit element 415 enables the cool-down indicator to prevent the generation of subsequent excitation signals. Advantageously, by preventing the generation of subsequent excitation signals, it becomes possible to reduce the temperature of the lens cover system 110.

[0115] The subburst generation circuit element 420 has a first input which can be coupled to one or more of the circuit elements 365, 370, 375, 380, and 385; a second input which is coupled to the subburst duration circuit element 405 and the subburst tracker circuit element 415; a third input which is coupled to the subburst frequency circuit element 410; and a fourth input which is coupled to the subburst tracker circuit element 415. The subburst generation circuit element 420 has an output which is coupled to the temperature control circuit element 325 and the signal generation circuit element 330. The subburst generation circuit element 420 receives burst excitation information, amplitude, phase, and frequency step, subburst duration, subburst start and stop frequencies, and subburst exponent. The subburst generation circuit element 420 receives subburst excitation information (SUB_BURST(A) where the amplitude, phase, and frequency step of the burst excitation information, subburst duration, and subburst start and stop frequencies correspond to the subburst exponent. D [n], F START_SUB F STOP_SUB F STEP Φ[n], DUR SUB_BURST The subburst generation circuit element 420 generates a subburst excitation information to the signal generation circuit element 330 in response to a modification of the subburst index.

[0116] In the exemplary operation, the subburst generation circuit element 420 generates subburst excitation information specific to each value of the subburst index. In such exemplary operation, the subburst start and stop frequencies are specific to the value of the subburst index. The subburst excitation information receives the subburst start and stop frequencies from the subburst frequency circuit element 410 for a predetermined value of the subburst index. In such an example, the subburst generation circuit element 420 supplies the subburst excitation information to the signal generation circuit element 330 in response to receiving the subburst start and stop frequencies for a modified value of the subburst index. In other examples, the subburst generation circuit element 420 may store one or more instances of the subburst excitation information to supply as the value of the subburst index changes.

[0117] The temperature-sensing sequencing circuit element 425 is coupled to the sub-burst duration circuit element 405, the sub-burst tracker circuit element 415, the temperature burst generation circuit element 450, the multiplication circuit 455, and the temperature comparison circuit element 465. In the example in Figure 4, the temperature-sensing sequencing circuit element 425 includes the temperature-sensing timer circuit element 430, the cool-down timer circuit element 435, the sensing interval value 440, and the sensing duration circuit element 445. The temperature-sensing sequencing circuit element 425 sequences the temperature measurements. In the example in Figure 4, the temperature-sensing sequencing circuit element 425 periodically sequences the temperature measurements based on the sensing interval value 440. The temperature-sensing sequencing circuit element 425 also implements a cool-down operation sequence for supplying sub-burst excitation information.

[0118] The temperature sensing timer circuit element 430 has an input coupled to a sensing interval value 440 and an output coupled to a temperature burst generation circuit element 450 and a multiplication circuit element 455. The temperature sensing timer circuit element generates a temperature sensing indicator (TEMP_EN) based on the sensing interval value 440. The temperature sensing indicator initiates temperature measurement. The temperature sensing timer circuit element 430 periodically initiates temperature measurement using the temperature sensing indicator. The temperature sensing timer circuit element 430 sets the interval between temperature measurements based on the sensing interval value 440. The temperature sensing timer circuit element 430 supplies the temperature sensing indicator to the temperature burst generation circuit element 450 and the multiplication circuit element 455.

[0119] The cool-down timer circuit element 435 has an input connected to the temperature comparison circuit element 465 and outputs connected to the sub-burst tracker circuit element 415 and the temperature sensing timer circuit element 430. The cool-down timer circuit element 435 receives a temperature OK indicator (TEMP_OK) from the temperature comparison circuit element 465. The temperature OK indicator represents a comparison between the determined temperature and the threshold temperature. When the temperature OK indicator indicates that the determined temperature is higher than the threshold temperature, the cool-down timer circuit element 435 generates a cool-down indicator indicating that cooling is necessary. The cool-down timer circuit element 435 holds the cool-down indicator until the temperature OK indicator indicates that the determined temperature of a subsequent temperature measurement is lower than the threshold temperature. The cool-down timer circuit element 435 supplies the cool-down indicator to the sub-burst tracker circuit element 415.

[0120] The sensing interval value 440 is coupled to the sub-burst duration circuit element 405 and the temperature sensing timer circuit element 430. The sensing interval value 440 represents the interval between temperature measurements. In some examples, the sensing interval value 440 is a register, memory location, etc.

[0121] The sensing duration value 445 is coupled to the sub-burst duration circuit element 405 and the sub-burst tracker circuit element 415. The sensing duration value 445 represents the duration of temperature measurement. In some examples, the sensing duration value 445 is a register, memory location, etc.

[0122] The temperature burst generation circuit element 450 has an input coupled to the temperature sensing timer circuit element 430 and the multiplication circuit element 455, and an output coupled to the signal generation circuit element 330 and the sub-burst generation circuit element 420. The temperature burst generation circuit element 450 receives a temperature sensing indicator. In response to the temperature sensing indicator indicating a temperature measurement, the temperature burst generation circuit element 450 generates temperature burst excitation information (TEMP_BURST(A D [n], F START_TEMP F STOP_TEMP Φ[n], DUR TEMPThe temperature burst excitation information is supplied to the signal generation circuit element 330. The temperature burst excitation information includes information that identifies the amplitude, temperature start frequency, temperature stop frequency, frequency step, phase, and temperature sensing duration. In some examples, the temperature start and stop frequencies are the same. In such examples, the temperature burst excitation information may have a single frequency. The regulator circuit element 105 supplies a temperature excitation signal to the lens cover system 110 in response to the temperature burst excitation information.

[0123] The multiplier circuit element 455 has a first input coupled to the temperature sensing timer circuit element 430 and the temperature burst generation circuit element 450, and a second input which may be coupled to the DFT circuit element 310 in Figure 3. The multiplier circuit element 455 has an output coupled to the temperature selection circuit element 460. The multiplier circuit element 455 receives the impedance of the transducer 150 in Figure 1 from the DFT circuit element 310. The multiplier circuit element 455 determines the impedance of the transducer 150 in response to the supply of temperature burst excitation information. The multiplier circuit element 455 determines the temperature measurement by multiplying the impedance by a gradient constant. In some examples, the multiplier circuit element 455 adds an offset value to the temperature measurement. The offset value takes into account the material of the transducer 150. The multiplier circuit element 455 supplies the temperature measurement to the temperature selection circuit element 460.

[0124] The temperature selection circuit element 460 has a first input coupled to the multiplication circuit element 455 and a second input which may be coupled to the storage 335 in Figure 3. The temperature selection circuit element 460 has an output coupled to the temperature comparison circuit element 465. The temperature selection circuit element 460 receives a temperature measurement and accesses candidate temperature measurements of the temperature LUT 340 in Figure 3. The temperature selection circuit element 460 controls the temperature (TEMP) of the transducer 150. ESTThe temperature selection circuit element 460 determines that the temperature of a candidate temperature measurement is approximately equal to the determined temperature measurement. In some cases, the temperature selection circuit element 460 may determine that the temperature of a candidate temperature measurement is closest to the determined temperature measurement. The temperature selection circuit element 460 supplies the determined temperature to the temperature comparison circuit element 465.

[0125] The temperature comparison circuit element 465 has an input coupled to the temperature selection circuit element 460 and an output coupled to the temperature comparison circuit element 465. The temperature comparison circuit element 465 receives the determined temperature of the transducer 150. In response to a comparison of the determined temperature with a threshold temperature, the temperature comparison circuit element 465 generates a temperature OK indicator. In some examples, the temperature threshold is close to and / or approximately equal to half the Curie temperature of the piezoelectric material of the transducer 150. In other examples, to further improve safety, the temperature threshold is close to and / or approximately equal to one-quarter of the Curie temperature of the piezoelectric material of the transducer 150. In such examples, the temperature comparison circuit element 465 prevents the temperature of the transducer 150 from reaching a temperature that could depolarize the transducer 150.

[0126] Figure 5 is an illustrative timing diagram 500 in which the sequencing circuit element of Figure 3 divides the exemplary burst excitation information 510 into a first exemplary sub-burst excitation information 520, a second exemplary sub-burst excitation information 530, a third exemplary sub-burst excitation information 540, a fourth exemplary sub-burst excitation information 550, and exemplary temperature burst excitation information 560. In the example of Figure 5, the timing diagram 500 illustrates the exemplary operation of the sweep circuit element 315 of Figures 3 and 4 for sequencing temperature measurements to generate excitation signals corresponding to the burst excitation information 510.

[0127] The burst excitation information 510 contains information that identifies the characteristics of the excitation signal. Circuit elements 365, 370, 375, 380, and 385 can generate the burst excitation information 510 to perform one or more operations. For example, the cleaning circuit element 385 can supply the burst excitation information 510 to generate a cleaning excitation signal. In such an example, the cleaning excitation signal excites the transducer 150 in Figure 1, which removes the contaminant 160 in Figure 1 from the lens cover 155 in Figure 1. In another example, the burst excitation information 510 may be generated as part of one or more operations for power regulation, fault detection, calibration, mass detection, etc. The sequencing circuit element 320 in Figures 3 and 4 receives the burst excitation information 510.

[0128] The sequencing circuit element 320 generates sub-burst excitation information 520, 530, 540, and 550 in response to determining that the burst duration of the burst excitation information 510 is longer than the maximum sub-burst duration. The maximum sub-burst duration is approximately equal to the interval between temperature measurements minus the duration of the temperature measurement. When the burst duration is longer than the maximum burst duration, the sequencing circuit element divides the burst excitation information 510 into sub-burst excitation information 520, 530, 540, and 550. By dividing the burst excitation information 510 into sub-burst excitation information 520, 530, 540, and 550, the temperature control circuit element 325 in Figures 3 and 4 can determine the temperature of the transducer 150 in Figure 1.

[0129] The temperature burst excitation information 560 corresponds to the generation of a temperature excitation signal. The temperature control circuit element 325 determines the temperature of the transducer 150 in response to supplying the temperature excitation signal to the lens cover system 110 in Figure 1. The sequencing circuit element 320 supplies the sub-burst excitation information 520, 530, 540, and 550 to the signal generation circuit element 330 in Figures 3 and 4, separates this from the temperature burst excitation information 560. Advantageously, the temperature control circuit element 325 periodically checks the temperature of the transducer 150 between each of the sub-burst excitation information 520, 530, 540, and 550.

[0130] Figure 6 is an example illustrating the waveforms generated by the regulator circuit element 105 in Figures 1, 2, 3, and 4. In the example in Figure 6, the waveforms are the exemplary triangular wave signal 620 and the exemplary chirp signal 620 (V D [n]), including a first exemplary preamplifier signal 630, a second exemplary preamplifier signal 640, and an exemplary relatively high-power signal 650. Signals 610-650 are illustrative representations of signals generated by the regulator circuit element 105 over exemplary durations.

[0131] The PWM generation circuit element 355 in Figure 3 generates a triangular wave signal 610 as a carrier signal. The PWM generation circuit element 355 modulates the chirp signal 620 using the triangular wave signal 610. The frequency of the triangular wave signal 610 may be called the carrier frequency. The frequency of the triangular wave signal 610 may be modulated to reduce even harmonics that may distort the modulated signal. The chirp signal 620 is generated by the signal generation circuit element 330 in Figures 3 and 4 in response to excitation information from the sequencing circuit element 320 in Figures 3 and 4 or the temperature control circuit element 325 in Figures 3 and 4.

[0132] The hardware interface circuit element 350 in Figure 3 generates preamplifier signals 630 and 640 by modulating the chirp signal 620 using the triangular wave signal 610. For example, the PWM generation circuit element 355 generates a PWM chirp signal by comparing the triangular wave signal 610 with the chirp signal 620. The preamplifier signals 630 and 640 represent different amplitudes of the chirp signal 620 using a fluctuating duty cycle. In such an example, the pre-driver circuit element 360 in Figure 3 generates the preamplifier signals 630 and 640 by converting the single-ended PWM chirp signal into a differential pair of signals. The pre-driver circuit element 360 may further modify the differential pair of signals to ensure that the preamplifier signals 630 and 640 can fully enable and / or disable the transistors of the amplifier circuit element 120 in Figures 1 and 2 (e.g., transistors 204, 208, 216, and 220 in Figure 2). The preamplifier signals 630 and 640 form a differential pair of signals from the pre-driver circuit element 360.

[0133] The amplifier circuit element 120 generates a relatively high power signal 650 in response to the preamplifier signals 630 and 640 controlling transistors 204, 208, 216, and 220. In some examples, the amplifier circuit element 120 generates the relatively high power signal 650 as a differential pair of relatively high power signals, as shown in Figure 2. The filter circuit element 125 in Figures 1 and 2 filters the fluctuating duty cycle of the relatively high power signal 650 to generate a sinusoidal excitation signal. The sinusoidal excitation signal of the filter circuit element 125 is a relatively high power version of the chirp signal 620. Advantageously, by modulating the chirp signal 620 to generate the preamplifier signals 630 and 640, the amplifier circuit element 120 can be made into a Class B amplifier circuit element. Advantageously, using a Class B amplifier circuit element increases power efficiency by reducing the need for linear operation of transistors 204, 208, 216, and 220. Alternatively, the regulator circuit element 105 may be modified to implement another type of amplifier circuit element, such as a Class A amplifier or a Class AB amplifier. In such an example, the chirp signal 620 can be supplied directly to the amplifier circuit element 120.

[0134] Figures 7A and 7B form flowcharts representing exemplary machine-readable instructions and / or exemplary operations 700 that can be executed, instantiated, and / or performed using exemplary programmable circuit element implementations of the sweep circuit element 315 in Figures 3 and 4 and / or more generally the controller circuit element 115 in Figures 1 and 3. The exemplary operation 700 begins in block 705, where the sequencing circuit element 320 in Figures 3 and 4 determines whether burst excitation information has been received. In some examples, circuit elements 365, 370, 375, 380, and 385 in Figure 3 supply burst excitation information to the sequencing circuit element 320 to generate an excitation signal for performing the operation. For example, the cleaning circuit element 385 may supply burst excitation information to the sequencing circuit element to generate a cleaning excitation signal. In such an example, the cleaning excitation signal excites the transducer 150 in Figure 1 to remove the contaminant 160 in Figure 1 from the lens cover 160 in Figure 1. If the sequencing circuit element 320 does not receive burst excitation information (for example, if block 705 returns a "no" result), control proceeds to return to block 705.

[0135] When the sequencing circuit element 320 receives burst excitation information (for example, when block 705 returns a "yes" result), the sequencing circuit element 320 parses the burst excitation information into sub-burst excitation information (operation 710). In some examples, the circuit elements 405, 410, and 420 in Figure 4 generate sub-burst excitation information based on the burst excitation information. Operation 710 is described further below in relation to Figure 8.

[0136] The subburst tracker circuit element 415 initializes the subburst exponent to zero (block 715). In some examples, the subburst tracker circuit element 415 sets the subburst exponent to its initial value in response to the sequencing circuit element 320 receiving burst excitation information.

[0137] The temperature burst generation circuit element 450 in Figure 4 supplies temperature burst excitation information to the signal generation circuit element 330 in Figures 3 and 4 (block 720). In some examples, the temperature sensing timer circuit element 430 sets a temperature sensing display to initiate temperature measurement. In such examples, the temperature burst generation circuit element 450 supplies temperature burst excitation information to the signal generation circuit element 330 to initiate temperature measurement.

[0138] The signal generation circuit element 330 generates an excitation signal based on temperature burst excitation information (block 725). In some examples, the signal generation circuit element 330 generates a chirp signal based on temperature burst excitation information. In such examples, the hardware interface circuit element 350 in Figure 3 responds to the chirp signal by supplying a preamplifier signal to the amplifier circuit element 120 in Figures 1 and 2. The amplifier circuit element 120 supplies a relatively high power signal of the preamplifier signal to the filter circuit element 125, thereby supplying the temperature excitation signal to the lens cover system 110.

[0139] The impedance determination circuit element 300 in Figure 3 receives the sensing voltage and current of the excitation signal (block 730). In some examples, the I / V sensing circuit element 135 steps down the temperature excitation signal and the voltage of the sensing resistor 130 in Figures 1 and 2 to generate the sensing current and voltage. In such examples, the I / V sensing circuit element 135 supplies the sensing current and voltage of the temperature excitation signal to the winding circuit element 305 in Figure 3.

[0140] The DFT circuit element 310 in Figure 3 determines functions representing the sensed voltage and current (block 735). In some examples, the DFT circuit element 310 receives multiple values ​​of multiple sensed currents and voltages from the windowing circuit element 305. In such examples, the DFT circuit element 310 determines a first function representing the sensed current and a second function representing the sensed voltage.

[0141] The DFT circuit element 310 determines the impedance of the transducer based on a function (block 740). In some examples, the DFT circuit element 310 determines the transfer function by dividing by the first and second functions. In such examples, the value of the transfer function is approximately equal to the impedance of transducer 150 in Figure 1.

[0142] The multiplier circuit element 455 in Figure 4 multiplies the impedance by a gradient constant and adds an offset (block 745). In some examples, the multiplier circuit element 455 determines a temperature measurement specific to the material of the transducer 150 based on the determined impedance. In such examples, the offset and gradient constant are determined based on the material of the transducer 150.

[0143] The temperature selection circuit element 460 in Figure 4 determines the transducer temperature based on multiplication (block 750). In some examples, the temperature selection circuit element 460 compares the temperature measurement with a candidate temperature measurement of the temperature LUT 340 in Figure 3. In such examples, the temperature selection circuit element 460 determines that the temperature of transducer 150 is approximately equal to a similar temperature measurement of the candidate temperature measurement.

[0144] The temperature comparison circuit element 465 in Figure 4 determines whether the temperature is higher than the threshold temperature (block 755). In some examples, the temperature comparison circuit element 465 determines whether the determined temperature is close to a temperature at which the transducer 150 can be depolarized. For example, the temperature threshold may be approximately equal to half the Curie temperature of the material of the transducer 150.

[0145] If the temperature comparison circuit element 465 determines that the temperature is higher than the threshold temperature (for example, block 755 returns a "yes" result), the temperature sensing timer circuit element 430 in Figure 4 determines whether it is time for another temperature measurement (block 760). In some examples, the cool-down timer circuit element 435 in Figure 4 sets a cool-down indicator to prevent the sub-burst tracker circuit element 415 from altering the sub-burst index. In such examples, the cool-down indicator remains set until subsequent temperature measurements determine that the transducer temperature is lower than the threshold temperature.

[0146] If the temperature sensing timer circuit element 430 determines that it is not time for another temperature measurement (for example, block 760 returns a "no" result), control proceeds to return to block 760. In some examples, the sequencing circuit element 320 does not provide subburst excitation information to the signal generation circuit element 330 until the next temperature measurement. If the temperature sensing timer circuit element 430 determines that it is time for another temperature measurement (for example, block 760 returns a "yes" result), control proceeds to return to block 720.

[0147] Next, looking at Figure 7B, if the temperature comparison circuit element 465 determines that the temperature is below the threshold temperature (for example, block 755 returns a "no" result), the subburst generation circuit element 420 supplies subburst excitation information corresponding to the subburst index to the signal generation circuit element 330 (block 765). In some examples, the subburst generation circuit element 420 generates subburst excitation information having subburst start and stop frequencies specific to the value of the subburst index. In such examples, the subburst generation circuit element 420 supplies subburst excitation information to the signal generation circuit element 330 to trigger the generation of an excitation signal.

[0148] The signal generation circuit element 330 generates another excitation signal based on the sub-burst excitation information (block 770). In some examples, the signal generation circuit element 330 generates a chirp signal based on the sub-burst excitation information. In such examples, the hardware interface circuit element 350 responds to the chirp signal by supplying a preamplifier signal to the amplifier circuit element 120. The amplifier circuit element 120 supplies a relatively high power signal of the preamplifier signal to the filter circuit element 125, thereby supplying an excitation signal to the lens cover system 110.

[0149] The subburst tracker circuit element 415 determines whether the subburst exponent value is less than the total number of subbursts (block 775). In some examples, the subburst tracker circuit element 415 stops modifying the subburst exponent in response to the subburst exponent being equal to the total number of subbursts. If the subburst tracker circuit element 415 determines that the subburst exponent value is not less than the total number of subbursts (for example, block 775 returns a "no" result), control proceeds to return to block 705 in Figure 7A.

[0150] If the subburst tracker circuit element 415 determines that the subburst index value is less than the total number of subbursts (for example, block 775 returns a "yes" result), the subburst tracker circuit element 415 increments the subburst index (block 780). In some examples, the subburst tracker circuit element 415 determines that there are still subbursts remaining out of the total number of subbursts that need to be supplied. In such examples, the subburst tracker circuit element 415 may modify the subburst index to proceed to the subsequent subburst. The control proceeds to return to block 720 in Figure 7A.

[0151] While the illustrated methods are described with reference to the flowcharts shown in Figures 7A and 7B, many other methods for implementing the sweep circuit element 315 may be used as alternatives in this description. For example, the execution order of the blocks may be changed, and / or some of the described blocks may be modified, excluded, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated examples.

[0152] Figure 8 is a flowchart representing exemplary machine-readable instructions and / or exemplary operation 710 in Figure 7A, which may be executed, instantiated, and / or implemented using exemplary programmable circuit element implementations of the sequencing circuit element 320 in Figures 3 and 4 and / or more generally the sweep circuit element 315 in Figures 3 and 4. Exemplary operation 710 begins in block 810, in which the subburst duration circuit element 405 determines the subburst duration based on the temperature sensing interval and duration. (Block 810). In some examples, the subburst duration circuit element 405 determines the maximum subburst duration by subtracting the temperature sensing duration from the temperature sensing interval. In such examples, the subburst duration circuit element 405 determines that the subburst duration is approximately equal to the maximum burst duration when the burst duration is longer than the maximum subburst duration. In another example, the subburst duration circuit element 405 determines that the subburst duration is equal to the burst duration in response to the burst duration being shorter than the maximum subburst duration.

[0153] The subburst duration circuit element 405 determines the total number of subbursts based on the subburst duration and burst duration (block 820). In some examples, the subburst duration circuit element 405 determines the total number of subbursts by dividing the burst duration by the subburst duration.

[0154] The subburst duration circuit element 405 determines whether the total number of subbursts is 1 (block 830). In some examples, the subburst duration circuit element 405 determines whether the sequencing circuit element 320 needs to divide the burst excitation information into multiple subburst excitation pieces. If the total number of subbursts is 1, the subburst duration is approximately equal to the burst duration, and there is no need to generate subbursts.

[0155] If the subburst duration circuit element 405 determines that the total number of subbursts is 1 (for example, block 830 returns a "yes" result), the subburst generation circuit element 420 in Figure 4 generates subburst excitation information that is approximately equal to the burst excitation information (block 840). When the total number of subbursts is 1, the subburst duration is approximately equal to the burst duration, and there is no need to generate subbursts. In such an example, the subburst excitation information is approximately equal to the burst excitation information. Control proceeds to return to the previous state.

[0156] If the subburst duration circuit element 405 determines that the total number of subbursts is not 1 (for example, block 830 returns the result "No"), the subburst frequency circuit element 410 in Figure 4 determines the subburst frequency for each subburst based on the burst excitation information (block 850). In some examples, the subburst frequency circuit element 410 determines the total number of frequencies of the burst excitation information by dividing the frequency range of the burst excitation information by the frequency step. In such examples, the subburst frequency circuit element 410 divides the total number of frequencies by the total number of subbursts.

[0157] The subburst generation circuit element 420 generates subburst excitation information for each subburst at the corresponding subburst frequency (block 860). In some examples, the subburst generation circuit element 420 generates subburst excitation information for each of the total number of subbursts based on the burst excitation information and the frequency of the subburst frequency circuit element 410. The control proceeds in reverse.

[0158] An illustrative method is described with reference to the flowchart shown in Figure 8, but many other methods for implementing the sequencing circuit element 320 may be used as alternatives in this description. For example, the execution order of the blocks may be changed, and / or some of the described blocks may be modified, excluded, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0159] Figures 7A, 7B, and 8 show flowcharts representing exemplary machine-readable instructions for implementing and / or instantiating the controller circuit element 115 of Figures 1, 3, and 4 in a programmable circuit element, and / or exemplary operations performed by the programmable circuit element to implement and / or instantiate the controller circuit element 115 of Figures 1, 3, and 4. The machine-readable instructions may be one or more executable programs for execution by a programmable circuit element, such as the programmable circuit element 912 shown in the exemplary processor platform 900 described later in relation to Figure 9, and / or one or more functions or functions performed by an exemplary programmable circuit element (e.g., FPGA) described later in relation to Figures 10 and / or 11. In some examples, the machine-readable instructions cause an operation, task, etc., to be performed and / or executed in an automated manner in the real world. As used herein, “automated” means without human involvement.

[0160] A program may be embodied in instructions (e.g., software and / or firmware) stored in one or more non-temporary computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray discs, compact discs (CDs), digital multipurpose discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROMs, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random-access memory (RAM), etc.), and / or any other storage devices or storage disks. Instructions in a non-temporary computer-readable and / or machine-readable medium may program and / or execute programmable circuit elements located in one or more hardware devices, but the entire program and / or parts thereof may alternatively be executed and / or instantiated by one or more hardware devices other than programmable circuit elements and / or embodied in dedicated hardware. Machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user), or by an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between a server and an endpoint client hardware device. Similarly, a non-temporary computer-readable storage medium may include one or more media.Furthermore, although the example program is described with reference to the flowcharts shown in Figures 7A, 7B, and 8, many other methods of implementing the example controller circuit element 115 may be used as alternatives. For example, the execution order of the blocks in the flowchart may be changed, and / or some of the described blocks may be modified, excluded, or combined. Additionally or alternatively, any or all blocks in the flowchart may be implemented by one or more hardware circuits (e.g., processor circuit elements, individual and / or integrated analog and / or digital circuit elements, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without running software or firmware. The programmable circuit elements may be distributed to different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, programmable circuit elements may be CPUs and / or FPGAs located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate enclosures), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, and / or any combination thereof.

[0161] The machine-readable instructions described herein may be stored in one or more formats, such as compressed, encrypted, fragmented, compiled, executable, or packaged. Machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bitstreams (e.g., computer-readable bitstreams, machine-readable bitstreams, etc.)), or as data structures (e.g., parts of instructions, code, code representations, etc.) that can be used to generate, manufacture, and / or create machine-executable instructions. For example, machine-readable instructions may be stored fragmented on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations on a network or a collection of networks. Machine-readable instructions may require one or more of the following actions to be directly readable, interpretable, and / or executable by computing devices and / or other machines: installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, expansion, decompression, distribution, reassignment, compilation, etc. For example, machine-readable instructions may be stored in multiple parts, which may be individually compressed, encrypted, and / or stored on separate computing devices, and when these parts are decrypted, expanded, and / or combined, they may form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations, thereby forming a program as described herein.

[0162] In another example, machine-readable instructions may be read by programmable circuit elements, but the execution of machine-readable instructions on a particular computing device or other device may require the addition of libraries (e.g., dynamic link libraries (DLLs)), software deployment kits (SDKs), application programming interfaces (APIs), etc. In yet another example, machine-readable instructions may need to be configured (e.g., storing settings, entering data, recording network addresses, etc.) before the machine-readable instructions and / or corresponding programs can be executed in whole or in part. Therefore, machine-readable, computer-readable, and / or machine-readable media as used herein may include instructions and / or programs, regardless of the particular form or state of machine-readable instructions and / or programs.

[0163] The machine-readable instructions described herein may be expressed in any past, present, or future instruction language, description language, programming language, etc. For example, machine-readable instructions may be expressed using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, hypertext markup language (HTML), structured query language (SQL), Swift, etc.

[0164] As described above, the operations illustrated in Figures 7A, 7B, and 8 can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored in one or more non-temporary computer-readable and / or machine-readable media. As used herein, the terms non-temporary computer-readable media, non-temporary computer-readable storage media, non-temporary machine-readable media, and / or non-temporary machine-readable storage media are explicitly defined to include any type of computer-readable storage device and / or storage disk, excluding propagated signals and transmission media. Examples of such non-temporary computer-readable media, non-temporary computer-readable storage media, non-temporary machine-readable media, and / or non-temporary machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks that store information for any duration (e.g., long-term, permanent, short-term, temporary buffering, and / or while caching information). As used herein, the terms “non-temporary computer-readable storage device” and “non-temporary machine-readable storage device” are defined to include any physical (mechanical, magnetic, and / or electrical) hardware that holds information for a certain period of time but excludes propagating signals and excludes transmission media. Examples of non-transient computer-readable storage devices and / or non-transient machine-readable storage devices include any type of random-access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array (RAID) systems of independent disks. As used herein, the term “device” means mechanical and / or electrical equipment, hardware, and / or circuit elements that may or may not be composed of computer-readable instructions, machine-readable instructions, etc., and / or are manufactured to perform computer-readable instructions, machine-readable instructions, etc.

[0165] Figure 9 is a block diagram of an exemplary programmable circuit platform 900 configured to execute and / or instantiate exemplary machine-readable instructions and / or exemplary operations in Figures 7A, 7B, and 8 in order to implement the controller circuit element 115 of Figures 1, 3, and 4. The programmable circuit element platform 900 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad®), a personal digital assistant (PDA), an internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable devices, or any other type of computing and / or electronic device.

[0166] The illustrated example programmable circuit element platform 900 includes a programmable circuit element 912. The illustrated example programmable circuit element 912 is hardware. For example, the programmable circuit element 912 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit element 912 may also be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit element 912 implements the circuit elements 300, 305, 310, 315, 320, 325, 330, 350, 355, 360, 365, 370, 375, 380, 385 in Figures 3 and 4, the circuit elements 405, 410, 415, 420, 425, 430, 435, 450, 455, 460, 465 in Figure 4, and / or more generally the controller circuit element 115 in Figures 1 and 3.

[0167] The programmable circuit element 912 in the illustrated example includes local memory 913 (e.g., cache, registers, etc.). The programmable circuit element 912 in the illustrated example communicates with main memory 914, 916, which includes volatile memory 914 and non-volatile memory 916, via bus 918. The volatile memory 914 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 916 may be implemented by flash memory and / or any other type of memory device. Access to the main memory 914, 916 in the illustrated example is controlled by a memory controller 917. In some examples, the memory controller 917 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit element for managing the flow of data to and from the main memory 914, 916.

[0168] The illustrated example programmable circuit element platform 900 also includes an interface circuit element 920. The interface circuit element 920 can be implemented by hardware in any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0169] In the illustrated example, one or more input devices 922 are connected to the interface circuit element 920. The input devices 922 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands to the programmable circuit element 912. The input devices 922 can be implemented, for example, by an audio sensor, microphone, camera (still image or video), keyboard, button, mouse, touchscreen, trackpad, trackball, isopoint device, and / or speech recognition system.

[0170] One or more output devices 924 are also connected to the interface circuit element 920 in the illustrated example. The output devices 924 can be implemented, for example, by display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-planar switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. Therefore, the interface circuit 920 in the illustrated example may include graphics driver cards, graphics driver chips, and / or graphics processor circuits such as GPUs.

[0171] The interface circuit element 920 in the illustrated example also includes transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external devices (e.g., any type of computing device) via the network 926. Communication may be performed by, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond line of sight wireless systems, line-of-sight wireless systems, mobile phone systems, optical connections, and the like.

[0172] The illustrated example programmable circuit element platform 900 also includes one or more mass storage disks or devices 928 for storing firmware, software and / or data. Examples of such mass storage disks or devices 928 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or flash memory devices and / or solid-state storage disks or devices such as SSDs.

[0173] The machine-readable instructions 932, which can be implemented by the machine-readable instructions in Figures 7A, 7B, and 8, may be stored in a mass storage device 928, in volatile memory 914, in non-volatile memory 916, and / or in at least one non-temporary computer-readable storage medium such as a removable CD or DVD.

[0174] Figure 10 is a block diagram of an illustrative implementation of the programmable circuit element 912 of Figure 9. In this example, the programmable circuit element 912 of Figure 9 is implemented by a microprocessor 1000. For example, the microprocessor 1000 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit element). The microprocessor 1000 executes some or all of the machine-readable instructions in the flowcharts of Figures 7A, 7B, and 8, effectively instantiating the circuit elements of Figure 2 as logic circuits to perform the operations corresponding to those machine-readable instructions. In some such examples, the circuit elements of Figures 1, 3, and 4 are instantiated by the hardware circuit of the microprocessor 1000 in combination with machine-readable instructions. For example, the microprocessor 1000 may be implemented by a multicore hardware circuit element such as a CPU, DSP, GPU, or XPU. The microprocessor 1000 in this example may contain any number of illustrative cores 1002 (e.g., 1 core), but is a multicore semiconductor device containing N cores. The cores 1002 of the microprocessor 1000 may operate independently or cooperate to execute machine-readable instructions. For example, a firmware program, an embedded software program, or machine code corresponding to a software program may be executed by one of the cores 1002, or by multiple cores 1002 at the same or different times. In some examples, the firmware program, an embedded software program, or machine code corresponding to a software program is divided into threads and executed in parallel by two or more of the cores 1002. The software program may correspond to some or all of the machine-readable instructions and / or operations represented by the flowcharts in Figures 7A, 7B, and 8.

[0175] Core 1002 may communicate by bus 1004, the first example. In some examples, bus 1004 may be implemented by a communication bus to enable communication associated with one (or more) of the cores 1002. For example, bus 1004 may be implemented by at least one of the following: Inter-Integrated Circuit (I2C) bus, Serial Peripheral Interface (SPI) bus, PCI bus, or PCIe bus. Additionally or alternatively, bus 1004 may be implemented by any other type of computing or electrical bus. Core 1002 may receive data, instructions, and / or signals from one or more external devices by interface circuit element 1006. Core 1002 may output data, instructions, and / or signals to one or more external devices by interface circuit element 1006. Core 1002 in this example includes exemplary local memory 1020 (e.g., an L1 cache which can be divided into a Level 1 (L1) data cache and an L1 instruction cache), but microprocessor 1000 also includes exemplary shared memory 1010 (e.g., Level 2 (L2 cache)) which can be shared by cores for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from shared memory 1010. The local memory 1020 and shared memory 1010 of each core 1002 may be part of a hierarchy of storage devices which include multiple levels of cache memory and main memory (e.g., main memories 914, 916 in Figure 9). Higher levels of memory in the hierarchy exhibit lower access times and have smaller storage capacities than lower levels of memory. Changes at various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

[0176] Each core 1002 may be called a CPU, DSP, GPU, or any other type of hardware circuit element. Each core 1002 includes a control unit circuit element 1014, an arithmetic logic operation (AL) circuit element (sometimes called an ALU) 1016, several registers 1018, local memory 1020, and a bus 1022 as in the second example. Other structures may also exist. For example, each core 1002 may include a vector unit circuit element, a single instruction multiple data (SIMD) unit circuit element, a load / store unit (LSU) circuit element, a branch / jump unit circuit element, a floating-point unit (FPU) circuit element, and so on. The control unit circuit element 1014 includes semiconductor-based circuitry structured to control (e.g., coordinate) the movement of data within the corresponding core 1002. The AL circuit element 1016 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on data within the corresponding core 1002. In some examples, the AL circuit element 1016 performs integer-based operation. In other examples, the AL circuit element 1016 also performs floating-point operation. In yet another example, the AL circuit element 1016 may include a first AL circuit element that performs integer-based operation and a second AL circuit element that performs floating-point operation. In some examples, the AL circuit element 1016 may be called an arithmetic logic unit (ALU).

[0177] Register 1018 is a semiconductor-based structure for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit element 1016 of the corresponding core 1002. For example, register 1018 may include vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1018 may be arranged in the banks shown in Figure 10. Alternatively, register 1018 may be organized into any other arrangement, format, or structure, such as by being distributed across cores 1002 to reduce access time. The second bus 1022 may be implemented by at least one of the I2C bus, SPI bus, PCI bus, or PCIe bus.

[0178] Each core 1002, and / or more generally, the microprocessor 1000, may include additional and / or alternative structures to those described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common mesh stops (CMS), one or more shifters (e.g., barrel shifters), and / or other circuit elements may be present. The microprocessor 1000 is a semiconductor device manufactured to include many transistors interconnected to implement the aforementioned structures in one or more integrated circuits (ICs) contained in one or more packages.

[0179] The microprocessor 1000 may include and / or cooperate with one or more accelerators (e.g., acceleration circuit elements, hardware accelerators, etc.). In some examples, the accelerator is implemented by logic circuit elements to perform a particular task more quickly and / or more efficiently than could be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs as described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be mounted on the microprocessor 1000, in the same chip package as the microprocessor 1000, and / or in one or more separate packages from the microprocessor 1000.

[0180] Figure 11 is a block diagram of another illustrative implementation of the programmable circuit element 912 of Figure 9. In this example, the programmable circuit element 912 is implemented by an FPGA circuit element 1100. For example, the FPGA circuit element 1100 may be implemented by an FPGA. The FPGA circuit element 1100 can be used to perform operations that could otherwise be performed by the illustrated microprocessor 1000 of Figure 10, which performs machine-readable instructions. However, once configured, the FPGA circuit element 1100 often instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware and therefore can perform operations / functions faster than they could be performed by a general-purpose microprocessor that runs the corresponding software.

[0181] More specifically, in contrast to the microprocessor 1000 in Figure 10 above (which can be programmed to execute some or all of the machine-readable instructions represented by the flowcharts in Figures 7A, 7B, and 8, but is a general-purpose device whose interconnects and logic circuit elements are fixed once manufactured), the FPGA circuit element 1100 in the example of Figure 11 includes interconnects and logic circuit elements that can be configured, structured, programmed, and / or interconnected in various ways after manufacturing to instantiate some or all of the operations and / or functions corresponding to the machine-readable instructions represented by the flowcharts in Figures 7A, 7B, and 8. In particular, the FPGA circuit element 1100 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless the FPGA circuit element 1100 is reprogrammed and until it is reprogrammed). The configured logic circuits allow logic gates to cooperate in various ways to perform different operations on data received by input circuit elements. These operations may correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowcharts in Figures 7A, 7B, and 8. Thus, FPGA circuit elements 1100 can be configured and / or structured to effectively instantiate some or all of the operations / functions corresponding to the machine-readable instructions in the flowcharts of Figures 7A, 7B, and 8 as dedicated logic circuits for performing the operations / functions corresponding to these software instructions in a dedicated manner similar to that of an ASIC. Therefore, FPGA circuit elements 1100 can perform some or all of the operations / functions corresponding to the machine-readable instructions in Figures 7A, 7B, and 8 faster than a general-purpose microprocessor could.

[0182] In the example in Figure 11, the FPGA circuit element 1100 is configured and / or structured in response to being programmed (and / or reprogrammed once or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, a very high-speed integrated circuit program (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program in HDL that corresponds to one or more operations / functions, and the code / program may be translated into a low-level language as needed, and the code / program (e.g., code / program in a low-level language) may be converted into a binary file (e.g., by a compiler, a software application, etc.). In some examples, the FPGA circuit element 1100 in Figure 11 may be configured and / or structured to access and / or load a binary file to cause the FPGA circuit element 1100 in Figure 11 to perform one or more operations / functions. For example, a binary file may be implemented with a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to the FPGA circuit element 1100 in Figure 11, thereby constituting and / or structuring the FPGA circuit element 1100 or a part thereof in Figure 11.

[0183] In some examples, binary files are compiled, generated, transitioned, and / or output in some other way from a uniform software platform used to program the FPGA. For example, the uniform software platform may translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in HDL. In some such examples, binary files are compiled, generated, transitioned, and / or output in some other way from the uniform software platform based on the second instruction. In some examples, the FPGA circuit element 1100 in Figure 11 may be configured and / or structured to access and / or load a binary file to cause the FPGA circuit element 1100 in Figure 11 to perform one or more operations / functions. For example, a binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions that can access the FPGA circuit element 1100 in Figure 11, thereby constituting and / or structuring the FPGA circuit element 1100 or a part thereof in Figure 11.

[0184] The FPGA circuit element 1100 in Figure 11 includes an exemplary input / output (I / O) circuit element 1102 for acquiring data from and / or outputting data from exemplary component circuit element 1104 and / or external hardware 1106. For example, component circuit element 1104 may be implemented by an interface circuit element that can acquire a binary file which can be implemented by bitstreams, data, and / or machine-readable instructions in order to constitute FPGA circuit element 1100 or a part thereof. In some such examples, component circuit element 1104 may acquire the binary file from a user, a machine (a hardware circuit element which can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file (e.g., a programmable or dedicated circuit element)), and / or any combination thereof. In some examples, external hardware 1106 may be implemented by an external hardware circuit element. For example, external hardware 1106 may be implemented by the microprocessor 1000 in Figure 10.

[0185] The FPGA circuit element 1100 also includes an exemplary logic gate circuit element 1108, a plurality of exemplary configurable interconnects 1110, and an array of exemplary storage circuit elements 1112. The logic gate circuit element 1108 and the configurable interconnects 1110 are configurable to instantiate one or more operations / functions that can correspond to at least some machine-readable instructions for desired operations in Figures 7A, 7B, 8, and / or others. The logic gate circuit element 1108 shown in Figure 11 is manufactured in blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide the basic building blocks for the logic circuit. Electrically controllable switches (e.g., transistors) are present in each of the logic gate circuit elements 1108, enabling configurations such that the electrical structure and / or logic gate configurations form a circuit for performing desired operations / functions. The logic gate circuit element 1108 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), and multiplexers.

[0186] The configurable interconnection 1110 in the illustrated example may include electrically controllable switches (e.g., transistors) whose state can be changed by programming one or more connections between one or more logic gate circuit elements 1108 to activate or deactivate, such as conductive paths, traces, vias, etc., for programming a desired logic circuit.

[0187] The storage circuit element 1112 in the illustrated example is structured to store the results of one or more operations performed by the corresponding logic gate. The storage circuit element 1112 may be implemented by registers or the like. In the illustrated example, the storage circuit element 1112 is distributed within the logic gate circuit element 1108 to facilitate access and increase execution speed.

[0188] The exemplary FPGA circuit element 1100 in Figure 11 also includes exemplary dedicated operation circuit elements 1114. In this example, the dedicated operation circuit element 1114 includes special-purpose circuit elements 1116 that can be called upon to implement commonly used functions, thereby avoiding the need to program those functions in the art. Examples of such special-purpose circuit elements 1116 include memory (e.g., DRAM) controller circuit elements, PCIe controller circuit elements, clock circuit elements, transceiver circuit elements, memory, and multiply-accumulate circuit elements. Other types of special-purpose circuit elements may also exist. In some examples, the FPGA circuit element 1100 may also include exemplary general-purpose programmable circuit elements 1118, such as exemplary CPU 1120 and / or exemplary DSP 1222. Additional or alternative general-purpose programmable circuit elements 1118, such as GPUs and XPUs, may exist, which can be programmed to perform other operations.

[0189] Figures 10 and 11 illustrate two illustrative implementations of the programmable circuit element 912 of Figure 9, but many other approaches are conceivable. For example, the FPGA circuit element may include an onboard CPU, such as one or more of the CPUs 1120 illustrated in Figure 10. Thus, the programmable circuit element 912 of Figure 9 can also be implemented by combining at least the microprocessor 1000 illustrated in Figure 10 and the FPGA circuit element 1100 illustrated in Figure 11. In some examples of such hybrids, one or more cores 1002 in Figure 10 may execute a first portion of machine-readable instructions represented by the flowcharts in Figures 7A, 7B, and 8 to perform a first operation / function, an FPGA circuit element 1100 in Figure 11 may be configured and / or structured to perform a second operation / function corresponding to a second portion of machine-readable instructions represented by the flowcharts in Figures 7A, 7B, and 8, and / or an ASIC may be configured and / or structured to perform a third operation / function corresponding to a third portion of machine-readable instructions represented by the flowcharts in Figures 7A, 7B, and 8.

[0190] Therefore, some or all of the circuit elements in Figures 1, 3, and 4 may be instantiated, either the same or different. For example, the same and / or different parts of the microprocessor 1000 in Figure 10 may be programmed to execute the same and / or different parts of machine-readable instructions. In some examples, the same and / or different parts of the FPGA circuit element 1100 in Figure 11 may be configured and / or structured to perform the same and / or different operations / functions corresponding to the same and / or different parts of machine-readable instructions.

[0191] In some examples, some or all of the circuit elements in Figures 1, 3, and 4 may be instantiated in one or more threads that run concurrently and / or sequentially. For example, the microprocessor 1000 in Figure 10 may execute machine-readable instructions in one or more threads that run concurrently and / or sequentially. In some examples, the FPGA circuit element 1100 in Figure 11 may be configured and / or structured to operate / function concurrently and / or sequentially. Also, in some examples, some or all of the circuit elements in Figures 1, 3, and 4 may be implemented in one or more virtual machines and / or containers that run on the microprocessor 1000 in Figure 10.

[0192] In some examples, the programmable circuit elements 912 in Figure 9 may reside in one or more packages. For example, the processing circuit elements 1000 in Figure 10 and / or the processing circuit elements 1100 in Figure 11 may reside in one or more packages. In some examples, the XPU may be implemented by the programmable circuit elements 912 in Figure 9, which may reside in one or more packages. For example, the XPU may include a CPU (e.g., microprocessor 1000 in Figure 10, CPU 1120 in Figure 11, etc.) in one package, a DSP (e.g., DSP 1122 in Figure 11) in another package, a GPU in yet another package, and an FPGA (e.g., FPGA circuit element 1100 in Figure 16) in yet another package.

[0193] The terms “including” and “comprising” (and all their forms and tenses) are used herein as open-ended terms. Therefore, where a claim uses any form of “including” or “comprising” (e.g., “comprises,” “includes,” “comprising,” “including,” “having,” etc.) within a preamble or any type of claim description, additional elements, terms, etc., may exist without departing from the scope of the corresponding claim or description. The expression “at least,” as used herein, is open-ended, just as the terms “comprising” and “including” are open-ended, for example, when used as a transition term in the preamble of a claim. The term "and / or" refers to any combination or subset of A, B, and C, for example, when used in the form of A, B, and / or C, such as (1) A only, (2) B only, (3) C only, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. As used herein in the context of describing structures, components, items, objects, and / or things, the expression "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the expression "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the expression "at least one of A and B" means an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, as used herein in contexts describing the performance or execution of processes, instructions, actions, or other similar activities, the expression “at least one of A and B” refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0194] As used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. As used herein, the term “a certain” object refers to one or more of those objects. “A certain,” “one or more,” and “at least one” are used interchangeably herein. Also, although listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. Also, different examples or claims may include different features, but these may be combined, and their inclusion in different examples or claims does not imply that the combination of features is not feasible and / or unfavorable.

[0195] As used herein, unless otherwise specified, the term “above” describes the relationship of the two parts to the Earth. If a part of the second part lies between the Earth and the first part, then the first part is above the second part. Similarly, as used herein, if the first part is closer to the Earth than the second part, then the first part is “below” the second part. As described above, the first part may be above or below the second part in one or more of the following states: with another part in between, without another part in between, touching the first and second parts, or not touching each other directly.

[0196] As used in this application, describing any part (e.g., a layer, film, area, region, or plate) as being on another part in any way (e.g., being placed on, located on, positioned on, or formed on) indicates that the referenced part is in contact with the other part, or that one or more intermediate parts are located between them and the referenced part is on top of the other part.

[0197] As used herein, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to the connection, and / or relative movement between those elements, unless otherwise stated. Thus, references to connections do not necessarily imply that two elements are directly connected and / or are in a fixed relationship with one another. As used herein, the statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0198] Unless otherwise specifically stated, descriptors such as “first,” “second,” and “third” are used without attributing any meaning to priority, physical order, placement in a list, and / or any sorting, or otherwise indicating any meaning. Rather, they are used herein simply as distinguishing marks and / or arbitrary names to facilitate understanding of the examples described. In some examples, the descriptor “first” may be used to refer to an element in a mode for carrying out the invention, but the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such cases, such descriptors are simply used to clearly identify those elements within the context of the description (e.g., in a claim) where they might otherwise share the same name.

[0199] As used herein, “approximately” and “about” modify the subject / value to acknowledge that there may be potential variations in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world imperfections. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance range of ±10%, unless otherwise stated herein.

[0200] As used herein, the expression “communicate,” including its variations, encompasses direct communication and / or indirect communication via one or more intermediate components, and also includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events, without requiring direct physical (e.g., wired) communication and / or constant communication.

[0201] As used herein, “programmable circuit element” is defined to include (1) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (2) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a particular function and / or operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit elements include programmable microprocessors such as central processing units (CPUs) that can execute a first instruction to perform one or more operations and / or functions; FPGAs that can be programmed with a second instruction to configure and / or structure a field-programmable gate array (FPGA) for instantiating one or more operations and / or functions corresponding to a first instruction; graphics processor units (GPUs) that can execute a first instruction to perform one or more operations and / or functions; digital signal processors (DSPs), XPUs, network processing units (NPUs) that can execute a first instruction to perform one or more operations and / or functions; one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit elements (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and integration techniques (e.g., application programming interfaces (APIs)) that assign computing tasks to any of the multiple types of programmable circuit elements suitable for performing those tasks.

[0202] As used herein, an integrated circuit / circuit element is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit may be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit element, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0203] In this description, the term "and / or" (when used in forms such as A, B, and / or C) refers to any combination or subset of A, B, and C, including (a) A only, (b) B only, (c) only, (d) A and B, (e) A and C, (f) B and C, and (g) A, B, and C. Also, as used herein, the expression "at least one of A or B" (or "at least one of A and B") refers to any implementation that includes (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0204] In this description, the term “to connect” may encompass any connection, communication, or signaling path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, if the intervening component C does not alter the functional relationship between device A and device B, device A is connected to device B via the intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0205] Numerical identifiers such as "first," "second," and "third" are used simply to distinguish between elements of substantially the same type in terms of structure and / or function. As used in the detailed description, these identifiers do not necessarily correspond to those used in the claims.

[0206] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by the manufacturer to perform that function, and / or may be configured (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the construction of hardware components and interconnections of the device, and / or via layout, or a combination thereof.

[0207] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean the interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0208] In this specification, a circuit or device described as including certain components may instead be adapted to be coupled with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage sources and / or current sources) may instead include only semiconductor elements (e.g., semiconductor dies and / or integrated circuit (IC) packages) in a single physical device, and may be adapted to be coupled with at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0209] The circuits described herein are reconfigurable to include components that have been replaced to provide functionality at least partially similar to that available before the component replacement. Components shown as resistors generally represent any one or more elements that are coupled in series and / or parallel to provide the amount of impedance represented by the indicated resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor. Certain elements in the examples described are included in an integrated circuit, while others are outside the integrated circuit, but in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being outside the integrated circuit may be included inside the integrated circuit, and / or some features illustrated as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0210] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise stated, "approximately," "nearly," or "substantially" preceding a value means ±10 percent of the stated value, and if the value is zero, it means a reasonable range near zero.

[0211] Modifications to the described embodiments are permitted within the scope of the claims, and other embodiments are possible.

Claims

1. It is a device, Machine-readable instructions and A programmable circuit element configured to perform at least one of the instantiation or execution of the machine-readable instruction, Includes, The aforementioned machine-readable instruction is Burst excitation information including a burst start frequency, a burst stop frequency, and a burst duration, wherein the burst start frequency and the burst stop frequency define a frequency range for the burst excitation information, and the burst excitation information is received. First and second subburst information, comprising the burst duration, a temperature sensing interval, and a subburst duration based on the temperature sensing duration, wherein the temperature sensing interval is the time between temperature measurements and the temperature sensing duration is the time of temperature measurement, the first and second subburst information is generated based on the burst excitation information, An excitation signal having the frequency range of the burst excitation information is generated in response to the first and second sub-burst excitation information and temperature measurement. A device designed for that purpose.

2. The apparatus according to claim 1, wherein the programmable circuit element is configured to determine the sub-burst duration as the temperature sensing interval minus the temperature sensing duration.

3. The apparatus according to claim 1, wherein the programmable circuit element is It generates temperature burst excitation information including the temperature start frequency, temperature stop frequency, and temperature sensing duration. The excitation signal is generated in response to the first and second subburst excitation information and the temperature burst excitation information. It is configured in such a way, The apparatus wherein the excitation signal has a first portion and a second portion, the first portion responding to the temperature burst excitation information and the second portion responding to the first sub-burst excitation information.

4. The apparatus according to claim 3, wherein the excitation signal further comprises a third portion and a fourth portion, the third portion responding to the temperature burst excitation information, and the programmable circuit element is In response to the third portion of the excitation signal, the temperature of the transducer is determined. In response to the temperature of the transducer being lower than a threshold, the fourth portion of the excitation signal is generated using the second subburst excitation information. In response to the temperature of the transducer being higher than the threshold, the fourth portion of the excitation signal is generated after the cool-down period using the temperature burst excitation information. A device configured in such a way.

5. The apparatus according to claim 1, wherein the programmable circuit element is The temperature burst excitation information including the temperature sensing duration is generated, The excitation signal is generated in response to the temperature burst excitation information. In response to the temperature burst excitation information, the current and voltage of the excitation signal are received. In response to the current and voltage of the excitation signal, the Fourier transform is determined. A device configured in such a way.

6. The apparatus according to claim 5, wherein the programmable circuit element is The impedance of the transducer that receives the excitation signal in response to the Fourier transform is determined, The temperature measurement is generated by multiplying it by the aforementioned impedance gradient constant. An offset value based on the material of the transducer is added to the aforementioned temperature measurement. The temperature of the transducer is determined by comparing the aforementioned temperature measurement with a candidate temperature measurement. A device configured in such a way.

7. The apparatus according to claim 1, wherein the burst excitation information further includes a frequency step for specifying the interval between the frequencies of the excitation signal between the burst start frequency and the burst stop frequency, and the first sub-burst excitation information further includes the frequency step, the sub-burst start frequency, and the sub-burst stop frequency, wherein the sub-burst start frequency and the sub-burst stop frequency are between or equal to the burst start frequency and the burst stop frequency.

8. A non-temporary computer-readable storage medium containing instructions, wherein when the instructions are executed, a programmable circuit element contains at least, Burst excitation information including a burst start frequency, a burst stop frequency, and a burst duration, wherein the burst start frequency and the burst stop frequency define a frequency range for the burst excitation information, and the burst excitation information is received. Based on the burst excitation information, first and second sub-burst information is generated, which includes the burst duration, temperature sensing interval, and sub-burst duration based on the temperature sensing duration, wherein the temperature sensing interval is the time between temperature measurements and the temperature sensing duration is the time of temperature measurement. In response to the first and second sub-burst excitation information and temperature measurement, an excitation signal having the frequency range of the burst excitation information is generated. At least one non-temporary computer-readable storage medium.

9. At least one non-temporary computer-readable storage medium according to claim 8, wherein the instruction is transmitted to the programmable circuit element, The system generates temperature burst excitation information including the temperature start frequency, temperature stop frequency, and temperature sensing duration. An excitation signal is generated in response to the first and second sub-burst excitation information and the temperature burst excitation information, wherein the excitation signal has a first part and a second part, the first part responding to the temperature burst excitation information and the second part responding to the first sub-burst excitation information. At least one non-temporary computer-readable storage medium.

10. At least one non-transient computer-readable storage medium according to claim 9, wherein the excitation signal further comprises a third portion and a fourth portion, the third portion responding to temperature burst excitation information, and the instruction is directed to the programmable circuit element, In response to the third portion of the excitation signal, the temperature of the transducer is determined. In response to the temperature of the transducer being lower than a threshold, the fourth portion of the excitation signal is generated using the second subburst excitation information. In response to the temperature of the transducer being higher than the threshold, the fourth portion of the excitation signal is generated using the temperature burst excitation information after a cool-down period. At least one non-temporary computer-readable storage medium.

11. At least one non-temporary computer-readable storage medium according to claim 8, wherein the instruction is transmitted to the programmable circuit element, The system generates temperature burst excitation information including the temperature start frequency, temperature stop frequency, and the temperature sensing duration. The excitation signal is generated in response to the temperature burst excitation information. In response to the temperature burst excitation information, the current and voltage of the excitation signal are received. In response to the current and voltage of the excitation signal, the Fourier transform is determined. At least one non-temporary computer-readable storage medium.

12. At least one non-temporary computer-readable storage medium according to claim 11, wherein the instruction is transmitted to the programmable circuit element, In response to the Fourier transform, the impedance of the transducer that receives the excitation signal is determined. The temperature measurement is generated by multiplying it by the aforementioned impedance gradient constant. An offset value based on the material of the transducer is added to the aforementioned temperature measurement. The temperature measurement value is compared with a candidate temperature measurement value to determine the temperature of the transducer. At least one non-temporary computer-readable storage medium.

13. At least one non-transient computer-readable storage medium according to claim 8, wherein the burst excitation information further includes a frequency step for specifying the interval between the frequencies of the excitation signal between the burst start frequency and the burst stop frequency, and the first sub-burst excitation information further includes the frequency step, the sub-burst start frequency, and the sub-burst stop frequency, wherein the sub-burst start frequency and the sub-burst stop frequency are between or equal to the burst start frequency and the burst stop frequency.

14. It is a device, A temperature control circuit element configured to generate temperature burst excitation information, A sequencing circuit element, The system receives burst excitation information, including the burst start frequency and burst stop frequency. A sequencing circuit element configured to generate first and second sub-burst information based on the burst excitation information, wherein the first and second burst excitation information includes a sub-burst start frequency and a sub-burst stop frequency, and the sub-burst start and stop frequencies define a frequency range. A signal generation circuit element, The signal generation circuit element is configured to generate an excitation signal in response to the temperature burst excitation information and the first and second sub-burst excitation information, wherein the first and second sub-burst excitation information changes the frequency of the excitation signal to a frequency within the frequency range, A device including a device.

15. The apparatus according to claim 14, wherein the signal generation circuit element further comprises In response to the temperature burst excitation information, a first portion of the excitation signal is generated. In response to the first subburst excitation information, a second portion of the excitation signal is generated. In response to the temperature burst excitation information, a third portion of the excitation signal is generated. In response to the second subburst excitation information, a fourth portion of the excitation signal is generated. A device configured in such a way.

16. The apparatus according to claim 15, wherein the temperature control circuit element further comprises In response to the first and third portions of the excitation signal, the temperature of the transducer is determined. The temperature is compared to a temperature threshold to determine whether a cooldown is necessary. A device configured in such a way.

17. The apparatus according to claim 14, further comprising an impedance determination circuit element, In response to the temperature burst excitation information, the current and voltage of the excitation signal are received. In response to the current and voltage of the excitation signal, the Fourier transform is determined. The impedance of the transducer that receives the excitation signal is determined in response to the Fourier transform. An apparatus including an impedance determination circuit element configured in such a way.

18. The apparatus according to claim 17, wherein the temperature control circuit element is The temperature measurement is generated by multiplying it by the aforementioned impedance gradient constant. An offset value based on the material of the transducer is added to the aforementioned temperature measurement. The temperature of the transducer is determined by comparing the aforementioned temperature measurement with a candidate temperature measurement. A device configured in such a way.

19. The apparatus according to claim 14, wherein the burst excitation information further includes a frequency step for specifying the interval between the frequencies of the excitation signal between the burst start frequency and the burst stop frequency, and the first sub-burst excitation information further includes the frequency step, the sub-burst start frequency, and the sub-burst stop frequency, wherein the sub-burst start frequency and the sub-burst stop frequency are between or equal to the burst start frequency and the burst stop frequency.

20. The apparatus according to claim 14, wherein the sequencing circuit is further configured to determine the sub-burst duration of the first and second sub-burst excitation information based on the temperature sensing interval and the temperature sensing duration, wherein the temperature sensing interval is the time between temperature measurements and the temperature sensing duration is the time of temperature measurements.

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