Semiconductor devices containing bimetallic silicide with reduced contact resistance

Abstract

This technology includes semiconductor devices and methods with improved contact resistance. The semiconductor device includes a substrate base, silicon oxide disposed on the base defining one or more features, a bimetallic silicide layer disposed on the substrate at one or more features, and at least a first metal layer. The bimetallic silicide layer includes a first metal, a second metal different from the first metal, and a silicon-containing compound, with the second metal atoms at approximately 0.8E+14 / cm². -2 The above is included. The first metal layer contains the first metal and overlaps the bimetallic silicide layer.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit and priority of U.S. Patent Application No. 18 / 185,242, filed March 16, 2023, entitled "SEMICONDUCTOR DEVICES CONTAINING BI-METALLIC SILICIDE WITH REDUCED CONTACT RESISTIVITY," which is incorporated herein by reference in its entirety.

[0002] Technical field This technology relates to a semiconductor processing method and a device formed thereby. More specifically, this technology relates to a method for reducing the contact resistance of a semiconductor device and a device incorporating such contacts. [Background technology]

[0003] Integrated circuits (INCS) have evolved into complex devices capable of housing millions of transistors, capacitors, and resistors on a single chip. In the evolution of INCS, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while form factor has decreased. Transistors are components or elements that are often formed on semiconductor devices. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate field-effect transistors (FETs), which allow current to flow through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] Integrated circuits are made possible by processes that manufacture intricately patterned material layers on a substrate surface. Manufacturing patterned materials on a substrate requires controlled methods for depositing and removing the material. As device sizes continue to shrink, the properties of the film can have a significant impact on device performance. As devices become smaller and more complex patterning schemes are adopted in the industry, thin film deposition is becoming a challenge. Furthermore, as material thickness continues to decrease, the properties of the deposited film can have a significant impact on device performance.

[0005] Therefore, there is a need for high-quality devices and structures with improved resistance, as well as methods for manufacturing such devices. This technology addresses these and other needs. [Overview of the Initiative]

[0006] Embodiments of this technology include semiconductor devices and methods with improved contact resistance. The semiconductor device includes a substrate, silicon oxide disposed on the base defining one or more features, a bimetallic silicide layer disposed on the substrate at one or more features, and at least a first metal layer. The bimetallic silicide layer includes a first metal, a second metal different from the first metal, and a silicon-containing compound, with the second metal atoms at approximately 0.8E+14 / cm². -2 The above is included. The first metal layer contains the first metal and overlaps the bimetallic silicide layer.

[0007] In the embodiment, the semiconductor device exhibits a Schottky barrier height at least about 5% lower than that of a semiconductor device without bimetal silicide. In the embodiment, the semiconductor device exhibits a Schottky barrier height of less than 0.39 eV. In a further embodiment, the bimetal silicide layer contains a second metal atom at about 3E+14 / cm². -2 This includes the above.

[0008] In further embodiments, the semiconductor device also includes a second metal layer containing a second metal, which is superimposed on the first metal layer. Additionally or alternatively, the second metal is titanium, zirconium, nickel, molybdenum, gold, tungsten, palladium, platinum, chromium, or a combination thereof. In embodiments, the first metal is titanium, zirconium, nickel, molybdenum, gold, tungsten, palladium, platinum, chromium, or a combination thereof. In yet another embodiment, the first metal is molybdenum, the second metal is titanium, and the bimetallic silicide is molybdenum(titanium)-silicide. In embodiments, the bimetallic silicide layer is located in the p-MOS region. Additionally or alternatively, in embodiments, the bimetallic silicide layer is located in the n-MOS region.

[0009] Embodiments of this technology include a semiconductor device processing system. The system includes a first processing chamber, a second processing chamber, and a third processing chamber. The system includes a system controller configured to etch at least a first feature into an oxide on a silicon-containing substrate within the first processing chamber. The system includes a system controller configured to deposit a first metal layer containing a first metal on the silicon-containing substrate at least the first feature within the second processing chamber. The system includes a system controller configured to deposit a second metal layer containing a second metal on the first metal layer within the second or third processing chamber. The system includes a system controller configured to anneal a semiconductor device and form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

[0010] In some embodiments, the first metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the first metal precursor and the first metal reactant in a second processing chamber. In more embodiments, the second metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the second metal precursor and the second metal reactant in a third processing chamber.

[0011] Embodiments of this technology include a method for forming a semiconductor structure. The method includes etching at least a first feature onto an oxide disposed on a silicon-containing substrate. The method includes depositing a first metal layer containing a first metal on the silicon-containing substrate at least the first feature. The method includes depositing a second metal layer containing a second metal different from the first metal on the first metal layer. The method includes annealing the semiconductor device to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

[0012] In embodiments, the method includes depositing a first metal layer by exposing a substrate in at least a first feature to a first metal precursor and a first metal reactant. In more embodiments, the method includes depositing a second metal layer by exposing the first metal layer to a second metal precursor and a second metal reactant. Additionally or alternatively, embodiments include cases where the first and second metals are individually selected from molybdenum, titanium, zirconium, nickel, or combinations thereof. In embodiments, the semiconductor device exhibits a Schottky barrier height at least about 5% lower than that of a semiconductor device without bimetallic silicide. In more embodiments, the second metal contains about 0.8E+14 / cm³ of second metal atoms in the bimetallic silicide layer. -2 A sufficient amount to generate the above is applied to the second metal layer. In yet another embodiment, the bimetallic silicide layer exhibits an adhesion energy to the substrate that is at least about 3% greater than that of a single metallic silicide layer for the same substrate.

[0013] Such technologies can offer many advantages over conventional technologies. For example, embodiments of this technology result in improved contact strength and reduced contact resistance, even with small contact sizes. In addition, this technology allows for control over the degree and strength of contact. Therefore, this technology can provide improved contact without requiring annealing techniques that may damage the substrate. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying drawings.

[0014] Further understanding of the nature and advantages of the disclosed technology can be gained by referring to the remainder of the specification and the drawings. [Brief explanation of the drawing]

[0015] [Figure 1] The image shows an exemplary top view of a processing chamber according to several embodiments of this technology. [Figure 2] Selected steps of a formation method according to several embodiments of this technology are shown. [Figure 3] Figures A through E show cross-sectional views of exemplary semiconductor structures according to several embodiments of this technology. [Modes for carrying out the invention]

[0016] Several diagrams are included as schematic representations. These diagrams are for illustrative purposes only, and scale should not be considered unless explicitly stated otherwise. Furthermore, the diagrams are provided as schematic representations to aid understanding and may not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0017] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished according to the reference numerals by letters that distinguish between similar components. When only the first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letters.

[0018] Microelectronic devices are manufactured as integrated circuits on semiconductor substrates, with various conductive layers interconnected to enable the propagation of electronic signals within the device. Such devices can include transistors such as complementary metal-oxide-semiconductor (CMOS), field-effect transistors (FETs), and MOSFETs (including finFETs, gate-all-around FETs, nanosheet FETs) that include both planar and three-dimensional structures, among other types of transistors. The drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor. Generally, faster transistors require larger gate widths. There is a trade-off between the size and speed of a transistor, and "fin" field-effect transistors (finFETs) and gate-all-around FETs have been developed to address the opposing goals of transistors having maximum drive current and minimum size.

[0019] An exemplary finFET or MOSFET includes a gate electrode on a gate dielectric layer on the surface of a semiconductor substrate. Source and drain regions are provided along opposite sides of the gate electrode. The source and drain regions are generally highly doped regions (p-type or n-type doped) of the semiconductor substrate. Typically, a capped silicide layer, such as molybdenum silicide, is used to connect contacts to the source and drain regions. However, such caps, as well as contact scaling, have led to undesirably high contact resistances, especially in miniaturization technologies, for the continued improvement of electrical characteristics. Specifically, at least in part due to the limited contact area between the source / drain regions and the corresponding metal contacts, the contact resistance becomes unacceptably high for the improvement of semiconductor devices.

[0020] In addition, in a middle-of-line (MOL) process, the aim is to minimize the via resistance of the MOL structure. However, MOL contact dimensions are also affected by technology scaling. Thus, appropriate scaling of the contact size can result in a significant increase in contact resistance. For example, the contact resistance to the silicide of an epi-substrate is estimated to potentially exceed 80% of the total resistance of each device. Attempts have been made to modify the silicidation process to improve deposition, reduce oxidation, and utilize different materials. In addition, in conventional processes, the use of a high-temperature thermal annealing process has been proposed to improve the adhesion of the contact and / or the crystallinity of the interface. However, such methods have proven insufficient to improve the contact resistance to the levels required by the technology, and also result in a reduction of materials available elsewhere on the device due to the high temperature (e.g., films, liners, etc. that cannot withstand the high annealing temperature).

[0021] This technology overcomes these and other challenges by providing strong and robust contacts, thereby promoting a reduction in barrier height and contact resistance. Specifically, the technology has found that, surprisingly, the strength and resistivity of the contacts are significantly improved by utilizing a second metal layer deposited on a first metal layer before silicide formation. In embodiments of this technology, the first metal layer is deposited on a silicon-containing layer, and a second metal, different from the first metal, is deposited on the first metal layer. By utilizing such methods and devices, the technology has found that, surprisingly, the adhesion between contact layers is improved by the formation of a mixed-metal adhesive layer (e.g., bimetal or bimetallic silicide) at the interface between the substrate and the first metal. Remarkably, the technology has found that this approach improves contact resistance in both the p-MOS and n-MOS regions.

[0022] The following disclosure identifies specific metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductors (CMOSs), and their components as appropriate, but it will be readily apparent that the devices and methods are equally applicable to other field-effect transistors, their orientations, and processes for forming such devices. Therefore, the technology should not be considered limited to use with these specific devices or methods alone. Before describing additional modifications and adjustments to the apparatus according to embodiments of the technology, this disclosure discusses the possibility of a single semiconductor device, possibly comprising one or more components, utilizing one or more self-aligned single-diffusion breaks according to embodiments of the technology.

[0023] Figure 1 shows a top view of a multi-chamber processing system 100, which may be specifically configured to carry out an aspect or process according to several embodiments of the present technology. The multi-chamber processing system 100 can be configured to carry out one or more manufacturing processes on any number of individual substrates, such as semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (which may also include dual load locks), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113, which can be mounted in the buffer chamber 108. The processing chambers 114, 116, 118, and 120 can be mounted in the transfer chamber 106. The processing chambers 122 and 124 can be mounted in the buffer chamber 108. Two substrate transfer platforms 102 and 104 are positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers to maintain different operating pressures between the transfer chamber 106 and the buffer chamber 108. Each of the transfer platforms 102 and 104 may be equipped with one or more tools 105 for orientation or measurement operations, etc.

[0024] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Thus, the computer system 130 may be a general-purpose computer configured with a controller or an array of controllers and / or software stored on a non-temporary computer-readable medium, the software which, when executed, can perform the operations described in relation to the methods according to embodiments of the Art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more process steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing operations, including dry etching processes, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0025] Figure 2 shows exemplary steps in Method 200 according to several embodiments of the present technology. The method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many of the steps described are provided to offer a broader range of structure formation, but are not critical to the technology or may be carried out by alternative methodologies that would be more readily understood.

[0026] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing steps may include forming a structure on the semiconductor substrate, which may include both the formation and removal of materials. The pre-processing steps may be performed in the chamber in which Method 200 may be carried out, or processing may be carried out in one or more other processing chambers before the substrate is transported to the semiconductor processing chamber in which Method 200 may be carried out. In any case, Method 200 may optionally include transporting the semiconductor substrate to the processing area of ​​the semiconductor processing system 100, such as the processing chambers 114, 116, 118, 120, 122, and / or 124 described above, or to other chambers that may include the components described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as a substrate platform 104, and this substrate support may be located within the processing area of ​​a chamber, such as the processing area 120 described above. Method 200 illustrates the steps schematically shown in Figures 3A to 3E, which will be explained in conjunction with the steps of Method 200. Figures 3A–3E show only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further components as shown in the figures, as well as alternative components of any size or configuration that may still benefit from aspects of this technology.

[0027] Method 200 may include or may not include optional steps for forming a semiconductor structure in accordance with a particular polishing step, such as one or more semiconductor processing steps for forming one or more material layers on a substrate, a step of clamping the substrate to a carrier head of a polishing system, or a step of depositing one or more metal layers on one or more features 302. Method 200 should be understood to be applicable to any number of semiconductor structures or substrates 305, including exemplary structures 300 on which silicon oxide 310 can be formed, as shown in Figure 3A. For example, in an embodiment, step 205 may include transferring the substrate 305 to a deposition chamber such as a processing chamber 114 and etching one or more features 302 into the silicon oxide 310.

[0028] Structure 300 can, in embodiments, show a partial diagram of a substrate that can be used for other types of semiconductor transistor structures, such as n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, complementary metal oxide semiconductors, and nanosheet FETs. Layers of material can be produced by a variety of methods, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or any other formation technique. In embodiments, one or more deposition methods or processes can be carried out in a processing chamber such as the processing chambers 118 and / or 120 described above. The substrate layers can include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0029] However, in the embodiment, the substrate 305 may be a bulk semiconductor substrate. As used herein, the term “bulk semiconductor substrate” refers to a substrate in which the entire substrate is composed of semiconductor material. A bulk semiconductor substrate can be composed of any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials, such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, silicon germanium, epitaxial substrates, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 305 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 305 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is within the spirit and scope of this disclosure.

[0030] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers. As discussed above, in embodiments, the technology can result in improved mobility in both p-type and n-type semiconductors (also referred to herein as p-MOS regions and n-MOS regions).

[0031] In the following description, silicon oxide deposited on substrate 305 is primarily discussed as the dielectric material, but any number of dielectric materials can be used in embodiments of this technique, and it should be understood that this technique should not be limited to any specific dielectric material on which features can be formed. As shown in Figure 3A, silicon oxide 310 can be processed to form one or more recesses or features 302, such as trenches, apertures, or vias, or any other structure useful for semiconductor processing. Substrate 305 can be any number of materials, such as a base wafer or substrate 305 made of silicon or a silicon-containing material, or any other substrate material discussed above. In embodiments, the method may include an optional step 205 of etching one or more features 302 in an etching chamber, such as a processing chamber 114. Although two features 302 are shown in the figure, it should be understood that the exemplary structure may have any number of features defined along the structure according to embodiments of this technique. Therefore, in the embodiment, only one feature may be formed, or more than two, for example, more than three, for example, more than four, for example, more than five, for example, more than six, for example, more than seven, for example, more than eight, for example, more than nine, for example, more than ten, or any range or value in between.

[0032] Nevertheless, in embodiments, depending on the prior processing steps, an optional etching step 205 may be the first step in the processing system 100. In such cases, the substrate 305 may be loaded onto load locks 110, 112 and transferred to an etching chamber (e.g., processing chamber 114) via robots 126, 128. Thus, the etching process can be considered an in-situ etching process within the processing system 100. However, in embodiments, if prior processes have been performed according to embodiments of the method, instead of loading via load locks 110, 112, a transfer from a first processing chamber (e.g., processing chamber 114) to a second processing chamber 116 may occur. That is, as will be described in more detail below, in embodiments, prevention and removal of oxides may be necessary in order to properly anneal two or more metal layers used to form the bimetallic silicide of the Art. Thus, in embodiments, the processing system 100 can provide an end-to-end platform so that each step, including the transfer between them, can be performed under vacuum.

[0033] However, in embodiments, it may be desirable to perform an optional pre-cleaning step 210 before or after the etching step 205 to remove any existing oxides, or if a complete vacuum process is not feasible. In embodiments, the cleaning step (also called the pre-cleaning step) is any cleaning process suitable for removing the oxide layer from the substrate 305. For example, in embodiments, a plasma-assisted etching process, a reactive etching process, or a cleaning process, or a combination thereof, can be performed to remove by-products formed on the substrate, such as surface oxidation. In embodiments, the pre-cleaning step 210 can be performed via a Siconi® etching process, or any reactive etching or cleaning process known in the art. For example, such pre-cleaning may be selected, just as an example, to remove silicon oxide formed on the upper surface 312 of the substrate 305 within a feature 302. Nevertheless, in embodiments, the substrate 305 may be transferred from the etching chamber 114 to a pre-cleaning chamber (e.g., processing chamber 116) via robots 126, 128. Thus, the pre-cleaning process can be considered an in-situ cleaning process within the processing system 100.

[0034] Furthermore, as discussed above, in the embodiment, after the pre-cleaning process, the substrate 305 is transferred under vacuum to a deposition chamber such as the processing chamber 118. That is, the formation of oxides on the silicon-containing substrate 305 prevents two or more metals from diffusing into the silicon-containing substrate 305. Therefore, in the embodiment, it may be necessary to transfer the substrate to the deposition chamber 118 under vacuum to prevent further oxide formation after the pre-cleaning step 210.

[0035] Nevertheless, in the embodiment, in step 215, a first metal layer 314 containing the first metal 315 is deposited on the substrate 305 in feature 302, as shown in Figure 3B. In the embodiment, the deposition can be carried out according to any suitable method in the art and can be performed in a processing chamber configured as a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a thermally enhanced chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, an electroless deposition chamber, or a plasma-enhanced atomic layer deposition chamber.

[0036] In embodiments, the first metal is tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof. However, in embodiments, the first metal should be understood to be a low-resistance conductive metal as known in the art. Nevertheless, in embodiments, the first metal is molybdenum, titanium, zirconium, nickel, metal-containing species thereof, alloys thereof, or combinations thereof. In embodiments, the first metal is molybdenum, metal-containing species thereof, or alloys thereof.

[0037] The deposition of the first metal 215 may include a masking step known in the art to mask areas of the structure 300 where the deposition of the first metal layer 314 is undesirable (e.g., all areas other than feature 302). Nevertheless, the deposition of the first metal layer 314 may include exposing (one or more) features 302 to a metal precursor (which may be one or more precursors of the first metals discussed above) to form the first metal layer 314 within one or more features 302. As used herein and in the appended claims, terms such as “reactive compound,” “reactive gas,” “reactive nuclide,” “precursor,” and “process gas” are used interchangeably to mean a substance having a nuclide that can react with the substrate 305 (or substrate surface 312) or a material on the substrate 305 (or substrate surface) in a surface reaction (e.g., chemisorption, oxidation, reduction). In embodiments, the precursor may be a metal vapor or plasma (e.g., when a PVD process is utilized), or a precursor and reactants, or other precursor forms known in the art.

[0038] After the formation of the first metal layer 314, conventional processes would involve annealing the structure 300 to form the first metal-silicide by a silicide process. However, as discussed above, such processes result in silicides with poor adhesion to the substrate and unacceptably high contact resistance (measured, e.g., by Schottky barrier height). Surprisingly, this technique has found that by subsequently depositing a second metal layer on top of the first metal layer, the silicide layer formed at the interface between the substrate and the first metal layer contains doping of the second metal atoms. By forcing the second metal atoms into the interface, this technique has surprisingly found that not only is the barrier height in the p-MOS region reduced due to a decrease in contact resistance, but the contact strength is dramatically improved, resulting in improved barrier height in both the p-MOS and n-MOS regions.

[0039] Therefore, in the embodiment, the substrate 305 is transferred to a deposition chamber, such as a processing chamber 120, under vacuum. That is, the formation of oxides on the first metal layer 314 prevents two or more metals from diffusing into the silicon-containing substrate 305. Therefore, in the embodiment, it may be necessary to transfer to a deposition chamber, which may be the same deposition chamber 118 or a second deposition chamber 120 under vacuum, to prevent further oxide formation. Additionally or alternatively, an optional further cleaning process according to one or more of the steps 210 described above may be performed before deposition in step 220.

[0040] Nevertheless, in the embodiment, in step 220, a second metal layer 316 containing a second metal 317 is deposited on the first metal layer 314 in feature 302, as shown in Figure 3C. In the embodiment, the deposition can be carried out according to any suitable method in the art and can be performed in a processing chamber configured as a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a thermally enhanced chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, an electroless deposition chamber, or a plasma-enhanced atomic layer deposition chamber.

[0041] In embodiments, the second metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species thereof, alloys thereof, or combinations thereof, but it should be noted that the second metal is different from the first metal. Therefore, each of the first and second metals may be selected from similar or identical groups of metals or species thereof, but the second metal should be understood to include at least one metal species different from the metal or metal species of the first metal. For example, just as an example, if the first metal is molybdenum or a molybdenum-containing species, the second metal may be tungsten, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal or metal-containing species thereof, metal-containing species thereof, alloys thereof, or combinations thereof. Nevertheless, in embodiments, the second metal should be understood to also be a low-resistance conductive metal, as known in the art. In embodiments, the second metal is molybdenum, titanium, zirconium, nickel, metal-containing species thereof, alloys thereof, or combinations thereof. In embodiments, the second metal is titanium, metal-containing species thereof, or alloys thereof.

[0042] The deposition of the second metal layer 316 may include a masking step known in the art to mask areas of the structure 300 where deposition of the second metal layer 316 is undesirable (e.g., all areas other than feature 302). The mask layer may be maintained from the first metal deposition step described above, or it may be a new masking step. Nevertheless, the deposition of the second metal layer 316 may include exposing (one or more) features 302 to a second metal precursor (which may be one or more precursors of the second metal described above) to form the second metal layer 316 on the first metal layer 314 in one or more features 302.

[0043] Both the first metal layer 314 and the second metal layer 316 can be formed using one or more of the deposition methods described above. In embodiments, the second metal layer 316 can be deposited by physical vapor deposition (PVD) method or system. That is, in embodiments, the second metal layer 316 can be applied as a thin film, since it exists to dope the first metal / main metal and is therefore a trace component of the bimetallic silicide.

[0044] For example, as shown in Figure 3C, in the embodiment, the first metal layer 314 may have a first height or thickness T1, and the second metal layer may have a second height or thickness T2. In the embodiment, the thickness T1 of the first metal layer may be about 1.1 times or more the thickness T2 of the second metal layer, for example, about 1.2 times or more the thickness T2 of the second metal layer 316, for example, about 1.3 times or more, for example, about 1.4 times or more, for example, about 1.5 times or more, for example, about 1.6 times or more, for example, about 1.7 times or more, for example, about 1.8 times or more, for example, about 1.9 times or more, for example, about 2 times or more, or any range or value in between. Naturally, in the embodiment, the thickness T1 of the first metal layer and the thickness T2 of the second metal layer are approximately equal (for example, about 1:1), or the second metal layer 316 may be thicker than the first metal layer 314, depending on the desired concentration of the first metal particles 315 and the second metal particles 317 in the bimetallic silicide layer 318.

[0045] Regardless of the method used to form the first metal layer 314 and / or the second metal layer 316, after the formation of the second metal layer 316, the substrate 305 is subjected to a thermal annealing process in step 225 to form a silicide layer 318. As shown in Figure 3D, during the diffusion process, the second metal particles 317 diffuse through the first metal layer 314 toward the upper surface 312, and the first metal particles 315 diffuse through the first metal layer 314 toward the upper surface 312, forming a bimetallic silicide layer 318 containing both the first metal particles 315 and the second metal particles 317 at the interface between the substrate 305 and the first metal layer 314.

[0046] This technology surprisingly found that even at low concentrations of the second metal 317, the adhesion between the bimetallic silicide layer 318 and the substrate 305 was dramatically improved compared to the same structure 300 using a single metal silicide layer. While we do not wish to be bound by theory, it is thought that the second metal particles 317 result in improved bonding orientation between the highly ordered silicon-containing substrate 305 and the silicide. Furthermore, while we do not wish to be bound by theory, in the embodiments, the second metal particles 317 were observed only at the interface between the substrate 305 and the bimetallic silicide layer 318. Therefore, in the embodiments, the second metal particles 317 can form a bonding interface between the silicide layer 318 and the substrate 305, as shown in Figure 3E, and may generally not be present at the interface between the silicide layer 318 and the first metal layer 314. Nevertheless, the second metal particles 317 are incorporated into the lattice of the bimetallic silicide layer 318 and should therefore be understood as being part of the bimetallic silicide layer 318. In embodiments, the second metal particles 317 may be present individually, at the interface between the substrate 305 and the bimetallic silicide layer 318, or throughout the entire bimetallic silicide layer 318.

[0047] Therefore, in the embodiment, the substrate 305 is a silicon-containing substrate such as a silicon-germanium substrate. In more embodiments, the substrate may be an epitaxially formed silicon-containing substrate such as an epitaxially formed silicon-germanium substrate. Therefore, in the embodiment, the bimetallic silicide may be molybdenum (titanium) silicide.

[0048] Nevertheless, in the embodiment, the thickness of the second metal layer 316 and / or the annealing time and temperature are approximately 0.8E+14 / cm² at the interface between the bimetallic silicide layer 318 and the substrate 305, the entire bimetallic silicide layer 318, or a combination thereof. -2 The above second metal atoms, for example, about 1E+14 / cm³ -2 The above second metal atoms, for example, about 1.5E+14 / cm³ -2 The above second metal atoms, for example, about 2E+14 / cm³-2 The above second metal atoms, for example, about 2.5E+14 / cm -2 The above second metal atoms, for example, about 3E+14 / cm -2 The above second metal atoms, for example, about 3.5E+14 / cm -2 The above second metal atoms, for example, about 4E+14 / cm -2 The above second metal atoms, for example, about 4.5E+14 / cm -2 The above second metal atoms, for example, about 5E+14 / cm -2 The above second metal atoms, for example, about 6E+14 / cm -2 The above second metal atoms, for example, about 7E+14 / cm -2 The above second metal atoms, for example, about 8E+14 / cm -2 The above second metal atoms, for example, about 9E+14 / cm -2 The above second metal atoms, for example, about 10E+14 / cm -2 It can be selected to provide a bimetal silicide layer 318 that includes the above second metal atoms, or any range or value therebetween.

[0049] That is, the present technology has found that by utilizing a bimetal silicide having a second metal, the resulting semiconductor device has a Schottky barrier height that is at least about 5% lower, for example about 6% or more lower, for example about 7% or more lower, for example about 8% or more lower, for example about 9% or more lower, for example about 10% or more lower, for example about 12.5% or more lower, for example about 15% or more lower, for example about 17.5% or more lower, for example about 20% or more lower, for example about 22.5% or more lower, for example about 25% or more lower, for example about 30% or more lower, than the Schottky barrier height of a semiconductor device formed identically except that the device does not include the bimetal silicide according to the present technology, or a Schottky barrier height of any range or value therebetween.

[0050] In other words, in the embodiments, the resulting semiconductor device formed using bimetal silicide according to the present technology may have a Schottky barrier height of about 0.55 eV or less, for example about 0.5 eV or less, for example about 0.45 eV or less, for example about 0.4 eV or less, for example about 0.35 eV or less, for example about 0.325 eV or less, for example about 0.3 eV or less, for example about 0.275 eV or less, or any range or value in between.

[0051] In the embodiment, the interfacial bonding between the bimetallic silicide layer and the substrate can be significantly improved. For example, in the embodiment, the bimetallic silicide exhibits an adhesion energy (cohesive force) to the substrate that is at least about 3% greater than the adhesion energy between single metal silicide layers to the same substrate, e.g., about 4% or more, e.g., about 5% or more, e.g., about 6% or more, e.g., about 7% or more, e.g., about 8% or more, e.g., about 9% or more, e.g., about 10% or more, e.g., about 11% or more, or any range or value in between. In other words, such interfacial bonding can also be expressed as the cohesive / adhesion energy between the bimetallic silicide and the substrate.

[0052] Nevertheless, as illustrated, in the embodiments, it should be understood that the annealing process does not completely eliminate the first metal layer 314, the second metal layer 316, or both the first and second metal layers 314 and 316. However, in the embodiments, it may be desirable to select annealing times and temperatures such that one or more of the first and second metal layers 314 and 316 completely diffuse into the bimetallic silicide layer 318 (not shown). If one or more of the first metal layer 314 and the second metal layer 316 remain after the formation of the bimetallic silicide layer 318, the thickness T1p of the first metal layer after annealing may be smaller than the thickness T1 of the first metal layer, for example, about 1.1 times smaller than the thickness T1 of the first metal layer before annealing, for example, about 1.2 times smaller than the thickness T1 before annealing, for example, about 1.3 times smaller, for example, about 1.4 times smaller, for example, about 1.5 times smaller, for example, about 1.6 times smaller, for example, about 1.7 times smaller, for example, about 1.8 times smaller, for example, about 1.9 times smaller, for example, about 2 times smaller, or any range or value in between. The thickness T2p of the second metal layer after annealing may also be smaller than the thickness T2 of the second metal layer, but may show less change than the thickness of the first metal layer, at least in part due to the small amount of second metal particles 317 available for diffusion. Therefore, in the embodiment, the thickness T2p of the second metal after annealing may be about 0.95 times or less the thickness T2 of the second metal layer before annealing, for example, about 0.925 times or less the thickness T2 before annealing, for example, about 0.9 times or less, for example, about 0.875 times or less, for example, about 0.875 times or less, for example, about 0.85 times or less, for example, about 0.825 times or less, for example, about 0.8 times or less, or any range or value in between.

[0053] After the formation of the bimetallic silicide layer 318, the structure 300 may undergo the deposition or formation of further layers or features. Additionally or alternatively, the structure 300 may be transferred to a polishing process, a wiring deposition process, or other processes known in the art.

[0054] In the preceding description, many details have been given for illustrative purposes to facilitate understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be carried out without some of these details, or with further details.

[0055] While several embodiments have been disclosed, it will be apparent to those skilled in the art that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the Art. In addition, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in a different order than described.

[0056] Where a range of values ​​is presented, it is understood that each intervention value up to the smallest unit of the lower limit between the upper and lower limits of that range is also specifically disclosed, unless the context explicitly indicates otherwise. Any narrow range between any listed value or unlisted intervention value within a listed range and any other listed value or intervention value within that listed range is also included. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range that includes one, neither, or both of the limit values ​​is also included in this technical scope and is subject to any specifically excluded limit values ​​within the specified range. Where one or both limit values ​​are included in the specified range, ranges that exclude one or both of those included limit values ​​are also included.

[0057] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” refer to multiple objects unless otherwise specified in the context. Thus, for example, “a metal” includes multiple such metals, and “the layer” includes one or more layers and their equivalents known to those skilled in the art.

[0058] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used in this specification and the appended claims, are intended to identify the presence of a described feature, integer, component, or process, but do not exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. It is a semiconductor device, substrate, Silicon oxide arranged on the substrate and defining one or more features, A bimetallic silicide layer disposed on the substrate in one or more of the features, wherein the bimetallic silicide comprises a first metal, a second metal different from the first metal, and a silicon-containing compound, and the bimetallic silicide layer contains the second metal atoms at approximately 0.8E+14 / cm². －２ The above includes a bimetallic silicide layer, and A first metal layer containing the first metal, which overlaps the bimetallic silicide layer. Semiconductor devices, including those mentioned above.

2. The semiconductor device according to claim 1, wherein the semiconductor device exhibits a Schottky barrier height that is at least about 5% lower than that of a semiconductor device that does not contain a bimetal silicide.

3. The semiconductor device according to claim 1, wherein the semiconductor device exhibits a Schottky barrier height of less than 0.55 eV.

4. The bimetallic silicide layer has a second metal atom density of approximately 3E+14 / cm². －２ The semiconductor device according to claim 1, including the above.

5. The semiconductor device according to claim 1, further comprising a second metal layer containing the second metal, which is superimposed on the first metal layer.

6. The semiconductor device according to claim 4, wherein the second metal is titanium, zirconium, nickel, molybdenum, or a combination thereof.

7. The semiconductor device according to claim 6, wherein the first metal is titanium, zirconium, nickel, molybdenum, or a combination thereof.

8. The semiconductor device according to claim 7, wherein the first metal is molybdenum, the second metal is titanium, and the bimetallic silicide is molybdenum (titanium)-silicide.

9. The semiconductor device according to claim 1, wherein the bimetallic silicide layer is arranged in the p-MOS region.

10. The semiconductor device according to claim 1, wherein the bimetallic silicide layer is arranged in the n-MOS region.

11. A semiconductor device processing system, First processing chamber, Second processing chamber, A third processing chamber, and System controller, At least a first feature is etched onto the oxide placed on the silicon-containing substrate in the first processing chamber. In the second processing chamber, a first metal layer containing a first metal is deposited on the silicon-containing substrate in at least the first feature. A second metal layer containing the second metal is deposited on the first metal layer within the second processing chamber or the third processing chamber, and The semiconductor device is annealed to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer. System controller configured as follows A semiconductor processing system, including a semiconductor processing system.

12. The semiconductor processing system according to claim 11, wherein the first metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the first metal precursor and the first metal reactant in the second processing chamber.

13. The semiconductor processing system according to claim 12, wherein the second metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the second metal precursor and the second metal reactant in the third processing chamber.

14. A method for forming a semiconductor device, Etching at least a first feature onto an oxide placed on a silicon-containing substrate, Depositing a first metal layer containing a first metal on the silicon-containing substrate in at least the first feature, Depositing a second metal layer containing a second metal different from the first metal on the first metal layer, and Annealing the semiconductor device to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer. Methods that include...

15. The method according to claim 14, wherein depositing the first metal layer includes exposing the substrate to a first metal precursor in at least the first feature.

16. The method according to claim 15, wherein depositing the second metal layer includes exposing the first metal layer to a second metal precursor.

17. The method according to claim 16, wherein the first metal and the second metal are individually selected from molybdenum, titanium, zirconium, nickel, or a combination thereof.

18. The method according to claim 14, wherein the semiconductor device exhibits a Schottky barrier height that is at least about 5% lower than that of a semiconductor device that does not contain a bimetal silicide.

19. The second metal contains approximately 0.8E+14 / cm² of second metal atoms in the bimetallic silicide layer. －２ Applied to the second metal layer in an amount sufficient to generate the above. The method according to claim 14.

20. The method according to claim 14, wherein the bimetallic silicide layer exhibits an adhesion energy to the substrate that is at least about 3% greater than that of a single metal silicide layer on the same substrate.

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