Multilayer substrate wafer having radially grown substrates

Abstract

The present invention relates to a multilayer substrate wafer (2320). The multilayer substrate wafer (2320) comprises at least a first substrate (2317) and a second substrate, the first substrate (2317) and the second substrate (2322) bonded to each other, the first substrate (2317) being a single-crystal SiC crystal (2317), the second substrate (2322) comprising polycrystalline 3C-SiC, where at least 30% [volume], particularly at least 50% [volume], preferably at least 70% [volume] of the polycrystalline 3C-SiC is grown radially around at least one or exactly one central element (857), the central element (857) preferably comprises or is made of SiC, the second substrate (2322) has an electrical resistivity of less than 15 mΩcm, and the second substrate (2322) is doped with at least nitrogen, 1 cm 3 Over 10¹⁸ nitrogen atoms are present in the second substrate (2322) due to doping.

Description

[Technical Field]

[0001] The present invention relates to a multilayer substrate wafer according to claim 1, a method for manufacturing a composite wafer according to claim 14, and an electronic device according to claims 21 and 22. [Background technology]

[0002] The technical background is disclosed, for example, in Japanese Patent Application Publication No. 2009117533, U.S. Patent Application Publication No. 2010 / 291328, and International Patent Application Publication No. 2022 / 123078. It is a common practice to grow polycrystalline SiC carrier wafers by epitaxy and then bond them with single-crystal SiC wafers to form composite wafers. However, such composite wafers are expensive and do not serve as a high-quality starting point for further processing. [Overview of the Initiative]

[0003] The object of the present invention is to provide a beneficial composite wafer, a method for manufacturing such a beneficial composite wafer, and an electronic device manufactured on or as part of a beneficial composite wafer. The present invention is solved by a composite wafer or multilayer substrate wafer according to claim 1. The composite wafer or multilayer substrate wafer according to the present invention preferably comprises at least a first substrate and a second substrate, the first substrate and the second substrate bonded to each other. The first substrate is a single-crystal SiC crystal. The second substrate includes, and more particularly consists of, polycrystalline SiC, especially polycrystalline 3C-SiC, wherein more than 90% [volume], especially more than 95% [volume], preferably more than 99% [volume], and most preferably more than 99.9% [volume] of the second substrate is polycrystalline SiC, or more than 90% [mass], especially more than 95% [mass], preferably more than 99% [mass], and most preferably more than 99.9% [mass] of the second substrate is polycrystalline SiC. The polycrystalline SiC of the second substrate preferably contains more than 50% [volume], particularly more than 75% [volume], preferably more than 90% [volume], and most preferably more than 95% [volume] of polycrystalline 3C-SiC, or the polycrystalline SiC of the second substrate preferably contains more than 50% [mass], particularly more than 75% [mass], preferably more than 90% [mass], and most preferably more than 95% [mass] of polycrystalline 3C-SiC. Preferably, at least 30% [volume], particularly at least 50% [volume], and preferably at least 70% [volume] of the polycrystalline SiC, particularly polycrystalline 3C-SiC, grows radially surrounding at least one or strictly one central element, the central element preferably contains or is made of SiC. The second substrate preferably has an electrical resistivity of less than 30 mΩcm, particularly less than 15 mΩcm, or less than 10 mΩcm, preferably less than 5 mΩcm, and most preferably less than 3 mΩcm. Furthermore, or alternatively, the second substrate can be doped, in particular with nitrogen. Preferably, due to the doping, 1 cm 3 10 hits 18More than 100 nitrogen atoms are present in the second substrate. Doping is preferably carried out by adding nitrogen and / or ammonium to the reaction chamber of a used CVD reactor during the growth of the second substrate. B. Jayant Baliga disclosed in Wide Bandgap Semiconductor Power Devices; Materials, Physics, Design, and Applications; A volume in Woodhead Publishing Series in Electronic and Optical Materials; Book; 2019; ISBN: 978-0-08-102306-8 that electrical resistivity may be affected by doping, particularly by nitrogen doping.

[0004] This solution is particularly beneficial because the second substrate is grown using a CVD process, since it grows at least partially radially. Such a CVD process is described, for example, in patent application EP22173970.9, filed with the European Patent Office on 18 May 2022. The subject matter of EP22173970.9 is incorporated in whole by reference. Thus, the growth initiation surface extends in two or more dimensions, surrounding or covering the three-dimensional structure, respectively. Growing a large SiC ingot using a CVD process allows for the removal of multiple polycrystalline SiC wafers in a very cost-effective manner. Thus, the radially grown second substrate can be manufactured at a much lower cost compared to conventional epitaxy processes. Furthermore, since uniform crystal orientations do not exist in radially grown polycrystalline SiC wafers, stresses causing warping and / or strain are offset by the non-uniform crystal orientations. Thus, fewer post-processing steps are required, and the resulting polycrystalline SiC wafer (second substrate) can be manufactured at an even lower cost.

[0005] However, a preferred method for manufacturing a second substrate or at least one second substrate, wherein the second substrate can be a SiC carrier wafer, in particular a crack-free SiC carrier wafer, preferably comprises the steps of: providing a CVD reactor, the CVD reactor comprising at least one SiC growth substrate, the at least one SiC growth substrate comprising a body, a first power connection, and a second power connection, the body having a certain length, the length of the body extending between the first power connection and the second power connection, the first power connection configured to transmit power to the body to heat the body, the second power connection configured to transmit power transmitted from outside the body to the body via the first power connection, the body forming a physical structure, the physical structure forming a deposition surface for depositing SiC. A method for manufacturing a second substrate or at least one second substrate includes the steps of growing a SiC solid by depositing SiC on a physical structure in a CVD reactor, and preferably removing at least one SiC piece from the SiC solid by mechanical means, particularly by cutting means, and preferably also including the step of removing at least one SiC carrier wafer from the SiC piece by mechanical means, particularly by cutting means.

[0006] A method for manufacturing a second substrate or at least one second substrate describes a preferred method for manufacturing a second substrate or at least one second substrate, and in particular can be the subject of an independent claim without further dependency on the aforementioned composite wafer or multilayer substrate wafer. A method for manufacturing a second substrate or at least one second substrate preferably includes a step of processing the carrier wafer to reduce the surface roughness of the surface of the SiC carrier wafer, the surface being embodied or exposed by a step of mechanically removing the SiC carrier wafer from the SiC solid.

[0007] A method for manufacturing a second substrate or at least one second substrate preferably includes a step of analyzing the SiC solid to determine a crack-free fragment of the SiC solid, the step of analyzing the SiC solid being performed prior to a step of mechanically removing at least one SiC fragment from the SiC solid, particularly by a cutting means. According to a more preferred embodiment of the method for manufacturing a second substrate or at least one second substrate, at least one SiC piece is removed from a crack-free fragment of SiC solid, and the crack-free fragment of SiC solid is removed as at least one SiC piece.

[0008] According to a more preferred embodiment of the method for manufacturing a second substrate or at least one second substrate, the step of analyzing the SiC solid to determine crack-free fragments of the SiC solid is carried out by optical inspection, particularly using calipers or threshold detection. A method for manufacturing a second substrate or at least one second substrate preferably includes a step of analyzing a SiC piece or SiC carrier wafer to determine defects, particularly cracks. The step of analyzing a SiC piece or SiC carrier wafer to determine defects is preferably carried out using bending tests, particularly two-point bending tests, three-point bending tests, or four-point bending tests, eddy current testing, and / or optical analysis methods, particularly caliper tests, threshold tests, or transmittance tests. According to a more preferred embodiment of the method for manufacturing the second substrate or at least one second substrate, the step of heating the physical structure is carried out by conducting power from the first power connection to the second power connection or from the second power connection to the first power connection, and an alternating voltage is applied.

[0009] According to a more preferred embodiment of the second substrate or a method for manufacturing at least one second substrate, the frequency of the AC voltage is preferably 1 Hz or greater than 1 Hz, preferably greater than 5 Hz, or greater than 20 Hz, or greater than 50 Hz, or greater than 100 Hz, or greater than 500 Hz, or 5000 Hz or less, particularly 2000 Hz or less, or 1000 Hz or less, or 500 kHz or less. Therefore, the range of 50 Hz to 500 kHz is very preferred. The frequency can be varied during SiC deposition, for example, in the initial stages of SiC deposition, the frequency can be set lower compared to later stages where the amount of deposited SiC increases compared to the initial stages. This is beneficial because the power is guided along the outer surface of the SiC as it grows by the AC voltage, and therefore there is less heating of the center compared to DC. This is beneficial because it is preferable that the temperature of the center is lower than the temperature of the outer surface. This is very beneficial for making the temperature profile between the center and the outer surface uniform, and therefore the temperature difference between the outer surface and the center is preferably lower than 200 K, more preferably lower than 100 K, and most preferably lower than 50 K. This is beneficial for growing SiC under low tension levels to avoid cracking of the SiC.

[0010] According to a more preferred embodiment of the second substrate or a method for manufacturing at least one second substrate, the deposited SiC has a minimum thickness of at least 1 cm, at least one SiC piece is formed between a first plane and a second plane, the first plane is perpendicular to the length of the body, the second plane is perpendicular to the length of the body, the distance between the first plane and the second plane is at least 1%, preferably at least 2%, and very preferably at least 5% of the length of the body, the deposited SiC is polycrystalline SiC, the deposited SiC forms volume portions having various crystal structures, the 3C crystal structure is mainly formed (by mass and / or volume), the volume and / or mass of the SiC formed in the 3C crystal structure constitutes more than 50% (by volume and / or mass) of the deposited SiC, and the SiC carrier wafer is crack-free. According to a more preferred embodiment for manufacturing a second substrate or at least one second substrate, at least one SiC piece is at least 4 cm 2preferably at least 8 cm 2 very preferably at least 12 cm 2 having a cross-sectional size of and a thickness of at least 0.1 cm, preferably at least 1 cm, very preferably at least 2 cm, and / or the volume of at least one SiC piece is 2 cm 3 more preferably 4 cm 3 most preferably 8 cm 3 more than, and at least one SiC piece is crack-free.

[0011] The method for manufacturing the second substrate or at least one second substrate describes a preferred manufacturing method for manufacturing the second substrate or at least one second substrate, and can be the subject of an independent claim, particularly without further dependency on the aforementioned composite wafer or multi-layer substrate wafer. More preferred embodiments of the present invention are described in the following part of the specification and / or in the dependent claims. According to a preferred embodiment of the present invention, the single-crystalline SiC crystal is formed by a crystal structure that defines a c-axis and grows perpendicular to the c-axis. The single-crystalline SiC crystal preferably has a flat upper surface, preferably a flat bottom surface, and a connecting surface connecting the upper and bottom surfaces. The c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal of the upper surface. The single-crystalline SiC crystal is made of 4H-type SiC. The distance between the flat bottom surface and the flat upper surface of the thin substrate layer is preferably less than 20 μm. This embodiment is beneficial because the growth direction is perpendicular to the c-axis, so the number of screw dislocations is significantly reduced. According to a more preferred embodiment of the present invention, the number of screw dislocations per 1 cm present in the single-crystalline SiC crystal is less than the number of basal plane dislocations per 1 cm. 3 per 3 per is less than the number of basal plane dislocations per.

[0012] The upper and bottom surfaces are considered "flat" because each surface has an Ra of less than 1 μm, preferably less than 100 nm, very preferably less than 10 nm, and most preferably less than 1 nm. The top and bottom surfaces are considered “parallel” if the imaginary plane extending through at least three highest peaks of the bottom surface is inclined by less than 1°, preferably less than 0.1°, very preferably less than 0.01°, and most preferably less than 0.001°, with respect to the imaginary plane extending through at least three highest peaks of the top surface. The term “peak” as used herein refers to surface roughness and represents the distance from the bisector, used to calculate the arithmetic mean of the deviations in profile height from the bisector (Ra calculation; see https: / / en.wikipedia.org / wiki / Surface_roughness; 27.03.2023). The production of single-crystal SiC crystals formed by a crystalline structure defining the c-axis and grown perpendicular to the c-axis has already been described in patent application EP22174029.3, filed with the European Patent Office on 18 May 2022. The subject matter of EP22174029.3 is incorporated in whole by reference.

[0013] However, a preferred method for manufacturing the first substrate is as follows: A step of increasing the number of SiC crystals, particularly in a direction perpendicular to the axial direction of one or more wafers or one or more Boules, using a PVT reactor according to any one of claims 1 to 8, At a minimum, follow these steps: A step of providing at least one SiC seed, particularly a seed boul or seed wafer or seed structure, in a PVT reactor in a first configuration having a top surface, a bottom surface, and a connecting surface connecting the top surface and the bottom surface, wherein the SiC seed is formed from a single crystal SiC crystal having a defined c-axis orientation. Includes. The first method for manufacturing a substrate preferably also includes the step of vaporizing the raw material supplied to the raw material containment space.

[0014] The manufacturing method of the first substrate preferably also includes a step of growing a SiC crystal in a direction perpendicular to the c-axis orientation defined for transferring the SiC crystal to the second configuration, and the accumulation of single crystal blocks on the connection surface of the SiC crystal is high compared to the accumulation of single crystal blocks on the upper surface and / or the bottom surface of the SiC crystal. The upper surface and / or the bottom surface and / or the connection surface preferably have a surface roughness of Ra < 20 nm. After the step of growing the upper surface and / or the bottom surface to form two parallel planes, the upper surface and / or the bottom surface are preferably processed, particularly ground and / or lapped and / or etched. The crystal lattice of the SiC crystal is preferably oriented at an off-angle of less than 10°, preferably less than 9°, very preferably less than 5°, most preferably less than 1°, or the crystal lattice of the SiC crystal is preferably oriented at an off-angle of 0° or 4° or 8°. The manufacturing method of the first substrate or at least one first substrate describes a preferred manufacturing method for manufacturing the first substrate or at least one first substrate, and in particular, it can be the subject of an independent claim without having a further subordinate relationship to the aforementioned composite wafer or multi-layer substrate wafer. According to a further preferred embodiment of the present invention, the second substrate preferably forms a flat upper surface, preferably a flat bottom surface, and a connection surface connecting the upper surface and the bottom surface. Preferably, the flat upper surface, preferably the flat bottom surface, and the connection surface are surrounded by a polycrystalline structure formed by particularly grown, particularly radially grown polycrystalline 3C-SiC. This embodiment is beneficial because the second substrate can be used as a carrier wafer.

[0015] According to a further preferred embodiment of the present invention, the polycrystalline structure forms a plurality of elements that are strip-shaped or linear, particularly at least partially curved, particularly at least partially circular, or at least partially arcuate, and / or at least partially linear. The plurality of strip-shaped or linear and / or at least partially linear elements are preferably visible on the bottom surface or the top surface, or visible through the bottom surface or the top surface. The plurality of strip-shaped or linear and / or at least partially linear elements preferably extend preferably in the height direction of the second substrate and at least partially surround the center of the second substrate. The plurality of strip-shaped or linear and / or at least partially linear elements are beneficial because they enable the assignment of individual second substrates to one ingot or boule. Further, or alternatively, the plurality of strip-shaped or linear and / or at least partially linear elements enable the analysis of the growth rate and composition of the grown polycrystalline structure. The plurality of strip-shaped or linear and / or at least partially linear elements are preferably obtained from variations in density in the polycrystalline structure. According to a preferred embodiment, the plurality of strip-shaped or linear and / or at least partially linear elements are generated by varying the gas supply during the growth of the polycrystalline structure.

[0016] According to a further preferred embodiment of the present invention, a plurality of linear, particularly at least partially curved, particularly at least partially circular or at least partially arcuate, and / or at least partially linear elements are preferably formed at a distance of at least 1 nm from the inside of the preferably flat top surface, preferably the flat bottom surface and the connecting surface. This embodiment is beneficial because a plurality of linear, particularly at least partially curved, particularly at least partially circular or at least partially arcuate, and / or at least partially linear elements can be easily obtained by an optical analysis tool. At least one, preferably at least two, curved, circular and / or arcuate and / or linear elements, according to a more preferred embodiment of the present invention, have a circumferential length of at least 10 nm, particularly at least 20 nm, or at least 50 nm, or at least 100 nm, or at least or up to 5000 nm, particularly up to 2000 nm, or 1000 nm of the second substrate.

[0017] The polycrystalline structure, according to a more preferred embodiment of the present invention, includes crystallites that extend in the longitudinal direction of individual crystallites by more than 5 μm, particularly more than 10 μm, and preferably more than 20 μm. More than 30%, particularly more than 50%, preferably more than 70%, of the crystallites that extend in the longitudinal direction of individual crystallites by more than 5 μm, particularly more than 10 μm, or more than 20 μm are preferably oriented at an angle of less than 75°, particularly less than 60°, preferably less than 45°, and most preferably less than 30° with respect to the radial direction of the polycrystalline structure, particularly the cross-section of the polycrystalline structure. The radial direction of the polycrystalline structure is preferably determined with respect to a plurality of cross-sections of the polycrystalline structure, each cross-section containing the radial direction of its respective cross-section at its center, each cross-section having a width of less than 500 μm, particularly less than 300 μm, preferably less than 100 μm, and the alignment between the radial direction of the polycrystalline structure and the longitudinal direction of individual crystallites extending more than 5 μm, particularly more than 10 μm, preferably more than 20 μm, is limited to the crystallites present in each cross-section and the radial direction of each cross-section. The height of the second substrate is less than 500 μm, and more particularly less than 400 μm, according to a more preferred embodiment of the present invention. This embodiment is advantageous because it allows a larger number of second substrates to be divided from a single ingot or boule compared to a larger second substrate.

[0018] The crystal structure of the single-crystal SiC crystal, according to a more preferred embodiment, contains less than 99.9999% (mass ppm) of one, more, or all of the following substances: B (boron), Al (aluminum), P (phosphorus), Ti (titanium), V (vanadium), Fe (iron), and Ni (nickel). Preferably, less than 99.99999% (mass ppm), very preferably less than 99.999999% (mass ppm), and most preferably less than 99.999999% (mass ppm). This embodiment is beneficial because it allows the production of power devices, or units used in power devices and logic devices, or units used in logic devices having a better efficiency factor, on top of the single-crystal SiC crystal. The flat top surface of the polycrystalline SiC has a surface roughness of Ra < 20 nm, preferably Ra < 10 nm, most preferably Ra < 5 nm, and single-crystal SiC crystals are bonded to the flat top surface of the polycrystalline SiC. The surface roughness of Ra < 20 nm, preferably Ra < 10 nm, most preferably Ra < 5 nm is preferably generated by grinding and / or lapping and / or etching, and Ra is preferably reduced to more than 30 nm, particularly more than 50 nm, or more than 100 nm, or more than 200 nm, or more than 500 nm, or more than 1000 nm, or more than 2000 nm, and / or up to 5000 nm, or up to 10000 nm, or up to 20000 nm, due to grinding and / or lapping and / or etching.

[0019] A single-crystal SiC crystal layer is provided on a thin substrate layer according to a further embodiment of the present invention, and the single-crystal SiC crystal is grown by epitaxy. This embodiment is advantageous because device manufacturing can be carried out on and / or within the single-crystal SiC crystal layer. The thin substrate layer is preferably less doped compared to the second substrate, and in particular, 1 cm compared to the second substrate. 3 The doping per unit is less than 1 / 10, preferably less than 1 / 100, or very preferably less than 1 / 1000. The thin substrate layer is preferably less than 1 μm, preferably less than 0.8 μm, or very preferably less than 0.5 μm, with a distance between the flat bottom surface and the flat top surface of the thin substrate layer of 0.01 μm to 1 μm, respectively.

[0020] Alternatively, the thin substrate layer has a distance of 1 μm to 15 μm, preferably 5 μm to 12 μm, between the flat bottom and flat top surfaces of the thin substrate layer. In this case, the thin substrate layer is preferably doped to meet the requirements for manufacturing electronic devices inside and / or on the thin substrate layer, such as MOSFETs or SCHOTTKEY diodes. A preferred doping level is 1 cm 3 10 hits 15 ~10 16 These are individual nitrogen atoms. The second substrate preferably acts as an n+ substrate, and the thin substrate layer preferably acts as an n-drift region. For doping levels, see: Kimoto, Tsunenobu, James A. Cooper; Fundamentals of silicon carbide technology: growth, characterization, devices and applications; 1963; ISBN 978-1-118-31352-7.

[0021] The present invention also covers a method for manufacturing a composite or composite wafer or a multilayer substrate wafer as described in any of claims 1 to 12. The method preferably includes at least the step of providing a first substrate, wherein the first substrate is a single-crystal SiC crystal, the single-crystal SiC crystal is formed by a crystal structure, the crystal structure defines a c-axis, the crystal structure grows perpendicular to the c-axis, the single-crystal SiC crystal preferably has a flat top surface, preferably a flat bottom surface, and a connecting surface connecting the top surface and the bottom surface, and the c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal to the top surface.

[0022] This specification also refers to the manufacture of a single-crystal SiC crystal having a crystalline structure defining a c-axis and growing perpendicular to the c-axis, which is already described in the aforementioned patent application EP22174029.3 filed with the European Patent Office on 18 May 2022, and the aforementioned method for manufacturing a first substrate. The method includes the step of providing a second substrate, wherein the second substrate is made of SiC, particularly polycrystalline 3C-SiC, and at least 60% [volume] of the SiC, particularly polycrystalline SiC, is grown radially, and the second substrate has an electrical resistivity of less than 15 mΩcm, particularly less than 10 mΩcm, preferably less than 5 mΩcm, or most preferably less than 3 mΩcm. This specification also refers to the manufacture of a second substrate that is at least partially grown radially, particularly using a CVD process. Such a CVD process is described, for example, in patent application EP22173970.9 filed with the European Patent Office on 18 May 2022. The method further includes the step of bonding a first substrate and a second substrate to each other. The flat bottom surface of the single-crystal SiC crystal is preferably bonded to the flat top surface of the second substrate. This method is beneficial because it provides a composite wafer that can be manufactured at low cost and provides a high-quality growth surface, particularly by an epitaxial method, for further processing. The high-quality growth surface is the surface of the thus realized single-crystal SiC crystal, in particular the opposite surface parallel to the surface bonded to the second substrate.

[0023] According to a more preferred embodiment of the present invention, the method also includes the step of converting the first substrate into a thin substrate layer by reducing the thickness of the first substrate to less than 20 μm, particularly less than 10 μm, or less than 5 μm, or less than 2 μm, or less than 1 μm. This embodiment is beneficial because only a small amount of single-crystal SiC crystal can be used. The production of single-crystal SiC crystals generally incurs high costs, and therefore reducing the required amount of single-crystal SiC crystal reduces the overall cost. The step of reducing the thickness of the first substrate to less than 20 μm is carried out according to a more preferred embodiment of the present invention after the first and second substrates have been bonded together. This embodiment is advantageous because the resulting thin layer of single-crystal SiC crystal is always supported by the solid structure.

[0024] The step of implanting ions into the first substrate via the surface of the first substrate bonded to the second substrate, before the first and second substrates are bonded to each other in order to define the crack plane within the first substrate, is carried out according to a more preferred embodiment of the present invention. This embodiment is beneficial because ions can be implanted via the bottom surface of the single-crystal SiC crystal before the bottom surface of the single-crystal SiC crystal is bonded to the second substrate. Ion implantation is generally not possible in the deep parts of a single-crystal SiC crystal. Therefore, due to ion implantation via the bottom surface, the single-crystal SiC crystal can have a thickness of more than 50 μm, preferably more than 100 μm, and very preferably more than 200 μm before its thickness is reduced.

[0025] The step of heating at least the implanted ions to a temperature above 800°C, particularly to a temperature of 850°C to 1200°C, is carried out according to a more preferred embodiment of the present invention after the first and second substrates have been bonded together in order to split the first substrate along a defined crack plane into at least two pieces, each of which is a thin substrate layer. This embodiment is beneficial because the remaining single-crystal SiC crystals separated from the thin substrate layer can preferably be used multiple times to split the thin substrate layer from there. The step of bonding the first substrate and the second substrate to each other is carried out using plasma bonding or argon beam bonding according to a more preferred embodiment of the present invention. This embodiment is advantageous because such bonding processes are well known and easy to handle.

[0026] According to a more preferred embodiment of the present invention, a step is performed in which a single-crystal SiC layer is grown by epitaxy on a thin substrate layer, and the single-crystal SiC layer has a thickness of 1 μm to 50 μm, particularly 2 μm to 40 μm, or 3 μm to 30 μm, or 4 μm to 20 μm, or 5 μm to 10 μm. This embodiment is beneficial because it allows the composite or composite wafer according to the preferred invention to be integrated into an electronic device manufacturing process. According to a preferred embodiment of the present invention, the thin substrate layer has a thickness of less than 1 μm, and the c-axis is preferably oriented at an angle of 4°. The allowable deviation of the angle is 0.5° or less than 0.5°, preferably 0.2° or less than 0.2°, and most preferably 0.1° or less than 0.1°. According to a preferred embodiment of the present invention, the single-crystal SiC crystal layer is provided on a thin substrate layer, and the single-crystal SiC crystal is grown by epitaxy.

[0027] According to a preferred embodiment of the present invention, the thin substrate layer has a thickness of 2 μm to 20 μm, particularly 5 μm to 12 μm, and the thin substrate layer is 1 cm 3 10 hits 15 ~10 16 It contains 1 nitrogen atom, and the c-axis is preferably oriented at an angle of 0°. The allowable deviation of the angle is 0.5° or less than 0.5°, preferably 0.2° or less than 0.2°, and most preferably 0.1° or less than 0.1°. The present invention relates in particular to an electronic device as described in claim 21. The electronic device preferably comprises at least one multilayer substrate wafer as described in claim 13, wherein at least one electronic component is grown or formed on or within a single-crystal SiC crystalline layer, which is grown by epitaxy, and the second substrate has a thickness greater than 50 μm, particularly greater than 60 μm, greater than 80 μm, greater than 100 μm, greater than 150 μm, or 350 μm or less. The electronic device may be a MOSFET or a Schottky diode. This solution is beneficial because it allows the electronic device to be manufactured at low cost and with higher quality.

[0028] The present invention relates in particular to an electronic device as described in claim 22. The electronic device preferably comprises at least one multilayer substrate wafer as described in claim 14, wherein at least one electronic component is grown or formed on or within a thin substrate layer, and the second substrate has a thickness of more than 50 μm, particularly more than 60 μm, more than 80 μm, more than 100 μm, more than 150 μm, or 350 μm or less. The present invention also relates to a multilayer substrate wafer comprising at least a first substrate and a second substrate, wherein the first substrate and the second substrate are bonded to each other, the first substrate is a single-crystal SiC crystal, the single-crystal SiC crystal is formed by a crystalline structure, the crystalline structure defines a c-axis, the crystalline structure grows perpendicular to the c-axis, the single-crystal SiC crystal preferably has a flat top surface, preferably a flat bottom surface, and a connecting surface connecting the top surface and the bottom surface, the c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal to the top surface, and the second substrate is made of polycrystalline SiC. Further advantages, objectives, and features of the present invention will be described with reference to the following description of the accompanying drawings, in which devices according to the present invention are shown as examples. Components or elements or methods of composite wafers according to the present invention correspond at least substantially in the figures with respect to their function and may be denoted by the same reference numerals, thereby eliminating the need to reference or describe these components or elements in all the figures. [Brief explanation of the drawing]

[0029] [Figure 1a-d] The steps for manufacturing a composite wafer according to the present invention are shown. [Figure 1e] Further steps for growing an epitaxial layer on a composite wafer are shown. [Figure 2a-d] A composite wafer is provided that can be used for device manufacturing without an epitaxial layer manufacturing step, as the thin substrate layer is thicker compared to Figures 1a-d, using a method similar to that shown in Figures 1a-d. [Figure 3] A high-resolution photograph of the crystal structure of the second substrate is shown. [Figure 4] This is a modified version of Figure 3, showing the main growth direction (emission direction) and the orientation of multiple large crystallites. [Figure 5a] This shows the conventional growth of carrier wafers. [Figure 5b-d] This shows a schematic diagram of the growth direction in a specific cross-section. [Figure 6] Figure 3 shows an enlarged cross-section, with the length and boundary of a single crystallite highlighted. [Figure 7a-b] This shows the line-shaped elements generated during the growth process. [Modes for carrying out the invention]

[0030] Figure 1a shows a polycrystalline SiC piece 2300, particularly an ingot or Boolean. Reference numeral 2414 schematically refers to crystallites oriented at least primarily in the radial direction (R). Line 2416 schematically shows a splitting plane along which the SiC piece 2300 is divided into two pieces. In the illustrated example, the smaller portion of the SiC piece 2300, i.e., the portion above line 2416, each forms a “second substrate” 2322, i.e., a carrier wafer 2322, according to the present invention. Figure 1b shows a first substrate 2317 and a second substrate 2322 according to the present invention. The first substrate 2322 is preferably a single-crystal SiC crystal, and the second substrate is preferably a polycrystalline SiC structure, and both the first substrate 2317 and the second substrate 2322 grow at least partially (by volume) and preferably mainly (by volume) or most preferably entirely in the radial direction.

[0031] The first substrate 2317 preferably contains ions positioned on layer 2418 to split a thin substrate layer 2318 from the first substrate 2317. The ions expand during a subsequent heating process, causing localized cracking of the crystalline structure, thereby splitting the first substrate 2317 into small pieces. Such splitting is known as the "smart cut process". Figure 1c shows the first substrate 2317 and the second substrate 2322 joined together. The arrows "H" indicate the height direction, showing the direction in which the top surface 2406 and the bottom surface 2408 of the second substrate are positioned at a constant distance from each other, and the direction in which the top surface 2400 and the bottom surface 2402 of the first substrate are positioned at a constant distance from each other. Figure 1d shows the composite wafer 2320 of the present invention after the step of separating the thin substrate layer 2318 from the first substrate 2317. Figure 1e shows an arbitrary step of growing the epitaxial layer 2319 on top of the thin substrate layer 2318. The epitaxial layer 2319 is a single-crystal SiC crystal layer 2319 manufactured on a thin substrate layer 2318, the single-crystal SiC crystal layer 2319 is grown by epitaxy, the thin substrate layer 2318 has a thickness of less than 1 μm, and the single-crystal SiC crystal layer 2319 preferably has a thickness of 0.5 μm to 20 μm, particularly 1 μm to 15 μm or 1 μm to 12 μm, or preferably 2 μm to 15 μm or 2 μm to 12 μm.

[0032] Thus, considering Figures 1a-d and 2a-d, the manufacturing method for each composite, each composite wafer, or multilayer substrate wafer 2320 according to the present invention preferably includes the steps of providing a first substrate, providing a second substrate 2322, and bonding the first substrate 2317 and the second substrate 2322 to each other. The first substrate 2317 is preferably a single-crystal SiC crystal, the single-crystal SiC crystal 2317 is formed by a crystal structure, the crystal structure defines a c-axis, the crystal structure grows perpendicular to the c-axis, the single-crystal SiC crystal 2317 preferably has a flat top surface 2400, preferably a flat bottom surface 2402, and a connecting surface 2404 connecting the top surface 2400 and the bottom surface 2402, and the c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal to the top surface 2400. The second substrate 2322 preferably contains or consists of polycrystalline SiC, particularly 3C-SiC, where at least 60% [by volume] of the polycrystalline SiC is grown radially, the second substrate 2322 has an electrical resistivity of less than 15 mΩcm, and the first substrate 2317 and the second substrate 2322 are bonded to each other.

[0033] This method preferably includes the step of converting the first substrate 2317 into a thin substrate layer 2318 by reducing the thickness of the first substrate 2317 to less than 20 μm, the step of reducing the thickness of the first substrate 2317 to less than 20 μm is performed after the first and second substrates 2322 are bonded to each other. Therefore, the present invention relates to a multilayer substrate wafer 2320. The multilayer substrate wafer 2320 comprises at least a first substrate 2317 and a second substrate, the first substrate 2317 and the second substrate 2322 bonded to each other, the first substrate 2317 being a single-crystal SiC crystal 2317, the second substrate 2322 comprising polycrystalline 3C-SiC, where at least 30% [volume], particularly at least 50% [volume], preferably at least 70% [volume] of the polycrystalline 3C-SiC is grown radially around at least one or exactly one central element 857, the central element 857 preferably comprising or made of SiC, the second substrate 2322 having an electrical resistivity of less than 15 mΩcm, and the second substrate 2322 is at least nitrogen-doped, 1 cm 3 10 hits 18 More than one nitrogen atom is present in the second substrate 2322 due to doping.

[0034] Figure 2a corresponds to Figure 1a. Figure 2b shows the first substrate 2317, which includes an ionic layer 2418 for removing the thin layer 2318, with the ionic layer 2418 positioned at a greater distance compared to Figure 1b. Figures 2a to 2d show that the thin substrate layer 2318 preferably has a thickness of 2 μm to 20 μm, particularly 5 μm to 12 μm, and very preferably 1 cm 3 10 hits 15 ~10 16 It contains n nitrogen atoms. Therefore, in the case of an electronic device such as a Schottky diode, for example, the substrate layer 2318 can function as an n-drift region and the second substrate can function as an n+ substrate. Figure 3 shows a high-resolution photograph of the cross-section of the second substrate 2322. Reference numeral 2414 indicates crystallites with an elongation length greater than 5 μm, and reference numeral 2415 indicates crystallites with an elongation length less than 5 μm.

[0035] Figure 4 shows a modified version of Figure 3. Multiple large crystallites 2414 are identified, and the longitudinal direction of these large crystallites 2414 is indicated by a dotted line. The overall radiation direction R indicates the expansion direction of the polycrystalline SiC during growth. Figure 5a shows a carrier wafer 2500 of the latest technology. The carrier wafer 2500 is grown by epitaxy in a flat growth substrate 2502. The growth direction 2504 is in only one direction, each perpendicular to the plane of the growth substrate 2502. Figure 5a also schematically shows that the longitudinal directions of several large crystallites 2506 are mainly oriented in one direction. Figure 5b shows that each growth substrate 857 of the central element provides a growth surface that extends not only in two-dimensional space but also in three-dimensional space, as shown in Figure 5b. Figures 5b and 5c / d show that the central element / SiC growth substrate 857 can take on multiple shapes.

[0036] With respect to Figures 5b, 5c, and 5d, it is important to understand that "radial" does not only apply when the central element / SiC growth substrate 857 has a circular (cross-section) with a "radius". In the context of this invention, "radial" refers to the growth direction as the polycrystalline structure grows and expands, and this direction is along the side, i.e., the growth surface. Therefore, the radial direction R of the polycrystalline structure 2322 can preferably be determined with respect to a plurality of parts of the polycrystalline structure 2322, each part 2420 preferably having its radial direction R at its center, each part 2420 preferably having a width of less than 500 μm, particularly less than 300 μm, and preferably less than 100 μm, and the alignment of the radial direction R of the polycrystalline structure 2322 and the longitudinal direction L of the individual crystallites 2414 that extend more than 5 μm, particularly more than 10 μm, and preferably more than 20 μm is limited to the crystallites 2414 present in each part 2420 and the radial direction R of each part 2420.

[0037] The central element / SiC growth substrate 857 is preferably grown radially as well, and is removed particularly from the radially grown portion of the SiC piece 2300, especially the ingot or boule. Figure 5d schematically shows that the orientation of the large crystallites 2414 changes in the circumferential direction of the polycrystalline structure 2322. Figure 6 shows an enlarged cross-section of Figure 3. The cross-section shows the crystallite 2414, and the boundary 2422 of the crystallite 2414 is indicated by a thin white line. The straight white line connects the two furthest points of the crystallite 2414. Therefore, the white line represents the longitudinal direction of the crystallite 2414. The above definition of the longitudinal direction L of the crystallite 2414 is used in reference to all embodiments of the present invention.

[0038] Figures 7a and 7b schematically show that band-shaped, linear, or straight elements 2412 representing growth rings or growth lines are present in the grown SiC piece 2300. Multiple linear, in particular at least partially curved, in particular at least partially circular or at least partially arc-shaped, and / or at least partially straight elements 2412 are preferably formed inside the flat top surface 2406, preferably at a distance of at least 1 nm from the flat bottom surface 2408 and connecting surface 2410. At least one, preferably at least two, curved, circular, linear, and / or arcuate elements 2412 have a length of at least 10 nm, particularly at least 20 nm, or 50 nm or 100 nm in the circumferential direction of the second substrate 2322. Preferably, at least one or two curved, circular, linear, and / or arcuate elements 2412 extend around the entire perimeter of the central element / SiC growth substrate 857. [Explanation of Symbols]

[0039] 857 Core element / SiC growth substrate 2300 SiC piece 2317 First substrate / single crystal SiC crystal 2318 Thin substrate layer 2319 Epithlayer 2320 Multilayer substrate wafer / composite substrate 2322 Second substrate / carrier wafer / polycrystalline SiC structure 2400 Top surface of the first substrate 2402 Bottom surface of the first substrate 2404 Connection surface of the first substrate 2406 Top surface of the second substrate 2408 Bottom surface of the second circuit board 2410 Connection surface of the second substrate 2412 Strip-shaped, linear, or straight element 2414 Large crystallite 2415 Tiny crystallites 2416 Cutting surface 2418 Ionized layer 2420 parts 2500 Latest Technology Carrier Wafers 2502 Growth substrate for epitaxial growth of carrier wafers using the latest technology 2504 Growth direction of carrier wafers in the latest technology 2506 Large crystallites of carrier wafers using the latest technology H (height direction) L is the length direction of the crystallite. Radiation direction of the polycrystalline structure of R

Claims

1. A multilayer substrate wafer (2320) comprising at least a first substrate (2317) and a second substrate, wherein the first substrate (2317) and the second substrate (2322) are bonded to each other, The first substrate (2317) is a single-crystal SiC crystal (2317), The second substrate (2322) contains polycrystalline 3C-SiC, At least 30% [by volume], particularly at least 50% [by volume], preferably at least 70% [by volume] of the polycrystalline 3C-SiC is grown radially around at least one or exactly one central element (857), the central element (857) preferably contains or is made of SiC. The second substrate (2322) has an electrical resistivity of less than 30 mΩcm, and more particularly less than 15 mΩcm. The second substrate (2322) is doped with at least nitrogen, preferably 1 cm 3 10 hits 18 More than 1 nitrogen atoms are present in the second substrate (2322) due to doping. Multilayer substrate wafer (2320).

2. The single-crystal SiC crystal (2317) is formed by a crystalline structure, the crystalline structure defines a c-axis, and grows perpendicular to the c-axis. The single crystal SiC crystal (2317) preferably has a flat top surface (2400), preferably a flat bottom surface (2402), and a connecting surface (2404) connecting the top surface (2400) and the bottom surface (2402). The c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal to the flat upper surface (2400). The aforementioned single-crystal SiC crystal (2317) is made of 4H-type SiC. A multilayer substrate wafer (2320) according to claim 1, characterized in that...

3. The second substrate (2322) preferably forms a flat top surface (2406), preferably a flat bottom surface (2408), and a connecting surface (2410) connecting the top surface (2406) and the bottom surface (2408), and the preferably flat top surface (2406), preferably a flat bottom surface (2408), and the connecting surface (2410) surround the polycrystalline structure (2322) formed of the radially grown polycrystalline 3C-SiC. A multilayer substrate wafer (2320) according to claim 2, characterized in that...

4. The polycrystalline structure (2322) forms a plurality of elements (2412) that are strip-shaped or linear, particularly at least partially curved, particularly at least partially circular or at least partially arc-shaped, and / or at least partially linear. A multilayer substrate wafer (2320) according to claim 3, characterized in that...

5. The linear, particularly at least partially curved, particularly at least partially circular or at least partially arc-shaped, and / or at least partially straight elements (2412) are formed inside the preferably flat top surface (2406), the preferably flat bottom surface (2408), and at a distance of at least 1 nm from the connecting surface (2410). A multilayer substrate wafer (2320) according to claim 4, characterized in that...

6. At least one, preferably at least two, curved, circular, and / or arc-shaped elements (2412) have a circumferential length of at least 10 nm, particularly at least 20 nm, 50 nm, or 100 nm of the second substrate (2322). A multilayer substrate wafer (2320) according to claim 4 or 5, characterized in that it is the same as described in claim 4 or 5.

7. The aforementioned polycrystalline structure (2322) includes crystallites (2414) that are greater than 5 μm, particularly greater than 10 μm, and preferably greater than 20 μm, and that extend in the longitudinal direction of each crystallite. In the longitudinal direction of each of the crystallites, more than 30%, particularly more than 50%, preferably more than 70%, of the crystallites that extend more than 5 μm, particularly more than 10 μm, or more than 20 μm, the longitudinal direction of the crystallites is oriented at an angle of less than 75°, particularly less than 60°, preferably less than 45°, and most preferably less than 30° with respect to the radial direction of the polycrystalline structure. A multilayer substrate wafer (2320) according to claim 3, 4, 5, or 6, characterized in that it is the same as described in claim 3, 4, 5, or 6.

8. The height of the second substrate (2322) is less than 500 μm, and more particularly less than 400 μm. A multilayer substrate wafer (2320) according to claims 3 to 7, characterized in that it is a multilayer substrate wafer (2320) according to claims 3 to 7.

9. The crystal structure of the single-crystal SiC crystal (2317) contains less than 99.9999% (mass ppm) of one, more, or all of the following substances: B (boron), Al (aluminum), P (phosphorus), Ti (titanium), V (vanadium), Fe (iron), and Ni (nickel). Preferably, it contains less than 99.99999% (mass ppm), very preferably less than 99.999999% (mass ppm), and most preferably less than 99.999999% (mass ppm). A multilayer substrate wafer (2320) according to claims 3 to 8, characterized in that it is a multilayer substrate wafer (2320) according to claims 3 to 8.

10. The flat upper surface (2406) of the polycrystalline 3C-SiC has a surface roughness of Ra < 20 nm, preferably Ra < 10 nm, most preferably Ra < 5 nm, and the single crystal SiC crystal (2317) is bonded to the flat upper surface (2406) of the polycrystalline 3C-SiC. A multilayer substrate wafer (2320) according to claims 3 to 9, characterized in that it is a multilayer substrate wafer (2320) according to claims 3 to 9.

11. The number of helical dislocations present in the aforementioned single-crystal SiC crystal (2317) is less than the number of basal plane dislocations. A multilayer substrate wafer (2320) according to claims 2 to 10, characterized in that it is a multilayer substrate wafer (2320) according to claims 2 to 10.

12. A multilayer substrate wafer (2320) according to claims 2 to 11, characterized in that the thin substrate layer (2318) has a thickness of less than 1 μm, and the c-axis is preferably oriented at an angle of 4°.

13. A single-crystal SiC crystal (2319) layer is provided on the thin substrate layer (2318), and the single-crystal SiC crystal (2319) is grown by epitaxy. A multilayer substrate wafer (2320) according to claim 12, characterized in that...

14. The thin substrate layer (2318) has a thickness of 2 μm to 20 μm, particularly 5 μm to 12 μm, and the thin substrate layer (2318) is 1 cm 3 10 hits 15 ~10 16 It contains nitrogen atoms, and the c-axis is preferably oriented at an angle of 0°. A multilayer substrate wafer (2320) according to claims 2 to 11, characterized in that it is a multilayer substrate wafer (2320) according to claims 2 to 11.

15. In particular, a method for manufacturing a multilayer substrate wafer according to any one of claims 1 to 14, The first step is to provide a substrate. The first substrate (2317) is a single-crystal SiC crystal, The single-crystal SiC crystal (2317) has a crystal structure that defines a c-axis and grows perpendicular to the c-axis. The single-crystal SiC crystal (2317) preferably has a flat top surface (2400), preferably a flat bottom surface (2402), and a connecting surface (2404) that connects the top surface (2400) and the bottom surface (2402). The c-axis is oriented at an angle of 0° to 8°, preferably 2° to 6°, with respect to the normal of the upper surface (2400), step, The step is to provide a second substrate (2322), The second substrate (2322) is made of polycrystalline 3C-SiC, At least 60% [by volume] of the aforementioned polycrystalline SiC is grown in the radial direction. The second substrate (2322) has an electrical resistivity of less than 15 mΩcm, step, Step of joining the first substrate (2317) and the second substrate (2322) to each other. A method that includes at least the following.

16. Steps to convert the first substrate (2317) into a thin substrate layer (2318) by reducing the thickness of the first substrate (2317) to less than 20 μm, particularly less than 10 μm, or less than 5 μm, or less than 2 μm, or less than 1 μm. The method according to claim 15, characterized by the above.

17. The step of reducing the thickness of the first substrate (2317) to less than 20 μm is performed after the first and second substrates (2322) are bonded together. The method according to claim 16, characterized in that

18. Before the first substrate (2317) and the second substrate (2322) are bonded to each other, the first substrate (2317) is implanted with ions to define a crack plane within the first substrate (2317) via the surface of the first substrate (2317) bonded to the second substrate (2322), The first substrate (2317) is divided along a defined crack plane into at least two pieces, one of which is the thin substrate layer (2318). After bonding the first substrate (2317) and the second substrate (2322) together, the implanted ions are heated to a temperature above 800°C, particularly between 850°C and 1200°C. The method according to claim 17, characterized by the above.

19. The step of bonding the first substrate (2317) and the second substrate (2322) to each other is performed using plasma coupling or argon beam coupling. The method according to claim 15, characterized in that

20. A step of growing a single-crystal SiC layer (2319) on the thin substrate layer (2318) by epitaxy, wherein the single-crystal SiC layer (2319) has a thickness of 1 μm to 50 μm, particularly 2 μm to 40 μm, or 3 μm to 30 μm, or 4 μm to 20 μm, or 5 μm to 10 μm. A method according to any one of claims 16 to 18, characterized by the above.

21. The multilayer substrate wafer (2320) described in claim 13 comprises at least the following: At least one electronic component is grown or formed on or within the single-crystal SiC crystal (2317) layer, The second substrate (2322) has a thickness of more than 50 μm, particularly more than 60 μm, or more than 80 μm, or more than 100 μm, or more than 150 μm, or 350 μm or less. Electronic devices.

22. The multilayer substrate wafer (2320) described in claim 14 comprises at least the following: At least one electronic component is grown or formed on or within the thin substrate layer, The second substrate (2322) has a thickness of more than 50 μm, particularly more than 60 μm, or more than 80 μm, or more than 100 μm, or more than 150 μm, or 350 μm or less. Electronic devices.

Images