Automated optical inspection defect classification before bonding

Abstract

A method, apparatus, and system for the automatic detection and measurement of chipping defects on a diced wafer includes receiving an image of at least a portion of the diced wafer; aligning the received image of at least a portion of the diced wafer; determining the edges of at least a portion of the diced wafer represented in the aligned received image; automatically determining at least one baseline from the determined edges for measuring chipping defects on at least a portion of the diced wafer; and measuring chipping defects on at least a portion of the diced wafer using each of the at least one determined baseline. In some embodiments, the method, apparatus, and system may further include applying a machine learning model to the measured chipping defects to determine whether a critical defect is present on the diced wafer.

Description

Technical Field

[0001] Embodiments of the present principle generally relate to detecting and quantifying chipping defects in diced wafers, and more particularly to the automated optical inspection of diced wafers for automatically detecting and quantifying chipping defects on the wafer caused, for example, by the dicing process.

Background Art

[0002] In the context of integrated circuit manufacturing, wafer dicing is the process by which dies are separated from a semiconductor wafer after processing of the wafer. The dicing process may include scribing and breaking, mechanical sawing, and other forms of cutting. However, in some cases, chipping may occur on the wafer during the dicing process. That is, since wafer materials are generally brittle, cutting / removal of the wafer material by polishing force may cause chipping at the groove edges of the wafer.

[0003] Manual processes currently exist for detecting and measuring chipping defects in wafers. For example, in some cases, process engineers can implement an image capture device such as an optical profiler tool, which can focus very precisely on an area of the diced wafer (i.e., a quadrant of the diced wafer). Using this optical tool, the process engineer can draw measurement lines to evaluate chipping deviation across the entire area of each quadrant of the wafer. However, such manual measurement of chipping deviation is a cumbersome process and is prone to errors due to the human perspective, i.e., the measurement lines being drawn from the engineer's viewpoint.

Summary of the Invention

Problems to be Solved by the Invention

[0004] A process is needed for automated optical inspection of diced wafers to automatically detect and quantify chipping defects on the wafer.

[0005] Methods, apparatus, and systems for the automated detection and measurement of chipping defects on diced wafers are presented herein. [Means for solving the problem]

[0006] In some embodiments, a method for automatic detection and measurement of chipping defects on a diced wafer includes receiving an image of at least a portion of the diced wafer; aligning the received image of at least a portion of the diced wafer; determining the edges of at least a portion of the diced wafer represented in the aligned received image; automatically determining at least one baseline from the determined edges for measuring chipping defects in at least a portion of the diced wafer; and measuring chipping defects in at least a portion of the diced wafer using each of the at least one determined baseline.

[0007] In some embodiments, the method may further include aligning the received image along the vertical axis. In some embodiments, the method may further include aligning the received image along the horizontal axis.

[0008] In some embodiments, the method may further include determining a reference axis and aligning the received image along the determined reference axis.

[0009] In some embodiments, the method may further include measuring the chipping defect as the distance from each determined baseline to the edge of the chipping defect.

[0010] In some embodiments, the method may further include applying a machine learning model to the measured chipping defects to determine whether a critical defect is present on the diced wafer. In some embodiments, the machine learning model is trained to recognize measured chipping defects that result in a critical defect on the diced wafer.

[0011] In some embodiments, an apparatus for automatic detection and measurement of chipping defects on a diced wafer includes a processor and a memory coupled to the processor. In some embodiments, the memory internally stores at least one of a program or instructions executable by the processor, and the apparatus is configured to receive an image of at least a portion of the diced wafer, align the received image of at least a portion of the diced wafer, determine the edges of at least a portion of the diced wafer represented in the aligned received image, automatically determine at least one baseline from the determined edges for measuring chipping defects in at least a portion of the diced wafer, and measure chipping defects in at least a portion of the diced wafer using the at least one determined baseline.

[0012] In some embodiments, the device is configured to align images received along at least one of the vertical or horizontal axes.

[0013] In some embodiments, the apparatus is further configured to determine a reference axis and to align the received image along the determined reference axis.

[0014] In some embodiments, the apparatus is configured to measure the chipping defect as the distance from each determined baseline to the edge of the chipping defect.

[0015] In some embodiments, the apparatus is further configured to apply a machine learning model to the measured chipping defects to determine whether a critical defect is present on the diced wafer. In such embodiments, the machine learning model is trained to recognize the measured chipping defects that result in a critical defect on the diced wafer.

[0016] In some embodiments, a system for automatic detection and measurement of chipping defects on a diced wafer includes an image acquisition device for capturing an image of at least a portion of the diced wafer, and an apparatus including a processor and memory. In some embodiments, the memory internally stores at least one program which includes instructions, when executed by the processor, causing the system to use the apparatus to perform a method which includes capturing an image of at least a portion of the diced wafer using the image acquisition device, aligning the captured image of at least a portion of the diced wafer, determining the edges of at least a portion of the diced wafer represented in the aligned received image, automatically determining at least one baseline from the determined edges for measuring chipping defects in at least a portion of the diced wafer, and measuring chipping defects in at least a portion of the diced wafer using each of the at least one determined baseline.

[0017] In some embodiments, the method implemented by the system further includes aligning images captured along at least one of a vertical axis or a horizontal line.

[0018] In some embodiments, the method implemented by the system further includes determining a reference axis and aligning the captured images along the determined reference axis.

[0019] In some embodiments, the method implemented by the system further includes measuring the chipping defect as the distance from each determined baseline to the edge of the chipping defect.

[0020] In some embodiments, the method implemented by the system further includes applying a machine learning model to the measured chipping defects to determine whether a critical defect is present on the diced wafer. In such embodiments, the machine learning model is trained to recognize measured chipping defects that result in a critical defect on the diced wafer.

[0021] Further embodiments of this disclosure are described below.

[0022] The embodiments of this disclosure, which are briefly summarized above and discussed in more detail below, can be understood by referring to the explanatory embodiments of this disclosure depicted in the accompanying drawings. However, the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered to limit the scope of this disclosure, as this disclosure may allow for other similarly effective embodiments. [Brief explanation of the drawing]

[0023] [Figure 1] This is a high-level block diagram of a wafer chipping inspection system according to one embodiment of this principle. [Figure 2] This figure shows two images of quadrants of a diced wafer to which an embodiment of the wafer chipping inspection system of the present principle can be applied, according to one embodiment of the present principle. [Figure 3] This figure shows an embodiment of the edge detection process of an edge detection module based on one embodiment of this principle. [Figure 4] This figure illustrates a chipping measurement performed on a quadrant of a diced wafer using a measurement module based on one embodiment of this principle. [Figure 5]Flow diagram of a method for automatically detecting and measuring chipping defects on a diced wafer according to an embodiment of the present principle. [Figure 6] High-level block diagram of a computing device suitable for use with an embodiment of a wafer chipping inspection system according to the present principle. [Figure 7] High-level block diagram of a network to which an embodiment of the wafer chipping inspection system of the present principle can be applied according to an embodiment of the present principle. **DETAILED DESCRIPTION OF THE INVENTION**

[0024] For ease of understanding, the same reference numbers are used to designate the same elements common to each figure whenever possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment can be advantageously incorporated into other embodiments without further elaboration.

[0025] In the following detailed description, techniques (e.g., methods, devices, and systems) for automatically detecting and measuring chipping defects on a diced wafer are described. Concepts of the present principle are capable of various modifications and alternative forms, and specific embodiments thereof are shown by way of example in the figures and described in detail below. It should be understood that there is no intention to limit the concepts of the present principle to the specific forms disclosed. Rather, the intention is to cover all modifications, equivalents, and alternative forms that are consistent with the present principle and the appended claims. For example, embodiments of the present principle are described herein with respect to automatically detecting and measuring specific wafer chipping defects resulting from wafer slicing, but embodiments of the present principle can be applied to automatically detect and measure substantially any wafer defect caused by any means.

[0026] Throughout this disclosure, the terms machine learning (ML) model, machine learning model / algorithm and similar are used interchangeably to describe an ML process that can be trained to identify chipping defects in a diced wafer / wafer portion that may lead to a critical defect.

[0027] Embodiments of this principle enable the automatic detection and measurement of chipping defects occurring during a dicing process applied to a wafer, for example, with consistency, reproducibility, and efficiency. According to embodiments of this principle, the process / algorithm of this principle can prepare a wafer for measurement and enable auxiliary measurements in order to quantify and qualitatively determine chipping defects on the wafer. For example, in some embodiments, in the first step the algorithm aligns an image of a diced wafer, in the second step the algorithm performs edge detection, and in the third step the algorithm performs defect measurement of the wafer image.

[0028] Figure 1 shows a high-level block diagram of a wafer chipping inspection system 100 according to one embodiment of the present principle. In the embodiment of Figure 1, the wafer chipping inspection system 100 exemplary includes an alignment module 110, an edge detection module 115, and a chipping measurement module 120. In the embodiment of the wafer chipping inspection system 100 of Figure 1, the chipping measurement module 120 includes an optional machine learning model / algorithm. In the embodiment of the wafer chipping inspection system 100 of Figure 1, the alignment module 110, the edge detection module 115, and the chipping measurement module 120 are represented as three separate modules for ease of explanation, but in alternative embodiments of the present principle, the alignment module 110, the edge detection module 115, and the chipping measurement module 120 may comprise one or at least one module. The wafer defect detection and classification system 100 of Figure 1 further exemplary includes an optional storage device 130.

[0029] As shown in Figure 1, embodiments of wafer chipping inspection systems based on this principle, such as the wafer chipping inspection system 100 in Figure 1, can be implemented by a computing device 600 based on this principle (described in more detail below). In the embodiment of the wafer chipping inspection system 100 in Figure 1 (and also see Figure 6), the computing device 600 is represented as a general-purpose computer, but in some embodiments of this principle, the computing device based on this principle can be part of an optical tool (e.g., an optical profiler tool) capable of capturing images of diced wafers.

[0030] In the wafer chipping inspection system 100 of Figure 1, the alignment module 110 can receive data including an image of the wafer being diced, which includes images of at least the edges of the diced wafer. In some embodiments, such image data can be received / acquired from an optional storage device 130. Alternatively or additionally, a wafer chipping inspection system of this principle, such as the wafer chipping inspection system 100 of Figure 1, can be part of an optical tool (e.g., an optical profiler tool) capable of capturing images of the diced wafer, and can receive data related to the captured images, or images of such diced wafers, from the optical tool (not shown). Furthermore, alternatively or additionally, a wafer chipping inspection system of this principle can receive data including images of the wafer being diced from a user of the wafer chipping inspection system of this principle, for example, via an input device of a computing device 600.

[0031] The received image of the diced wafer is aligned by the alignment module 110. For example, Figure 2 shows two images of a quadrant of a diced wafer, demonstrating how an embodiment of the wafer chipping inspection system of this principle can be applied by one embodiment of this principle. In Figure 2, the first image 202 represents the image of the quadrant of the diced wafer before alignment. The second image 204 in Figure 2 represents the image of the quadrant of the diced wafer that has been vertically aligned by the alignment module 110. In the embodiment of Figure 2, the image 204 of the quadrant of the diced wafer was aligned in the vertical direction / axis by rotating the image 204 with the alignment module 110.

[0032] In the embodiment of Figure 2, images 202 and 204 represent quadrant images of a diced wafer; however, in alternative embodiments, the image received by the alignment module 110 may represent an image of a vertically diced wafer portion. In such embodiments, the alignment module of this principle can align the image of the vertically diced wafer portion in the vertical direction / axis. In some embodiments, the image received by the alignment module 110 may represent an image of a horizontally diced wafer portion. In such embodiments, the alignment module of this principle can align the image of the horizontally diced wafer portion in the horizontal direction / axis. In some embodiments, and as shown in the embodiment of Figure 2, the image received by the alignment module 110 may represent quadrant images of vertically and horizontally diced wafer portions. In such embodiments, the alignment module of this principle can align the image of the horizontally diced wafer portion in the horizontal direction / axis, the vertical direction / axis, or a combination of both the vertical and horizontal directions / axis. For example, in some embodiments, an image rotation alignment process may be used with the alignment module of this principle to align the image. In such embodiments, the average value can be determined along the horizontal and / or vertical edges of the diced wafer portion to determine a reference axis, which can then be used to rotate the image so that the reference axis is parallel to the horizontal or vertical axis. The rotated image can then be corrected along the relevant axis for further measurement processes.

[0033] Data from the alignment module 110 is transmitted to the edge detection module 120. The edge detection module 115 processes the data from the alignment module 110 to determine the edges of the portion of the diced wafer. For example, Figure 3 shows an embodiment of the edge detection process of an edge detection module of this principle, such as the edge detection module 115 of the wafer chipping inspection system 100 of Figure 1, according to an embodiment of this principle. In the embodiment of Figure 3, the edges of the quadrant portion of the diced wafer shown in Figure 2 are determined as quadrant pairs, specifically in Figure 3, the horizontal edges of the two left quadrants of the diced wafer in Figure 2 are determined. In some embodiments of this principle, as shown in the first image 302 of Figure 3, the edges are determined in pairs for each quadrant of the diced wafer. For example, as shown in the embodiment of Figure 3 and the second image 304, the center reference line between two quadrant images of the diced wafer can be determined by analyzing adjacent quadrants. In the embodiment shown in Figure 3, the edge detection process may be used to detect image edges, for example, in a third image 306. For example, in embodiments of this principle, relevant edge detection gradient image processing operations, such as Canny Edge, which represents brightness changes due to chipping, can be used to extract gradients in the image. Such techniques help detect image boundaries / edges using existing chipping.

[0034] The edge detection process of the edge detection module of this principle can continue until the edges of all diced wafer portions represented in the image are determined. For example, in the embodiment of Figure 3, the edge detection process of the edge detection module 115 can continue until the horizontal edges of the two right-hand quadrants of the diced wafer in Figure 2 are determined, and the vertical edges of the two upper quadrants and the two bottom quadrants of the diced wafer in the example of Figure 2 are determined.

[0035] Edge information determined by an edge detection module of this principle, such as the edge detection module 115 of the wafer chipping inspection system 100 in Figure 1, is transmitted to a chipping measurement module of this principle, such as the chipping measurement module 120 of the wafer chipping inspection system 100 in Figure 1. The chipping measurement module 120 uses the edge information to establish a measurement baseline for the diced wafer area where the edge has been determined. That is, once a baseline is determined from the determined edge information for each portion of the diced wafer (i.e., each quadrant of the diced wafer), the measurement module 120 can measure the distance between the baseline and the edges of any chipping at multiple locations in the diced wafer portion to determine chipping information for that portion of the diced wafer, such as the intermediate chipping value, average chipping value, maximum chipping value, and so on.

[0036] For example, Figure 4 shows a chipping measurement performed on a quadrant of a diced wafer by a measurement module of the present principle, such as the measurement module 120 of the wafer chipping inspection system 100 of Figure 1, according to one embodiment of the present principle. As shown in the embodiment of Figure 4, the measurement module measured the distance between each determined baseline 4021-4028 and the edges of multiple chips 4071-4077 at multiple locations in each quadrant 4041-4044 of the diced wafer.

[0037] In some embodiments of this principle, the chipping measurement information determined by the measurement module of this principle can be used to determine whether a wafer contains a critical defect. Such information can be used by a wafer chipping inspection system of this principle, such as the wafer chipping inspection system 100 in Figure 1, to determine whether the wafer should be discarded or whether the wafer should be allowed to remain in the wafer processing system.

[0038] For example, as shown in the wafer chipping inspection system 100 of Figure 1, in some embodiments the measurement module 120 may include an optional machine learning model 122. According to this principle, the machine learning model 122 can be trained to identify chipping measurements that may lead to critical defects in diced wafers, either individually or in any combination of chipping measurements. For example, in some embodiments, historical data on chipping measurements that lead to critical defects in all types of diced wafers may be used, either individually or in combination, to train the machine learning module 122 to identify chipping measurements that may lead to critical defects in diced wafers.

[0039] In some embodiments, the models / algorithms of this principle, such as machine learning model / algorithm 122, may include a multilayer neural network with nodes trained to have specific weights and biases. In some embodiments, machine learning model / algorithm 122 employs artificial intelligence or machine learning techniques to analyze received data images containing wafer defects. In some embodiments of this principle, appropriate machine learning techniques may be applied to learn commonalities in sequential application programs and to determine from the machine learning techniques to what level sequential application programs can be normalized. In some embodiments, machine learning techniques that can be applied to learn commonalities in sequential application programs may include, but are not limited to, regression methods, set methods, or neural networks such as "Se2oSeq" recurrent neural networks (RNNs) / Long Short-Term Memory (LSTM) networks, convolutional neural networks (CNNs), graph neural networks applied to abstract syntax trees corresponding to sequential program applications, and similar, as well as deep learning. In some embodiments, however, supervised machine learning (ML) classifiers / algorithms such as multilayer perceptrons, random forests, naive Bayes, support vector machines, logistic regression, and similar methods may be used. In addition, in some embodiments, the ML classifiers / algorithms of this principle may employ at least one of sliding window or sequence-based techniques to analyze the data.

[0040] The machine learning model / algorithm 122 can be trained using multiple (e.g., hundreds, thousands, etc.) specific examples of severe defects in diced wafers, and the training data includes data related to severe defects in diced wafers caused by chipping defects in the diced wafer portion, in order to train the machine learning model / algorithm of this principle to recognize / detect and distinguish various types of chipping defects on the diced wafer that lead to severe defects.

[0041] Figure 5 shows a flowchart of method 500 for automatic detection and measurement of chipping defects on a diced wafer according to one embodiment of the present principle. The method can be started from 502, where an image of at least a portion of the diced wafer is received. Method 500 can proceed to 504.

[0042] In 504, the received image of at least a portion of the diced wafer is aligned. Method 500 can then proceed to 506.

[0043] In step 506, the edges of at least a portion of the diced wafer represented in the received image are determined. The method can then proceed to step 508.

[0044] In step 508, at least one baseline for measuring chipping defects on at least a portion of the diced wafer is automatically determined from the determined edge. The method can then proceed to step 510.

[0045] In step 510, chipping defects in at least a portion of the diced wafer are measured using the respective baselines determined. Method 500 can then be performed.

[0046] In some embodiments of this principle, method 500 may further include applying a machine learning model to the determined chipping measurements to determine whether the diced wafer contains significant defects.

[0047] As shown in Figure 1, embodiments of the wafer chipping inspection system of this principle, such as the wafer chipping inspection system 100 in Figure 1, can be implemented in a computing device 600 based on this principle. That is, in some embodiments, wafer image data and similar data can be transmitted to the wafer chipping inspection system of this principle using the computing device 600, for example, via any input / output means associated with the computing device 600. Chipping measurement data associated with the wafer chipping inspection system of this principle can be presented to the user using an output device of the computing device 600, such as a display, printer, or any other form of output device.

[0048] For example, Figure 6 shows a high-level block diagram of a computing device 600 suitable for use with embodiments of wafer chipping inspection systems based on this principle, such as the wafer chipping inspection system 100 of Figure 1. In some embodiments, the computing device 600 can be configured to implement the method of this principle in various embodiments as a processor-executable program instruction 622 (e.g., a program instruction executable by the processor 610).

[0049] In the embodiment shown in Figure 6, the computing device 600 includes one or more processors 610a to 610n coupled to system memory 620 via an input / output (I / O) interface 630. The computing device 600 further includes a network interface 640 coupled to the I / O interface 630, and one or more input / output devices 650, such as a cursor control device 660, a keyboard 670, and a display 680. In various embodiments, a user interface may be generated and displayed on the display 680. In some cases, the embodiment can be implemented using a single specific example of the computing device 600, while in other embodiments, it is intended that multiple such systems, or multiple nodes constituting the computing device 600, may be configured to host different parts or specific examples of various embodiments. For example, in one embodiment, several elements may be implemented via one or more nodes of the computing device 600, separate from the nodes implementing the other elements. In another example, multiple nodes may implement the computing device 600 in a distributed manner.

[0050] In different embodiments, the computing device 600 may be any of various types of devices, including but not limited to personal computer systems, desktop computers, laptops, notebooks, tablet or netbook computers, mainframe computer systems, handheld computers, workstations, network computers, cameras, set-top boxes, mobile devices, consumer devices, video game consoles, handheld video game devices, application servers, storage devices, peripheral devices (such as switches, modems, and routers), or any type of computing device or electronic device in general.

[0051] In various embodiments, the computing device 600 may be a uniprocessor system including one processor 610, or a multiprocessor system including several processors 610 (e.g., two, four, eight, or another appropriate number). The processors 610 can be any suitable processor capable of executing instructions. For example, in various embodiments, the processors 610 may be general-purpose processors or embedded processors implementing any of various instruction set architectures (ISAs). In a multiprocessor system, each of the processors 610 may, but does not necessarily, implement the same ISA.

[0052] The system memory 620 can be configured to store program instructions 622 and / or data 632 accessible by the processor 610. In various embodiments, the system memory 620 can be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash memory, or any other type of memory. In the exemplary embodiment, program instructions and data that implement any of the elements of the embodiments described above can be stored in the system memory 620. In other embodiments, program instructions and / or data can be received, transmitted, or stored by a different type of computer-accessible medium or similar medium separate from the system memory 620 or computing device 600.

[0053] In one embodiment, the I / O interface 630 can be configured to coordinate I / O traffic between the processor 610, the system memory 620, and any peripheral devices in the device, including other peripheral interfaces such as the network interface 640 or input / output device 650. In some embodiments, the I / O interface 630 can perform any necessary protocol conversion, timing conversion, or other data conversion to convert data signals from one component (e.g., the system memory 620) into a format suitable for use by another component (e.g., the processor 610). In some embodiments, the I / O interface 630 may include supports for devices attached via various types of peripheral buses, such as the Peripheral Component Interconnect (PCI) bus standard or a variant of the Universal Serial Bus (USB) standard. In some embodiments, the functionality of the I / O interface 630 can be divided into two or more separate components, such as a northbridge and a southbridge. Also, in some embodiments, some or all of the functionality of the I / O interface 630, such as the interface with the system memory 620, may be directly integrated into the processor 610.

[0054] The network interface 640 can be configured to allow data to be exchanged between the computing device 600 and other devices attached to a network (e.g., network 690), such as one or more external systems, or between nodes of the computing device 600. In various embodiments, network 690 can include, but is not limited to, one or more networks, including, a local area network (LAN) (e.g., Ethernet or an enterprise network), a wide area network (WAN) (e.g., the Internet), a wireless data network, any other electronic data network, or some combination thereof. In various embodiments, the network interface 640 can support communication over, for example, a wired or wireless general-purpose data network, such as any suitable type of Ethernet network; over a digital fiber optic communication network; over a storage area network such as a Fibre Channel SAN; or over any other suitable type of network and / or protocol.

[0055] In some embodiments, the input / output device 650 may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other device suitable for inputting or accessing data by one or more computer systems. Multiple input / output devices 650 may reside within a computer system or be distributed across various nodes of the computing device 600. In some embodiments, similar input / output devices may be isolated from the computing device 600 and may interact with one or more nodes of the computing device 600 via wired or wireless connections, such as through a network interface 640.

[0056] Those skilled in the art will understand that computing device 600 is merely illustrative and does not limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the functions shown in various embodiments, including computers, network devices, internet equipment, PDAs, wireless telephones, pagers, and the like. Computing device 600 may also be connected to other devices not illustrated, or it may instead operate as a standalone system. In addition, the functions provided by the illustrated components may, in some embodiments, be integrated into fewer components or distributed among additional components. Similarly, in some embodiments, some functions of the illustrated components may not be provided, and / or other additional functions may be available.

[0057] Computing device 600 can communicate with other computing devices based on various computer communication protocols, such as Wi-Fi, Bluetooth® (and / or other standards for exchanging data over short distances, including protocols that use short-wavelength wireless transmission), USB, Ethernet, cellular, and ultrasonic local area communication protocols. Computing device 600 may also include a web browser.

[0058] Although the computing device 600 is represented as a general-purpose computer, it is programmed to perform various specialized control functions and is configured to operate as a specialized, dedicated computer according to the present principle. Embodiments can be implemented in hardware, for example, as an application-specific integrated circuit (ASIC). Therefore, the process steps described herein are intended to be broadly interpreted as being equivalently implemented by software, hardware, or a combination thereof.

[0059] Figure 7 is a high-level block diagram of a network to which embodiments of the wafer chipping inspection system of this principle can be applied, such as the wafer chipping inspection system 100 of Figure 1. The network environment 700 in Figure 7 exemplifies a user domain 702 including a user domain server / computing device 704. The network environment 700 in Figure 7 further includes a computer network 706 and a cloud environment 710 including a cloud server / computing device 712.

[0060] In the network environment 700 of Figure 7, a wafer chipping inspection system based on this principle, such as the wafer chipping inspection system of Figure 1, may be included in at least one of the user domain server / computing device 704, the computer network 706, and the cloud server / computing device 712. That is, in some embodiments, a user can use a local server / computing device (e.g., user domain server / computing device 704) to detect and measure chipping defects in diced wafers using this principle.

[0061] In some embodiments, a user can implement a system for detecting and measuring chipping defects in diced wafers according to this principle on a computer network 706. Alternatively, or additionally, in some embodiments, a user can implement a system for detecting and measuring chipping defects in diced wafers on a cloud server / computing device 712 in a cloud environment 710 to provide container forensics according to this principle. For example, in some embodiments, it may be advantageous to implement the processing functions of this principle in the cloud environment 710 in order to utilize the processing and storage capabilities of the cloud environment 710. In some embodiments of this principle, a system for detecting and measuring chipping defects in diced wafers can be located in one and / or more locations / servers / computers to perform all or part of the functions of the system according to this principle as described herein. For example, a wafer chipping inspection system according to this principle can be located in one or more of the user domain 702, the computer network environment 706, and the cloud environment 710 to detect and measure chipping defects in diced wafers according to this principle.

[0062] Those skilled in the art will understand that, although various items are illustrated as being stored in memory or storage while in use, these items or parts thereof may be transferred between memory and other storage devices for the purposes of memory management and data integrity. Alternatively, in other embodiments, some or all of the software components in memory may be executed in the memory of another device and communicate with the illustrated computer system via intercomputer communication. Some or all of the system components or data structures may also be stored in computer-accessible media or portable devices read by a suitable drive (e.g., as instructions or structured data), various examples of which are described above. In some embodiments, instructions stored in computer-accessible media separate from the computing device 600 may be transmitted to the computing device 600 via a transmission medium or via signals such as electrical, electromagnetic, or digital signals transmitted by a communication medium such as a network and / or wireless link. Various embodiments may further include storing instructions and / or data to be performed in accordance with the foregoing description in computer-accessible media, or receiving and transmitting them via a communication medium. Generally, computer-accessible media may include storage or memory media such as magnetic or optical media (e.g., disks or DVD / CD-ROMs) and volatile or non-volatile media such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), ROM, etc.

[0063] The methods and processes described herein can be implemented in software, hardware, or a combination thereof in different embodiments. In addition, the order of the methods can be changed, and various elements can be added, rearranged, combined, omitted, or otherwise modified. All examples described herein are presented non-limitingly. Various modifications and changes are possible, as will be apparent to those skilled in the art who benefit from this disclosure. Embodiments according to embodiments are described in relation to specific embodiments. These embodiments are illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Thus, multiple specific examples may be provided with respect to the components described herein as a single specific example. The boundaries between various components, operations, and data storage devices are somewhat arbitrary, and certain operations are illustrated in relation to specific exemplary configurations. Other assignments of functions are assumed and may fall within the scope of the appended claims. Structures and functions presented as individual components of exemplary configurations can be implemented as combined structures or components. These, and other variations, modifications, additions, and improvements may fall within the scope of embodiments as defined in the appended claims.

[0064] The preceding description includes numerous specific details, examples, and scenarios to provide a more complete understanding of the disclosure. However, it should be understood that embodiments of the disclosure can be practiced without such specific details. Furthermore, such examples and scenarios are presented for illustrative purposes only and are not intended to limit the disclosure. Those skilled in the art should be able to perform the appropriate functions without unnecessary experimentation based on the included description.

[0065] In this specification, references to "one embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in relation to an embodiment, it is considered within the knowledge of those skilled in the art that such feature, structure, or characteristic will be affected in relation to other embodiments, whether or not it is explicitly shown.

[0066] Embodiments provided in this disclosure can be implemented in hardware, firmware, software, or any combination thereof. Embodiments can also be implemented as instructions stored using one or more machine-readable media, which can be read and executed by one or more processors. The machine-readable media can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device, or a “virtual machine” operating on one or more computing devices). For example, the machine-readable media can include any suitable form of volatile or non-volatile memory.

[0067] The modules, data structures, and similar entities defined herein are defined so for the sake of ease of discussion and do not imply that details of any particular embodiment are required. For example, any of the modules and / or data structures described may be combined or divided into submodules, subprocesses, or other units of computer code or data, as may be required by a particular design or embodiment.

[0068] Drawings may show a specific arrangement or order of diagrammatic elements for ease of explanation. However, a specific order or arrangement of such elements does not imply that a specific order or sequence of operations, or separation of processes, is required in all embodiments. Generally, diagrammatic elements used to represent instruction blocks or modules can be implemented using any suitable form of machine-readable instruction, each such instruction can be implemented using any suitable programming language, library, application programming interface (API), and / or other software development tools or frameworks. Similarly, diagrammatic elements used to represent data or information can be implemented using any suitable electronic arrangement or data structure. Furthermore, some connections, relationships, or combinations between elements may be simplified or omitted in the drawings so as not to obscure this disclosure.

[0069] While the above applies to embodiments of the Disclosure, other further embodiments of the Disclosure can be conceived without departing from the basic scope of the Disclosure.

Claims

1. A method for automatic detection and measurement of chipping defects on a diced wafer, Receiving an image of at least a portion of the diced wafer, Aligning the received image of at least a portion of the diced wafer, Determining the edges of at least a portion of the diced wafer as represented in the aligned received image, From the determined edge, at least one baseline for measuring chipping defects in at least a portion of the diced wafer is automatically determined, Using at least one determined baseline for each of the chipped wafers, measure the chipping defects in at least a portion of the wafer. Methods that include...

2. The method according to claim 1, further comprising aligning the received image along the vertical axis.

3. The method according to claim 1, further comprising aligning the received image along the horizontal axis.

4. Determining the reference axis, Aligning the received image along the determined reference axis and The method according to any one of claims 1 to 3, further comprising:

5. The method according to any one of claims 1 to 4, further comprising measuring the chipping defect as the distance from each of the determined baselines to the edge of the chipping defect.

6. Applying a machine learning model to the measured chipping defects to determine whether critical defects are present on the diced wafer. The method according to any one of claims 1 to 5, further comprising:

7. The method according to claim 6, wherein the machine learning model is trained to recognize measured chipping defects that result in a critical defect in the diced wafer.

8. An apparatus for automatic detection and measurement of chipping defects on a diced wafer, Processor and The memory coupled to the aforementioned processor and The memory includes, and internally stores at least one of the programs or instructions that can be executed by the processor. Receiving an image of at least a portion of the diced wafer, Aligning the received image of at least a portion of the diced wafer, Determining the edges of at least a portion of the diced wafer represented in the aligned received image, From the determined edge, automatically determine at least one baseline for measuring chipping defects in at least a portion of the diced wafer. Using the at least one determined baseline, measure the chipping defects in at least a portion of the diced wafer. An apparatus configured to perform the above-mentioned function.

9. The apparatus according to claim 8, wherein the received image is aligned along the vertical axis.

10. The apparatus according to claim 8, wherein the received image is aligned along the horizontal axis.

11. The aforementioned device Determining the reference axis and Aligning the received image along the determined reference axis and The apparatus according to any one of claims 8 to 10, further configured to do the following.

12. The apparatus according to any one of claims 8 to 11, wherein the chipping defect is measured as the distance from each of the determined baselines to the edge of the chipping defect.

13. The aforementioned device A machine learning model is applied to the measured chipping defects to determine whether critical defects are present on the diced wafer. The apparatus according to any one of claims 8 to 12, further configured as follows.

14. The apparatus according to claim 13, wherein the machine learning model is trained to recognize measured chipping defects that result in serious defects in the diced wafer.

15. A system for automatic detection and measurement of chipping defects on a diced wafer, An image acquisition device for capturing an image of at least a portion of a diced wafer, It is a device, Processor, and Memory that internally stores at least one program Apparatus and The program comprises, and the at least one program includes an instruction, which, when executed by the processor, the system To capture an image of at least a portion of the diced wafer, Aligning the captured image of at least a portion of the diced wafer, Determining the edges of at least a portion of the diced wafer as represented in the aligned received image, From the determined edge, at least one baseline for measuring chipping defects in at least a portion of the diced wafer is automatically determined, Using at least one determined baseline for each of the chipped wafers, measure the chipping defects in at least a portion of the wafer. A system that implements methods including those mentioned above.

16. The method described above is Aligning images captured along at least one of the vertical or horizontal axes. The system according to claim 15, further comprising:

17. The method described above is Determining the reference axis, Aligning the captured image along the determined reference axis and The system according to claim 15, further comprising:

18. The method described above is The chipping defect is measured as the distance from each of the determined baselines to the edge of the chipping defect. The system according to any one of claims 15 to 17, further comprising:

19. The method described above is Applying a machine learning model to the measured chipping defects to determine whether critical defects are present on the diced wafer. The system according to any one of claims 15 to 18, further comprising:

20. The system according to claim 19, wherein the machine learning model is trained to recognize measured chipping defects that result in serious defects in the diced wafer.

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