TDC and FPGA including the same that can increase time resolution

Abstract

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

Description

Technical Field

[0001] The present invention relates to a technology for a TDC of an FPGA, and particularly relates to a TDC technology capable of enhancing time resolution.

Background Art

[0002] A TDC (Time-to-Digital Converter) is a device or circuit that converts the time interval between two events into a digital output. The TDC plays an important role in many scientific and industrial application fields that require precise timing measurement. It is widely used in application fields that require high-precision timing measurement, such as time-of-arrival (TOF) measurement in particle physics, medical imaging, radar systems, and laser distance measurement. The TDC operates by measuring the time difference between two events, such as the arrival of a signal or the transmission and reflection of a signal, at two points within a circuit. Generally, a counter is used to count the number of clock cycles between two events. Then, the count is converted into a digital output indicating the time interval. There are various types of TDCs, such as rising-edge TDCs, falling-edge TDCs, and interpolating TDCs. A rising-edge TDC measures the time between the rising edge of a start signal and the rising edge of a stop signal, and a falling-edge TDC measures the time between the falling edge of a start signal and the falling edge of a stop signal. An interpolating TDC estimates the time interval between two clock cycles using interpolation techniques to increase the resolution of the TDC.

[0003] TDC can be implemented using ASICs (Application-Specific Integrated Circuits), MCUs (Microcontrollers), PSoCs (Programmable System-on-Chip), DSPs (Digital Signal Processors), FPAAs (Field Programmable Analog Arrays), TACs (Time-to-Amplitude Converters), TFCs (Time-to-Frequency Converters), and FPGAs (Field Programmable Gate Arrays), among others.

[0004] When implementing TDC using an FPGA, the following problems may arise: Firstly, the resources provided to the FPGA, including logic cells, lookup tables (LUTs), and routing channels, are limited, which can limit the resolution and accuracy of the TDC implemented in the FPGA. Secondly, at high clock frequencies, jitter can introduce errors in TDC measurements. Here, jitter refers to fluctuations in the timing of the clock signal caused by factors such as noise and temperature. Thirdly, factors such as voltage drop, temperature changes, and differences in the manufacturing process can cause the TDC to behave non-linearly, resulting in errors in TDC measurements at high resolution. Fourthly, delays occur in FPGAs through signal processing and routing, and such delays can introduce errors in TDC measurements, especially at small time intervals.

[0005] Routing in FPGAs refers to the process of connecting programmable logic elements (e.g., lookup tables, flip-flops, and multiplexers) on a chip to form a desired logic circuit. Routing determines how signals propagate through the chip and can significantly impact the overall performance of the design. One of the main factors causing delay in FPGA routing is the capacitance of the interconnect wires that connect the logic elements. As the number of logic elements and the distance between them increases, the capacitance of the interconnect wires also increases. This capacitance can delay signal propagation through the wires, increasing the overall delay of the design. Another factor causing delay in FPGA routing is routing congestion. Routing congestion occurs when the FPGA's routing resources are limited and there are many logic elements that need to be connected. Routing congestion can cause delay because it increases the distance between logic elements and increases the capacitance of the interconnect wires.

[0006] A tapped delay line is a digital signal processing technique used to implement thermometer codes. In a thermometer code, each bit of a binary number is represented by a separate signal line, with the line corresponding to the "on" bit representing the binary value. To implement a thermometer code using a tapped delay line, a series of delay elements representing each bit are used. The input binary number is converted into a series of pulses, each pulse representing one bit of the binary number. These pulses are delayed by a different amount depending on the position of each bit before being fed into the tapped delay line. At the output of the tapped delay line, each output signal line represents a bit of the binary number, and the "on" line represents the binary value. This technique is commonly used in digital-to-analog converters (DACs) to convert digital signals to analog signals.

[0007] In FPGAs, a carry chain block is a hardware block used to perform high-speed arithmetic operations, particularly addition and subtraction. Addition and subtraction of multi-bit numbers in digital circuits require the calculation of carry bits, which can become a bottleneck in high-speed operations. Carry chain blocks efficiently handle such carry bit calculations, enabling faster and more efficient arithmetic operations. A carry chain block typically consists of a sequence of full adder circuits interconnected in a specific manner to form a carry chain. Each full adder circuit calculates one bit of its output and the carry bit to be propagated to the next stage in the chain. By chaining such full adder circuits, the carry bits propagate through the chain during a single clock cycle, enabling high-speed addition and subtraction of multi-bit numbers. Carry chain blocks can be used not only to provide high-speed arithmetic operations but also to implement counters and other sequential circuits that require carry bit calculations.

[0008] A timing report tool is a software tool used to analyze the timing performance of a design implemented on an FPGA. This tool generates a report that provides information about the design's timing characteristics. This report includes information about the design's timing characteristics, including data path delay, critical path, setup and hold times, clock skew, and maximum operating frequency. The data path delay mentioned above is the time it takes for a data signal to propagate through the logic elements of the FPGA.

[0009] A multiplexer, abbreviated as "MUX," is an electronic circuit that selects one of several input signals and transmits the selected input to an output line. The input-output structure of a multiplexer generally consists of multiple input lines, a selection line, and one or more output lines. The number of input lines corresponds to the number of input signals the multiplexer can select, and the selection line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a selection line that determines which of the four input signals to send to the output. The selection line may be controlled by a binary code indicating the selected input line. Multiplexers are frequently used in digital systems to reduce the number of wires required to transmit data and control signals. They can be used to implement functions such as data selectors, memory address decoders, and bus assignment circuits. [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] The present invention aims to provide a time-to-time converter (TDC) capable of correcting errors due to jitter and improving time resolution, and an FPGA including the TDC. [Means for solving the problem]

[0011] According to one aspect of the present invention, the provided FPGA(1) is programmed to include a first delay line section(20) to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input; a code conversion section(30) that converts the order of the elements of a thermometer code output by the first delay line section and outputs it; and a calculation section(60) that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is an arrangement of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops (FFs) included in the first delay line section.

[0012] In this case, the FPGA(1) is programmed to further include a second delay line section to which the input pulse is input, and the code conversion section is configured to align and combine the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, wherein the predetermined second criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section and the second delay line section.

[0013] In this case, the FPGA(1) may be programmed to further include an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting unit (40) that counts the number of clock pulses that occur during the duration of the input pulse; and a calculation unit that determines the value of the generation time difference using a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses, and the number of counted clock pulses.

[0014] According to another aspect of the present invention, the provided FPGA is programmed to include: a plurality of delay line sections to which input pulses having a width equal to the time difference between the occurrence of a start signal and an end signal are input; a code conversion section that combines a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that uses the conversion code to determine the occurrence time difference, wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

[0015] In this case, the FPGA may be programmed to further include an input signal generation unit that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting unit that counts the number of clock pulses that occur during the duration of the input pulse; and a calculation unit that determines the value of the generation time difference using a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses, and the number of counted clock pulses.

[0016] According to one aspect of the present invention, a non-volatile recording medium readable by a provided electronic device may record a binary file containing configuration data that programmed the FPGA to implement a digital circuit including: a first delay line section (20) to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input; a code conversion section (30) that converts and outputs the order of the elements of a thermometer code output by the first delay line section; and a calculation section (60) that determines the occurrence time difference using the converted code output by the code conversion section. In this case, the converted code is an arrangement of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops (FFs) included in the first delay line section.

[0017] In this case, the digital circuit further includes a second delay line section to which the input pulse is input, and the code conversion section is configured to align and combine the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, wherein the predetermined second criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section and the second delay line section.

[0018] In this case, the digital circuit may further include an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting unit (40) that counts the number of clock pulses generated during the duration of the input pulse; and a calculation unit that determines the value of the generation time difference using the number of counted clock pulses, a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the generated clock pulses.

[0019] According to another aspect of the present invention, a non-volatile recording medium readable by a provided electronic device may record a binary file containing configuration data that programmed the FPGA to implement a digital circuit comprising: a plurality of delay line sections to which input pulses having a width equal to the time difference between the occurrence of a start signal and an end signal are input; a code conversion section that combines a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that determines the occurrence time difference using the conversion code. In this case, the conversion code is an arrangement of the elements of the plurality of thermometer codes according to a predetermined criterion, the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

[0020] According to one aspect of the present invention, the provided TDC system may include a PCB board (600) containing the aforementioned FPGA (1); and a computing device (700) for acquiring the generated time difference from the PCB board. [Effects of the Invention]

[0021] According to the present invention, it is possible to provide a TDC that can correct errors due to jitter and improve time resolution, and an FPGA including the TDC.

Brief Description of Drawings

[0022] FIG. 1 shows a configuration diagram of an FPGA according to an embodiment of the present invention.

[0023] FIG. 2 is a diagram for explaining an input pulse input to a first delay line unit according to an embodiment of the present invention.

[0024] FIG. 3 shows a configuration of a first delay line unit according to an embodiment of the present invention.

[0025] FIG. 4 is a diagram for explaining the index of the buffer in FIG. 3.

[0026] FIG. 5 shows a table for explaining a data path delay according to an embodiment of the present invention.

[0027] FIGS. 6A and 6B are configured by arranging a plurality of delay line units in parallel according to an embodiment of the present invention.

[0028] FIG. 7A shows the configurations of the first delay line unit and the second delay line unit in FIG. 6B, and FIG. 7B is for explaining the operation of the code conversion unit when two delay line units are used according to an embodiment of the present invention.

[0029] FIG. 8 shows a graph of the delay depending on the presence or absence of application of the code conversion unit according to an embodiment of the present invention.

[0030] FIG. 9 is a diagram for explaining the array reference of the flip-flop output value depending on the presence or absence of application of the code conversion unit and the increase value of the number of taps in FIG. 8 according to an embodiment of the present invention.

[0031] Figure 10 is a block diagram of a TDC system provided according to one embodiment of the present invention. [Modes for carrying out the invention]

[0032] Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and can be embodied in various other forms. The terms used herein are for the purpose of aiding the understanding of the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular nouns used herein also include plural nouns unless the context clearly indicates the opposite.

[0033] Figure 1 shows a diagram of the FPGA configuration according to one embodiment of the present invention.

[0034] Figure 2 is a diagram illustrating the input pulse input to the first delay line section according to one embodiment of the present invention.

[0035] The following explanation will refer to both Figure 1 and Figure 2.

[0036] The FPGA(1) may include an input signal generation unit (10), a first delay line unit (20), a code conversion unit (30), a clock pulse count unit (40), a priority encoder unit (50), and a calculation unit (60).

[0037] Specifically, the FPGA(1) configuration described above could be a TDC (Time to Digital converter) configuration.

[0038] As shown in Figure 2, the input signal generation unit (10) can generate an input pulse (P1) whose width is the time difference (T) between the rising edge (E1) of a predetermined given start signal (S1) and the rising edge (E2) of a predetermined given end signal (S2). The input signal generation unit (10) can be composed of logic gates necessary for the above generation.

[0039] The first delay line section (20) can receive an input pulse (P1) having a width equal to the time difference (T) between the start signal (S1) and the end signal (S2). The first delay line section (20) can output a thermometer code (O1). In this case, the thermometer code is, for example, an 8-bit value composed of the output values ​​of the flip-flops included in the first delay line section (20), and the output value of each flip-flop can be referred to as an element of the thermometer code.

[0040] Figure 3 shows the configuration of the first delay line section according to one embodiment of the present invention.

[0041] Figure 4 is a diagram illustrating the buffer index in Figure 3.

[0042] The first delay line section (20) may include a delay line (D_L) containing a plurality of buffers (delay elements) (B), and D-flip-flops (FF) tapped to the output terminals of each buffer (B) of the delay line.

[0043] Multiple buffers can be connected in a cascade delay configuration. That is, the multiple buffers can be arranged in the order in which the input pulse (P1) flows.

[0044] The waveform (Signal) of the input pulse (P1) in Figure 3 can be output at the output terminals of each buffer (B) with a predetermined delay. That is, the output value of the first buffer (B1) is output at the output terminal of the first buffer (B1) with a predetermined delay, and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value of the first buffer (B1) (for example, "1") can also be input to the first flip-flop (FF1).

[0045] In this case, data path delays can occur between each buffer (B) and through the flip-flops (FF). For example, a delay of d1 may occur before the input value ("1") of the first buffer (B1) is transmitted to the second buffer (B2), and a delay of d11 may occur before the output value ("1") of the first buffer (B1) is transmitted to the first flip-flop (FF1). Similarly, a delay occurs each time data is transmitted from the previous buffer to the next buffer, and a delay occurs each time data is transmitted from any buffer to a flip-flop connected to that buffer.

[0046] Figure 4 is a diagram illustrating the buffer index according to one embodiment of the present invention.

[0047] Each field in the table in Figure 4 represents the buffer name, index, and output value of the buffer.

[0048] Each buffer may be assigned an index that defines the order of the buffers. For example, the first buffer (B1) may be assigned index "1", the second buffer (B2) may be assigned index "2", and similarly the eighth buffer (B8) may be assigned index "8". In this way, if each buffer (B) is arranged in the order in which the input pulse (P1) flows, and the indices are arranged according to that order, then for example, 1000 buffers may each be assigned an index from 1 to 1000.

[0049] Figure 5 shows a table illustrating data path delay according to one embodiment of the present invention.

[0050] Referring to Figures 1 and 5, the code conversion unit (30) can convert the order of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line unit (20) and output it. At this time, the code output by the code conversion unit (30) (e.g., 11010000) (the order of the indices in the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) can be called the "converted code (CO1)".

[0051] The converted code (CO1) output by the code conversion unit (30) may be an arrangement of the elements of the thermometer code (O1) according to a predetermined criterion. In this case, the predetermined criterion may be the data path delay from the output node (N1) of the input pulse (P1) to the output node (N2) of each of the multiple flip-flops (FF) included in the first delay line unit (20). This will be explained in detail with reference to Figure 5.

[0052] Each field in the table shown in Figure 5 can represent the buffer index number, the value of the first delay, the value of the second delay, and the sum value (rank). In this case, the rank can represent the rank relative to the overall sum value. In this case, the buffer with the smallest sum value can have rank 1, and the buffer with the highest sum value can have the last rank. Alternatively, in other embodiments, the reverse is also possible.

[0053] As described above in Figure 3, the sum value may represent the time it takes for data to be transmitted from the node (N1) where the input pulse (P1) is output to any flip-flop (e.g., FF4).

[0054] A first delay may occur, which is the time it takes for the input value of any buffer to be transmitted to another buffer adjacent to the buffer, and a second delay may occur, which is the time it takes for the output value of the buffer to be transmitted as the input to a flip-flop connected to the buffer.

[0055] In this case, the sum of the first delay value and the second delay value for each buffer can be called the data path delay.

[0056] Referring to both Figures 3 and 5, when the indices of each buffer are arranged in order, the rank of the sum of the values ​​of the first and second delays may differ from the rank of the index numbers of each buffer. For example, in the case of the third buffer, the buffer array rank is 3, so the index number is "3", but the rank of the sum may be "5". Looking at it in detail, in order for data to be transmitted to the third flip-flop (FF3), it must pass through the first buffer (B1), the second buffer, and the third buffer. At this time, a predetermined delay (d1, d2, d3) occurs each time the data passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur before the data output from the third buffer (B3) is output as the output value of the third flip-flop (FF3). In other words, the delay from the output node (N1) of the input pulse (P1) to the output nodes (N2, N23) of the third flip-flop (FF3) can be the sum of d1, d2, d3, and d13.

[0057] In this way, the delay (i.e., the sum) until data is transmitted to the output node of each flip-flop (FF3) can be calculated.

[0058] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3, and the buffer index for the fourth flip-flop (FF4) is 4. That is, even though the fourth flip-flop (FF4) must pass through one more buffer than the third flip-flop (FF3), the total delay value up to the output node of the third flip-flop, which has a buffer index of 3, may be greater.

[0059] The code conversion unit (30) can convert the order of the elements of the thermometer code (O1) based on the calculated delay (sum value) (for example, in ascending order of sum value).

[0060] The converted code (CO1) output by the code conversion unit (30) can be provided to the priority encoder unit (50).

[0061] The priority encoder unit (50) can digitize long thermometer codes. For example, the priority encoder unit (50) can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if there are 5200 buffers (delay elements) (B) and 5200 flip-flops (FFs) connected to the buffer as shown in Figure 3, a sequence of 5200 consecutive binary numbers will be output, which can be represented as a 13-bit binary number.

[0062] In other words, the priority encoder unit (50) can represent a 5200-bit first thermometer code (TC1) and a second thermometer code (TC2) as 13-bit binary numbers, as output values ​​(CO1) corresponding to the time of the code conversion unit (30).

[0063] Referring to Figure 2, the first thermometer code (TC1) may be the code output by the code conversion unit (30) in relation to the rising edge of the input pulse (P1) at the time of the rising edge (E4) of the first clock pulse (CK2) that occurred after the rising edge (E1) of the input pulse (P1) among the generated clock pulses (CK). The first thermometer code (TC1), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0064] The second thermometer code (TC2) may be the code output by the code conversion unit (30) in relation to the falling edge (E2) of the input pulse (P1) at the rising edge (E6) of the first clock pulse (CK4) that occurred after the falling edge (E2) of the input pulse (P1). The second thermometer code (TC2), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0065] In this case, the time intervals of the first thermometer code (TC1) and the second thermometer code (TC2) may be smaller than the period of the clock pulse (CK).

[0066] Referring again to Figures 1 and 2, the clock pulse counting unit (40) can receive an input pulse (P1) from the input signal generation unit (10).

[0067] The clock pulse counting unit (40) can count the number of clock pulses (CK) that occur during the duration (T) of the input pulse (P1). For example, in Figure 2, since there are two rising edges of the clock pulses that occur during the period when the input pulse (P1) is ON, such as edges (E4, E5), the counted value may be 2.

[0068] The output value (coarse count) of the clock pulse counting unit (40), that is, the counted value, can be provided to the calculation unit (60).

[0069] Referring to Figures 1 and 2, the calculation unit (60) can determine the value of the occurrence time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses. For example, the occurrence time difference may be 2*Period+TC1-TC2.

[0070] Figures 6a and 6b show an embodiment of the present invention in which multiple delay line sections are configured in parallel.

[0071] As shown in Figure 6a, two or more delay line sections (20) can be connected in parallel. In this case, the input pulse (P1) output from the input signal generation unit (10) can be input to the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24), respectively. The first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24) can then be input to the code conversion unit (30).

[0072] As shown in Figure 6b, we can consider the possibility that in another embodiment, two delay line sections (20) are connected in parallel.

[0073] For example, the input pulse (P1) output from the input signal generation unit (10) can be provided along a first path (path1) in which the output terminal of the input signal generation unit (10) and the input terminal of the first delay line unit (21) are connected to each other, and along a second path (path2) in which the output terminal of the input signal generation unit (10) and the input terminal of the second delay line unit (22) are connected to each other.

[0074] In this case, the time it takes for the input pulse (P1) output from the input signal generation unit (10) to reach the input terminal of the first delay line unit (21) and the input terminal of the second delay line unit (22) may be different. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path2). In the embodiment shown in Figure 6b, since the length of the first path (path1) is shorter than the length of the second path (path2), it can be seen that the input time interval of the input pulse (path1) through the first path (path1) is smaller than the input time interval of the input pulse (path2) through the second path (path2).

[0075] Figure 7a shows the configuration of the first and second delay line sections in Figure 6b, and Figure 7b is for explaining the operation of the code conversion section when two delay line sections are used according to one embodiment of the present invention.

[0076] For the sake of explanation, Figure 7a shows that each delay line contains four buffers and four flip-flops (tabs).

[0077] Each field in the table in Figure 7b can represent the delay line section number, buffer index number, first delay value, second delay value, first sum value (first rank), and first sum value (overall rank). In this case, the first rank can represent the rank of each sum value relative to the buffer index of the buffer in each delay line section. The overall rank can represent the rank of each sum value relative to the buffer index of all buffers in the first and second delay line sections. In this case, the buffer with the smallest sum value can have the first rank, and the buffer with the highest sum value can have the last rank. Alternatively, in other embodiments, the reverse is also possible. The method for calculating the sum value is as described in Figure 5.

[0078] The code conversion unit (30) may sort and combine the elements of a first set (for example, {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) obtained by sorting the sum of the elements of the thermometer code output by the first delay line unit (21) and the buffer index pairs in ascending order of sum, and the elements of a second set (for example, {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) obtained by sorting the sum of the elements of the thermometer code output by the second delay line unit (22) and the index pairs in ascending order of sum, to generate a single conversion code.

[0079] In other words, each element of the first set and each element of the second set can be sorted in descending order of their summation.

[0080] For example, the output values ​​based on the buffer index of the first delay line section (21) may be {1, 2, 3, 4}, and the output values ​​based on the buffer index of the second delay line section (22) may be {5, 6, 7, 8}. Furthermore, in the embodiments of Figures 6b and 7a, delay (d1) may be smaller than delay (d5). Therefore, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output values ​​of the flip-flops for each buffer index can be sorted in the sorted order. For example, the sorted values ​​(buffer indices) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0081] As described above, when multiple delay line sections (20) are used, the input delay may differ slightly depending on their arrangement. Figure 8, described below, shows the delays resulting from the arrangement when multiple delay line sections are used.

[0082] Figure 8 shows a graph of delay with and without the application of the code conversion unit according to one embodiment of the present invention.

[0083] Figure 9 is a diagram illustrating, according to one embodiment of the present invention, the arrangement criteria for flip-flop output values ​​and the increase in the number of taps in Figure 8, depending on whether or not the code conversion unit is applied.

[0084] Figure 8(a) shows a delay graph corresponding to the number of taps when the code conversion unit (30) is not applied, and Figure 8(b) shows a delay graph corresponding to the number of taps when the code conversion unit (30) is applied.

[0085] The fields in the table in Figure 9 include the sorting order, the sorting criteria for the flip-flop output values, and the sorting order of the total delay sum.

[0086] The following explanation will refer to both Figures 8 and 9.

[0087] The horizontal axis of the graph (g1, g2) represents the number of taps. Referring to Figure 7b, one tap may represent a pair of a buffer (delay element) (e.g., B1) and a flip-flop (FF1) connected to it. For example, if the total number of buffer and flip-flop pairs is 1000, then the total number of taps may be 1000.

[0088] The vertical axis of graph (g1, g2) represents the delay time (ns). This delay time may represent the sum of the delays required for data to be transmitted to the output nodes of the flip-flops tapped to each buffer as described above in Figure 5.

[0089] Referring to FIGS. 7a to 9 together, an increase in the number of taps in graph (g1) may mean, for example, an increase in the buffer index. For example, when the number of taps on the horizontal axis of graph (g1) is 4, it may mean a buffer index of 4. At this time, the delay value on the vertical axis of graph (g1) may be D4 (= d1 + d2 + d3 + d4 + d14) as shown in FIG. 7b. For example, when the number of taps is 5, it may mean a buffer index of 5. At this time, the delay value on the vertical axis of graph (g1) may be D5 (= d5 + d15) as shown in FIG. 7b. At this time, referring to FIG. 9, D4 > D5 may be true. Here, it can be known that the delay observed in each flip-flop of each tap does not increase as the index of the tap (for example, index 4 -> index 5) increases, but may locally decrease even when the index of the tap increases.

[0090] On the other hand, an increase in the number of taps in graph (g2) does not mean an increase in the buffer index, but may mean an increase in the position corresponding to the alignment order in the state where the output values of each flip-flop are aligned by the code conversion unit (30). For example, when the number of taps on the horizontal axis of graph (g2) is 4, the position order of the aligned buffer index is 1, 2, 5, 3, and it may mean a buffer index of 3. And the delay value on the vertical axis of graph (g2) in this case may be D3 (= d1 + d2 + d3 + d13). For example, when the number of taps is 5, the position order of the aligned buffer index is 1, 2, 5, 3, 6, and it may mean a buffer index of 6. And the delay value in this case may be D6 (= d5 + d6 + d16). At this time, referring to FIG. 9, D3 < D6 may be true.

[0091] In other words, as shown in Figure 8(a), when the code conversion unit (30) of the present invention is not applied, it can be seen that the graph (g1) relating to the delay associated with an increase in the number of taps does not exhibit a monotonically increasing property. On the other hand, as shown in Figure 8(b), when the code conversion unit (30) of the present invention is applied, it can be seen that the graph (g2) relating to the delay associated with an increase in the number of taps exhibits an increasing phenomenon without decrease.

[0092] For example, unlike ASICs, which are custom-ordered semiconductors, FPGAs can be directly designed through programming, allowing the chip's functionality to be changed through programming. Therefore, unlike ASICs, the functionality of each component included in an FPGA can change (or change depending on the arrangement of the components), so the delay does not always increase with each increase in the number of taps; it may decrease, and it may not even result in an increase without decrease.

[0093] However, as explained, it can be confirmed through graph (g2) that the code conversion unit (30) can correct the output of the first delay line unit (20).

[0094] As described above, when multiple delay line sections (20) are used, delay alignment can be provided through the code conversion section. As a result, errors due to jitter can be corrected, and a TDC with high time resolution can be provided. For example, when four delay line sections are configured in parallel to have a total of 9600 taps, a TDC with a resolution of 0.8 ps per tap can be provided.

[0095] Figure 10 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0096] The TDC system (1000) may include a PCB board (600) and a computing device (700).

[0097] The PCB board (600) is a device capable of digital signal processing and may include the FPGA (1), data interface (601), signal interface (602), clock generation unit (603), and power supply unit (604) described above.

[0098] The data interface (601) is a device that enables data exchange between the PCB board (600) and the computing device (700), and may, but may not be, consist of USB, Ethernet, or UART.

[0099] The signal interface (602) has the function of receiving signals from an external source that attempt to measure a time difference using the FPGA (1) and transmitting them to the FPGA (1).

[0100] The clock generation unit (603) can provide a train of clock pulses that the FPGA (1) counts.

[0101] The time difference between the two selected signals calculated by FPGA(1) can be output from FPGA(1) and provided to the data interface(601). The data interface(601) can then provide the time difference between the two signals to the computing device(700).

[0102] The power supply unit (604) supplies power used by the PCB board (600).

[0103] The computing device (700) may include a data interface (701), a CPU (702), and memory (703).

[0104] The computing device (700) may be configured to execute a predetermined algorithm based on the time difference between two selected signals received from the PCB board (600). The time difference between the two received signals may be processed by a process executed on the CPU (702). A program consisting of instructions for executing the process may be stored in memory (703). The program may be loaded from memory (703) to the CPU (702) and executed. The memory (703) may be non-volatile memory.

[0105] By utilizing the embodiments of the present invention described above, persons in the art of the present invention will be able to easily make various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other unreferenced claims to the extent that can be understood herein.

[0106] [Explanation of Symbols]

[0107] 1: FPGA

[0108] 10: Input signal generation unit

[0109] 20: First Delay Line Section

[0110] 30: Code conversion section

[0111] 40: Clock pulse counting section

[0112] 50: Priority Encoder Section

[0113] 60: Arithmetic section

[0114] 600: PCB board

[0115] 700: Computing equipment

[0116] 1000: TDC System

Claims

1. FPGA(1) is programmed to include: a first delay line section (20) to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input; a code conversion section (30) that converts the order of the elements of the thermometer code output by the first delay line section and outputs it; and a calculation section (60) that uses the converted code output by the code conversion section to determine the occurrence time difference; wherein the converted code is an arrangement of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops (FFs) included in the first delay line section.

2. The FPGA according to claim 1, further programmed to include a second delay line section to which the input pulse is input, wherein the code conversion section aligns and combines the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, wherein the predetermined second criterion is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section and the second delay line section.

3. An FPGA, characterized in that it is further programmed to include: an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting unit (40) that counts the number of clock pulses that occur during the duration of the input pulse; and a calculation unit that determines the value of the time difference of occurrence using the number of counted clock pulses; a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses.

4. The FPGA according to claim 1, wherein the FPGA is programmed to further include a plurality of delay line sections to which the input pulse is input, the plurality of delay line sections including the first delay line section, the converted code output by the code conversion section is generated by combining a plurality of thermometer codes output by the plurality of delay line sections, the converted code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined second criterion, and the predetermined second criterion is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

5. A non-volatile recording medium readable by an electronic device is recorded, which contains a binary file containing configuration data that programmed the FPGA to implement a digital circuit including: a first delay line section (20) to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input; a code conversion section (30) that converts and outputs the order of the elements of the thermometer code output by the first delay line section; and a calculation section (60) that determines the occurrence time difference using the converted code output by the code conversion section; wherein the converted code is an arrangement of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the multiple flip-flops (FFs) included in the first delay line section.

6. Claim 5, wherein the digital circuit further includes a second delay line section to which the input pulse is input, and the code conversion section is configured to align and combine the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, wherein the predetermined second criterion is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section and the second delay line section, wherein the electronically readable non-volatile recording medium is provided.

7. The digital circuit of claim 5 or 6 further comprises: an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting unit (40) that counts the number of clock pulses generated during the duration of the input pulse; and a calculation unit that determines the value of the generation time difference using the number of counted clock pulses; an electronically readable non-volatile recording medium.

8. Claim 5, a non-volatile recording medium readable by an electronic device, wherein the digital circuit includes a plurality of delay line sections to which the input pulse is input, the plurality of delay line sections includes the first delay line section, the converted code output by the code conversion section is generated by combining a plurality of thermometer codes output by the plurality of delay line sections, the converted code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined second criterion, and the predetermined second criterion is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

9. A TDC system comprising a PCB board (600) including an FPGA (1) according to any one of claims 1 to 4; and a computing device (700) for acquiring the generated time difference from the PCB board.

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