Wafer cleaning apparatus and cleaning method using the same

Abstract

The wafer cleaning apparatus of the present invention includes: a cleaning tank containing a cleaning solution and wafers to be cleaned; a plurality of megasonic diaphragms provided in the cleaning tank for generating megasonics; a lift unit for stacking wafers and housing the stacked wafers in the cleaning tank, or for lifting wafers housing in the cleaning tank; and a processor for controlling the lift unit and the plurality of megasonic diaphragms, and controlling the plurality of megasonic diaphragms differently in correspondence with at least one lift section in which the wafers are lifted.

Description

Technical Field

[0001] The present invention relates to a wafer cleaning apparatus and a cleaning method thereof, and more particularly to an abnormal pattern control occurring in a drying process after cleaning in wet cleaning and a wafer cleaning apparatus capable of ensuring a uniform quality level.

Background Art

[0002] Generally, wafers are produced as wafers for semiconductor device manufacturing through a series of processes such as a slicing process, a grinding process, a lapping process, an etching process, and a polishing process. At this time, the surface of the wafer is contaminated by various contaminants as the process progresses. Typical contaminants include fine particles, organic contaminants, metal contaminants, etc., and these contaminants cause a decrease in the production yield of semiconductor devices. Therefore, in order to remove these contaminants, generally, a wet cleaning process using an etching solution such as an acid or an alkali or deionized water is performed.

[0003] FIG. 1 is a diagram for explaining a conventional wet cleaning apparatus.

[0004] Referring to FIG. 1, generally, a batch type wet cleaning apparatus serves to remove contaminants such as particles, organic substances, and metal contaminants present on the surface of the wafer 10 using appropriate chemicals such as SC1 (Standard Cleaning-1) and SC2 (Standard Cleaning-2).

[0005] As shown in FIGS. 1(a) and (b), even if particles are easily removed using an appropriate chemical, when the wafer 10 comes out of the bath, if the meniscus between the surface of the wafer 10 and the solution in the bath is not properly maintained, the problem of particle re-adsorption occurs.

[0006] In other words, if particles or suspended matter remain on the surface of the solution in the washing tank (Bath), an abnormal predetermined pattern occurs on the surface of wafer 10, even if a proper meniscus is maintained. The attributes of this pattern cause a decrease in yield in the device process as particles. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The technical problem that this invention aims to solve is to provide a wafer cleaning apparatus and a cleaning method using the same that can prevent abnormal pattern control that occurs during the drying process after cleaning in wet cleaning, and ensure a uniform quality level.

[0008] The technical problems that this invention aims to solve are not limited to those described above, and other technical problems not mentioned can be clearly understood by a person with ordinary skill in the art to which this invention belongs from the following description. [Means for solving the problem]

[0009] To solve the aforementioned technical problems, the wafer cleaning apparatus of the present invention includes: a cleaning tank containing a cleaning solution and wafers to be cleaned; a plurality of megasonic diaphragms provided in the cleaning tank for generating megasonics; a lift unit for stacking the wafers and housing the stacked wafers in the cleaning tank, or for lifting the wafers housing the cleaning tank; and a processor for controlling the lift unit and the plurality of megasonic diaphragms, and controlling the plurality of megasonic diaphragms differently in correspondence with at least one lift section in which the wafers are lifted.

[0010] Furthermore, the plurality of megasonic diaphragms may include a first megasonic diaphragm provided on the lower surface of the cleaning tank; a second megasonic diaphragm provided on the outer surface of the cleaning tank; and a third megasonic diaphragm provided on the outer surface of the cleaning tank and spaced apart from the second megasonic diaphragm at a predetermined distance.

[0011] Furthermore, the at least one lift section may include: a first lift section in which the entire wafer is housed in the cleaning tank; a second lift section from the first lift section onward in which the wafer is housed in the cleaning tank up to a first portion of the wafer; a third lift section from the second lift section onward in which the wafer is housed in the cleaning tank up to a second portion of the wafer; and a fourth lift section from the third lift section onward in which the wafer is not housed in the cleaning tank.

[0012] Furthermore, the processor may control the first megasonic diaphragm from the second lift section to the third lift section to generate a first megasonic, and in the third lift section, control at least one of the second megasonic diaphragm and the third megasonic diaphragm to generate a second megasonic, a third megasonic, or at least one of the second megasonic and the third megasonic.

[0013] Furthermore, the processor can supply power of a specific intensity in the range of 2000 to 2400 watts (W), and control the intensity of the first megasonic, the second megasonic, and the third megasonic as specific values.

[0014] Furthermore, according to an embodiment of the present invention, a cleaning method using a wafer cleaning apparatus comprising: a cleaning tank containing a cleaning solution and wafers to be cleaned; a plurality of megasonic diaphragms provided in the cleaning tank, each comprising a first megasonic diaphragm provided on the lower surface of the cleaning tank, a second megasonic diaphragm provided on the outer surface of the cleaning tank, and a third megasonic diaphragm provided on the outer surface of the cleaning tank and spaced apart from the second megasonic diaphragm at a predetermined distance; a lift unit for stacking the wafers and housing the stacked wafers in the cleaning tank, or for lifting the wafers housing the cleaning tank; and a processor for controlling the lift unit and the plurality of megasonic diaphragms, includes the step of controlling the plurality of megasonic diaphragms differently in correspondence with at least one lift section in which the wafers are lifted, under the control of the processor.

[0015] Furthermore, the at least one lift section includes a first lift section in which the wafer is entirely housed in the cleaning tank; a second lift section from the first lift section onward in which the wafer is housed in the cleaning tank up to a first portion of the wafer; a third lift section from the second lift section onward in which the wafer is housed in the cleaning tank up to a second portion of the wafer; and a fourth lift section from the third lift section onward in which the wafer is not housed in the cleaning tank; and the steps of controlling the plurality of megasonic diaphragms differently may include, under the control of the processor, controlling the first megasonic diaphragm from the second lift section to the third lift section to generate a first megasonic; and controlling at least one of the second megasonic diaphragm and the third megasonic diaphragm in the third lift section to generate a second megasonic, a third megasonic, or at least one of the second megasonic and the third megasonic.

[0016] Furthermore, in the step of controlling the multiple megasonic diaphragms in different ways, the processor can supply power of a specific intensity in the range of 2000 to 2400 watts (W) to control the intensity of the first megasonic, the second megasonic, and the third megasonic, each as a specific value.

[0017] The embodiments described above represent only a portion of preferred embodiments of the present invention, and various embodiments reflecting the technical features of the present invention can be derived and understood by a person ordinary in the art based on the detailed description of the present invention described below. [Effects of the Invention]

[0018] The wafer cleaning apparatus and cleaning method of the present invention described above have the following effects.

[0019] By removing abnormal patterns and other defects that occur during the drying process after wet cleaning, it is possible to ensure wafers of uniform quality.

[0020] The effects obtained from the present invention are not limited to those mentioned above, and other effects not mentioned can be clearly understood by a person with ordinary skill in the art to which the present invention pertains from the following description. [Brief explanation of the drawing]

[0021] [Figure 1] This is a diagram illustrating a conventional wet cleaning apparatus.

[0022] [Figure 2] This is a diagram illustrating a wafer cleaning apparatus according to an embodiment of the present invention.

[0023] [Figure 3] This is a diagram illustrating the raising and lowering of a wafer housed in a wafer cleaning apparatus according to an embodiment of the present invention.

[0024] [Figure 4] A diagram for explaining at least one lift section according to an embodiment of the present invention.

[0025] [Figure 5] A diagram for explaining Experiment 1 using the wafer cleaning apparatus of the present invention.

[0026] [Figure 6] A diagram for explaining Experiment 2 using the wafer cleaning apparatus of the present invention.

[0027] [Figure 7] A diagram for explaining Experiment 3 using the wafer cleaning apparatus of the present invention.

[0028] [Figure 8] A diagram for explaining Experiment 4 using the wafer cleaning apparatus of the present invention.

[0029] [Figure 9] A diagram for explaining Experiment 5 using the wafer cleaning apparatus of the present invention.

[0030] [Figure 10] A diagram for explaining Experiment 6 using the wafer cleaning apparatus of the present invention.

[0031] [Figure 11] A diagram for explaining the wafer cleaning method according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0032] Hereinafter, embodiments will be given to specifically explain the present invention, and detailed explanations will be made with reference to the accompanying drawings to assist in understanding the invention.

[0033] In drawings, dimensions are exaggerated, omitted, or shown schematically for the sake of clarity and ease of explanation. Furthermore, the dimensions of each component do not fully reflect their actual dimensions, and the same reference number indicates the same element throughout the drawing description.

[0034] Figure 2 is a diagram illustrating a wafer cleaning apparatus according to an embodiment of the present invention, and Figure 3 is a diagram illustrating the raising and lowering of a wafer housed in the wafer cleaning apparatus according to an embodiment of the present invention.

[0035] Referring to Figures 2 and 3, the wafer cleaning apparatus 100 of the present invention may include a cleaning tank 110, a plurality of megasonic diaphragms 130a, 130b, 130c, a lift unit 120, and a processor 140.

[0036] The cleaning tank 110 can contain the cleaning solution and the wafer 10 to be cleaned. The cleaning tank 110 may include an inner tank 111 and an outer tank 112. Here, the cleaning tank 110 may be referred to as a bath.

[0037] The inner tank 111 can contain the cleaning solution and the wafer 10. Although not shown, the inner tank 111 can be physically connected to a cleaning solution supply means for supplying the cleaning solution.

[0038] The outer tank 112 is positioned outside the inner tank 111 and can be used to circulate the cleaning fluid that overflows from the inner tank 111. Although not shown, the outer tank 112 can be physically connected to a discharge pipe for discharging the cleaning fluid that overflows after use, a pump for circulating the cleaning fluid, and a filter for removing contaminants from the cleaning fluid.

[0039] Multiple megasonic diaphragms 130a, 130b, and 130c can be provided in the cleaning tank 110. The multiple megasonic diaphragms 130a, 130b, and 130c can generate megasonic sounds under the control of the processor 140. For example, the multiple megasonic diaphragms 130a, 130b, and 130c may include a first megasonic diaphragm 130a, a second megasonic diaphragm 130b, and a third megasonic diaphragm 130c.

[0040] The first megasonic diaphragm 130a is electrically connected to the processor 140 and can generate the first megasonic under the control of the processor 140. Such a first megasonic diaphragm 130a can be provided on the lower surface of the washing tank 110. For example, the first megasonic diaphragm 130a may be provided on the lower surface of the outer tank 112. However, it is not limited to this, and the first megasonic diaphragm 130a may be provided on the lower interior surface of the outer tank 112.

[0041] The second megasonic diaphragm 130b is electrically connected to the processor 140 and can generate a second megasonic under the control of the processor 140. Such a second megasonic diaphragm 130b can be provided on the outer surface of the washing tank 110. For example, the second megasonic diaphragm 130b may be provided on a part of the outer surface of the inner tank 111. However, it is not limited to this, and the second megasonic diaphragm 130b may be provided on the inner surface of the inner tank 111.

[0042] The third megasonic diaphragm 130c is electrically connected to the processor 140 and can generate a third megasonic under the control of the processor 140. Such a third megasonic diaphragm 130c is provided on the outer surface of the washing tank 110, but may be provided at a predetermined distance from the second megasonic diaphragm 130b. For example, the third megasonic diaphragm 130c may be provided on a part of the outer surface of the inner tank 111 and at a predetermined distance from the second megasonic diaphragm 130b. However, it is not limited to this, and the third megasonic diaphragm 130c may be provided on the inner surface of the inner tank 111 at a predetermined distance from the second megasonic diaphragm 130b.

[0043] The first megasonic diaphragms 130a to the third megasonic diaphragms 130c described so far have been illustrated as a single diaphragm, but are not limited to this. For example, the first megasonic diaphragm 130a may include the 11th megasonic diaphragm to the 1nth megasonic diaphragm, the second megasonic diaphragm 130b may include the 21st megasonic diaphragm to the 2nth megasonic diaphragm, and the third megasonic diaphragm 130c may include the 31st megasonic diaphragm to the 3nth megasonic diaphragm. Here, n can be an integer greater than 0.

[0044] The lift unit 120 can stack wafers 10, place the stacked wafers 10 into the cleaning tank 110, or lift the wafers 10 placed in the cleaning tank 110. The lift unit 120 may include a wafer boat 122 and a lifting lever 121.

[0045] The wafer boat 122 can stack at least one or more wafers 10. The wafer boat 122 may include at least one comb. The at least one comb may be spaced apart at predetermined intervals.

[0046] The lifting lever 121 is physically connected to the wafer boat 122, allowing the wafer boat 122 to be raised and lowered. Although not shown in Figure 2, it may include a servo motor that provides power for raising and lowering the lifting lever 121. A detailed explanation of this can be sufficiently inferred from the prior art, etc., and is therefore omitted here.

[0047] The processor 140 can control the lift unit 120 and the multiple megasonic diaphragms 130a, 130b, and 130c. The processor 140 is electrically connected to the lift unit 120 and the multiple megasonic diaphragms 130a, 130b, and 130c, and can control the operation of the lift unit 120 or the operation of the multiple megasonic diaphragms 130a, 130b, and 130c.

[0048] For example, the processor 140 can control multiple megasonic diaphragms 130a, 130b, and 130c differently in correspondence with at least one lift section in which the wafer 10 stacked on the lift section 120 is lifted. A detailed explanation of this will be given later.

[0049] Figure 4 is a diagram illustrating at least one lift section according to an embodiment of the present invention.

[0050] Referring to Figure 4, at least one lift section may be set according to the width of the area in which the wafer 10 is housed in the cleaning tank 110.

[0051] For example, at least one lift section may include the first lift section T0 to the fourth lift section T3.

[0052] The first lift section T0 may be the section in which the entire wafer 10 is housed in the cleaning tank 110. The first megasonic diaphragms 130a to the third megasonic diaphragms 130c may be turned off under the control of the processor 140.

[0053] The second lift section T1 may be the section from the first lift section T0 onwards in which the wafer 10 is housed in the cleaning tank 110 up to the first portion of the wafer 10. The second lift section T1 may be the section in which the wafer 10 housed in the cleaning tank 110 is gradually lifted so that 2 / 3R of the wafer 10 is removed from the cleaning tank 110 and exposed to the outside. Here, the first portion of the wafer 10 may be the 2 / 3R portion of the wafer 10. At this time, 1 / 3R of the wafer 10 may remain housed in the cleaning tank 110. The first megasonic diaphragm 130a can be turned on under the control of the processor 140 to generate the first megasonic during the second lift section T1.

[0054] The third lift section T2 may be the section from the second lift section T1 onwards until the wafer 10 is housed in the cleaning tank 110 up to the second portion of the wafer 10. The third lift section T2 may be the section from when 1 / 3R of the wafer 10 is housed in the cleaning tank 110 until just before the wafer 10 is removed from the cleaning tank 110. Here, the second portion of the wafer 10 may be the part that comes into contact with the cleaning solution. At this time, a very small portion of the wafer 10 may be housed in the cleaning tank 110.

[0055] The first megasonic diaphragm 130a maintains a turned-on state under the control of the processor 140 and can continuously generate the first megasonic during the third lift section T2. ​​The second megasonic diaphragm 130b and the third megasonic diaphragm 130c are turned on under the control of the processor 140 and can generate the second and third megasonic during the third lift section T2. ​​However, the processor 140 can turn on only one of the second megasonic diaphragm 130b or the third megasonic diaphragm 130c to generate only one of the second or third megasonic.

[0056] The fourth lift section T3 may be a section from the third lift section T2 onward where the wafer 10 is not housed in the cleaning tank 110. The fourth lift section T3 may be a section where the entire wafer 10 is removed from the cleaning tank 110 and exposed to the outside.

[0057] The first megasonic diaphragm 130a to the third megasonic diaphragm 130c can be turned off under the control of the processor 140.

[0058] As described above, the processor 140 can control the first megasonic diaphragm 130a from the second lift section T1 to the third lift section T2 to generate a first megasonic, and in the third lift section T2, it can control at least one or more of the second megasonic diaphragm 130b and the third megasonic diaphragm 130c together with the first megasonic diaphragm 130a to generate a second megasonic and / or a third megasonic along with the first megasonic.

[0059] The processor 140 is not limited to this, and can control the first megasonic diaphragm 130a in the second lift section T1 to generate a first megasonic, and in the third lift section T2, it can control the second megasonic diaphragm 130b and / or the third megasonic diaphragm 130c together with the first megasonic diaphragm 130a to generate a second megasonic and / or the third megasonic together with the first megasonic.

[0060] As described above, the processor 140 can easily ensure a clean wafer 10 from which the source of contamination has been removed by controlling the timing at which megasonic is applied differently depending on the section in which the wafer 10 is lifted.

[0061] For example, the processor 140 can ensure a clean wafer 10 from which contamination sources have been removed by turning on the first megasonic diaphragm 130a to generate a first megasonic from point 0 to 2 / 3R of the wafer 10, which is the second lift section T1, and then turning on the second megasonic diaphragm 130b and / or the third megasonic diaphragm 130c together with the first megasonic diaphragm 130a to generate a second megasonic and / or the third megasonic along with the first megasonic.

[0062] In other words, the reason for turning on the second megasonic diaphragm 130b and / or the third megasonic diaphragm 130c in the third lift section T2 is that if they are turned on from the second lift section T1, the irregular flow (vortex generation) of the contaminant source in the cleaning tank 110 will not only cause a phenomenon in which particles become inferior, but the particle removal performance of the first megasonic generated by the first megasonic diaphragm 130a from the third lift section T2 will also be significantly reduced.

[0063] Furthermore, if the second megasonic diaphragm 130b and / or the third megasonic diaphragm 130c are turned on later than the third lift section T2, the wafer 10 may already be contaminated by particles by the time particles begin to adhere to it.

[0064] For these reasons, the most effective way for the processor 140 to remove particles and ensure a clean wafer 10 is to turn on the second megasonic diaphragm 130b and / or the third megasonic diaphragm 130c together with the first megasonic diaphragm 130a in the third lift section T2. ​​Experimental results related to this are explained in Figures 5 to 10.

[0065] Furthermore, the processor 140 can control the first megasonic diaphragm 130a to the third megasonic diaphragm 130c in the second lift section T1 to the third lift section T2 to adjust the intensity of the first megasonic to the intensity of the third megasonic to a constant level. For example, the processor 140 can control the first megasonic diaphragm 130a to the third megasonic diaphragm 130c to adjust the intensity of the first megasonic to the third megasonic to between 2000W and 2400W.

[0066] As mentioned above, the reason for adjusting the intensity of the first to third megasonics to between 2000W and 2400W is as follows: When the intensity of the megasonics is applied at 2000W or less, the pollution source removal performance decreases, and when it is applied at 2400W or more, an irregular flow is formed, causing a phenomenon in which the particles become even more degraded.

[0067] Figure 5 is a diagram illustrating Experiment 1, which utilizes the wafer cleaning apparatus of the present invention.

[0068] Referring to Figure 5, Experiment 1 of the present invention is an experiment in which only the first megasonic diaphragm 130a is turned on, regardless of the section, while lifting the wafer 10 housed in the cleaning tank 110. Here, 0 and 1 shown in Figure 5(a) represent the sections in which the wafer 10 is cleaned.

[0069] The processor 140 turns on the first megasonic diaphragm 130a to generate the first megasonic, and controls the intensity or power of the first megasonic to be maintained between 2000W and 2400W.

[0070] At this time, the second megasonic diaphragm 130b and the third megasonic diaphragm 130c are in a turned-off state.

[0071] As a result of this experiment, a predetermined pattern was generated on wafer 10, as shown in Figure 5(b).

[0072] In other words, when a wafer 10 housed in a cleaning tank 110 is lifted by turning on only the first megasonic diaphragm 130a, which is the lower megasonic diaphragm, and generating only the first megasonic, Experiment 1 revealed that the particle removal performance decreases as the wafer 10 moves further away from the first megasonic diaphragm 130a, and particles of a specific pattern are generated on the wafer 10.

[0073] Figure 6 is a diagram illustrating Experiment 2, which utilizes the wafer cleaning apparatus of the present invention.

[0074] Referring to Figure 6, Experiment 2 of the present invention involves dividing the wafer 10 housed in the cleaning tank 110 into a first section and a second section while lifting it. The first megasonic diaphragm 130a is turned on in the first section, and the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section. Here, as shown in Figure 6(a), the first section represents the range from 0 to 1 / 3R, and the second section represents the range from 1 / 3R to 1.

[0075] The processor 140 turned on the first megasonic diaphragm 130a in the first section to generate the first megasonic, and then turned on all of the first megasonic diaphragms 130a to the third megasonic diaphragm 130c in the second section to generate the first to third megasonic. At this time, the intensity or power of the first to third megasonic was controlled to be maintained between 2000W and 2400W.

[0076] As a result of this experiment, as shown in Figure 6(b), particles and a predetermined pattern were generated across the entire surface of wafer 10.

[0077] In other words, when the first megasonic diaphragm 130a is turned on in the first section to generate the first megasonic, and then the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section to generate the first, second, and third megasonic for lifting, Experiment 2 confirmed that irregular flow (vortex generation) occurs in the cleaning fluid due to the generation of the second and third megasonic, resulting not only in the generation of a predetermined pattern on the wafer 10, but also in the generation of particles across the entire wafer 10.

[0078] Figure 7 is a diagram illustrating Experiment 3, which utilizes the wafer cleaning apparatus of the present invention.

[0079] Referring to Figure 7, Experiment 3 of the present invention involves dividing the wafer 10 housed in the cleaning tank 110 into a first section and a second section while lifting it. The first megasonic diaphragm 130a is turned on in the first section, and the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section. Here, as shown in Figure 7(a), the first section represents the range from 0 to 1 / 2R, and the second section represents the range from 1 / 2R to 1.

[0080] The processor 140 turned on the first megasonic diaphragm 130a in the first section to generate the first megasonic, and then turned on all of the first megasonic diaphragms 130a to the third megasonic diaphragm 130c in the second section to generate the first to third megasonic. At this time, the processor controlled the intensity or power of the first to third megasonic to be maintained between 2000W and 2400W.

[0081] As a result of this experiment, as shown in Figure 7(b), particles were generated across the entire surface of wafer 10.

[0082] Specifically, when the first megasonic diaphragm 130a is turned on in the first section to generate the first megasonic, and the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section to generate the first, second, and third megasonic and lift the wafer, irregular flow (vortex generation) occurs in the cleaning solution due to the generation of the second and third megasonic, resulting in the generation of particles across the entire wafer 10. However, compared to Experiment 2, Experiment 3 confirmed that the predetermined pattern disappeared and the overall particle distribution tended to be slightly better.

[0083] Figure 8 is a diagram illustrating Experiment 4, which utilizes the wafer cleaning apparatus of the present invention.

[0084] Referring to Figure 8, Experiment 4 of the present invention involves dividing the wafer 10 housed in the cleaning tank 110 into a first section and a second section while lifting it. The first megasonic diaphragm 130a is turned on in the first section, and the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section. Here, as shown in Figure 8(a), the first section is the section from 0 to 2 / 3R, and the second section is the section from 2 / 3R to 1. Here, the first section may be the second lift section described in Figure 4, and the second section may be the third lift section.

[0085] The processor 140 turned on the first megasonic diaphragm 130a in the first section to generate the first megasonic, and then turned on all of the first megasonic diaphragms 130a to the third megasonic diaphragm 130c in the second section to generate the first to third megasonic. At this time, the processor controlled the intensity or power of the first to third megasonic to be maintained between 2000W and 2400W.

[0086] As a result of this experiment, as shown in Figure 8(b), no particles or the predetermined pattern were generated across the entire wafer 10.

[0087] In other words, when the first megasonic diaphragm 130a is turned on in the first section to generate the first megasonic, and then the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section to generate the first megasonic, second megasonic, and third megasonic for lifting, Experiment 4 confirmed that no particles or predetermined patterns are generated on the wafer 10 as a whole.

[0088] As can be seen from Experiment 4, in the present invention, when the first megasonic diaphragm 130a to the third megasonic diaphragm 130c are turned on at the 2 / 3R point, which is the third lift section, the performance of removing particles is improved, and a clean wafer 10 can be manufactured.

[0089] Figure 9 is a diagram illustrating Experiment 5, which utilizes the wafer cleaning apparatus of the present invention.

[0090] Referring to Figure 9, Experiment 5 of the present invention involves dividing the wafer 10 housed in the cleaning tank 110 into a first section and a second section while lifting it. The first megasonic diaphragm 130a is turned on in the first section, and the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section. Here, as shown in Figure 9(a), the first section represents the range from 0 to 4 / 5R, and the second section represents the range from 4 / 5R to 1.

[0091] The processor 140 turned on the first megasonic diaphragm 130a in the first section to generate the first megasonic, and then turned on all of the first megasonic diaphragms 130a to the third megasonic diaphragm 130c in the second section to generate the first to third megasonic. At this time, the processor controlled the intensity or power of the first to third megasonic to be maintained between 2000W and 2400W.

[0092] As a result of this experiment, a predetermined pattern was generated on wafer 10, as shown in Figure 9(b).

[0093] In other words, when the first megasonic diaphragm 130a is turned on in the first section to generate the first megasonic, and then the first megasonic diaphragm 130a, the second megasonic diaphragm 130b, and the third megasonic diaphragm 130c are turned on in the second section to generate the first megasonic, second megasonic, and third megasonic for lifting, the overall particles caused by the generation of the second and third megasonic were removed, but specific or predetermined patterns were generated.

[0094] This means that the particle removal performance should be maximized at the point where a specific pattern occurs. However, Experiment 5 revealed that beyond this point, the generation of second and third megasonics prevents sufficient particle removal.

[0095] As explained above, the wafer cleaning apparatus 100 of the present invention operates the first megasonic diaphragm 130a to the third megasonic diaphragm 130c together at the third lift space, 2 / 3R, to generate the first megasonic to the third megasonic, thereby maximizing particle removal performance and enabling the production of a clean wafer 10.

[0096] Figure 10 is a diagram illustrating Experiment 6, which utilizes the wafer cleaning apparatus of the present invention.

[0097] Referring to Figure 10, the processor 140 controls the first megasonic diaphragm 130a to fix the intensity of the first megasonic, and then controls the second megasonic diaphragm 130b and the third megasonic diaphragm 130c to adjust the intensity of the second and third megasonic. In contrast, the processor 140 controls the second megasonic diaphragm 130b and the third megasonic diaphragm 130c to fix the intensity of the second and third megasonic, and then controls the first megasonic diaphragm 130a to adjust the intensity of the first megasonic, and these are the results of various experiments.

[0098] The first experiment involved fixing the intensity of the first megasonic pulse between 2000W and 2400W, while adjusting the intensities of the second and third megasonic pulses to 2000W or less. The results of the first experiment showed good control of particles in the lower part of the wafer, but the generation of specific patterns and inferior particle quality were observed in the upper region of the wafer.

[0099] The second experiment involved fixing the intensity of the first megasonic pulse between 2000W and 2400W, while adjusting the intensities of the second and third megasonic pulses between 2000W and 2400W. The results of the second experiment showed that both the bottom and sides of the wafer were in good condition, making it possible to secure wafers with excellent cleanliness.

[0100] The third experiment involved fixing the intensity of the first megasonic pulse between 2000W and 2400W, while adjusting the intensities of the second and third megasonic pulses to 2400W or higher. The results of the third experiment showed good control of particles in the lower part of the wafer, but the generation of specific patterns and inferior particle quality were observed in the upper region of the wafer.

[0101] Experiment 4 involved fixing the intensities of the second and third megasonic waves between 2000W and 2400W, while adjusting the intensity of the first megasonic wave to 2000W or less. The results of Experiment 4 showed a decrease in the ability to remove particles from the bottom of the wafer, and overall particle inferiority was confirmed, but no specific patterns occurred.

[0102] Experiment 5 involved fixing the intensity of the second and third megasonic waves between 2000W and 2400W, and adjusting the intensity of the first megasonic wave between 2000W and 2400W. The results of Experiment 5 showed that both the bottom and sides of the wafer were in good condition, making it possible to secure wafers with excellent cleanliness.

[0103] Experiment 6 involved fixing the intensities of the second and third megasonic waves between 2000W and 2400W, while adjusting the intensity of the first megasonic wave to over 2400W. The results of Experiment 6 showed a decrease in the ability to remove particles from the bottom of the wafer, and overall particle inferiority was confirmed, but no specific patterns occurred.

[0104] As described above, it was confirmed that when at least one of the intensities from the first to the third megasonic pulses is applied at 2000W or less, the contamination source removal performance decreases, and when applied at 2400W or more, an irregular flow is formed, resulting in a phenomenon where particles become even less efficient. Furthermore, it was found that when the intensities from the first to the third megasonic pulses are adjusted between 2000W and 2400W, wafers with excellent cleanliness can be easily obtained.

[0105] Figure 11 is a diagram illustrating a wafer cleaning method according to an embodiment of the present invention.

[0106] Since the wafer cleaning apparatus according to the embodiment of the present invention shown in Figures 1 to 10 has been sufficiently explained above, any overlapping content will be omitted in Figure 11.

[0107] Referring to Figure 11, the wafer cleaning method according to an embodiment of the present invention may include a step of controlling a plurality of megasonic diaphragms 130a to 130c differently in correspondence with at least one lift section in which the wafer 10 is lifted, under the control of the processor 140.

[0108] For example, at least one lift section may include the first lift section T0 to the fourth lift section T3.

[0109] In other words, the step of controlling the multiple megasonic diaphragms 130a to 130c in different ways may include the step of controlling the first megasonic diaphragm 130a from the second lift section T1 to the third lift section T2 under the control of the processor 140 to generate a first megasonic, and the step of controlling the second megasonic diaphragm 130b or the third megasonic diaphragm 130c in the third lift section T2 to generate a second megasonic or a third megasonic.

[0110] The first lift section T0 may be the section in which the entire wafer 10 is housed in the cleaning tank 110. The first megasonic diaphragms 130a to the third megasonic diaphragms 130c can be turned off under the control of the processor 140.

[0111] The second lift section T1 may be the section from the first lift section T0 onwards in which the wafer 10 is housed in the cleaning tank 110 up to the first portion of the wafer 10. Here, the first portion of the wafer 10 may be the 2 / 3R portion of the wafer 10. At this time, the remaining 1 / 3R of the wafer 10 may be housed in the cleaning tank 110. The first megasonic diaphragm 130a is turned on under the control of the processor 140 and can generate the first megasonic during the second lift section T1.

[0112] The third lift section T2 may be the section from the second lift section T1 onwards in which the wafer 10 is housed in the cleaning tank 110 up to the second portion of the wafer 10. Here, the second portion of the wafer 10 may be the part that comes into contact with the cleaning solution. At this time, a very small portion of the wafer 10 may be housed in the cleaning tank 110.

[0113] The first megasonic diaphragm 130a maintains a turned-on state under the control of the processor 140 and can continuously generate the first megasonic during the third lift section T2. ​​The second megasonic diaphragm 130b and the third megasonic diaphragm 130c are turned on under the control of the processor 140 and can generate the second and third megasonic during the third lift section T2.

[0114] The fourth lift section T3 may be a section from the third lift section T2 onwards in which the wafer 10 is not housed in the cleaning tank 110. The first megasonic diaphragm 130a to the third megasonic diaphragm 130c can be turned off under the control of the processor 140.

[0115] As described above, the processor 140 can control the first megasonic diaphragm 130a from the second lift section T1 to the third lift section T2 to generate a first megasonic, and in the third lift section T2, it can control at least one or more of the second megasonic diaphragm 130b and the third megasonic diaphragm 130c together with the first megasonic diaphragm 130a to generate a second megasonic and / or a third megasonic along with the first megasonic.

[0116] As described above, the processor 140 can easily ensure a clean wafer 10 from which the source of contamination has been removed by controlling the timing of the application of megasonic depending on the section in which the wafer 10 is lifted. A detailed explanation of this has been sufficiently explained above and will be omitted here.

[0117] Furthermore, in the stage of controlling multiple megasonic diaphragms differently, a specific intensity of power in the range of 2000 to 2400 watts (W) is supplied under the control of the processor 140, allowing the intensity of the first megasonic, second megasonic, and third megasonic to be controlled to specific values.

[0118] Furthermore, the processor 140 can control the first megasonic diaphragm 130a to the third megasonic diaphragm 130c in the second lift section T1 to the third lift section T2, thereby adjusting the intensity of the first megasonic to the intensity of the third megasonic to a constant level.

[0119] For example, the processor 140 can control the first megasonic diaphragm 130a to the third megasonic diaphragm 130c to adjust the intensity of the first to third megasonic waves to between 2000W and 2400W. A detailed explanation of this has been sufficiently explained above and will be omitted here. The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, the contents of these combinations and modifications should also be interpreted as being included in the scope of the present invention. [Embodiment]

[0120] The embodiments for carrying out the present invention have been sufficiently described in the above-mentioned "Embodiments for Carrying Out the Invention," so that description will be omitted here.

Claims

1. A cleaning tank containing a cleaning solution and wafers to be cleaned, The cleaning tank is provided with a plurality of megasonic diaphragms that generate megasonics, A lift unit for stacking the wafers and housing the stacked wafers in the cleaning tank, or for lifting the wafers housing the cleaning tank, A processor that controls the lift section and the plurality of megasonic diaphragms, and controls the plurality of megasonic diaphragms differently in accordance with at least one lift section in which the wafer is lifted, A wafer cleaning system, including a wafer cleaning device.

2. The aforementioned multiple megasonic diaphragms are, A first megasonic diaphragm is provided on the bottom surface of the cleaning tank, A second megasonic diaphragm is provided on the outer surface of the aforementioned cleaning tank, A third megasonic diaphragm is provided on the outer surface of the cleaning tank and is positioned at a predetermined distance from the second megasonic diaphragm, A wafer cleaning apparatus according to claim 1, comprising:

3. The aforementioned at least one lift section is A first lift section in which all of the wafers are housed in the cleaning tank, From the first lift section onward, there is a second lift section in which the wafer is housed in the cleaning tank up to the first portion of the wafer, From the second lift section onward, there is a third lift section in which the wafer is housed in the cleaning tank up to the second portion of the wafer, From the third lift section onward, there is a fourth lift section in which the wafer is not housed in the cleaning tank, A wafer cleaning apparatus according to claim 2, including the following:

4. The aforementioned processor, The first megasonic diaphragm is controlled from the second lift section to the third lift section to generate the first megasonic, In the third lift section, at least one of the second megasonic diaphragm and the third megasonic diaphragm is controlled. The wafer cleaning apparatus according to claim 3, which generates a second megasonic, a third megasonic, or at least one of the second megasonic and the third megasonic.

5. The aforementioned processor, The wafer cleaning apparatus according to claim 4, wherein power of a specific intensity in the range of 2000 to 2400 watts (W) is supplied to control the intensity of the first megasonic, the second megasonic, and the third megasonic to specific values.

6. A cleaning tank containing a cleaning solution and wafers to be cleaned, A plurality of megasonic diaphragms are provided in the cleaning tank, each comprising a first megasonic diaphragm provided on the bottom surface of the cleaning tank, a second megasonic diaphragm provided on the outer surface of the cleaning tank, and a third megasonic diaphragm provided on the outer surface of the cleaning tank and positioned at a predetermined distance from the second megasonic diaphragm. A lift unit for stacking the wafers and housing the stacked wafers in the cleaning tank, or for lifting the wafers housing the cleaning tank, A processor that controls the lift section and the plurality of megasonic diaphragms, A cleaning method using a wafer cleaning apparatus, including, A wafer cleaning method comprising the step of controlling the plurality of megasonic diaphragms to move differently in accordance with at least one lift section in which the wafer is lifted, under the control of the processor.

7. The aforementioned at least one lift section is A first lift section in which all of the wafers are housed in the cleaning tank, From the first lift section onward, there is a second lift section in which the wafer is housed in the cleaning tank up to the first portion of the wafer, From the second lift section onward, there is a third lift section in which the wafer is housed in the cleaning tank up to the second portion of the wafer, From the third lift section onward, there is a fourth lift section in which the wafer is not housed in the cleaning tank, Includes, The step of controlling the aforementioned multiple megasonic diaphragms in different ways is as follows: The steps include: controlling the first megasonic diaphragm from the second lift section to the third lift section under the control of the processor to generate the first megasonic; The steps include controlling at least one of the second megasonic diaphragm and the third megasonic diaphragm in the third lift section to generate a second megasonic, a third megasonic, or at least one of the second megasonic and the third megasonic, A wafer cleaning method according to claim 6, including the following:

8. The step of controlling the aforementioned multiple megasonic diaphragms in different ways is as follows: The wafer cleaning method according to claim 7, wherein the processor supplies power of a specific intensity in the range of 2000 to 2400 watts (W) to control the intensity of the first megasonic, the second megasonic, and the third megasonic to specific values.

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