Method for generating high-resistivity semiconductor stacks and related stacks.

Abstract

One aspect of the present invention relates to a method for generating a semiconductor stack (10), comprising: - forming a silicon carbide layer (12) extending over a first silicon layer (11) called a support layer; and - annealing the layer until cavities (13) are formed, each cavity (13) extending from the silicon carbide layer (12) into the support layer (11).

Description

Technical Field

[0001] The technical field of the present invention relates to the technical field of semiconductor stacks for forming silicon-on-insulator substrates, also called "SOI" substrates, and more particularly to SOI substrates implemented in the radio frequency field.

Background Art

[0002] High resistivity semiconductor stacks, such as silicon-on-insulator substrates, i.e., SOI substrates, are widely used for radio frequency applications because they promote the integrity of signals circulating within the devices fabricated on their surfaces.

[0003] An SOI substrate includes a first semiconductive layer of silicon, called the "support layer" or "substrate", and a second semiconductive layer of silicon, called the "active layer". The active layer is for accommodating microelectronic components manufactured within or on the active layer. In this case, these are also called "initial" or "front end" components, or "FEOL" (Front End Of Line) components. The active layer is separated from the support layer by an insulating layer, for example, an insulating layer of silicon oxide, disposed between the support layer and the active layer, and more particularly under the active layer. At this time, the insulating layer is called "BOX" which means "buried" or "Buried Oxide". The insulating layer makes it possible to confine the main charge carriers within the active layer, which makes it possible to contemplate the operating frequency of front end components that is high, for example, up to several tens of gigahertz at most.

[0004] However, charge carriers can accumulate in the support layer near the insulating layer, creating a conductive sublayer that significantly impairs the conductivity within the active layer. Therefore, it is necessary to reduce the circulation of charge carriers in the support layer near the insulating layer.

[0005] The article ["RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate," Dimitri Lederer and Jean-Pierre Raskin, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 7, July 2008] presents a solution to this problem by forming a trapping layer disposed between the support layer and the insulating layer, whose role is to trap charge carriers. The trapping layer contains polycrystalline silicon. The trapping of charge carriers is then carried out at the grain boundaries where silicon dangling bonds are located. The trapping layer is deposited by Low Pressure Chemical Vapor Deposition (LPCVD), followed by rapid annealing at a temperature of 1000°C to form silicon particles.

[0006] The effectiveness of the trapping layer depends on the density of the silicon dangling bonds and, consequently, the density of the grain boundaries. However, the heat treatment performed during the fabrication of microelectronic components in the active layer tends to reduce the number of particles and, consequently, the number of grain boundaries. Therefore, polycrystalline silicon trapping layers require a limited thermal budget.

[0007] Another technique for trapping charge carriers is to form bubbles within the support layer near the interface between the support layer and the insulating layer. Dangling bonds on the free surface of each bubble allow charge carriers to be trapped. The article ["Chemical and electrical properties of cavities in silicon and germanium," SMYers, DMFollstaedt, GAPetersen, CHSeager, HJStein & WRWampler, Nuclear instruments and Methods in Physics Research B106(1995)379-385] describes a method for forming bubbles within a silicon layer by helium ion implantation. However, the bubbles formed are located about 200 nm away from the interface between the support layer and the insulating layer. In addition, the maximum bubble density is located between 1000 nm and 1500 nm, away from the interface. Thus, the trapping capability at the interface is limited. Furthermore, adjusting the implantation energy to bring bubbles closer to the interface can cause delamination of the insulating layer. Furthermore, the injection time may be longer (10mA injection current and 10 17 cm -2 At this dosage, it takes approximately 20 minutes to implant ions into a 300mm diameter substrate.

[0008] Another known solution is described in French Patent Application Publication No. 3091011 A1, which discloses an SOI substrate comprising a polycrystalline silicon carbide layer extending over the surface of a support layer. The carbide layer is preferably polycrystalline, thus allowing charge carriers to be trapped in the same manner as in a polycrystalline silicon trapping layer. Growing the carbide layer is performed by growing it from the support layer using a carbon precursor or by CVD. However, the thickness of the disclosed carbide layer is limited to 5 nm. However, at such thin thicknesses, the carbide layer is chemically fragile, and seeds introduced during complementary manufacturing steps (such as the manufacturing of the insulating and / or active layers) can migrate to the carbide layer, potentially contaminating it.

[0009] Therefore, there is a need to provide a semiconductor stack that effectively traps charge carriers within a support layer, and this semiconductor stack is also robust with respect to complementary manufacturing steps (such as the manufacturing of insulating layers, active layers, or even front-end components). [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] French Patent Application Publication No. 3091011 [Non-patent literature]

[0011] [Non-Patent Document 1] "RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate," Dimitri Lederer and Jean-Pierre Raskin, IEEE Transactions on Electron Devices, Vol. 55, No. 7, July 2008. [Non-Patent Document 2] "Chemical and electrical properties of cavities in silicon and germanium", SM Myers, DM Follstaedt, GA Petersen, CHSeager, HJ Stein & WRWampler, Nuclear instruments and Methods in Physics Research B106 (1995) 379-385 [Overview of the project] [Means for solving the problem]

[0012] The present invention relates to a method for manufacturing a semiconductor stack, comprising a first silicon layer called a support layer: - To form a silicon carbide layer extending over a support layer, having a thickness greater than 5 nm as measured from the support layer, wherein the ratio of carbon atoms in the silicon carbide layer within 20 nm from the support layer is strictly greater than 50%, The present invention relates to a method comprising annealing a support layer and a silicon carbide layer until a cavity is formed, wherein each cavity extends from the silicon carbide layer into the support layer, and during annealing, the concentration of oxygen in contact with the silicon carbide layer is less than 10 ppm, preferably less than 5 ppm, or even zero.

[0013] During annealing, silicon atoms in the support layer migrate toward the carbide layer, thus forming cavities, or hollow zones, located within the support layer.

[0014] The cavities formed in the support layer provide silicon dangling bonds, thus allowing charge carriers to be trapped within the support layer. The placement of the cavities is as close as possible to the interface between the support layer and the carbide layer, enabling effective trapping of charge carriers.

[0015] In addition, silicon carbide is a semiconductor with an indirect bandgap having a difference greater than 2 eV, or even greater than 3 eV. The carbide layer thus prevents the circulation of charge carriers near the insulating layer.

[0016] Since trapping does not rely on the presence of grain boundaries that are temperature-sensitive, the stack then has improved shape stability. In addition, during heat treatment, the temperature involved in the coalescence of voids is significantly higher than the temperature involved in the coalescence of particles in the polycrystalline structure. Also, the temperature involved in the coalescence of voids is higher than the temperature executed during complementary manufacturing steps. In addition, while the coalescence of particles is accompanied by the disappearance of traps, the expected coalescence of voids is carried out with a constant surface area.

[0017] The silicon carbide layer, being richer in carbon, activates the movement of silicon atoms from the support layer during annealing and enables the effective formation of voids.

[0018] A silicon carbide layer thickness greater than 5 nm improves its robustness, particularly chemically, in relation to complementary manufacturing steps (such as the manufacture of "front-end" components). In fact, it is less susceptible to the influence of contaminants that can move.

[0019] When the silicon carbide layer is annealed in an oxygen-containing environment, there is a possibility of pitting oxidation. Pitting can damage the silicon carbide layer, slow down the movement of silicon atoms, and thus slow down the formation of voids. Annealing in a low-oxygen environment limits the occurrence of pitting and thus improves the reproducibility of the method.

[0020] Finally, the method does not rely on ion implantation to form voids, simplifying its implementation.

[0021] The annealing step can be carried out at a temperature between 900 °C and 1100 °C for a duration between 15 minutes and 2 hours.

[0022] The silicon carbide layer resulting from the forming step is preferably amorphous, and the step of annealing the layer is preferably carried out so as to crystallize the silicon carbide layer into a polycrystalline structure.

[0023] The support layer is preferably oriented in a plane.

[0024] The ratio of carbon atoms in the silicon carbide layer within 20 nm from the support layer measured perpendicular to the plane is preferably 70% or less.

[0025] The thickness of the silicon carbide layer is preferably less than 500 nm.

[0026] Each cavity may have facets, and each facet is preferably oriented parallel to a crystal plane that forms part of a group of {111} crystal planes, or part of a group of {113} crystal planes, for example.

[0027] The cavities preferably extend over a distance measured perpendicular to the plane from the silicon carbide layer between 5 nm and 100 nm.

[0028] The method preferably includes the step of forming an insulating layer that extends over the silicon carbide layer. Advantageously, the insulating layer is for forming a "buried" layer, referred to as "BOX" which means "Buried Oxide".

[0029] According to a first embodiment, the step of forming the insulating layer is carried out by deposition before the annealing step.

[0030] The steps of annealing the support layer, the silicon carbide layer, and the insulating layer may be carried out in an atmosphere containing an oxygen concentration of less than 1%.

[0031] According to a second embodiment, the step of forming the insulating layer is carried out by transfer from a donor substrate after annealing the layer.

[0032] In common to the two embodiments described above, the method may include the step of forming a second crystalline layer extending over the insulating layer. The insulating layer then forms a "BOX" layer.

[0033] Another aspect of the present invention is a semiconductor stack: - The first silicon layer, referred to as the support layer, - A silicon carbide layer extending over the support layer, having a thickness greater than 5 nm as measured from the support layer, - A cavity, where each cavity extends from the silicon carbide layer into the supporting layer, and This relates to a semiconductor stack comprising the following features.

[0034] The silicon carbide layer is preferably polycrystalline.

[0035] Preferably, the support layer is oriented in a plane, and the cavities extend perpendicular to the plane and over a distance measured from the silicon carbide layer, between 5 nm and 100 nm.

[0036] Preferably, when the cavity is greater than 15 nm, perpendicular to the plane, and extends over a distance measured from the silicon carbide layer, each cavity has facets, and each facet is oriented parallel to the crystal plane.

[0037] Preferably, each cavity has a pyramidal shape and a bottom surface aligned with the interface between the support layer and the silicon carbide layer.

[0038] Preferably, the apex of the pyramid extends into the supporting layer.

[0039] Preferably, the cavities are located only at the interface between the support layer and the silicon carbide layer. In other words, each cavity extends only from the silicon carbide layer into the support layer.

[0040] Preferably, the silicon carbide layer is non-porous.

[0041] Preferably, each cavity comprises a free surface surrounding an internal volume, with at least one portion of the free surface separating the internal volume from the support layer, and at least one other portion of the free surface separating the internal volume from the silicon carbide layer.

[0042] Preferably, each portion of the free surface separating the cavity volume from the support layer contains silicon atoms, and at least some of these silicon atoms have dangling bonds.

[0043] The present invention and its various applications will be better understood by reading the following description and examining the accompanying drawings.

[0044] The figures are provided to illustrate the purpose of the present invention and are not intended to limit it in any way. Unless otherwise stated, the same elements appearing in different figures shall have a single reference symbol. [Brief explanation of the drawing]

[0045] [Figure 1] This figure schematically represents a first embodiment of the semiconductor stack according to the present invention. [Figure 2] This figure schematically represents a first embodiment of the manufacturing method according to the present invention. [Figure 3a] This figure schematically represents a first example of the first step of the manufacturing method according to the present invention. [Figure 3b] This figure schematically illustrates a second example of the first step of the manufacturing method according to the present invention. [Figure 4] This diagram schematically represents the second step of the manufacturing method according to the present invention. [Figure 5] This diagram schematically represents the third step of the manufacturing method according to the present invention. [Figure 6] This diagram schematically represents the fourth step of the manufacturing method according to the present invention. [Figure 7] This figure schematically represents a second first embodiment of the manufacturing method according to the present invention. [Figure 8]This diagram schematically represents the fifth step of the manufacturing method according to the present invention. [Figure 9] This figure shows an image of a semiconductor stack manufactured by the manufacturing method according to the present invention, obtained by a transmission microscope. [Modes for carrying out the invention]

[0046] This invention proposes an improvement to semiconductor stacks intended for forming SOI substrates, and in particular substrates for radio frequency applications.

[0047] Figure 1 schematically shows a first embodiment of the semiconductor stack 10 according to the present invention. The stack 10 is: - A first silicon layer 11, referred to as the support layer, - Silicon carbide layer 12, - Cavity 13 and It is equipped with.

[0048] The support layer 11 extends, for example, in a given plane P, which is, for example, the plane of the silicon wafer on which the SOI substrate will be formed. Advantageously, the support layer 11 is a resistive support, i.e., has a resistivity greater than 1 kΩ·cm.

[0049] The silicon carbide layer 12 (also called the SiC layer) extends over the support layer 11 in a given plane P. The SiC layer 12 is in direct contact with the support layer 11, forming an interface 112 between the two layers.

[0050] The stack 10 is characterized by containing a plurality of cavities 13 extending within the support layer 11. Each cavity 13 is hollow, i.e., contains no solid or liquid material. They may contain species in a gaseous state with a low partial pressure. However, they are preferably completely empty. Each cavity 13 extends from the SiC layer 12 into the support layer 11; that is, each cavity 13 extends from the interface 112 into the support layer 11. In this case, each cavity 13 has free surfaces 131, 132 surrounding the internal volume 130 of the cavity 130. At least one portion 131 of the free surface separates the internal volume 130 from the support layer 11, and at least one other portion 132 of the free surface separates the internal volume 130 of the cavity from the SiC layer 12.

[0051] The free surface portion(s) 131 separating the cavity volume 130 from the support layer 11 is formed of silicon atoms, at least some of which have dangling bonds. Dangling bonds mean that the atomic orbitals are not involved in chemical bonding with other elements. Dangling bonds allow charge carriers to circulate within the support layer 11 and trap near the SiC layer 12.

[0052] The dangling bonds and cavities also allow for the trapping of impurities such as hydrogen ions or atoms, helium atoms, or metals such as lithium or copper that have migrated into the support layer 11 during additional manufacturing steps (such as the manufacturing of "front-end" components). Therefore, the resistivity of the support layer 11 is not degraded during additional manufacturing steps.

[0053] The thermodynamic stability and diffusion formation of the cavity 13 tend to promote facet formation of the cavity. The portions 131 of the free surfaces 131, 132 of each cavity 13 are then preferably aligned along the crystal planes of the support layer 11. For example, when the support layer 11 has a (001) plane at the interface 112 with the SiC layer 12 (i.e., the (001) plane and plane P coincide), the cavity 13 may have facets formed by having portions parallel to the crystal planes of the group of {111} planes (i.e., the (111), (-111), (1-11), and (-1-11) planes) or the group of {113} planes (i.e., the (113), (-113), (1-13), and (-1-13) planes). In this case, the cavity 13 may have an inverted pyramidal shape with a square or triangular base, the base of which coincides with the interface between the support layer 11 and the SiC layer 12. However, facet formation does not necessarily depend on the plane at the interface 112 between the SiC layer 12 and the support layer 11. A group of other crystal planes is conceivable.

[0054] To determine the orientation of the crystal planes, it is advantageous to consider cavities 13 extending over a distance 133 greater than 15 nm and measured perpendicular to the plane P. In fact, it may be difficult to distinguish between groups of planes {113} below this distance.

[0055] Figure 1 shows the

[0111] and

[0001] directions, which are perpendicular to the (001) and (111) crystal planes, represented by arrows.

[0056] Each cavity 13 preferably extends from the SiC layer 12 over a distance 133 between 5 nm and 100 nm. The distance 133 is measured perpendicular to the plane P over which the SiC layer 12 extends, i.e., along

[0001] in this example. The distance 133 is measured from the carbide layer 12, i.e., from the interface 112 separating the support layer 11 and the carbide layer 12.

[0057] In the example in Figure 1, the stack 10 also comprises an insulating layer 14 and an active layer 15. This allows the stack 10 to form an SOI substrate. The insulating layer 14 extends over the SiC layer 12. Preferably, it has a thickness between 100 nm and 1000 nm. For example, it contains an oxide such as silicon oxide SiO2. The active layer 15 comprises a crystalline or polycrystalline semiconductor and extends over the insulating layer 14. The insulating layer 14 thereby separates the SiC layer 12 from the active layer 15. It is said to be "embedded" beneath the active layer 15. The active layer 15 preferably has a thickness between 50 nm and 500 nm and contains, for example, crystalline silicon or polycrystalline silicon, or another crystalline semiconductor material used in the radio frequency field, such as indium phosphide or gallium nitride.

[0058] The SiC layer 12 is preferably polycrystalline. Therefore, it contributes to the trapping of charge carriers in the same manner as polycrystalline silicon trapping layers described in the prior art. The charge carriers are trapped by dangling bonds located at the grain boundaries of the polycrystalline structure.

[0059] Figure 2 schematically illustrates the manufacturing method according to the present invention for manufacturing stack 10.

[0060] The manufacturing method 20 includes step 22 of forming a silicon carbide layer 12 (referred to as a SiC layer) extending over the support layer 11 from the support layer 11. Two examples of the obtained silicon carbide layer 12 are illustrated in Figures 3a and 3b.

[0061] The SiC layer 12 is formed from the support layer 11 by, for example, Chemical Vapor Deposition (CVD). For example, it is Plasma Enhanced CVD Deposition (PECVD). The SiC layer 12 is obtained by PECVD deposition of a carbon precursor such as tetramethylsilane Si(CH3)4, also known as "TMS". The resulting SiC layer 12 extends over the support layer 11.

[0062] The support layer 11 extends in a plane P. It preferably has a (001) crystal plane in plane P. The SiC layer 12 has a thickness 121, measured perpendicular to plane P from the support layer 11, and is greater than 5 nm and preferably less than 500 nm.

[0063] Method 20 further includes a step 23 of annealing the support layer 11 and the SiC layer 12 until cavities 13 extending into the support layer 11 are formed, as shown in Figure 4. Each cavity 13 at this time extends from the SiC layer 12 into the support layer 11. During the annealing step 23, the temperature increases the mobility of silicon atoms in the support layer 11, and increases the mobility of some of these atoms, particularly those closer to the SiC layer 12. The difference in the proportion of silicon atoms between the support layer 11 and the SiC layer 12 tends to induce the movement of silicon atoms from the support layer 11 towards the SiC layer 12, thus forming several cavities 13 within the support layer 11. The formation of each cavity 13 at this time begins at the interface between the support layer 11 and the SiC layer 12. Each cavity 13 at this time extends into the support layer 11 along a direction substantially perpendicular to the plane P. "Subject to perpendicular" means an angle of up to 20° with respect to the perpendicular. Step 23, in which the support layer 11 and the SiC layer 12 are annealed, preferably occurs simultaneously.

[0064] Since the formation of each cavity 13 begins at the interface between the support layer 11 and the SiC layer 12, this method forms only cavities extending from the interface between the support layer 11 and the SiC layer 12. In other words, this method does not allow the formation of cavities away from the aforementioned interface between the support layer 11 and the SiC layer 12 (these cavities away from the interface may be called pores or bubbles).

[0065] When the support layer 11 contains defects such as amorphous zones or grain boundaries, these defects may assist or facilitate the movement of silicon atoms toward the SiC layer 12.

[0066] The annealing temperature 23 that enables the formation of the cavities 13 is preferably between 900°C and 1100°C. Below 900°C, the mobility of silicon atoms is insufficient, and cavities 13 cannot be formed for a duration compatible with industrial throughput. Above 1100°C, the mobility of silicon atoms increases, promoting the movement of atoms between cavities 13, and tends to form fewer but very large cavities (i.e., extending beyond 100 nm from the SiC layer 12). Charge carrier trapping improves as the density of cavities 13 (i.e., the number of cavities 13 per unit area of ​​the interface 112) increases. On the other hand, trapping decreases as the density of cavities 13 decreases.

[0067] The SiC layer 12 is preferably formed at a temperature between 300°C and 500°C. In this manner, prior to the annealing step 23, it has an amorphous phase. The annealing step 23 of the layer, in particular the SiC layer 12, at a temperature between 900°C and 1100°C has the effect of crystallizing the SiC layer 12 into a polycrystalline structure. Such crystallization has two beneficial effects. First, the grain boundaries of the polycrystalline structure contribute to the trapping of charge carriers, thereby enhancing the trapping performed by the cavities 13. Second, crystallization also has the effect of accelerating the migration of silicon atoms from the support layer 11 to the SiC layer 12 in the same manner as the pumping of silicon atoms, thereby accelerating the formation rate of the cavities 13.

[0068] Both before and after annealing, the SiC layer 12 is nonporous. For example, when the SiC layer 12 is polycrystalline (e.g., after annealing), the nonporous nature is provided by the grain boundaries of the SiC layer 12.

[0069] The annealing step 23 is preferably performed for a duration between 15 minutes and 2 hours to allow for the migration of silicon atoms from the support layer 11 to acquire cavities 13 extending at least 5 nm from the SiC layer 12 and up to 100 nm from this layer. The dimensions of the cavities 13 (measured perpendicular to the plane P and from the SiC layer 12) are proportional to the duration of the annealing step 23. An annealing duration of about 15 minutes is compatible with industrial throughput. An annealing duration of about 2 hours allows for the formation of larger cavities 13 close to 100 nm, extending the trapping range of charge carriers within the support layer 11. An annealing duration of about 2 hours is also compatible with industrial throughput. In practice, annealing can be performed in a furnace, allowing several plates, e.g., dozens of plates, to be processed simultaneously. In contrast, ion implantation, as performed in the prior art, processes one plate at a time.

[0070] The migration of silicon atoms and, therefore, the rate of cavity formation 13, is accelerated when the SiC layer 12 has a carbon atom ratio (also called the carbon ratio) that is at least equal to the silicon atom ratio before the annealing step 23. Thus, the SiC layer 12 has a carbon ratio greater than 50% and preferably less than 70% before the annealing step 23. Therefore, the silicon ratio in the SiC layer 12 is less than 50% before the annealing step 23.

[0071] The formation rate of the cavity 13 is particularly accelerated when the difference in the ratio of carbon atoms to silicon atoms is large near the interface 112 between the SiC layer 12 and the support layer 11. On the other hand, the carbon ratio in the SiC layer 12 beyond 20 nm from the support layer 11 does not have a significant effect on the formation rate of the cavity 13. Therefore, as shown in Figure 3a, when the SiC layer 12 has a thickness 121 greater than 20 nm (measured perpendicular to the plane P and from the interface 112 with the support layer 11), it has a portion extending at least 20 nm from the support layer 11, where the carbon ratio is greater than 50% and preferably 70% or less. As shown in Figure 3b, when the SiC layer 12 has a thickness 121 of 20 nm or less, it has a carbon ratio greater than 50% and preferably 70% or less throughout its entire thickness 121. In other words, the carbon ratio of the SiC layer 12 within 20 nm of the support layer 11 (measured perpendicular to the plane P and from the interface 112) is preferably between 50% and 70%.

[0072] The SiC layer 12 reacts with oxygen and can be oxidized, for example, by pitting. Therefore, the annealing step 23 is carried out by minimizing the amount of oxygen in contact with the SiC layer 12. The annealing step 23 of the stack 10 is carried out by maintaining an oxygen concentration in contact with the SiC layer 12 of less than 10 ppm, preferably less than 5 ppm, or even zero.

[0073] Step 23, which involves annealing, is performed in a neutral atmosphere, for example, containing at least one neutral gas such as nitrogen or argon. The neutral atmosphere is then adjusted to have an oxygen concentration of less than 10 ppm or even less for at least the duration of step 23 of annealing.

[0074] Method 20, as shown in the implementation configuration of Figure 2, may also include a step 25 of forming an insulating layer 14 and a step 26 of forming a semiconducting active layer 15, so that the final stack 10 forms an SOI substrate, as shown in Figure 1.

[0075] Step 25, in which the insulating layer 14 shown in Figure 6 is formed, is preferably carried out by transfer from a donor substrate 30. The principle of transfer from the donor substrate 30 is known as SmartCut™. When step 25, in which the insulating layer 14 is formed, is carried out by transfer, step 26, in which the active layer 15 is formed, is also preferably carried out by transfer from a donor substrate and, if possible, from the same donor substrate 30. Preferably, steps 25 and 26, in which the two aforementioned layers are formed, are carried out simultaneously.

[0076] Before step 25, which involves forming the insulating layer 14, is performed, it may be necessary to prepare the surface 122 of the SiC layer 12 that will receive the insulating layer 14. In this case, method 20 includes step 24 of smoothing the surface 122 before step 25, which involves forming the insulating layer 14. As shown in Figure 5, step 24 of smoothing may be performed by Chemical Mechanical Polishing (CMP). Step 24 of smoothing is performed so that the SiC layer 12 has a surface roughness of 5 Å or less. Surface roughness is also called mean roughness or RMS (Root Mean Square) roughness. The roughness of the surface 122 of the SiC layer may be evaluated using an Atomic Force Microscope (AFM). The roughness is approximately 1 μm. 2 A portion of the surface area 122 can be evaluated.

[0077] Steps 25 and 26, in which the insulating layer 14 and the active layer 15 are simultaneously formed by transfer, may be performed from the same donor substrate 30, in which case the donor substrate 30 includes a semiconducting layer 35 made of, for example, crystalline silicon, polycrystalline silicon, crystalline indium phosphide, or crystalline gallium nitride, on which an insulating layer 34 is extended, for example, silicon oxide. For example, the insulating layer 34 has a thickness between 100 nm and 1000 nm. For example, the thickness of the underlying semiconducting layer 35 may exceed 50 nm, or even exceed 500 nm.

[0078] The simultaneously formed steps 25 and 26 may include a substep in which light ions (e.g., hydrogen or helium ions) are implanted into the semiconducting layer 35 of the donor substrate 30 to a depth of 50 nm to 500 nm below the insulating layer 34. The implantation may take, for example, several tens of 16 / cm 2 It is performed with a dose and at energies of several tens of keV.

[0079] The simultaneously formed steps 25 and 26 include a substep of cleaning the free surface 341 of the insulating layer 34 of the donor substrate 30 in order to enable direct bonding between the insulating layer 34 of the donor substrate 30 and the SiC layer 12 of the stack 10. To clean the free surface 341 of the insulating layer 34, a recipe known from silicon technology, such as the so-called "RCA" (Radio Corporation of America) recipe or even the so-called CARO recipe, which includes a mixture of hydrogen peroxide and sulfuric acid, is preferably used.

[0080] However, in order to enable good adhesion of the insulating layer 34 to the SiC layer 12, it is advantageous to activate the free surface 341 of the insulating layer 34 on the donor substrate 34 after such cleaning. For example, the above activation is carried out using, for example, an oxygen or nitrogen plasma.

[0081] Steps 25 and 26, which simultaneously form the insulating layer 14 and the active layer 15 by transfer, include a substep of bonding the donor substrate 30 to the stack 10, as shown in Figure 6, where the free layer 341 of the insulating layer 34 of the donor substrate 34 is pressed against the SiC layer 12 of the stack 10. Following bonding, a so-called "separation annealing" process is performed, aiming to separate the semiconducting layer 35 of the donor substrate 30 into two parts in a plane containing pre-implanted light ions. After separation annealing, the stack 10 comprises an insulating layer 14 extending over the SiC layer 12 (as the insulating layer 14 is bonded to the SiC layer 12), as shown in Figure 1. The semiconducting layer 35 forms the active layer 15 of the stack 10.

[0082] Planarization of the active layer 15 and / or complementary annealing of the stack 10 may be performed to prepare the active layer 15 and / or to improve the adhesion of the layers of the stack 10.

[0083] Figure 7 schematically illustrates the second implementation form of Method 20. In this implementation form, step 25, in which the insulating layer 14 is formed, is performed before step 23, in which the stack 10 is annealed. This reversal of steps simplifies the annealing step 23, in that it no longer needs to have an oxygen concentration of less than 10 ppm in the neutral atmosphere described earlier. It can be as low as less than 1%. Therefore, manufacturing method 20 is easier to implement, especially using industrial equipment.

[0084] In this implementation, the insulating layer 14 is formed on the SiC layer 12, as shown in Figure 8. It forms a barrier that reduces, or even stops, the diffusion of species originating from the surrounding atmosphere into the SiC layer 12. The stack 10 can then be simply annealed 23 in a neutral atmosphere with an oxygen concentration of less than 1%.

[0085] Step 25, which involves forming an insulating layer 14 before annealing, is preferably carried out by CVD deposition of a precursor, such as tetraethyl orthosilicate Si(OCH2CH3)4 (also known as "TEOS"). The CVD deposition is preferably plasma-excited (referred to as PECVD) to produce a layer of silicon dioxide SiO2 from the precursor. Such deposition may be carried out at a temperature between 300°C and 500°C so as not to interfere with step 23, which involves annealing the stack 10. The deposition is carried out to form an insulating layer 14 having a thickness 121 between 100 nm and 1000 nm, measured perpendicular to the plane P.

[0086] Step 25, which involves forming the insulating layer 14, is preferably performed within the same facility used to form the SiC layer 12. This prevents water vapor from the external atmosphere (e.g., from a cleanroom) from accumulating on the SiC layer 12 (which poses a risk of oxidizing the latter).

[0087] Method 20 may also include a step 26 to form an active layer 15 in order to manufacture an SOI substrate type stack 10. Unlike the packaging configuration in Figure 2, Method 20 according to Figure 7 forms only the active layer 15 after the annealing step 23. The active layer 15 may be formed by transfer from a donor substrate 30, as illustrated in Figure 6. However, the donor substrate 30 in this specification consists only of a crystalline or polycrystalline semiconducting layer 35. Therefore, step 25, in which an insulating layer 14 is formed before the annealing step 23, allows for simplification of step 26, in which only a single layer is transferred, in that only a single layer is transferred.

[0088] Step 26, which forms the active layer 15 by transfer, preferably includes light ion implantation, as previously described. However, the implantation depth is adjusted to transfer the active layer 15 having a thickness between 50 nm and 500 nm onto the stack 10. Bonding the donor substrate 30 is also preferably done as previously described. The free surface of the donor substrate 30 is also activated using oxygen or nitrogen plasma in particular to improve bonding.

[0089] The insulating layer 14 of the stack 10 may also include a step 24 of smoothing the surface 141 of the insulating layer for receiving the active layer 15, prior to the step 26 of forming the active layer 15. The smoothing step 24 is preferably similar to the smoothing described with reference to Figure 5.

[0090] Method 20 may also include a step 21 of providing a support layer 11 prior to the step of forming the SiC layer 12, in a manner common to the embodiments in Figures 2 and 7. In addition to providing the support layer 11, the providing step 21 may include preparing the support layer 11 so as to allow, or even facilitate, the diffusion of silicon atoms from the support layer 11 to the SiC layer 12 during the annealing step 23. Preparation may include the removal of organic or metallic contaminants, dopants, or particles. Removal may be carried out by implementing a known recipe, such as the so-called "CARO" wet recipe (aimed at removing organic contaminants), or a sequence of "RCA" recipes including, for example, the so-called "HF" wash (aimed at removing dopants), the so-called "SC1" wash (aimed at removing organic contaminants and particles), and / or the so-called "SC2" wash (aimed at removing metallic contaminants). When the support layer 11 contains native oxides, it is preferable to remove them by plasma, for example, preferably in step 22, which forms the SiC layer 12, or even in step 23, which receives the stack 10 annealing.

[0091] Figure 9 shows a bright-field image of a semiconductor stack 10 according to the present invention, obtained by Transmission Electron Microscopy ("TEM"). This stack was obtained using the method according to the present invention. The stack 10 comprises a single-crystal silicon support layer 11, a polycrystalline SiC layer 12, and a plurality of cavities 13 extending into the support layer 11 from the interface 112 between the support layer 11 and the SiC layer 12. The support layer 11 has a

[0001] plane at the interface 112 with the SiC layer 12 such that the cavities have facets extending along the {111} crystal plane (represented by arrows oriented along the

[0111] direction perpendicular to the (111) plane).

[0092] The different orientations of the SiC particles within the SiC layer 12 result in significant differences in contrast within this layer. However, such differences in contrast should not be interpreted as the presence of pores, bubbles, or voids. In the particular case of Figure 9, the SiC layer also has different crystalline structures, e.g., crystallized particles of the majority 3C polytype, as well as a small number of other polytype particles, including 4H and 6H. Such differences in structure also contribute to the appearance of the SiC layer 12 observed in Figure 9. The SiC layer 12 is nonporous. The support layer 11 is also nonporous.

[0093] In this image, the height of the cavity 13 is between 10 nm and 40 nm. This height is measured perpendicular to the plane P and from the SiC layer 12.

[0094] Each cavity 13 has a pyramidal shape and a base that aligns with the interface between the support layer 11 and the SiC layer 12. In other words, the base of the pyramid coincides with this interface. The apex of the pyramid is located within the support layer 11 at various depths depending on the size of the cavity 13.

[0095] As can be seen in Figure 9, the cavity 13 is located only at the interface between the support layer 11 and the SiC layer 12.

Claims

1. A method (20) for manufacturing a semiconductor stack (10), comprising a first silicon layer (11) called a support layer - To form a silicon carbide layer (12) extending on the support layer (11) having a thickness (121) measured from the support layer (11) that is greater than 5 nm (22), wherein the ratio of carbon atoms in the silicon carbide layer (12) within 20 nm from the support layer (11) is strictly greater than 50% (22), A method (20) comprising: annealing the support layer (11) and the silicon carbide layer (12) until a cavity (13) is formed (23), wherein each cavity (13) extends from the silicon carbide layer (12) into the support layer (11), and the concentration of oxygen in contact with the silicon carbide layer (12) during the annealing (23) is less than 10 ppm (23).

2. The method according to claim 1 (20), wherein annealing (23) is performed at a temperature between 900°C and 1100°C for a duration between 15 minutes and 2 hours.

3. The method according to claim 1 or 2 (20), wherein the silicon carbide layer (12) resulting from forming (22) is amorphous, and annealing (23) of the layer is performed to crystallize the silicon carbide layer (12) into a polycrystalline structure.

4. The method according to any one of claims 1 to 3 (20), wherein the support layer (11) is oriented in a plane (P), and the ratio of carbon atoms in the silicon carbide layer (12) within 20 nm from the support layer (11) is 70% or less.

5. The method according to any one of claims 1 to 4 (20), wherein the thickness (121) of the silicon carbide layer (12) is less than 500 nm.

6. The method according to any one of claims 1 to 5 (20), wherein the support layer (11) is oriented in a plane (P), and the cavity (13) extends perpendicular to the plane (P) and over a distance (133) measured from the silicon carbide layer (12) between 5 nm and 100 nm.

7. The method according to any one of claims 1 to 6 (20), comprising forming an insulating layer (14) extending over a silicon carbide layer (12) (25).

8. The method according to claim 7 (20), wherein forming an insulating layer (14) (25) is performed by deposition prior to annealing (23).

9. The method according to claim 7 or 8 (20), wherein annealing (23) the support layer (11), the silicon carbide layer (12), and the insulating layer (14) is performed in an atmosphere containing less than 1% oxygen.

10. A semiconductor stack (10), - The first silicon layer (11), referred to as the support layer, - A silicon carbide layer (12) extending on the support layer (11) having a thickness (121) measured from the support layer (11) that is greater than 5 nm, - A cavity (13), where each cavity (13) extends from the silicon carbide layer (12) into the support layer (11), and A semiconductor stack (10) comprising the above.

11. The semiconductor stack (10) according to claim 10, wherein the support layer (11) is oriented in a plane (P), and the cavity (13) extends perpendicular to the plane (P) and over a distance (133) measured from the silicon carbide layer (12) between 5 nm and 100 nm.

12. The semiconductor stack (10) according to claim 11, wherein each cavity (13) has a facet, and each facet is oriented parallel to the crystal plane, when the cavity (13) extends perpendicular to a plane (P) and over a distance (133) measured from the silicon carbide layer (12) that is greater than 15 nm.

13. The semiconductor stack (10) according to any one of claims 10 to 12, wherein each cavity (13) has a pyramidal shape and a bottom surface that aligns with the interface between the support layer (11) and the silicon carbide layer (12).

14. The semiconductor stack (10) according to any one of claims 10 to 13, wherein the cavity (13) is located only at the interface between the support layer (11) and the silicon carbide layer (12).

15. The semiconductor stack (10) according to any one of claims 10 to 14, wherein the silicon carbide layer (12) is nonporous.

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