Digital-to-analog converter circuit with a linear programmable gain stage

Abstract

Circuit (154A) includes a digital-to-analog converter (302) and a gain stage (312). The gain stage includes an operational amplifier (322), a variable gain network (340), and a leakage current control circuit (330). The first input (324) of the operational amplifier (322) is coupled to the input (314) of the gain stage (312). The output (328) of the operational amplifier (322) is coupled to the output (318) of the gain stage (312). The first terminal (342) of the variable gain network (340) is coupled to the second input (326) of the operational amplifier (322). The second terminal (344) of the variable gain network (340) is coupled to the output (328) of the operational amplifier (322). The first terminal (334) of the leakage current control circuit (330) is coupled to the output (328) of the operational amplifier (322). The second terminal (336) of the leakage current control circuit (330) is coupled to the third terminal (346) of the variable gain network (340).

Description

Technical Field

[0001] Digital-to-analog converters (DACs) are included in many integrated circuits (ICs) to convert digital signals to analog signals. There are various different DACs with respect to speed, resolution, accuracy, and output voltage range. To improve the output range of a DAC, a gain stage may be included in the output of the DAC. There are two problems that affect the accuracy or integral non-linearity (INL) of the topology of the DAC and the gain stage. One problem is leakage current in the gain stage. The other problem is noise in the DAC ground when the gain stage shares a ground.

Summary of the Invention

[0002] In one example, a circuit includes a digital-to-analog converter (DAC) having an input and an output, and a gain stage having an input and an output, where the input of the gain stage is coupled to the output of the DAC. The gain stage includes an operational amplifier having a first input, a second input, and an output, where the first input of the operational amplifier is coupled to the input of the gain stage and the output of the operational amplifier is coupled to the output of the gain stage. The gain stage also includes a variable gain network having a first terminal, a second terminal, and a third terminal, where the first terminal of the variable gain network is coupled to the second input of the operational amplifier and the second terminal of the variable gain network is coupled to the output of the operational amplifier. The gain stage also includes a leakage current control circuit having a first terminal and a second terminal, where the first terminal of the leakage current control circuit is coupled to the output of the operational amplifier and the second terminal of the leakage current control circuit is coupled to the third terminal of the variable gain network.

[0003] In another example, the circuit includes a common-ground control circuit element having a first terminal, a second terminal, and a third terminal; a DAC having an input, an output, and a first ground terminal, the first ground terminal of which is coupled to the first terminal of the common-ground control circuit element; and a gain stage having an input, an output, and a second ground terminal, the input of which is coupled to the output of the DAC, and the second ground terminal of which is coupled to the second terminal of the common-ground control circuit element. The gain stage includes an operational amplifier having a first input, a second input, and an output, the first input of which is coupled to the input of the gain stage, and the output of which is coupled to the output of the gain stage. The gain stage also includes a variable gain network having a first terminal, a second terminal, and a third terminal, the first terminal of which is coupled to the second input of which is coupled to which is coupled to which is coupled to the output of which is coupled to which is coupled to the output of which is coupled to which is coupled to which is coupled to the output of which is coupled to which is coupled to which is coupled to the output of which is coupled to which is coupled to the first terminal of which is coupled to which is coupled to the second input of which is coupled to which is coupled to the output the output of which is coupled to which is coupled to which is coupled to which The gain stage also includes a leakage current control circuit having a first terminal and a second terminal, the first terminal of the leakage current control circuit being coupled to the output of the operational amplifier, and the second terminal of the leakage current control circuit being coupled to a third terminal of the variable gain network.

[0004] In yet another example, the circuit includes a DAC having an input, an output, and a first ground terminal; a gain stage having a first input, a second input, an output, and a second ground terminal, the input of which is coupled to the output of the DAC; and a common ground control circuit element having a first terminal, a second terminal, and a third terminal, the first terminal of which is coupled to the first ground terminal, and the second terminal of which is coupled to the second ground terminal. The DAC is configured to receive a code at its input and, in response to the code, provide an analog signal at its output. The gain stage is configured to receive an analog signal at its first input, receive a gain control signal at its second input, generate a leakage current control signal based on the analog signal, and provide an output voltage in response to the analog signal, the gain control signal, and the leakage current control signal. The common ground control circuit element is configured to provide a first impedance between the first and third terminals of the common ground control circuit element and a second impedance between the second and third terminals of the common ground control circuit element. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of the example system.

[0006] [Figure 2] This is a block diagram of the example parametric measurement unit.

[0007] [Figure 3] This is a diagram illustrating an example of a digital-to-analog converter (DAC) circuit.

[0008] [Figure 4] This graph shows the drain-source voltage (VDS) and drain-source current (Ids) of the example transistor as functions of the digital input code.

[0009] [Figure 5]This is a schematic diagram of an example gain-selection circuit with reduced leakage current.

[0010] [Figure 6] This is a schematic diagram of an example leakage current control circuit.

[0011] [Figure 7] This is a schematic diagram of an example programmable gain stage for a DAC circuit.

[0012] [Figure 8A] This is a schematic diagram of another example DAC circuit.

[0013] [Figure 8B] Figure 8A is a cross-sectional view of the landing pad for the DAC circuit.

[0014] [Figure 9A] This is a schematic diagram of another example DAC circuit.

[0015] [Figure 9B] Figure 9A is a cross-sectional view of the landing pad for the DAC circuit.

[0016] [Figure 10] This is a graph of integral nonlinearity (INL) as a function of code for different DAC circuits. [Modes for carrying out the invention]

[0017] In the drawings, the same reference number or other reference identifier is used to represent the same or similar features. Such features may be identical or similar in function and / or structure.

[0018] This specification describes a digital-to-analog converter (DAC) circuit that includes a DAC core and a programmable gain stage. As used herein, a "DAC core" refers to a circuit that generates an analog signal (VFDAC) as a function of a digital input code (referred to herein as D or "code") and a reference voltage (VREF). The operation of the DAC core follows the equation VFDAC = VREF × D / 2 N where N is the number of bits in D. The topology of the DAC core can be a resistor matrix topology (e.g., R2R ladder topology, or resistor string topology), or another topology. As used herein, a "programmable gain stage" refers to a circuit that receives an analog input (e.g., VFDAC) and provides an analog output (e.g., VOUT), where the voltage range of the analog output is increased proportionally to the analog input. A programmable gain stage may also be referred to as an "adjustable gain stage".

[0019] The exemplary DAC circuit receives a digital input code (hereinafter abbreviated as "code"), receives a mode control signal to program (i.e., adjust) the output range of the programmable gain stage, generates a leakage current control signal, and operates to provide an analog signal in response to the code, the mode control signal, and the leakage current control signal. The code is a multi-bit code (e.g., an 18-bit code or other multi-bit code). In some examples, the mode control signal determines the gain and output range of the programmable gain stage. The leakage current control signal and associated leakage current reduction circuit elements improve the linearity of the exemplary DAC circuit. Another option for improving the linearity of the exemplary DAC circuit involves using a common ground control circuit element for the DAC core and the programmable gain stage. The common ground control circuit element takes into account and reduces the effect of the variable ground current of the programmable gain stage (e.g., variations as a function of the code) on the ground current of the DAC core. Stabilizing the ground current of the DAC core in this way improves the linearity of the exemplary DAC circuit.

[0020] FIG. 1 is a block diagram of an exemplary system 100. In some examples, system 100 represents an automatic test equipment (ATE) environment or other device under test (DUT) environment. As shown, system 100 includes a field programmable gate array (FPGA) 102, a parametric measurement unit (PMU) 120, and a DUT 182. In some examples, FPGA 102, PMU 120, and DUT 182 are separate integrated circuits (ICs). Other components of system 100 include a reference voltage (VREF) source 106, a buffer 108, an analog-to-digital converter (ADC) 110, and a printed circuit board (PCB) 184.

[0021] As shown, the FPGA has a first terminal 104 and a second terminal 105. The VREF source 106 has terminals. The buffer 108 has a first terminal and a second terminal. The ADC 110 has a first terminal 112, a second terminal 114, and a third terminal 116. The PMU 120 has a first terminal 122, a second terminal 124, a third terminal 126, a fourth terminal 128, a fifth terminal 130, and a sixth terminal 132. The PCB 184 has a first terminal 186 and a second terminal 188.

[0022] In the example of FIG. 1, the PMU 120 includes a forced voltage and current circuit element 140 and is used to force and measure voltages and currents to the DUT 182. The forced voltage and current circuit element 140 has a first terminal 142, a second terminal 146, a third terminal 148, a fourth terminal 150, and a fifth terminal 152. In some examples, the forced voltage and current circuit element 140 includes a DAC circuit 154, a buffer 156, a resistor R1, a first sense amplifier 158, a second sense amplifier 166, and a multiplexer 174. In the example of FIG. 1, the first sense amplifier 158 is a voltage sense amplifier and the second sense amplifier 166 is a current sense amplifier.

[0023] The DAC circuit 154 has a first terminal and a second terminal. The buffer 156 has a first terminal and a second terminal. The resistor R1 has a first terminal and a second terminal. The first sensing amplifier 158 has a first terminal 160, a second terminal 162, and a third terminal 164. The second sensing amplifier 166 has a first terminal 168, a second terminal 170, and a third terminal 172. The multiplexer 174 has a first terminal 176, a second terminal 178, a third terminal 180, and a fourth terminal 181.

[0024] The first terminal 122 of PMU120 is connected to the first terminal 104 of FPGA102. The second terminal 124 of PMU120 is connected to the terminal of VREF source 106. The third terminal 126 of PMU120 is connected to the first terminal of buffer 108. The second terminal of buffer 108 is connected to the first terminal 112 of ADC110. The second terminal 114 of ADC110 is connected to the output of VREF source 106. The third terminal 116 of ADC110 is connected to the second terminal 105 of FPGA102. The fourth terminal 128 of PMU120 is connected to the first terminal 186 of PCB184. The fifth terminal 130 of PMU120 is connected to the first terminal 186 of PCB184. The sixth terminal 132 of PMU120 is connected to the second terminal 188 of PCB184.

[0025] The first terminal 122 of the PMU 120 is also coupled to the first terminal 142 of the forced voltage and current circuit element 140. The third terminal 126 of the PMU 120 is coupled to the second terminal 146 of the forced voltage and current circuit element 140. The fourth terminal 128 of the PMU 120 is coupled to the third terminal 148 of the forced voltage and current circuit element 140. The fifth terminal 130 of the PMU 120 is coupled to the fourth terminal 150 of the forced voltage and current circuit element 140. The sixth terminal 132 of the PMU 120 is coupled to the fifth terminal 152 of the forced voltage and current circuit element 140.

[0026] The first terminal of the DAC circuit 154 is coupled to the first terminal 142 of the forced voltage and current circuit element 140. The second terminal of the DAC circuit 154 is coupled to the first terminal of the buffer 156. The second terminal of the buffer 156 is coupled to the first terminal of the resistor R1 and to the first terminal 160 of the first sensing amplifier 158. The second terminal of the resistor R1 is coupled to the third terminal 148 of the forced voltage and current circuit element 140 and to the second terminal 162 of the first sensing amplifier 158. The third terminal 164 of the first sensing amplifier 158 is coupled to the first terminal 176 of the multiplexer 174. The first terminal 168 of the second sensing amplifier 166 is coupled to the fourth terminal 150 of the forced voltage and current circuit element 140. The second terminal 170 of the second sensing amplifier 166 is coupled to the fifth terminal 152 of the forced voltage and current circuit element 140. The third terminal 172 of the second sensing amplifier 166 is coupled to the second terminal 178 of the multiplexer 174.

[0027] In operation, FPGA102 provides a digital control signal at its first terminal 104, and in response to the digital control signal and the operation of PMU120, it receives digitized measurement results from DUT182 at its second terminal 105, and operates to store / analyze the digitized measurement results.

[0028] The PMU120 operates to receive a digital control signal at its first terminal 122, receive VREF at its second terminal 124, provide a forced voltage and / or forced current at its fourth terminal 128 in response to the digital control signal, VREF, and the operation of the forced voltage and current circuit element 140, acquire a sensed current across the DUT182 in response to the forced voltage and / or forced current and the operation of the forced voltage and current circuit element 140, and provide a sensed current or sensed voltage at its third terminal 126 in response to the operation of the forced voltage and current circuit element 140.

[0029] The DAC circuit 154 of the forced voltage and current circuit element 140 operates to receive a digital control signal and to provide an analog signal in response to the digital control signal. Buffer 156 buffers the analog signal provided by the DAC circuit 154 and operates to provide a forced voltage and / or forced current. The forced voltage and / or forced current are provided to the DUT 182 via resistor R1. The voltage drop across resistor R1 and the operation of the first sensing amplifier 158 are used to determine the sensing current.

[0030] The first sensing amplifier 158 receives a first voltage at the first terminal of resistor R1 at its first terminal 160, and a second voltage at the second terminal of resistor R1 at its second terminal 162, and operates to provide a sensing current at its third terminal 164 in response to the first and second voltages. The voltages at the fifth terminal 130 and sixth terminal 132 of the PMU 120 and the operation of the second sensing amplifier 166 are used to determine the sensing voltage.

[0031] The second sensing amplifier 166 receives a second voltage at the second terminal of resistor R1 (in this example, the first terminal 186 of PCB 184) at its first terminal 168, and a third voltage at the second terminal 188 of PCB 184 at its second terminal 170, and operates to provide a sensing voltage at the third terminal 172 in response to the second and third voltages.

[0032] The multiplexer 174 receives a sensed current at its first terminal 176, a sensed voltage at its second terminal 178, and a control signal (CS1) at its third terminal 180, and in response to CS1, it operates to provide a sensed current or a sensed voltage at its fourth terminal 181.

[0033] In some examples, the DAC circuit 154 includes a DAC core and a programmable gain stage. The DAC circuit 154 receives a code (e.g., a digital control signal from FPGA 102), a mode control signal to program the output range of the programmable gain stage, generates a leakage current control signal, and operates to provide analog signals in response to the code, the mode control signal, and the leakage current control signal. In some examples, the mode control signal sets the gain and output range of the programmable gain stage. The leakage current control signal and associated leakage current reduction circuit elements improve the linearity of the DAC circuit 154. Another option to improve the linearity of the DAC circuit 154 involves using a common ground control circuit element for the DAC core and the programmable gain stage.

[0034] Figure 2 is a block diagram of an exemplary PMU120A. The PMU120A is an example of the PMU120 in Figure 1. As shown, the PMU120A includes a wired interface 202, a power supply circuit element 208, a state signaling circuit element 210, a clock circuit element 212, a signal input / output (I / O) protection circuit element 214, a memory circuit element 218, an arbitrary waveform generator circuit element 220, a digital processing circuit element 222, an internal calibration circuit element 224, a pin measurement circuit element 226, a switching circuit element 232, and a DUT board interface 234. In some examples, the pin measurement circuit element 226 includes a forced voltage and current circuit element 140 and a DAC circuit 154, as described in Figure 1.

[0035] The wired interface 202 may include, but is not limited to, digital isolator circuit elements, receiver circuit elements, serial communication interfaces (e.g., I2C), serial peripheral interfaces (SPI), voltage level translators, and / or other components. The power supply circuit element 208 may include, but is not limited to, a DC-DC converter, a low-dropout regulator (LDO), or other voltage / current regulators. In some examples, the power supply circuit element 208 may be omitted (e.g., an external power converter and / or LDO may be used).

[0036] Examples of state signaling circuit elements 210 include light-emitting diode (LED) drivers and associated control circuit elements. Examples of clock circuit elements 212 include oscillator circuit elements, clock generators, clock buffers, and phase-locked loops (PLLs). Examples of signal I / O protection circuit elements 214 include electrostatic discharge (ESD) protection circuit elements and transient voltage protection (TVP) circuit elements. Examples of memory circuit elements 218 include synchronous dynamic random access memory (SDRAM), flash memory, memory power and interface circuit elements, and voltage level translator circuit elements. Examples of arbitrary waveform generator circuit elements 220 include DACs, low-pass filters (LPFs), buffers, and multiplexers. Examples of digital processing circuit elements 222 include processors, digital signal processors (DSPs), or FPGAs.

[0037] Examples of internal calibration circuit elements 224 include circuit elements for temperature sensing, current sensing, voltage reference control, gain setting control, digital potentiometers, buffers, and I / O interfaces. Without limit, the internal calibration circuit elements 224 may determine the gain and offset for each PMU channel and each mode, perform forced voltage calibration, measured voltage calibration, forced current calibration, measured current calibration, and adjust or override the DAC and / or other control circuit elements in response to the determined gain, determined offset, and / or calibration results.

[0038] Examples of switching circuit elements 232 include multiplexers, VO expanders, switches, logic, electrically erasable programmable read-only memory (EEPROM), and relays. In some examples, the PMU 210A may also include internal calibration circuit elements, sensing voltage / sensing current circuit elements, digitizer circuit elements, and / or components. Using the DAC circuit 154, the accuracy of the forced current level and / or forced voltage level for DUT operation meets the target criteria. In some examples, the DAC circuit 154 is an 18-bit DAC with an accuracy of 1 LSB or less.

[0039] Figure 3 is a diagram of an exemplary DAC circuit 154A. DAC circuit 154A is an example of DAC circuit 154 in Figures 1 and 2. As shown, DAC circuit 154 includes a DAC core 302, a programmable gain stage 312, and a common ground control circuit element 354. The DAC core 302 has a first terminal 304, a second terminal 306, a third terminal 308, and a ground terminal 310. The programmable gain stage has a first terminal 314, a second terminal 315, a third terminal 316, a fourth terminal 317, a fifth terminal 318, and a ground terminal 319. The common ground control circuit element 354 has a first terminal 356, a second terminal 358, and a third terminal 360.

[0040] In some examples, the programmable gain stage 312 includes an operational amplifier 322, a leakage current control circuit 330, a variable gain network 340, a resistor R2, and an output voltage (VOUT) mode control circuit element 362. The operational amplifier 322 has a first terminal 324, a second terminal 326, and a third terminal 328. The leakage current control circuit 330 has a first terminal 332, a second terminal 334, a third terminal 336, and a ground terminal 338. The variable gain network 340 has a first terminal 342, a second terminal 344, a third terminal 346, a fourth terminal 348, a fifth terminal 350, a sixth terminal 351, and a ground terminal 352. The resistor R2 has a first terminal and a second terminal. The VOUT mode control circuit element 362 has a first terminal 363, a second terminal 364, a third terminal 365, and a fourth terminal 366. The VOUT mode control circuit element 362 may also include a ground terminal (not shown). In some examples, the VOUT mode control circuit element 362 includes a DAC core 368 and an amplifier circuit 376. The DAC core 368 has a first terminal 369, a second terminal 370, a third terminal 372, and a ground terminal 374. The amplifier circuit 376 has a first terminal 378, a second terminal 379, a third terminal 380, and a fourth terminal 382. In some examples, the amplifier circuit 376 may include multiple stages of an operational amplifier.

[0041] In the example in Figure 3, the first terminal 304 of the DAC core 302 receives a code. The second terminal 306 of the DAC core 302 receives VREF. The third terminal 308 of the DAC core 302 is coupled to the first terminal 314 of the programmable gain stage 312. The ground terminal 310 of the DAC core 302 is coupled to the first terminal 356 of the common ground control circuit element 354. The second terminal 358 of the common ground control circuit element 354 is coupled to the ground terminal 319 of the programmable gain stage 312. The second terminal 315 of the programmable gain stage 312 receives a control signal (CS2). The third terminal 316 of the programmable gain stage 312 receives a control signal (CS3). The fourth terminal 317 of the programmable gain stage 312 receives VREF. The fifth terminal 318 of the programmable gain stage 312 provides VOUT.

[0042] The first terminal 324 of the operational amplifier 322 is coupled to the first terminal 314 of the programmable gain stage 312. The second terminal 326 of the operational amplifier 322 is coupled to the first terminal 342 of the variable gain network 340. The third terminal 328 of the operational amplifier 322 is coupled to the fifth terminal 318 of the programmable gain stage 312.

[0043] The first terminal 332 of the leakage current control circuit 330 is coupled to the fourth terminal 317 of the programmable gain stage 312 and receives VREF. The second terminal 334 of the leakage current control circuit 330 is coupled to the third terminal 328 of the operational amplifier 322 and receives VOUT. The third terminal 336 of the leakage current control circuit 330 is coupled to the third terminal 346 of the variable gain network 340 and provides VCOM. The ground terminal 338 of the leakage current control circuit 330 is coupled to the ground terminal 319 of the programmable gain stage 312.

[0044] The second terminal 344 of the variable gain network 340 is coupled to the third terminal 328 of the operational amplifier 322. The fourth terminal 348 of the variable gain network 340 is coupled to the fourth terminal 317 of the programmable gain stage 312 and receives VREF. The fifth terminal 350 of the variable gain network 340 is coupled to the second terminal of resistor R2. The sixth terminal 351 of the variable gain network 340 is coupled to the second terminal 315 of the programmable gain stage 312 and receives CS2. The ground terminal 352 of the variable gain network 340 is coupled to the ground terminal 319 of the programmable gain stage 312.

[0045] The first terminal 363 of the VOUT mode control circuit element 362 is connected to the fourth terminal 317 of the programmable gain stage 312 and receives VREF. The second terminal 364 of the VOUT mode control circuit element 362 is connected to the third terminal 316 of the programmable gain stage 312 and receives CS3. The third terminal 365 of the VOUT mode control circuit element 362 is connected to the fourth terminal 348 of the programmable gain stage 312 and receives CS3. The fourth terminal 366 of the VOUT mode control circuit element 362 is connected to the first terminal of resistor R2. Specifically, the first terminal 369 of the DAC core 368 receives the code (CODE2). In some examples, the DAC core 368 is a 16-bit DAC core. In such examples, CODE2 is a 16-bit digital signal. The second terminal 370 of the DAC core 368 is connected to the first terminal 363 of the VOUT mode control circuit element 362 and receives VREF. The third terminal 372 of the DAC core 368 is coupled to the first terminal 378 of the amplifier circuit 376. The ground terminal 374 of the DAC core 368 is coupled to the ground terminal 319 of the programmable gain stage 312. The second terminal 379 of the amplifier circuit 376 is coupled to the second terminal 364 of the VOUT mode control circuit element 362 and receives CS3. The third terminal 380 of the amplifier circuit 376 is coupled to the third terminal 365 of the VOUT mode control circuit element 362. The third terminal 380 of the amplifier circuit 376 is coupled to the third terminal 365 of the VOUT mode control circuit element 362. The fourth terminal 382 of the amplifier circuit 376 is coupled to the fourth terminal 366 of the VOUT mode control circuit element 362.

[0046] In the example in Figure 3, the DAC core 302 receives a code at its first terminal 304, a VREF at its second terminal 306, and in response to the code and VREF, operates to provide an analog signal (VFDAC) at its third terminal 308. In some examples, the digital input signal to the DAC core 302 is an 18-bit DAC core. In such examples, the code is an 18-bit digital signal. The programmable gain stage 312 receives VFDAC at its first terminal 314, CS2 at its second terminal 315, CS3 at its third terminal 316, and VREF at its fourth terminal 317, and in response to the operation of the variable gain network 340, the leakage current control circuit 330, and the VOUT mode control circuit element 362, it operates to provide VOUT at its fifth terminal 318.

[0047] Specifically, the leakage current control circuit 330 receives VREF at its first terminal 332 and VOUT at its second terminal 334, and in response to VREF and VOUT, it operates to provide a leakage current control signal (VCOM) at its third terminal 336. In some examples, VCOM approximates VFDAC within a threshold tolerance range. The variable gain network 340 operates to receive VFDAC at its first terminal 342, VOUT at its second terminal 344, VCOM at its third terminal 346, a buffered VREF (VREFB) at its fourth terminal 348 or a buffered adjustment signal (ADJ) at its fifth terminal 350, and CS2 at its sixth terminal 351, providing a first resistance value between its first terminal 342 and its second terminal 344, and providing a second resistance value between its first terminal 342 and its ground terminal 352 in response to VFDAC, VOUT, VCOM, VREFB or ADJ, and CS2.

[0048] The VOUT mode control circuit element 362 receives VREF at its first terminal 363 and CS3 at its second terminal 364, and in response to VREF and CS3, it operates to provide VREFB at its third terminal 365, or in response to VREF and CS3, it provides a buffered control voltage (e.g., 1V to VREF) at its fourth terminal 366. Specifically, the DAC core 368 of the VOUT mode control circuit element 362 receives CODE2 at its first terminal 369 and VREF at its second terminal 370, and in response to the digital input signal and VREF, it operates to provide an analog signal at its third terminal 372. The amplifier circuit 376 of the VOUT mode control circuit element 362 receives an analog signal from the DAC core 368 at its first terminal 378, receives CS3 at its second terminal 379, and operates to either provide VREFB at its third terminal 380 in response to the analog signals from the DAC core 368 and CS3, or to provide a control voltage (e.g., 1V to VREF) at its fourth terminal 382 in response to the analog signals from the AC core 368 and CS3. R2 operates to adjust the buffered control voltage (e.g., 1V to VREF), resulting in the generation of ADJ for use in the variable gain network 340.

[0049] There are three types of VOUT available from the programmable gain stage 312: bipolar, unipolar, and asymmetric. When the desired VOUT is either bipolar or unipolar, the VOUT mode control circuit element 362 operates to provide VREFB to the variable gain network 340 in response to VREF and CS3. When the desired VOUT is asymmetric, the VOUT mode control circuit element 362 operates to provide a control voltage (e.g., 1V to VREF) in response to VREF and CS3, and as a result ADJ is provided to the variable gain network 340.

[0050] The common ground control circuit element 354 operates to receive a first ground current from the DAC core 302 at its first terminal 356, a second ground current from the programmable gain stage 312 at its second terminal 358, provide a first impedance between the first terminal 356 and the third terminal 360, and provide a second impedance between the second terminal 358 and the third terminal 360. In some examples, the common ground control circuit element 354 uses a ground buffer or compensation circuit to maintain a stable ground current from the DAC core 302 and to account for fluctuations in the ground current from the programmable gain stage 312.

[0051] Figure 4 is graph 400, showing the drain-source voltage (Vds) and drain-source current (Ids) of an exemplary transistor as functions of code. In Figure 4, the exemplary transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, Ids corresponds to the leakage current, a gate-source voltage (Vgs) of 0 is assumed, and a temperature of 105°C is assumed. As shown in graph 400, as Vds increases linearly from 0V to 4V, Ids increases rapidly initially and then flattens to a value of approximately 20nA. Such leakage current is undesirable and affects the VOUT accuracy of DAC circuits such as DAC circuit 154 in Figures 1 and 2, or DAC circuit 154A in Figure 3.

[0052] Figure 5 is a schematic diagram of an exemplary gain selector circuit 500 with reduced leakage current. In Figure 5, the gain selector circuit 500 includes two NMOS transistors MN1 and MN2 in series between the VFDAC node 502 and the ground terminal (REF_GND). When Figure 5 is related to Figure 3, REF_GND may be the ground terminal 319 of the programmable gain stage 312 in Figure 3. In the example in Figure 5, transistors MN1 and MN2 each include a first terminal, a second terminal, and a control terminal. The first terminal of MN1 is coupled to the VFDAC node 502. The second terminal of MN1 is coupled to the first terminal of MN2. The second terminal of MN2 is coupled to the ground terminal. The control terminals of MN1 and MN2 receive the same control signal (CS4). By applying VCOM (approximately equal to VFDAC) to node 504 between the second terminal of MN1 and the first terminal of MN2, Vds becomes approximately 0, and therefore leakage current through MN1 is avoided. Even when VCOM is provided, leakage current exists through MN2, but this leakage current does not affect the accuracy of VOUT. In some examples, the gain selection circuit 500 includes a switch SW1 to control when VCOM is provided to node 504. In operation, when transistors MN1 and MN2 are turned on (CS4 is high), switch SW1 is closed. When MN1 and MN2 are turned off (CS4 is low), switch SW1 is opened. In some examples, the gain selection circuit 500 is used within a variable gain network, such as the variable gain network 340 in Figure 3, to support variable gain selection where the leakage current problem is reduced and therefore the accuracy is improved.

[0053] Figure 6 is a schematic diagram of an exemplary leakage current control circuit 330A. The leakage current control circuit 330A is a model for the leakage current control circuit 330 in Figure 3. As shown, the leakage current control circuit 330A includes a voltage source 602 in series with a resistor Rs. The voltage source 602 operates to provide VCOM. After the voltage drop across Rs, the voltage at node 604 is VCOM' = VCOM - Vs. In the example in Figure 6, Vs = Rs × ΣIleak, where Ileak is the leakage current. In some examples, the leakage current control circuit 330A is achieved by providing VCOM using a replication network, where VCOM approximates VFDAC. As used herein, a replication network refers to a circuit for obtaining an exact replication of an active electrical parameter (e.g., a voltage such as VFDAC). In some examples, the replication voltage may be a scaled-down version of VFDAC. In some examples, the replication network is based on the topology of another circuit, such as the variable gain network 340. As an alternative option, the VCOM can also be generated using a replication DAC. The replication DAC may receive the same code, the same VREF, and have the same ground (e.g., REF_GND) as the DAC core 302. As used herein, the replication DAC refers to a DAC circuit for obtaining an exact replication of the active electrical parameters (e.g., output voltage such as VFDAC) of another DAC. In some examples, the replication DAC provides a replication of VFDAC from the DAC core 302 up to a target tolerance value of VFDAC.

[0054] Figure 7 is a schematic diagram of an exemplary programmable gain stage 312A for a DAC circuit such as the DAC circuit 154 in Figures 1 and 2, or the DAC circuit 154A in Figure 3. The programmable gain stage 312A in Figure 7 is an example of the programmable gain stage 312 in Figure 3. As shown, the programmable gain stage 312A includes an operational amplifier 322, a leakage current control circuit 330B, and a variable gain network 340A. The leakage current control circuit 330B is an example of the leakage current control circuit 330 in Figure 3 or the leakage current control circuit 330A in Figure 6. The variable gain network 340A is an example of the variable gain network 340 in Figure 3.

[0055] In the example shown in Figure 7, the leakage current control circuit 330B includes resistors R3a to R3f, transistors MN3 to MN12, and transistors MP1 to MP3 in the arrangement shown. Each of the resistors R3a to R3f has its own first and second terminals. Transistors MN3 to MN12 are NMOS transistors. Each of the transistors MN3 to MN12 has its own first terminal, its own second terminal, and its own control terminal. Transistors MP1 to MP3 are p-channel metal oxide semiconductor (PMOS) transistors. Each of the transistors MP1 to MP3 has its own first terminal, its own second terminal, and its own control terminal.

[0056] The variable gain network 340A includes resistors R4a to R4f, transistors MN13 to MN22, transistors MP4 to MP6, switches SW2 to SW6, and a controller 702 in the arrangement shown. Each of the resistors R4a to R4f has its own first and second terminals. Transistors MN13 to MN22 are NMOS transistors. Each of the transistors MN13 to MN22 has its own first terminal, its own second terminal, and its own control terminal. Transistors MP4 to MP6 are PMOS transistors. Each of the transistors MP4 to MP6 has its own first terminal, its own second terminal, and its own control terminal. Each of the switches SW2 to SW6 may be complementary metal oxide semiconductor (CMOS) transistors (i.e., parallel NMOS and PMOS transistors). The controller 702 has a first terminal 704 and a second terminal 706.

[0057] In some examples, resistors R3a to R3f each have a first resistance value, and resistors R4a to R4f each have a second resistance value. To reduce the power consumption of the leakage current control circuit 330B, the first resistance value can be greater than the second resistance value. In one example, the first resistance value is 150 kQ and the second resistance value is 30 kQ. In some examples, each of transistors MN3 to MN12 has a first size, each of transistors MN13 to MN22 has a second size, each of transistors MP1 to MP3 has a third size, and each of transistors MP4 to MP6 has a fourth size. The second size of each of transistors MN13 to MN22 is larger than the first size of each of transistors MN3 to MN12 (for example, the second size is 5 times larger than the first size). The fourth size of each transistor MP4 to MP6 is larger than the third size of each transistor MP1 to MP3 (for example, the fourth size is 5 times larger than the third size).

[0058] In the example in Figure 7, the first terminal of resistor R3a is coupled to the second terminal 334 of the leakage current control circuit 330B, receiving VOUT. The second terminal of resistor R3a is coupled to the third terminal 336 of the leakage current control circuit 330B, providing VCOM. The second terminal of resistor R3a is also coupled to the first terminals of resistors R3b, R3c, R3d, R3e, and R3f, respectively. The second terminal of resistor R3b is coupled to the first terminal of transistor MN3.

[0059] As shown in the diagram, the second terminal of transistor MN3 is connected to the first terminal of transistor MN4. The second terminal of transistor MN4 is connected to the ground terminal 338 of the leakage current control circuit 330B. The second terminal of resistor R3c is connected to the first terminal of transistor MN5. The second terminal of transistor MN5 is connected to the first terminal of transistor MN6. The second terminal of transistor MN6 is connected to the ground terminal 338 of the leakage current control circuit 330B.

[0060] As shown in the diagram, the second terminal of resistor R3d is connected to the first terminal of transistor MP1. The second terminal of transistor MP1 is connected to the first terminal 332 of the leakage current control circuit 330B, which receives VREF. The second terminal of resistor R3d is also connected to the first terminal of transistor MN7. The second terminal of transistor MN7 is connected to the first terminal of transistor MN8. The second terminal of transistor MN8 is connected to the ground terminal 338 of the leakage current control circuit 330B.

[0061] As shown in the diagram, the second terminal of resistor R3e is connected to the first terminal of transistor MP2. The second terminal of transistor MP2 is connected to the first terminal 332 of the leakage current control circuit 330B, which receives VREF. The second terminal of resistor R3e is also connected to the first terminal of transistor MN9. The second terminal of transistor MN9 is connected to the first terminal of transistor MN10. The second terminal of transistor MN10 is connected to the ground terminal 338 of the leakage current control circuit 330B.

[0062] As shown in the diagram, the second terminal of resistor R3f is connected to the first terminal of transistor MP3. The second terminal of transistor MP3 is connected to the first terminal 332 of the leakage current control circuit 330B and receives VREF. The second terminal of resistor R3f is also connected to the first terminal of transistor MN11. The second terminal of transistor MN11 is connected to the first terminal of transistor MN12. The second terminal of transistor MN12 is connected to the ground terminal 338 of the leakage current control circuit 330B.

[0063] As shown in the diagram, the first terminal of resistor R4a is coupled to the second terminal 344 of the variable gain network 340A and receives VOUT. The second terminal of resistor R4a is coupled to the first terminal 342 of the variable gain network 340A. The second terminal of resistor R4a is also coupled to the fifth terminal 350 of the variable gain network 340A and receives ADJ. The second terminal of resistor R4a is also coupled to the first terminals of resistors R4b, R4c, R4d, R4e, and R4f. The second terminal of resistor R4b is coupled to the first terminal of transistor MN13.

[0064] As shown in the diagram, the second terminal of transistor MN13 is coupled to the first terminal of transistor MN14. The second terminal of transistor MN14 is coupled to the ground terminal 352 of the variable gain network 340A. The second terminal of resistor R4c is coupled to the first terminal of transistor MN15. The second terminal of transistor MN15 is coupled to the first terminal of transistor MN16. The second terminal of transistor MN16 is coupled to the ground terminal 352 of the variable gain network 340A. The second terminal of resistor R4d is coupled to the first terminal of transistor MP4. The second terminal of transistor MP4 is coupled to the fourth terminal 348 of the variable gain network 340A and receives VREF. The second terminal of resistor R4d is also coupled to the first terminal of transistor MN17.

[0065] As shown in the diagram, the second terminal of transistor MN17 is coupled to the first terminal of transistor MN18. The second terminal of transistor MN18 is coupled to the ground terminal 352 of the variable gain network 340A. The second terminal of resistor R4e is coupled to the first terminal of transistor MP5. The second terminal of transistor MP5 is coupled to the fourth terminal 348 of the variable gain network 340A and receives VREF. The second terminal of resistor R4e is also coupled to the first terminal of transistor MN19.

[0066] As shown in the figure, the second terminal of transistor MN19 is coupled to the first terminal of transistor MN20. The second terminal of transistor MN20 is coupled to the ground terminal 352 of the variable gain network 340A. The second terminal of resistor R4f is coupled to the first terminal of transistor MP6. The second terminal of transistor MP6 is coupled to the fourth terminal 348 of the variable gain network 340A and receives VREF. The second terminal of resistor R4f is also coupled to the first terminal of transistor MN21. The second terminal of transistor MN21 is coupled to the first terminal of transistor MN22. The second terminal of transistor MN22 is coupled to the ground terminal 352 of the variable gain network 340A.

[0067] In the example in Figure 7, the first terminal of switch SW2 is connected to the third terminal 346 of the variable gain network 340A to receive VCOM. The second terminal of switch SW2 is connected to the second terminal of MN13 and the first terminal of MN14. The first terminal of switch SW3 is connected to the third terminal 346 of the variable gain network 340A to receive VCOM. The second terminal of switch SW3 is connected to the second terminal of MN15 and the first terminal of MN16. The first terminal of switch SW4 is connected to the third terminal 346 of the variable gain network 340A to receive VCOM. The second terminal of switch SW4 is connected to the second terminal of MN17 and the first terminal of MN18. The first terminal of switch SW5 is connected to the third terminal 346 of the variable gain network 340A to receive VCOM. The second terminal of switch SW5 is connected to the second terminal of MN19 and the first terminal of MN20. The first terminal of switch SW6 is connected to the third terminal 346 of the variable gain network 340A to receive VCOM. The second terminal of switch SW6 is connected to the second terminal of MN21 and the first terminal of MN22.

[0068] The first terminal 704 of controller 702 is coupled to the sixth terminal 351 of the variable gain network 340A to receive CS2. The second terminal 706 of controller 702 is coupled to the respective control terminals of transistors MN13-MN22, transistors MP4-MP6, and switches SW2-SW6 to provide their respective control signals CSn. In the example in Figure 7, the control signals CSn include s1n_a, s1n_b, s2n_a, s2n_b, s3n_a, s3n_b, s4n_a, s4n_b, s5n_a, s5n_b, s1p, s2p, and s3p. As shown, the control signals for transistors MN13-MN22 of the variable gain network 340A are also used for transistors MN3-MN12 of the leakage current control circuit 330B. Furthermore, the control signals for transistors MP4 to MP6 of the variable gain network 340A are also used for transistors MP1 to MP3 of the leakage current control circuit 330B. The control signal CSn also includes control signals for switches SW2 to SW6 (not specifically shown).

[0069] In some examples, the control signal CSn is selected based on CS2 to provide a target gain for the variable gain network 340A. ADJ is provided to adjust the range or mode of the variable gain network 340A. Exemplary modes include unipolar mode, bipolar mode, and asymmetric mode. The unipolar mode provides a VOUT with a range of 0V to +TV, where +TV is the target positive voltage. The bipolar mode provides a VOUT with a range of -TV2 to +TV2, where -TV2 is the target negative voltage and +TV2 is the target positive voltage of the same magnitude as -TV2. The asymmetric mode provides a VOUT with a range of -TV3 to +TV3, where -TV3 is the target negative voltage and +TV3 is the target positive voltage of a magnitude not equal to -TV3.

[0070] The leakage current control circuit 330A receives VREF at its first terminal 332 and VOUT at its second terminal 334, and operates to provide VCOM at its third terminal 336 in response to VREF, VOUT, resistors R3a to R3f, transistors MN3 to MN12 and associated control signals, and transistors MP1 to MP3 and associated control signals. In some examples, VCOM approximates VFDAC, which is the voltage at the first terminal 342 of the variable gain network 340A.

[0071] The variable gain network 340A receives VFDAC at its first terminal 342, VOUT at its second terminal 344, VCOM at its third terminal 346, VREF at its fourth terminal 348, ADJ at its fifth terminal 350, and CS2 at its sixth terminal, and operates to provide a first resistance value between its first terminal 342 and its second terminal 344 based on resistor R4a, and to provide a second resistance value between its first terminal 342 and its ground terminal 352 in response to VFDAC, VOUT, VCOM, VREF, ADJ, CS2, resistors R4b to R4f, transistors MN13 to MN22 and associated control signals, transistors MP4 to MP5 and associated control signals, and switches SW2 to SW6 and associated control signals. The variable gain network 340A and VOUT mode control elements such as the VOUT mode control element 362 in Figure 3 may support gains of 2, 4, and 6 in unipolar or bipolar mode, and may support gains of 6 and 9 in asymmetric mode. In the example in Figure 7, the exemplary gain of 2 is achieved in unipolar VOUT mode based on s1n_a and s1n_b being ON or asserted, and s2n_a, s2n_b, s3n_a, s3n_b, s4_a, s4_b, s5_a, s5_b, s1p, s2p, and s3p being OFF or deasserted.

[0072] Figure 8A is a schematic diagram of another example DAC circuit 800. As shown, the DAC circuit 800 includes a DAC core 302, a programmable gain stage 312B, and a common ground control circuit element 354A. The programmable gain stage 312B is a simplified representation of the programmable gain stage 312 in Figure 3 or the programmable gain stage 312A in Figure 7 after programming is complete. The common ground control circuit element 354A is an example of the common ground control circuit element 354 in Figure 3.

[0073] In the example in Figure 8A, the programmable gain stage 312B includes an operational amplifier 322 and resistors R5 and R6. In some examples, the values ​​of resistors R5 and R6 may be selected using a variable gain network such as the variable gain network 340 in Figure 3 or the variable gain network 340A in Figure 7. In other words, resistor R5 is an example of a first resistance value (e.g., R4a) of the variable gain network 340A in Figure 7. Resistor R6 is an example of a second resistance value of the variable gain network 340A in Figure 7, where the value of resistor R6 is a function of CS2, CS3, VOUT, and VREF.

[0074] As shown in the figure, the first terminal 356 of the common ground control circuit element 354A is coupled to the ground terminal 310 of the DAC core 302. The second terminal 358 of the common ground control circuit element 354A is coupled to the ground terminal 319 of the programmable gain stage 312B. The third terminal 360 of the common ground control circuit element 354A is coupled to ground. In some examples, the common ground control circuit element 354A includes a landing pad 802 and a ground buffer 812. The landing pad 802 includes a first metal layer M1, a second metal layer M2, and a third metal layer M3. A resistor R7 is connected between the first metal layer M1 and the second metal layer M2. A resistor R8 is connected between the second metal layer M2 and the third metal layer M3. In some examples, resistors R7 and R8 are metal resistors such as via resistors. As shown in the figure, the ground buffer 812 has a first terminal 814, a second terminal 816, and a third terminal 818.

[0075] In the example shown in Figure 8A, the first terminal 356 of the common ground control circuit element 354A is coupled to the ground terminal 310 of the DAC core 302. The second terminal 358 of the common ground control circuit element 354A is coupled to the ground terminal 319 of the programmable gain stage 312B. The metal layer M2 of the landing pad 802 is coupled to the first terminal 356 of the common ground control circuit element 354A. The metal layer M3 of the landing pad 802 is coupled to the second terminal 358 of the common ground control circuit element 354A. The metal layer M1 of the landing pad 802 is coupled to the first terminal 814 of the ground buffer 812. The second terminal 816 of the ground buffer 812 is coupled to the third terminal 360 of the common ground control circuit element 354A. The third terminal 818 of the ground buffer 812 is coupled to the metal layer M3 of the landing pad 802.

[0076] The common ground control circuit element 354A receives a first ground current from the DAC core 302 at its first terminal 356 and a second ground current from the programmable gain stage 312B at its second terminal 358, and operates to provide a first impedance between the first terminal 356 and the third terminal 360, and a second impedance between the second terminal 358 and the third terminal 360. More specifically, the landing pad 802 contributes to the first impedance using resistor R7 and to the second impedance using resistor R8. The first impedance is also a function of the impedance between the first terminal 814 and the second terminal 816 of the ground buffer 812. The second impedance is also a function of the impedance between the third terminal 818 and the second terminal 816 of the ground buffer 812.

[0077] Figure 8B is a cross-sectional view of the landing pad 802 for the DAC circuit 800 of Figure 8A. In the example of Figure 8B, metal layer M1 is below metal layer M2, and metal layer M3 is above metal layer M2. Between metal layer M1 and metal layer M2 is a metal via 806 that provides the target resistance for resistor R7. Between metal layer M2 and metal layer M3 is a metal via 804 that provides the target resistance for resistor R8. In different examples, the relative dimensions and / or orientations of metal layers M1, M2, and M3 may vary depending on the physical layout of the DAC circuit 800.

[0078] In some examples, the landing pad 802 may be a square metal stack with ground lines connected in a star configuration. The sensing / feedback line (first terminal 814) of the ground buffer 812 is coupled to metal layer M1 of the landing pad 802. The ground terminal 310 of the DAC core 302 is coupled to metal layer M2 of the landing pad 802. The ground terminal 319 of the programmable gain stage 312B is coupled to metal layer M3 of the landing pad 802. In some examples, resistors R7 and R8 are equivalent routing resistors between the metal stacks. Using the arrangement in Figure 8A, a code-dependent current from the programmable gain stage 312B flows through metal layer M3 to the third terminal 818 of the ground buffer 812. This current is Vg It does not affect the DAC (ground voltage at the ground terminal 310 of the DAC core 302), and therefore any potential INL degradation is avoided. In some examples, the metal layer M1 is tapped to the metal layer M2 in the middle, and Vg This provides the best virtual ground effect for the DAC. The ground current from the DAC core 302 flows through R8, generating a voltage error in the metal layer M3. However, this only generates an offset in VOUT, which can be calibrated.

[0079] Figure 9A is a schematic diagram of another example DAC circuit 900. As shown, the DAC circuit 900 includes a DAC core 302, a programmable gain stage 312B, and a common ground control circuit element 354B. In this case as well, the programmable gain stage 312B is a simplified representation of the programmable gain stage 312 in Figure 3 or the programmable gain stage 312A in Figure 7 after programming is complete. The common ground control circuit element 354B is an example of the common ground control circuit element 354 in Figure 3.

[0080] In the example of Figure 9A, the description provided for the programmable gain stage 312B in Figure 8A applies. As shown, the first terminal 356 of the common ground control circuit element 354B is coupled to the ground terminal 310 of the DAC core 302. The second terminal 358 of the common ground control circuit element 354B is coupled to the ground terminal 319 of the programmable gain stage 312B. The third terminal 360 of the common ground control circuit element 354B is coupled to ground.

[0081] In some examples, the common ground control circuit element 354B includes a landing pad 902 and a ground current compensation circuit 912. The landing pad 902 includes a metal layer ground pad (M5_GND_PAD), a metal layer DAC pad (M5_DAC), and another metal layer M4. A resistor R9 is connected between the metal layer M5_DAC and the metal layer M5_GND_PAD. A resistor R10 is connected between the metal layer M4 and the metal layer M5_GND_PAD. As shown, the ground current compensation circuit 912 has a first terminal 914, a second terminal 916, and a third terminal 918.

[0082] The metal layer M5_DAC of the landing pad 902 is coupled to the first terminal 356 of the common ground control circuit element 354B. The metal layer M4 of the landing pad 902 is coupled to the second terminal 358 of the common ground control circuit element 354B. The metal layer M5_GND_PAD of the landing pad 802 is coupled to the third terminal 360 of the common ground control circuit element 354B. The first terminal 914 of the ground current compensation circuit 912 receives a power supply voltage. The second terminal 916 of the ground current compensation circuit 912 receives a code (e.g., the 3 MSBs of D labeled as "D<N:(N - 3)" in FIG. 9A). The third terminal 918 of the ground current compensation circuit 912 is coupled to the metal layer M4 of the landing pad 902.

[0083] The common ground control circuit element 354B operates to receive a first ground current from the DAC core 302 at its first terminal 356, receive a second ground current from the programmable gain stage 312B at its second terminal 358, provide a first impedance between the first terminal 356 and the third terminal 360, and provide a second impedance between the second terminal 358 and the third terminal 360. More specifically, the landing pad 902 contributes to the first impedance using the resistor R9 and contributes to the second impedance using the resistor R10.

[0084] In the example of FIG. 9A, a ground buffer is avoided. Instead, the ground current compensation circuit 912 operates to inject current into the metal layer M4 of the landing pad 902 to cancel the ground current from the programmable gain stage 312B. In some examples, a low-resolution current DAC is used to generate the injected current. As a result, the injected current and the ground current from the programmable gain stage 312B are related to the code (D <n:0>) becomes a function of these two factors, and they cancel each other out. The total current flowing through M5_GND_PAD is the DAC ground current (Idac) + ground compensation current (Ic-a.code) + programmable gain stage current (a.code), and the total current is Ic+Idac. As a result, the total ground current to the third terminal 360 of the common ground control circuit element 354B is approximately constant or independent of the code.

[0085] In some examples, the current DAC for the ground current compensation circuit 912 is code <n:0>The injection current is generated using only three or four of the most significant bits (MSB). This is sufficient to reduce the INL error of an 18-bit DAC to an acceptable level using low-region resolution. In some examples, the common ground control circuit element 354B is used with single-channel products or low-voltage (e.g., less than 5.5V) multi-channel products where the die area is small and the routing distance between the DAC core 302, the programmable gain stage 312B, and the input / output ring (IORING) with I / O pads is below a threshold. As an alternative option, in products in ball grid array (BGA) or flip-chip ball grid array (FCBGA) packages, the use of a ground buffer can be avoided by placing the ground pads very close to the DAC core 302 and the programmable gain stage 312B.

[0086] In one example, the ground current compensation current cannot be obtained from the output stage of the programmable gain stage (e.g., the output of operational amplifier 322). This is because the output stage carries load current in addition to code-dependent ground current. In some examples, the target package size is a 16x16mm FCBGA with 144 pins. When there are many functional pins per channel, there may be only one REF_GND (signal ground) available for the entire chip. Also, in the final system, many PMUs may be densely packaged on the PCB, increasing the difficulty of adding external amplifiers to drive VREF and REF_GND. Therefore, VREF and REF_GND can have high impedance.

[0087] Figure 9B is a cross-sectional view of the landing pad 902 for the DAC circuit 900 of Figure 9A. In the example of Figure 9B, metal layer M4 is above metal layers M5_GNG_PAD and M5_DAC. In some examples, metal layers M5_GNG_PAD and M5_DAC may be formed as a single metal layer before etching or other metal removal techniques are applied to separate metal layers M5_GNG_PAD and M5_DAC. Between metal layer M4 and metal layer M5_GND_PAD is a metal via 904 providing the target resistance for resistor R10. Between metal layer M5_GND_PAD and metal M5_DAC is a metal via 906 providing the target resistance for resistor R9. In different examples, the relative dimensions and / or orientations of metal layers M4, M5_GNG_PAD and M5_DAC may vary depending on the physical layout of the DAC circuit 900.

[0088] Figure 10 is a graph of INL 1000 as a function of code for different DAC circuits. In graph 1000, INL 1002 without the ground buffer and common ground control circuit element (e.g., common ground control circuit element 354A in Figure 8A or common ground control circuit element 354B in Figure 9) varies as a function of code and increases by more than 1 LSB for an 18-bit DAC. INL 1004 with common ground control circuit element 354B varies somewhat as a function of code, but the change is limited to about 0.1 LSB for an 18-bit DAC. INL 1006 with common ground control circuit element 354A remains near zero, providing the best INL reduction for an 18-bit DAC.

[0089] Graph 1000 shows the INL improvement due to common-ground control circuit element options, but not the INL improvement due to leakage current reduction. As shown in Graph 1000, using the common-ground control circuit element 354A in Figure 8A reduces INL from over 1 LSB to nearly zero INL (compared to the case without the common-ground control circuit element in Figure 8A). Using the common-ground control circuit element 354B in Figure 9 reduces INL from over 1 LSB to nearly 0.1 LSB INL (compared to the case without the common-ground control circuit element in Figure 9). Leakage current reduction is another INL reduction option and can be used instead of or in addition to the common-ground control circuit element. In the worst-case leakage current scenario, leakage current reduction can reduce the INL due to switch leakage from 15 LSB to nearly 1 LSB. When both options (leakage current reduction and common-ground control circuit element) are implemented, the INL due to common-ground impedance becomes very low, and the main cause of INL becomes residual leakage in the switches.

[0090] In this description, the term “coupled” may encompass connections, communications, or signaling paths that enable a functional relationship consistent with the description herein. For example, if device A generates a signal that controls control device B to perform a certain action, then (a) in the first example, device A is coupled to device B by a direct connection, or (b) in the second example, if the intervening component C does not alter the functional relationship between device A and device B, device A is coupled to device B via the intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0091] Furthermore, in this document, the phrase "based on ~" means "based on ~ at least partially." Therefore, if X is based on Y, X can be a function of Y and any number of other factors.

[0092] A device “configured” to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform that function (e.g., by programming and / or wiring), or may be configured (or reconfigurable) by the user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be via the device’s firmware and / or software programming, or via the configuration and / or layout of hardware components, the interconnection of devices, or a combination thereof.

[0093] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, field-effect transistors (FETs) such as NFETs or PFETs, bipolar junction transistors (BJTs—e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in conjunction with one or more of the devices described herein. Transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0094] In the claims, there may be references to the control input of a transistor and its first and second terminals. In the context of an FET, the control terminal is the gate, and the first and second terminals are the drain and source. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter.

[0095] In this specification, a reference to an FET being "on" means that a conductive channel exists in the FET and that drain current can flow through the FET. A reference to an FET being "off" means that a conductive channel does not exist and therefore no drain current flows through the FET. However, an "off" FET may have current flowing through the transistor's body diode.

[0096] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0097] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current power supplies) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), adapted to be coupled to at least some of the passive elements and / or power sources, thereby forming the described structure, either at the time of manufacture or at a later point in time, for example, by an end user and / or a third party.

[0098] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to the functionality available before the replacement of components. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series or in parallel to provide the amount of impedance represented by the indicated resistors. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors that can each be coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors that are each coupled in series between the same two nodes as a single resistor or capacitor.

[0099] In the examples described, some elements are included in the integrated circuit, while other elements are outside the integrated circuit, but in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown to be outside the integrated circuit may be included in the integrated circuit, and / or some features shown to be inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0100] In the preceding description, the use of the term "grounding" includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings described herein. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10 percent of the parameter, and if the parameter is zero, it means a reasonable range of values ​​near zero.

[0101] Modifications to the described embodiments are permitted within the scope of the claims, and other embodiments are possible.

Claims

1. It is a circuit, A digital-to-analog converter (DAC) having inputs and outputs, A gain stage having an input and an output, Includes, The input of the gain stage is coupled to the output of the DAC. The aforementioned gain stage, An operational amplifier having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to the input of the gain stage, and the output of the operational amplifier is coupled to the output of the gain stage, A variable gain network having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the variable gain network is coupled to the second input of the operational amplifier, and the second terminal of the variable gain network is coupled to the output of the operational amplifier, A leakage current control circuit having a first terminal and a second terminal, wherein the first terminal of the leakage current control circuit is coupled to the output of the operational amplifier, and the second terminal of the leakage current control circuit is coupled to the third terminal of the variable gain network, A circuit that includes this.

2. The circuit according to claim 1, wherein the variable gain network is A first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the output of the operational amplifier and the second terminal of the first resistor is coupled to the second input of the operational amplifier, A second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second terminal of the first resistor, A first transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the second terminal of the second resistor, and the second terminal of the first transistor is coupled to the third terminal of the variable gain network, A second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first transistor, A circuit that includes this.

3. The circuit according to claim 2, wherein the variable gain network is A third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the second terminal of the first resistor, A third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the third resistor, and the second terminal of the third transistor is coupled to the third terminal of the variable gain network, A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, A circuit that includes this.

4. The circuit according to claim 3, wherein the variable gain network has a fourth terminal, and the variable gain network includes a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor being coupled to the second terminal of the third resistor, and the second terminal of the fifth transistor being coupled to the fourth terminal of the variable gain network.

5. The circuit according to claim 4, wherein the leakage current control circuit is A fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the output of the operational amplifier, and the second terminal of the fourth resistor is coupled to the second terminal of the leakage current control circuit, A fifth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the second terminal of the fourth resistor, A sixth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor is coupled to the second terminal of the fifth resistor, A seventh transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the second terminal of the sixth transistor, A circuit that includes this.

6. The circuit according to claim 5, wherein the leakage current control circuit is A sixth resistor having a first terminal and a second terminal, wherein the first terminal of the sixth resistor is coupled to the second terminal of the fourth resistor, An eighth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the eighth transistor is coupled to the second terminal of the sixth resistor, A ninth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the ninth transistor is coupled to the second terminal of the eighth transistor, A circuit that includes this.

7. The circuit according to claim 6, wherein the leakage current control circuit has a third terminal, and the leakage current control circuit includes a tenth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the tenth transistor being coupled to the second terminal of the sixth resistor, and the second terminal of the tenth transistor being coupled to the third terminal of the leakage current control circuit.

8. A circuit according to claim 1, wherein the DAC has a first grounding terminal, the gain stage has a second grounding terminal, and the circuit includes a common grounding control circuit element having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the common grounding control circuit element is connected to the first grounding terminal, and the second terminal of the common grounding control circuit element is connected to the second grounding terminal.

9. The circuit according to claim 8, A landing pad comprising a first metal layer, a second metal layer, and a third metal layer, wherein the second metal layer of the landing pad is coupled to the first terminal of the common ground control circuit element, and the third metal layer of the landing pad is coupled to the second terminal of the common ground control circuit element, A first set of metal vias between the first metal layer and the second metal layer, A second set of metal vias between the second metal layer and the third metal layer, A grounding buffer having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the grounding buffer is coupled to the first metal layer of the landing pad, the second terminal of the grounding buffer is coupled to the third terminal of the common grounding control circuit element, and the third terminal of the grounding buffer is coupled to the third metal layer of the landing pad, A circuit that further includes the following.

10. The circuit according to claim 8, A landing pad comprising a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer of the landing pad is coupled to the first terminal of the common ground control circuit element, the second metal layer of the landing pad is coupled to the second terminal of the common ground control circuit element, and the third metal layer of the landing pad is coupled to the third terminal of the common ground control circuit element, A first set of metal vias between the first metal layer and the third metal layer, A second set of metal vias between the second metal layer and the third metal layer, A ground current compensation circuit having an output coupled to the second terminal of the common ground control circuit element, wherein the ground current compensation circuit is configured to change the compensation current at its output in response to a code received at the input of the DAC, A circuit that further includes the following.

11. It is a circuit, A common ground control circuit element having a first terminal, a second terminal, and a third terminal, A digital-to-analog converter (DAC) having an input, an output, and a first grounding terminal, wherein the first grounding terminal is coupled to the first terminal of the common grounding control circuit element, A gain stage having an input, an output, and a second grounding terminal, wherein the input of the gain stage is coupled to the output of the DAC, and the second grounding terminal is coupled to the second terminal of the common grounding control circuit element, Includes, The aforementioned gain stage, An operational amplifier having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to the input of the gain stage, and the output of the operational amplifier is coupled to the output of the gain stage, A variable gain network having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the variable gain network is coupled to the second input of the operational amplifier, and the second terminal of the variable gain network is coupled to the output of the operational amplifier, A leakage current control circuit having a first terminal and a second terminal, wherein the first terminal of the leakage current control circuit is coupled to the output of the operational amplifier, and the second terminal of the leakage current control circuit is coupled to the third terminal of the variable gain network, A circuit that includes this.

12. The circuit according to claim 11, wherein the variable gain network has a fourth terminal, and the variable gain network is A first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the output of the operational amplifier and the second terminal of the first resistor is coupled to the second input of the operational amplifier, A second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second terminal of the first resistor, A first transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the second terminal of the second resistor, and the second terminal of the first transistor is coupled to the third terminal of the variable gain network, A second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first transistor, A third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the second terminal of the first resistor, A third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the third resistor, and the second terminal of the third transistor is coupled to the third terminal of the variable gain network, A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, A fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the third resistor, and the second terminal of the fifth transistor is coupled to the fourth terminal of the variable gain network, A circuit that includes this.

13. The circuit according to claim 12, wherein the leakage current control circuit has a third terminal, The aforementioned leakage current control circuit A fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the output of the operational amplifier, and the second terminal of the fourth resistor is coupled to the second terminal of the leakage current control circuit, A fifth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the second terminal of the fourth resistor, A sixth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor is coupled to the second terminal of the fifth resistor, A seventh transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the second terminal of the sixth transistor, A sixth resistor having a first terminal and a second terminal, wherein the first terminal of the sixth resistor is coupled to the second terminal of the fourth resistor, An eighth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the eighth transistor is coupled to the second terminal of the sixth resistor, A ninth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the ninth transistor is coupled to the second terminal of the eighth transistor, A 10th transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the 10th transistor is coupled to the second terminal of the 6th resistor, and the second terminal of the 10th transistor is coupled to the third terminal of the leakage current control circuit, A circuit that includes this.

14. A circuit according to claim 11, further comprising a ground buffer having a first terminal, a second terminal, and an output, wherein the first terminal of the ground buffer is coupled to the third terminal of the common ground control circuit element, and the output of the ground buffer is coupled to the second terminal of the common ground control circuit element.

15. A circuit according to claim 11, further comprising a ground current compensation circuit having an output coupled to the second terminal of the ground current compensation circuit, wherein the ground current compensation circuit is configured to change the compensation current at its output in response to a code received at the input of the DAC.

16. A circuit according to claim 11, wherein the common ground control circuit element includes a first metal layer of an integrated circuit (IC) coupled to the first terminal of the common ground control circuit element, a second metal layer of the IC coupled to the second terminal of the common ground control circuit element, a third metal layer of the IC coupled to the third terminal of the common ground control circuit element, a first resistor between the first metal layer and the second metal layer, and a second resistor between the second metal layer and the third metal layer.

17. It is a circuit, A digital-to-analog converter (DAC) having an input, an output, and a first ground terminal, A gain stage having a first input, a second input, an output, and a second ground terminal, A common ground control circuit element having a first terminal, a second terminal, and a third terminal, Includes, The DAC, In that input, a code is received, In response to the aforementioned code, an analog signal is provided at its output. It is configured in such a way, The input of the gain stage is coupled to the output of the DAC, and the gain stage, The first input receives the analog signal, The second input receives a gain control signal. Based on the aforementioned analog signal, a leakage current control signal is generated. The system provides an output voltage in response to the analog signal, the gain control signal, and the leakage current control signal. It is configured in such a way, The first terminal of the common grounding control circuit element is connected to the first grounding terminal, and the second terminal of the common grounding control circuit element is connected to the second grounding terminal, The aforementioned common grounding control circuit element is A first impedance is provided between the first terminal and the third terminal of the common ground control circuit element. A second impedance is provided between the second terminal and the third terminal of the common ground control circuit element. A circuit configured in such a way.

18. The circuit according to claim 17, wherein the gain stage includes a variable gain network, the gain stage is configured to generate the leakage current control signal based on a replication network of the variable gain network, the replication network uses a higher resistance value than the variable gain network, and the leakage current control signal approximates the analog signal.

19. A circuit according to claim 17, wherein the common ground control circuit element includes a ground current compensation circuit having an output coupled to the second terminal of the common ground control circuit element, and the ground current compensation circuit is configured to change the compensation current at its output in response to the code received at the input of the DAC.

20. A circuit according to claim 17, further comprising a ground buffer having a first terminal, a second terminal, and an output, wherein the first terminal of the ground buffer is coupled to the third terminal of the common ground control circuit element, and the output of the ground buffer is coupled to the second terminal of the common ground control circuit element.

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