Semiconductor device with low concentration, opposite-type doping drain-end gate electrode

Abstract

Examples of disclosed devices include, for example, a microelectronic device (100) having a source region (138) and a drain region (139) extending into a semiconductor substrate (103), such as an integrated circuit, wherein the semiconductor substrate (103) has a second conductivity type, and the source region (138) and drain region (139) have the opposite first conductivity type. A channel region having the second conductivity type extends between the source region (138) and the drain region (139). A gate electrode (128) on the channel region has a first portion (158) and a second portion (150). The first portion (158) has the second conductivity type and a first dopant concentration. The second portion (150) extends from the first portion toward the source region and has the second conductivity type and a second, even higher dopant concentration.

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronic devices. More specifically, the present disclosure relates to, but is not limited to, gate devices such as MOS transistors.

Background Art

[0002] Semiconductor components are continuously improved to operate reliably with smaller feature sizes. It is difficult to manufacture semiconductor devices that are increasingly high-performance while meeting reliability specifications.

Summary of the Invention

[0003] This summary is provided to introduce a concise excerpt of the disclosed concepts that will be further described in the detailed description, including the provided drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0004] The disclosed examples include microelectronic devices such as integrated circuits. One such example includes a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, and the source region and the drain region having an opposite first conductivity type. A channel region having the second conductivity type extends between the source region and the drain region. A gate electrode over the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second, higher dopant concentration.

[0005] The disclosed examples further include a method of forming an integrated circuit. In one example, a method includes forming source and drain regions having a first conductivity type that extend into a semiconductor substrate having a second, opposite conductivity type. A gate electrode is formed over the semiconductor substrate between the source and drain regions, and the gate electrode has a first portion and a second portion having a second conductivity type. The first portion is between the second portion and the drain region and has a first dopant concentration, and the second portion has a second, higher dopant concentration.

Brief Description of the Drawings

[0006] [Figure 1A] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation. [Figure 1B] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation. [Figure 1C] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation. [Figure 1D] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation. [Figure 1E] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation. [Figure 1F] FIG. 8 is a cross-sectional view of an exemplary microelectronic device including a transistor with a depletable recess gate electrode at various stages of formation.

[0007] [Figure 2] FIG. 29 is a graph showing a gate electrode doping profile for an exemplary microelectronic device having a depletable recess gate electrode of FIGS. 1A-1F.

[0008] [Figure 3A] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. [Figure 3B] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. [Figure 3C] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. [Figure 3D] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. [Figure 3E] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. [Figure 3F] This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.

[0009] [Figure 4] Figures 3A to 3F are graphs showing the gate electrode doping profiles for LDMOS transistors equipped with depletable resurface gate electrodes.

[0010] [Figure 5] This is a top view of an LDMOS transistor with a depletable resurface gate electrode in a racetrack configuration.

[0011] [Figure 6] This is a cross-sectional view of a DENMOS transistor equipped with a depletable resurf gate electrode.

[0012] [Figure 7] This graph compares the electric field in the channel under the gate electrode between the source and drain regions for a reference transistor and a transistor equipped with a depletable resurface gate electrode.

[0013] [Figure 8] This is a graph of a depletion-capable resurf gate electrode LDMOS transistor. [Modes for carrying out the invention]

[0014] This disclosure is described in relation to the accompanying drawings. The drawings are not drawn to scale and are provided solely for illustrative purposes. Several aspects of this disclosure are described below with reference to illustrative examples of application. Please understand that many specific details, relationships, and methods are described in order to understand this disclosure. This disclosure is not limited by the order of the actions or events illustrated, and some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all illustrated actions or events are required to implement the methodology according to this disclosure.

[0015] Furthermore, while some of the examples illustrated herein are shown in two-dimensional diagrams with various regions having depth and width, it should be clearly understood that these regions are only illustrative of parts of a device that is actually a three-dimensional structure. Therefore, when fabricated on an actual device, these regions will have three dimensions, including length, width, and depth. Also, although this disclosure may be illustrated by examples relating to active devices, these examples are not intended to limit the scope or applicability of this disclosure. Active devices of this disclosure are not intended to be limited to the illustrated physical structures. These structures are included to demonstrate the usefulness and applicability of this disclosure to various examples.

[0016] Note that terms such as top, bottom, above, above, and below may be used in this disclosure. These terms should not be interpreted as limiting the position or orientation of a structure or element, but rather should be used to indicate the spatial relationship between structures or elements. The terms “lateral” and “lateral” refer to a direction parallel to a plane corresponding to a surface of a certain layer, such as the top surface of a semiconductor substrate. Also, the term “approximately” as used herein may, in some cases, refer to a variation of ±5% to ±10% of the stated value. In other cases, the term “approximately” may refer to a variation of ±10% to ±20% of the stated value.

[0017] Microelectronic devices are continuously being improved to operate reliably with higher performance and smaller feature sizes. Manufacturing such microelectronic devices that meet area scaling and reliability requirements is challenging. Certain gate-controlled devices, such as metal-oxide-semiconductor (MOS) transistors, feature characteristics to support high-voltage operation, for example, voltages of approximately 20V, 30V, 40V, or higher, applied to the drain (or drain structure). Such MOS transistors may include a drain diffusion profile (or drain junction profile) designed to support the high voltage applied to the drain, for example, having an extension to distribute the voltage drop over a longer distance. Thus, such MOS transistors may be called drain-extended MOS transistors, e.g., drain-extended n-channel MOS (DENMOS) transistors, drain-extended p-channel MOS (DEPMOS) transistors, lateral diffusion MOS (LDMOS) transistors, and the group of DENMOS and DEPMOS transistors (sometimes called complementary drain-extended MOS or DECMOS transistors). Other gate-controlled microelectronic devices may include gate bipolar semiconductor devices, gate unipolar semiconductor devices, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor (MOS) triggered SCRs, MOS-controlled thyristors, and gate diodes.

[0018] Conventional field-effect transistors typically have a gate electrode above the channel region, the gate electrode being doped with the same conductivity type as the channel region, and the channel region being located between the source region and the drain region having the opposite conductivity type. Therefore, when the transistor is off, the gate electrode has a majority carrier type opposite to that of the channel region. For example, conventional n-type transistors, such as n-channel MOSFETs, have a p-type body region before channel inversion, and the gate electrode is typically highly doped for high conductivity. In the case of extended-drain (ED) transistors, the operating voltage may be limited by avalanche breakdown at the drain-body junction, which often occurs on the silicon surface. In contrast, an example of the present disclosure involves the innovative idea that by applying a light doping of the opposite doping type to the drain end of the gate electrode to the channel's majority charge carriers (e.g., electrons in the case of an n-channel device) when the channel is inverted, the gate electrode can be depleted by the electric field generated by the drain at high drain voltages. Thus, the gate electrode can act as a semiconductor "resurf" element, where resurf refers to reduced surface field. The gate electrode of the example device may be called a "depletable resurf gate electrode." This is because the carriers within the gate electrode are depleted simultaneously with the carriers in the drain drift region of the example ED device. Due to the electric field from the junction reverse bias, electrons and holes deplete each other. As a result, the electric field within the gate oxide at the drain end of the gate electrode is reduced, and aging degradation in microelectronic devices is reduced by decreasing failure mechanisms such as channel hot carriers (CHC) and gate oxide fracture. In this way, it is possible to improve the reliability of the device and / or reduce the size of the device.

[0019] Further context reveals that the gate electrode of an operating ED transistor performs a crucial function in controlling the silicon surface potential in the channel region. The bottom surface of the portion of the gate electrode that overlaps the channel must enforce metallic boundary conditions during gate switching to control the surface potential of the underlying channel silicon. As the gate electrode changes from 0V to a positive on-state voltage (NMOS transistor) or a negative on-state voltage (PMOS transistor), it transitions the silicon surface carrier profile through accumulation (transistor gate off-state), depletion (subthreshold), and ultimately to a strong inversion state (on-state).

[0020] To achieve this channel surface potential control, the portion of the semiconductor gate electrode where the lower surface lies above the channel must have a high dopant concentration. This is because, in order to maintain the metallic boundary conditions, the vertical electric field within the gate dielectric must be shielded by free carriers, resulting in zero electric field within the conductive interior of this portion of the gate electrode. To obtain a sufficiently high concentration of free carriers, the majority carrier doping concentration must be high in the portion of the gate electrode located above the channel. In some examples, the dopant concentration within the channel becomes high enough for the carrier profile to enter a degenerate state, i.e., at least 1 × 10⁻⁶. 19 cm -3 It is desirable that this be the case.

[0021] At the drain end of the gate electrode, the doping profile of the drain region underlaps with the gate electrode. In the gate-off state of the transistor, especially when the drain region is held under a high reverse bias (commonly called a blocking state), the majority carriers in this drain underlap portion of the gate electrode become depleted, exposing ionized majority carrier dopants. If the doping type of the gate electrode overlapping the drain region is the same as that of the drain, the majority carriers are attracted to the bottom near the drain end, including the drain end of the gate electrode, forming a storage layer that provides metallic boundary conditions. This generates a localized high electric field within the gate dielectric near the drain end, and the electric field can be further amplified by the curvature of the gate electrode corner at the bottom drain-opposite angle of the gate electrode. This localized electric field peak can become high enough to cause transistor degradation mechanisms such as channel hot carrier (CHC) injection and dielectric failure of the gate dielectric, which can lead to serious limitations on the use of the transistor at high drain cutoff voltages.

[0022] In an example consistent with this disclosure, the drain end of the gate is doped with a conductivity type (e.g., p-type) opposite to the conductivity type (e.g., n-type) of the drain doping. In this configuration, the majority carriers at the drain end of the gate electrode can be depleted under the action of the electric field generated by the reverse-biased drain. In various examples, the concentration of majority carriers at the drain end of the gate electrode is 1 × 10⁻⁶. 13 cm -2The dopant dose can be low enough to deplete without causing breakdown, as ensured by resurf conditions with lower dopant doses. A large portion of the gate (e.g., wider than the thickness of the gate electrode) can be depleted during reverse drain bias, and this portion of the gate electrode becomes a charged dielectric region that cancels out the exposed charge in the underlying silicon due to the opposite doping sign. This charge balance mitigates the high surface electric field across the entire overlapping region between the drain doping profile and the gate electrode, enabling drain-extended transistor operation at high cutoff drain voltages without causing high local electric field degradation effects, especially during pulse-mode operation. This mutual depletion effect between the drain carrier profile and the carrier profile at the drain-opposite end of the gate electrode is analogous to the mutual depletion of n-layer and p-layers in the resurf drift region; therefore, drain-extended transistors employing this gate electrode doping profile are called depletable resurf gate electrode drain-extended transistors.

[0023] The extent of depletion at the drain-opposite end of the gate electrode should be limited to avoid extending to source-opposite end features such as silicides on the gate electrode apex surface, in order to avoid fracture effects such as avalanche. To suppress such effects, in some examples, the doping concentration of the gate electrode increases as it approaches surface silicides or other features that could cause fracture.

[0024] Figures 1A to 1F illustrate a first type of electronic device to which the principles of the present disclosure can be advantageously applied. These figures show a cross-section of an exemplary microelectronic device 100, such as a MOS transistor, which includes a depletion-capable buried electrode 128 (see Figure 1B below), referred to herein as gate electrode 128. Without intending to be limiting, in this example, gate electrode 128 is implemented in an n-type metal oxide semiconductor (NMOS) transistor 101 shown in successive steps of an exemplary formation method. Other implementations of gate electrode 128 in a PMOS transistor are also within the scope of this example. In the exemplary NMOS transistor 101, the dopant of the first conductivity type is an n-type dopant and the dopant of the second conductivity type is a p-type dopant.

[0025] Figure 1A shows a microelectronic device 100 including an NMOS transistor 101 after formation of a gate dielectric layer 120 and a gate polysilicon layer 122. The structures and methods formed within the microelectronic device 100 prior to formation of the gate dielectric layer 120 may include an epitaxial layer 102 on a base wafer 104, collectively referred to herein as a substrate 103 having a top surface 106. The base wafer 104 may be, for example, p-type silicon having a dopant concentration of 1×10 17 cm -3 ~1×10 19 cm -3 . Alternatively, the base wafer 104 may be lightly doped with an average dopant concentration lower than 1×10 16 cm -3 . The epitaxial layer 102 may be, for example, p-type silicon having a dopant concentration of 1×10 15 cm -3 ~1×10 16 cm -3 . The epitaxial layer 102 is optional in some examples in that the NMOS transistor 101 may be formed directly within the base wafer 104.

[0026] The insulating layer of an NMOS transistor may be formed by either shallow trench insulation (STI) or localized silicon oxidation (LOCOS), and either method may be prior art or a method to be discovered in the future. An example shown includes an STI structure 105.

[0027] A p-type well region 108 (DWELL) is also formed on the substrate 103. A p-type dopant, which may contain boron and / or indium, is injected into the p-type well region 108. The p-type well region 108 has a depth of 0.5 μm to 1.5 μm from the top surface 106, with a volume of 3 × 10⁻¹⁶. 16 cm -3 ~1 × 10 19 cm -3 It may have a peak dopant density of . The p-type well region 108 (in some examples, in combination with the epitaxial layer 102) may be called the body region (e.g., the p-type body region) of the NMOS transistor 101. An n-type well region 131 is also formed on the substrate 103. The n-type well region 131 is doped with an n-type dopant which may include, for example, phosphorus or arsenic. The n-type well region 131 has a peak dopant density of 3 × 10¹⁶ at a depth of 0.5 μm to 1.5 μm from the top surface 106. 16 cm -3 ~1 × 10 19 cm -3 It may have a peak dopant density.

[0028] While not limited to the features formed on the substrate 103 of the NMOS transistor 101 as described in Figure 1A, the gate dielectric layer 120 and the gate polysilicon layer 122 are formed on the top surface 106. The gate dielectric layer 120 may be formed by high-temperature furnace operation or a rapid thermal process. Other methods for forming the gate dielectric layer 120 are also within the scope of this disclosure. The gate dielectric layer 120 may be of any material and thickness suitable for the technical application. The gate polysilicon layer 122 is formed on the gate dielectric layer 120 by conventional or future-discovered methods. In the illustrated example, the gate polysilicon layer 122 is formed by depositing polycrystalline silicon (also called polysilicon) by a deposition process using one or more silane-based precursors. In other examples, the gate polysilicon layer 122 may also be formed using a substitution gate process. The thickness of the gate polysilicon layer 122 may be in the range of about 50 nm to 300 nm. The gate polysilicon layer 122 is a semiconductor layer and may be undoped or doped during deposition. The gate polysilicon layer 122 may be a polySiGe layer, polyGe layer, polySiC layer, or another semiconductor that can be grown or deposited on the gate dielectric. In the example shown in Figure 1A, the gate polysilicon layer 122 is undoped. (Figure 3A shows an example of polysilicon doped during deposition).

[0029] Figure 1B shows a cross-section of the NMOS transistor 101 after the gate resist 124 has been formed and after gate plasma etching 126. Gate plasma etching 126 removes the pre-formed gate dielectric layer 120 and gate polysilicon layer 122 in areas not covered by the gate resist 124. The area below the gate resist 124 defines the gate electrode 128, which consists of the gate polysilicon layer 122 and gate dielectric layer 120 remaining after gate plasma etching 126. After gate plasma etching 126 is complete, the gate resist 124 is removed, and a wet or dry process may be used to clean the wafer surface.

[0030] Referring to Figure 1C, a sidewall spacer 130 is formed on the vertical surface of the gate electrode 128 and may extend 50 nm to 200 nm from the lateral edge of the gate electrode 128. After the formation of the sidewall spacer 130, a first source and drain resist 132 is deposited and patterned. A first source / drain injection 136 injects an n-type dopant into the substrate 103 through a source / drain opening 134 for injection into the source region 138, the drain region 139, and a portion 135 of the gate electrode. The first source / drain injection 136 may include one or more injection steps, and the source region 138, the drain region 139, and a portion 135 of the gate electrode 128 are filled to 1 × 10⁻¹⁶ 19 cm -3 ~1 × 10 21 cm -3 Conditions can be set such that the dopant concentration has a peak at a certain point. The doping level injected into portion 135 of the gate electrode is set so as not to be depleted during the operation of the NMOS transistor 101. The source region 138 and drain region 139 contain an average dopant density at least twice that of the epitaxial layer 102, which has a peak dopant density between 0.5 μm and 1.5 μm from the top surface 106. The source / drain resist extension 133 extends the resist beyond the edge of the gate electrode 128 toward the drain region 139. The source / drain resist extension 133 prevents the n-type dopant from the first source / drain injection 136 from extending beneath the gate electrode 128 after a subsequent thermal annealing process. After the formation of the source region 138 and drain region 139, the source and drain resists 132 are removed.

[0031] Figure 1D shows a cross-section of the NMOS transistor 101 after the second source / drain injection resist 144 has been deposited and patterned to form an opening 146 for the second source / drain injection 148. The second source / drain injection 148 can inject a dopant into the second source / drain region for the p-channel device (not shown) of the microelectronic device 100. The second source / drain injection 148 can also inject a p-type dopant through the opening 146 to form a heavily p-type doped portion 150 of the gate electrode 128.

[0032] Similar to the first source / drain injection 136, the second source / drain injection 148 can be performed in one or more steps. The second source / drain injection 148 injects a species containing boron (or indium) in an overall dose and energy that provides degenerate doping of a portion 150 of the gate electrode 128. For example, near the solubility limit of the dopant atom in the gate electrode 128, the average active dopant concentration is 1 × 10⁻¹⁶. 19 cm -3 The value is to exceed [value]. After the second source / drain injection 148, the second source / drain injection resist 144 is removed.

[0033] Figure 1E shows a cross-section after the resurf resist 152 has been deposited and patterned with an opening 154. The resurf implanter 156 implants p-type dopants using ion implantation to form the first portion 158 of the gate electrode 128. In the following discussion, the gate electrode portions 158, 150, and 135 may be referred to as the first portion 158, the second portion 150, and the third portion 135, respectively. In the first portion 158 of the gate electrode 128, the resurf region, the p-type doping density is sufficiently low to deplete during the operation of the NMOS transistor 101 and function as a resurf region. The resurf implanter 156 has a capacity of 1 × 10⁻⁶ 12 cm -2 ~1 × 10 13 cm -2The total dose can be achieved in one or more steps using an injection species containing one or more boron or indium. The second portion 150 of the gate electrode 128 is a heavily n-type doped third portion 135 (1 × 10⁻¹⁶). 18 cm -2 Between the above and the lightly p-doped first portion 158 of the gate electrode 128, there is a heavily p-doped region (1 × 10⁻¹⁰ 18 cm -3 The above is provided. The second portion 150 prevents the n-type dopant of the third portion 135 from reverse-doping the p-type dopant of the first portion 158. After the resurf injection 156, the resurf resist 152 is removed.

[0034] Figure 1F shows a cross-section of the NMOS transistor 101 after the first level 168 of the interconnection is completed. In some examples, the silicide shielding layer 160 may be formed on a first portion 158 of the gate electrode 128, partially extending over a second portion 150 of the gate electrode 128, leaving an area of ​​the second portion 150 uncovered by the silicide shielding layer 160. The silicide shielding layer 160 may be formed by depositing one or more sublayers of oxide, nitride, oxidnitride, or any combination thereof on the entire wafer, and patterning them to leave open areas where silicide formation is desired. In some examples, a metallic silicide layer 162 may be formed on the source region 138, the drain region 139, and the exposed portion of the gate electrode 128. The metal silicide layer 162 can provide resistive electrical connections to the source region 138, drain region 139, and gate electrode 128 with lower resistance compared to similar microelectronic devices without the metal silicide layer 162.

[0035] A premetallic dielectric (PMD) layer 164 is formed on the top surface 106 of the substrate 103. The PMD layer 164 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, or silicon dioxide. In some examples, the PMD layer 164 includes a PMD liner and a main dielectric sublayer formed on the PMD liner. The PMD layer 164 can then be planarized by a chemical mechanical polishing (CMP) process. Contacts 166, such as tungsten plugs, are formed within the PMD layer 164 to provide electrical connections to the source region 138 and the drain region 139. Interconnections 168, electrically connected to the contacts 166, are formed on the PMD layer 164 using any suitable metallization method to provide electrical contact between the NMOS transistor 101 and other components of the microelectronic device 100.

[0036] Figure 2 is a schematic diagram of the total dopant atom concentration (vertical axis) of the NMOS transistor 101 along the gate electrode 128. The gate electrode 128 shows a first region corresponding to the first portion 158 (Figure 1F) closest to the drain region 139, and has a p-type dopant density within a range that allows the first portion 158 to be depleted during operation. The second region corresponds to the second portion 150 (Figure 1F), which is also p-type doped and in contact with the first portion 158. The second portion 150 has a p-type doping density such that it cannot be depleted during operation, as shown in the figure. The third region corresponds to the third portion 135 (Figure 1F). The third portion 135 is n-type doped with a doping density such that it does not become depleted during the operation of the NMOS transistor 101. Therefore, while the third portion 135 can function as a switching element, the second portion 150 functions as a region that prevents the n-type dopant of the third portion 135 from back-doping the lightly p-type doped first region 158 that provides a resurf region.

[0037] Figures 3A to 3F illustrate a second type of electronic device to which the principles of this disclosure can be beneficially applied. These figures illustrate a method for forming an exemplary microelectronic device 300, which includes an LDMOS transistor 301 with a depletion resurf gate electrode (hereinafter shown as gate electrode 328 in Figure 3B). Figure 3A is a cross-sectional view of the microelectronic device 300 showing a region of the LDMOS transistor 301 after the gate dielectric layer 320 and the gate polysilicon layer 322 have been formed. The preceding process includes providing a substrate 303 comprising a semiconductor material (e.g., silicon, germanium, etc.) and having a top surface 304. The substrate 303 may include, for example, a portion of a bulk semiconductor wafer, a portion of a semiconductor wafer having an epitaxial layer, a portion of a silicon-on-insulator (SOI) wafer, or other structures suitable for forming the microelectronic device 300.

[0038] The substrate 303 may include an optional n-type embedded layer (NBL) 306 on the p-type layer 305. The p-type layer 305 may be part of a bulk semiconductor wafer on which the microelectronic device 300 is formed, for example, 1 × 10⁻¹⁶ 18 cm -3 ~1 × 10 19 cm -3 It may have a p-type dopant concentration of 1 × 10⁻¹⁵. Alternatively, the p-type layer 305 may have an average p-type dopant concentration of 1 × 10⁻¹⁵. 18 cm -3 It can be doped to a lower degree. NBL306 can be, for example, 2 μm to 10 μm thick, and 1 × 10⁻⁶ 19 cm -3 It may have higher n-type dopant (e.g., arsenic, antimony) concentrations. The substrate 303 may include an epitaxial layer 308 containing silicon on top of the NBL 306. The epitaxial layer 308 can be considered part of the substrate 303 and may have a thickness of, for example, 2 μm to 12 μm. The epitaxial layer 308 may have, for example, 1 × 10 15 cm -3 ~1 × 10 16 cm -3It can be p-type doped at a dopant concentration, i.e., "lightly". In the case where NBL306 is not present on the substrate 303, the epitaxial layer 308 may be directly on the p-type layer 305. Also, the epitaxial layer 308 is optional, and the LDMOS transistor 301 may be formed directly within the p-type layer 305.

[0039] To provide lateral isolation from other electrical devices on the substrate 303, an STI structure 310 may be included. A field relaxation dielectric layer 312 may be formed by a LOCOS process and may have a thickness in the range of 50 nm to 500 nm. The field relaxation dielectric layer 312 may have a tapered edge along its peripheral edge adjacent to the top surface 304 of the substrate 303. The tapered edge of the field relaxation dielectric layer 312 may be called a "birdsbeak" region. The exemplary LDMOS transistor 301 shown in Figures 3A to 3F includes an STI structure 310 and a field relaxation dielectric layer 312, but any of these features may be omitted in other examples within the scope of this disclosure. For example, the field relaxation dielectric layer 312 may be replaced with another STI structure. Similarly, the STI structure 310 may be replaced with another LOCOS structure, for example, a structure similar to the field relaxation dielectric layer 312.

[0040] A drift region 314 is formed in the substrate 303 below the field relaxation dielectric layer 312 and a portion of the gate dielectric layer 320. One or more n-type injections are performed to form the drift region 314 (also called an n-drift region) in the substrate 303. The n-type dopant defining the n-drift region 314 can be injected in one or more steps. For example, phosphorus can be injected at an energy of 1 × 10⁻¹⁶ with or without subsequent thermal cycling to form the n-drift region 314. 12 cm -2 ~1 × 10 13 cm -2 It can be injected in a total dose. Arsenic can also be injected in a similar dose, but at a relatively lower energy than phosphorus.

[0041] In addition to the n-drift region 314, a DWELL region 336 is formed. A p-type dopant, which may contain boron and / or indium, and an n-type dopant such as arsenic are injected into the DWELL region 336. The DWELL region 336 has a depth of 0.5 μm to 1.5 μm from the top surface 304, with a density of 1 × 10⁻¹⁶. 17 cm -3 ~1 × 10 19 cm -3 It may have a p-type peak dopant density. The n-type dopant density is 1 × 10⁻⁶. 18 cm -3 The layers are deposited at a higher depth, with the p-type / n-type junction depth being 50 nm to 300 nm from the top surface 304. The DWELL region 336 is p-type, but as a result of the final distribution of p-type and n-type dopants after the thermal annealing treatment preceding the processing steps shown in Figure 3A, an n-type region 338 is located within the DWELL region 336. The p-type portion of the DWELL region 336 (in some examples, in combination with the epitaxial layer 308) may be called the body region of the LDMOS transistor 301 (e.g., the p-type body region).

[0042] Continuing to refer to Figure 3A, the gate dielectric layer 320 may be formed by thermal oxidation of the top surface 304 by known methods, or the gate dielectric layer 320 may be formed by blanket deposition of a dielectric material such as silicon nitride (SiON) on the top surface 304. The gate dielectric layer 320 may have a thickness in the range of about 3 nm to about 50 nm, depending on the desired device characteristics. The gate polysilicon layer 322 is formed in a prior process step, for example, by a deposition process using one or more silane-based precursors. Alternatively, a substitution gate process may be used. In either case, conventionally known processes or processes to be developed in the future may be used to form the gate polysilicon layer 322, and the thickness of the gate polysilicon layer 322 may be in the range of about 50 nm to 300 nm. The gate polysilicon layer 322 may be undoped or in situ-doped during deposition. In this formation example, the gate polysilicon layer 322 is co-deposited with p-type precursors such as diborane, boron chloride, and tris(2,4-pentanedionic acid) gallium(III) and the amount of p-type dopant (integral value of the net p-type doping concentration over the entire thickness of the gate electrode) is 1 × 10⁻⁶ 12 cm -2 ~1 × 10 13 cm -2 The low doping concentration of the gate polysilicon layer 322 provides a resurfacing region that is defined in a later processing step.

[0043] Figure 3B shows a cross-section after the gate resist 324 has been deposited and patterned. The gate electrode 328 is defined using gate plasma etching 326. The gate electrode 328 may have a racetrack layout, similar to the gate electrode 528 shown in Figure 5. After the gate plasma etching 326 is complete, the gate resist 324 is removed. As shown in Figure 3B, the gate electrode 328 extends over a portion of the DWELL region 336, a portion of the n-type region 338, a portion of the epitaxial layer 308, and a portion of the n-drift region 314, where these regions intersect with the top surface 304. For convenience of explanation, the gate electrode 328 is defined as terminating where the gate dielectric layer meets the field relaxation dielectric layer 312, and the polysilicon on top of the field relaxation dielectric layer 312 is the polysilicon field plate 329. The end of the gate electrode 328 opposite to the polysilicon field plate 329 terminates on the DWELL region 336, for example, on the n-type region 338.

[0044] Figure 3C shows the LDMOS transistor 301 after sidewall spacers 340 have been formed on the gate electrode 328 and the vertical surface (e.g., sidewall) of the polysilicon field plate 329. The sidewall spacers 340 may be formed by currently known methods or methods to be developed in the future and may extend laterally from the corresponding sidewalls of the gate electrode 328 and the polysilicon field plate 329 at a distance of 50 nm to 200 nm.

[0045] Figure 3D shows a cross-section after the first source / drain resist 342 has been deposited and patterned to form openings 344 and 345 for the subsequent first source / drain ion implantation 346. Opening 345 allows n-type dopants from the source / drain implantation 346 to be implanted to form the drain region 350, and opening 344 allows n-type dopants to form the source region 348. The patterned source / drain resist 342 covers the gate electrode 328, thereby protecting the gate electrode 328 from the first source / drain implantation 346. The conditions for the first source / drain implantation 346 are such that the dopant concentrations in the resulting source region 348 and drain region 350 are 1 × 10⁻¹⁶. 19 cm -3 ~1 × 10 21 cm -3 A peak is formed, and the peak doping density can be set to 0.05 μm to 0.03 μm from the top surface 304. The average dopant density of the drain region 350 can be at least twice that of the n-drift region 314. The average dopant density of the source region 348 can be at least twice that of the DWELL region 336. The source region 348 is laterally separated from the edge of the gate electrode 328, but the n-type region 338 provides a continuous n-type path under the sidewall spacer 340, thereby providing electrical overlap with the gate electrode 328 so that the source region 348 is electrically coupled to the channel under the gate electrode 328. After the first source / drain injection 346, the source / drain resist 342 is removed.

[0046] Figure 3E shows the LDMOS transistor 301 after the second source / drain resist 354 has been deposited and patterned to form various source / drain resist openings for the second source / drain injection 358. The second source / drain injection 358 can inject p-type dopants into the source and drain regions of a p-channel transistor (not shown) simultaneously formed within the substrate 303. Similar to the first source / drain injection 346, the second source / drain injection 358 may be performed in one or more steps using injection species containing boron and / or indium, and this injection has an overall dose and energy suitable for providing degenerate doping to the source and drain regions of a p-channel transistor, for example, close to the dissolution limit of dopant atoms in the source and drain regions, 1 × 10⁻⁶ 19 cm -3 It has a higher effective average dopant density.

[0047] An opening 356 in the second source / drain resist 354 exposes a portion of the top surface 304 to form a back gate region 360. The back gate region 360 forms a continuous p-type conductive path to the DWELL region 336 and the epitaxial layer 308. The second source / drain resist 354 also includes an opening 357 positioned to selectively introduce the p-type dopant of the second source / drain injection 358 into a second portion 362 of the gate electrode 328.

[0048] As a result of the second source / drain injection 358, the second portion 362 of the gate electrode 328 is, for example, 1 × 10⁻¹⁰ 19 cm -3It is heavily p-type doped, such as being degenerately doped with a higher effective average dopant density. The first portion 323 of the gate electrode 328 remains lightly p-type doped due to the in situ doping described with respect to Figure 3A. In other words, the gate electrode 328 has a lightly p-type doped first portion 323 that may be depleted during the operation of the LDMOS transistor 301. Therefore, this first portion 323 of the gate electrode 328 can function as a depletion resurf region. The polysilicon field plate 329 on the field relaxation dielectric layer 312 abuts the first portion 323 of the gate electrode 328 at the intersection of the field relaxation dielectric layer 312 and the gate dielectric layer 320 and terminates on the field relaxation dielectric layer 312. The second portion 362 of the gate electrode 328 abuts the first portion of the gate electrode 328 near the intersection of the DWELL region 336 and the epitaxial layer 308 on the top surface 304 of the substrate 303, and terminates on the n-type region 338. The second portion 362 of the gate electrode 328 provides the switching region of the LDMOS transistor 301.

[0049] Figure 3F shows a cross-section of the LDMOS transistor 301 after the first level interconnection 370 is completed. The silicide shielding layer 364 protects the first portion 323 of the gate electrode 328 from silicide formation, while the silicide 366 is formed over the source region 348, the drain region 350, and the back gate region 360, as well as over a portion of the second portion 362 of the gate electrode 328.

[0050] A premetallic dielectric (PMD) layer 368 is formed on the top surface 304 of the substrate 303. The PMD layer 368 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, or silicon dioxide. In some examples, the PMD layer 368 includes a PMD liner and a main dielectric sublayer formed on the PMD liner.

[0051] Contacts 372 via the PMD layer 368 provide electrical contact to the source region 348, the drain region 350, and the back gate region 360, while interconnects 370 provide electrical connections to other components of the microelectronic device 300. Contacts 372 and interconnects 370 can be formed by any suitable metallization process.

[0052] Continuing with Figure 3F, Figure 4, similar to Figure 2, shows a schematic diagram of the total dopant atom concentration (vertical axis) of the LDMOS transistor 301 along the axis between the source region 348 and the drain region 350 via the gate electrode 328. On the right side of Figure 4, region 3 of the dopant concentration represents the first portion 323 of the gate electrode 328 closest to the drain region 350. The first portion 323 has a p-type dopant density that can deplete this portion of the gate electrode 328 during operation of the LDMOS transistor 301. Region 2 in Figure 4 corresponds to the second portion 362 (Figure 3F), which is also p-type doped and adjacent to the first portion 323. The second portion 362 has a p-type doping density that does not deplete during operation of the LDMOS transistor 301. Therefore, the second portion 362 can function as a switching element of the LDMOS transistor 301, while the first portion can provide a resurf effect. For the gate electrode 328, it is advantageous to have a resurf region integrated as a first portion 323 of the gate electrode 328, thereby providing a depletion region in which the electric field across the entire gate during operation is lower and more uniform than that of a gate electrode with a uniformly high doping level.

[0053] Figure 5 is a top view of a microelectronic device 500, which includes an LDMOS transistor 501 in a racetrack configuration, for example, a racetrack layout (or a generally rectangular layout with rounded corners) in which the dimensions in a first orientation are generally larger than the dimensions in a second orientation perpendicular to the first orientation. The racetrack configuration may also be called a closed-loop configuration. The LDMOS transistor 501 includes embodiments of the LDMOS transistor 501 described with reference to Figures 3A to 3F. The LDMOS transistor 501 includes a gate electrode 528 in a racetrack configuration.

[0054] As shown in Figure 5, the drain region 550 may be the linear innermost element of the LDMOS transistor 501, and the other elements shown form a series of concentric closed-loop elements around the drain region 550. The field relaxation dielectric layer 512 abuts against the drain region 550. The other elements of the LDMOS transistor 501 include the field plate 529, the first portion 523 and the second portion 562 of the gate electrode 528, the side wall 540, the source region 548, the back gate region 560, and the STI region 510.

[0055] Figure 6 shows a third type of electronic device to which the principles of this disclosure can be beneficially applied. This figure is a cross-sectional view of a microelectronic device 600, which includes a DENMOS transistor 601 having a depletion-resurf gate electrode 628. The gate electrode 628 is similar to the gate electrode 128 in Figures 1A to 1F in the following respects: The gate electrode 628 has a first portion 623 that terminates closest to the drain, is lightly p-doped and allows depletion during operation; a second portion 662 that abuts the first portion 623, is heavily p-doped and does not deplete during operation; and a third portion 650 that abuts the second portion 662, is heavily n-doped and does not deplete during operation. Similar to the structures described in Figures 1A-1F and 3A-3F, the first portion 623 of the gate electrode 628 is lightly p-doped and functions as a resurfacing element. This reduces the electric field at the drain end of the gate electrode 628, enabling a higher operating voltage and more favorable reliability characteristics against CHC and gate dielectric degradation compared to the DENMOS transistor 601 without a resurfacing element. Furthermore, at certain operating voltages, the gate electrode 628 including the first portion 623 acting as a resurfacing element can advantageously eliminate the need for a field relaxation dielectric layer, as the electric field across the entire gate electrode 628 is lower and more uniform, as shown in the exemplary DENMOS transistor 601.

[0056] Other structural elements of the DENMOS transistor 601 include a substrate 603, a top surface 604 of the substrate, a p-type wafer 605, an NBL layer 606, an optional p-type embedding layer 616, an epitaxial layer 608, an STI isolation 610, an n-type drift region 614, a p-type well 636, a source 646 as an injected region, a source region 647 after furnace annealing, a drain 648 as an injected region, a drain region 649 after furnace annealing, a back gate 660 as an injected region, a back gate region 661 after furnace annealing, a silicide isolation layer 664, a silicide layer 666, a PMD layer 668, a contact 672, and interconnects 670.

[0057] Figures 7 and 8 graphically illustrate some useful results from the described principle. Referring first to Figure 7, a graph is shown comparing the electric field under the gate electrode of a reference LDMOS transistor (dashed line) with that of a similar depletable resurf gate electrode LDMOS transistor (solid line) derived from TCAD modeling. The gate electrode of the reference transistor is conventionally uniformly n-type doped. The depletable resurf gate electrode of the LDMOS transistor has a lightly doped p-type region corresponding to a first portion 158 (Figure 1F) extending between the drain and source, and a heavily doped p-type region corresponding to a portion 150 extending from the first portion 158 toward the source. The lightly doped first region 158 acts as the resurf region of the depletable resurf gate electrode LDMOS transistor. The magnitude of the electric field under the gate electrode is shown between the source and drain regions. The two modeled transistors were simulated to operate in pulse mode with pulse lengths of less than 1 μs. As the graph shows, the electric field under the gate electrode of a depletable resurf gate electrode LDMOS transistor is more uniformly distributed than under the gate electrode of a reference transistor. Furthermore, the peak electric field value under the gate electrode is lower near the drain end of the gate electrode in the depletable resurf gate electrode LDMOS. This lower electric field under the gate electrode near the drain of the depletable resurf gate electrode is advantageous compared to the reference transistor because it improves the CHC characteristics and reliability against gate dielectric degradation.

[0058] Also, referring to Figure 8, in the depletable resurf gate electrode LDMOS transistor, the BVDSS in pulse mode is greater than the BVDSS in DC mode. The increase in BVDSS of the depletable resurf gate electrode LDMOS transistor in pulse mode may be advantageous in applications where resistance to inductive ringing is desired.

[0059] While various examples of this disclosure have been described above, it should be understood that these are merely illustrative and not limiting. Therefore, although the aforementioned examples describe the use of various resist layers (e.g., photoresist layers or photomask layers) to carry out various process steps (e.g., injection and etching steps), this disclosure is not limited thereto. For example, one or more hard masks (including one or more layers) may be patterned to define various regions for applying subsequent process steps (e.g., regions for accepting dopant atoms, regions for blocking etching agents). Furthermore, in some examples, the resist layers may include multi-level resists rather than single-level resists. Many modifications can be made according to the disclosed examples without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited by any of the above examples. Rather, the scope of this disclosure should be defined according to the following claims and their equivalents.

Claims

1. A microelectronic device, A source region and a drain region extending within a semiconductor substrate, wherein the semiconductor substrate has a second conductivity type, and the source region and the drain region have a first conductivity type opposite thereto, A channel region having the second conductivity type extending between the source region and the drain region, A gate electrode having a first portion and a second portion on the channel region, wherein the first portion has the second conductivity type and a first dopant concentration, and the second portion extends from the first portion toward the source region, and the second portion has the second conductivity type and a second, even higher dopant concentration, Microelectronic devices, including those mentioned above.

2. A microelectronic device according to claim 1, further comprising, below the first portion, a drain drift region of the first conductivity type extending from the drain region toward the source region, wherein the drain drift region has an average dopant concentration lower than the average dopant concentration of the drain region.

3. A microelectronic device according to claim 2, further comprising a field relaxation dielectric layer on the drain drift region, wherein the field relaxation dielectric layer extends from a gate dielectric layer located below the first portion of the gate electrode, and the field relaxation dielectric layer has a thickness greater than the thickness of the gate dielectric layer.

4. A microelectronic device according to claim 1, wherein the channel region includes a DWELL region having the second conductivity type.

5. A microelectronic device according to claim 1, wherein the second part is 1 × 10 １８ cm －３ It has a higher second dopant concentration, and the first portion is 1 × 10 １３ cm －２ A microelectronic device having a lower dose of the first dopant.

6. A microelectronic device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

7. A microelectronic device according to claim 1, further comprising a silicide shielding layer on the first portion of the gate electrode.

8. A microelectronic device according to claim 1, wherein a gate electrode field plate extends from the first portion of the gate electrode toward the drain region, the gate electrode field plate rests on a field relaxation dielectric layer, and the gate electrode field plate has a second conductivity type and the same dopant concentration as the first portion.

9. A microelectronic device according to claim 1, wherein a third portion of the gate electrode extends from the second portion toward the source region, and the third portion has the first conductivity type.

10. A microelectronic device according to claim 1, wherein the microelectronic device is selected from the group consisting of metal oxide semiconductor transistors, laterally diffused metal oxide semiconductor (LDMOS) transistors, drain-extended metal oxide semiconductor (DENMOS) transistors, gate bipolar semiconductor devices, gate unipolar semiconductor devices, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor (MOS) triggered SCRs, MOS-controlled thyristors, and gate diodes.

11. A microelectronic device according to claim 1, wherein the gate electrode comprises a semiconductor layer selected from the group consisting of polysilicon, polySiGe, polyGe, and polySiC.

12. A method for forming a microelectronic device, To form a source region and a drain region having a first conductivity type that extend into a semiconductor substrate having a second conductivity type opposite to the first, A gate electrode is formed on the semiconductor substrate between the source region and the drain region, Includes, A method wherein the gate electrode has a first portion and a second portion having the second conductivity type, the first portion being located between the second portion and the drain region and having a first dopant concentration, and the second portion having a second, even higher dopant concentration.

13. A method according to claim 12, further comprising forming a drain drift region having the first conductivity type in the semiconductor substrate, which extends from the drain region toward the source region, extends below the first portion, and terminates before the second portion, wherein the drain drift region has an average dopant concentration lower than the average dopant concentration of the drain region.

14. A method according to claim 12, further comprising forming a field relaxation dielectric layer on a drain drift region, wherein the field relaxation dielectric layer extends from a gate dielectric layer toward the drain region and has a thickness greater than the thickness of the gate dielectric layer.

15. A method according to claim 12, further comprising forming a DWELL in the semiconductor substrate having the second conductivity type and extending from the source region below the second portion toward the drain region.

16. The method according to claim 12, further comprising 1 × 10 １８ cm ‐３ The second portion having a higher second dopant concentration, and 1 × 10 １３ cm －２ A method further comprising forming the first portion having a lower amount of the first dopant dose.

17. A method according to claim 12, further comprising forming a silicide shielding layer on the first portion of the gate electrode, leaving a certain area of ​​the second portion not covered by the silicide shielding layer.

18. A method according to claim 12, further comprising forming a gate electrode field plate extending from the first portion of the gate electrode toward the drain region, wherein the gate electrode field plate rests on a field relaxation dielectric layer, and the gate electrode field plate has the second conductivity type and the same dopant concentration as the first portion.

19. The method according to claim 12, further comprising forming a third portion of the gate electrode that extends from the second portion toward the source region, the third portion having the first conductivity type and a doping concentration higher than 1×10 １８ cm -３ .

20. A method according to claim 12, wherein the first portion of the gate electrode is doped by in situ doping of the polysilicon layer on which the first portion is formed.

21. A method according to claim 12, wherein the first portion of the gate electrode is doped by ion implantation.

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