Semiconductor device having a hybrid junction layer and its fabrication process

Abstract

At least one aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a first substrate including a first region and a second region; a second substrate including a third region and a fourth region; a first junction layer including a first dielectric material for bonding the first region to the third region; and a second junction layer including a second dielectric material for bonding the second region to the fourth region. The first dielectric material is different from the second dielectric material.

Description

Technical Field

[0001] (Cross - reference to related patents and applications) This application claims the benefit of U.S. Non - Provisional Patent Application No. 18 / 309,678, filed on April 28, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] (Technical field of the present disclosure) The present disclosure relates to semiconductor devices and a method of bonding a plurality of semiconductor substrates.

Background Art

[0003] Typically, in semiconductor devices, various electronic components (e.g., transistors, diodes, resistors, capacitors, and the like) are formed on a semiconductor wafer. Thereafter, these semiconductor wafers (or one or more of their respective device dies) can be bonded to each other to form a functional device. These semiconductor wafers (or device dies) can be bonded together using any of a variety of bonding techniques for forming a functional device (e.g., stacked on top of each other).

Summary of the Invention

Means for Solving the Problems

[0004] At least one aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes a first substrate including a first region and a second region, a second substrate including a third region and a fourth region, a first bonding layer including a first dielectric material that bonds the first region to the third region, and a second bonding layer including a second dielectric material that bonds the second region to the fourth region. The first dielectric material is different from the second dielectric material.

[0005] In some embodiments, the first substrate includes a first dielectric layer disposed on the first substrate, a first interconnection structure extending into the first dielectric layer through a first bonding layer and having a first upper surface that does not overlap with the first bonding layer, and a second interconnection structure extending into the first dielectric layer through a second bonding layer and having a second upper surface that does not overlap with the second bonding layer.

[0006] In some embodiments, the second substrate includes a second dielectric layer disposed on the second substrate, a third interconnection structure extending into the second dielectric layer through the first bonding layer and having a third upper surface that does not overlap the first bonding layer, and a fourth interconnection structure extending into the second dielectric layer through the second bonding layer and having a fourth upper surface that does not overlap the second bonding layer.

[0007] In some embodiments, the first interconnection structure contacts the third interconnection structure when the first upper surface and the third upper surface are in contact with each other, and the second interconnection structure contacts the fourth interconnection structure when the second upper surface and the fourth upper surface are in contact with each other. The first bonding layer surrounds a portion of the combined sidewalls of the contacting first and third interconnection structures. The second bonding layer surrounds a portion of the combined sidewalls of the contacting second and fourth interconnection structures.

[0008] In some embodiments, the first substrate each includes a plurality of first logic devices in a first region and a plurality of first memory cells in a second region. The second substrate each includes a plurality of second logic devices in a third region and a plurality of second memory cells in a fourth region. The first interconnection structure is electrically coupled to at least one of the plurality of first logic devices, and the third interconnection structure is electrically coupled to at least one of the plurality of second logic devices. The second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.

[0009] In some embodiments, the first dielectric material includes silicon carbonitride, and the second dielectric material includes a high-k dielectric.

[0010] In some embodiments, the first dielectric material includes silicon carbonitride, and the second dielectric material includes silicon oxide.

[0011] At least another aspect of this disclosure relates to semiconductor devices. Each semiconductor device includes a first substrate having a first interconnection structure and a second interconnection structure in a first region and a second region, respectively; a second substrate having a third interconnection structure and a fourth interconnection structure in a third region and a fourth region, respectively, wherein the first interconnection structure is in contact with the third interconnection structure and the second interconnection structure is in contact with the fourth interconnection structure; a first bonding layer comprising a first dielectric material bonding the first region to the third region; and a second bonding layer comprising a second dielectric material bonding the second region to the fourth region. The first dielectric material is different from the second dielectric material.

[0012] In some embodiments, the first dielectric material includes silicon carbonitride, and the second dielectric material includes a high-k dielectric.

[0013] In some embodiments, the first dielectric material includes silicon carbonitride, and the second dielectric material includes silicon oxide.

[0014] In some embodiments, the first substrate includes a plurality of first logic devices in a first region and a plurality of first memory cells in a second region, and the second substrate includes a plurality of second logic devices in a third region and a plurality of second memory cells in a fourth region.

[0015] In some embodiments, the first interconnection structure is electrically coupled to at least one of a plurality of first logic devices, the third interconnection structure is electrically coupled to at least one of a plurality of second logic devices, the second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.

[0016] Further embodiments of this disclosure may relate to a method for manufacturing a semiconductor device. The method includes: preparing a first substrate including a first dielectric layer; stacking a first junction layer including a first dielectric material and a second junction layer including a second dielectric material on a first region and a second region of the first dielectric layer, respectively; preparing a second substrate including a second dielectric layer; stacking a third junction layer including a first dielectric material and a fourth junction layer including a second dielectric material on a third region and a fourth region of the second dielectric layer, respectively; and bonding the first substrate to the second substrate through the first to fourth junction layers such that the first region is bonded to the third region and the second region is bonded to the fourth region, respectively. The first dielectric material is different from the second dielectric material.

[0017] In some embodiments, the first dielectric material includes silicon carbonitride, and the second dielectric material includes a high-k dielectric or silicon oxide.

[0018] In some embodiments, the method further includes forming a first interconnection structure in a first region that extends into a first dielectric layer through a first bonding layer; forming a second interconnection structure in a second region that extends into a first dielectric layer through a second bonding layer; forming a third interconnection structure in a third region that extends into a second dielectric layer through a third bonding layer; and forming a fourth interconnection structure in a fourth region that extends into a second dielectric layer through a fourth bonding layer. After the step of bonding the first substrate to the second substrate, the first interconnection structure is in contact with the third interconnection structure, and the second interconnection structure is in contact with the fourth interconnection structure.

[0019] These and other embodiments and implementations are described in detail below. The information above and the detailed description below include illustrative examples of various embodiments and implementations and provide an overview or framework for understanding the nature and features of the claimed embodiments and implementations. The drawings provide examples and further understanding of various embodiments and implementations and are incorporated herein and constitute part of this specification. It will be readily apparent that multiple embodiments can be combined, and that features described in the context of one embodiment of the invention can be combined with other embodiments. Embodiments can be implemented in any convenient form. When used herein and in the claims, the singular forms "a," "an," and "the" refer to multiple subjects unless the context otherwise explicitly indicates.

[0020] (Brief explanation of the drawing) Non-limiting embodiments of this disclosure are described by reference to the attached figures, which are schematic and not intended to be drawn to actual size. Unless otherwise indicated as representing the background art, the figures represent aspects of this disclosure. For clarity, not all components are necessarily labeled in all drawings. [Brief explanation of the drawing]

[0021] [Figure 1] Figure 1 shows a flowchart illustrating a method for forming a semiconductor device having a hybrid junction layer according to various embodiments. [Figure 2] Figure 2 shows an exemplary top view of a semiconductor substrate that can be implemented in the method of Figure 1 according to various embodiments. [Figure 3] Figure 3 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments. [Figure 4] Figure 4 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments. [Figure 5] Figure 5 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments. [Figure 6]FIG. 6 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 1 according to various embodiments. [Figure 7] FIG. 7 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 1 according to various embodiments. [Figure 8] FIG. 8 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 1 according to various embodiments. [Figure 9] FIG. 9 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 1 according to various embodiments. [Figure 10] FIG. 10 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 1 according to various embodiments. [Figure 11] FIG. 11 shows a flowchart of a method for forming a semiconductor device having a hybrid bonding layer according to various embodiments. [Figure 12] FIG. 12 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 13] FIG. 13 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 14] FIG. 14 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 15] FIG. 15 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 16] FIG. 16 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 17] FIG. 17 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 18] FIG. 18 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments. [Figure 19] FIG. 19 shows cross-sectional views of the device during various manufacturing stages of the method of FIG. 11 according to various embodiments.

DETAILED DESCRIPTION OF THE INVENTION

[0022] In the following, exemplary embodiments depicted in the drawings will be described using specific terminology. However, it will be understood that this is not intended to limit the claims or the scope of this disclosure. Modifications and further alterations to the features of the invention illustrated herein, as well as further uses of the principles of the subject matter illustrated herein, which can be conceived by those skilled in the art who have obtained this disclosure, are included within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other modifications may be made without departing from the spirit or scope of this disclosure. The exemplary embodiments described in the detailed description are not intended to limit the subject matter presented.

[0023] Wafer-to-wafer bonding and chip-to-chip bonding are being implemented to continue scaling the power-performance-area-cost (PPAC) of complex circuits, such as in Systems on Chip (SoC) implementations. Many bonding techniques utilize interdielectric bonding to form integrated interconnect structures through hybrid bonding techniques that enable the formation of interconnects at the bonding interface between two wafers or dies. Current technologies typically use a single dielectric material as the bonding layer for each wafer. Because each wafer to be bonded is covered and homogenized by a single bonding layer, some trade-offs may sometimes be required. For example, bonding layers with silicon carbonitride (SiCN) are typically used to prevent copper migration, but SiCN can be associated with relatively weak bonding strength. In another example, bonding layers with silicon oxide (SiO2) and / or high-k dielectric materials can exhibit high bonding strength, but such materials can typically be associated with copper diffusion problems and / or high RC delay. Therefore, existing technologies for integrating wafers using hybrid bonding techniques are not entirely satisfactory in many respects.

[0024] This disclosure provides various embodiments of semiconductor devices having at least first and second semiconductor wafers (or substrates) joined together using one or more hybrid junction layers, and methods for forming them. Depending on the embodiment, each of the first and second semiconductor wafers may have a first region and a second region configured to form different functional circuits, respectively. The first and second regions may be oriented laterally relative to each other. In non-limiting examples, the first region may be configured to form a plurality of logic devices (e.g., transistors, etc.), and the second region may be configured to form a plurality of memory cells (e.g., NAND memory cells, NOR memory cells, etc.). Given such different functional properties, the “hybrid” junction layer may, according to various embodiments of this disclosure, have a first dielectric material and a second dielectric material covering the first (logic) region and the second (memory) region of each of the first and second wafers, respectively. A first dielectric material (for the logic domain), such as SiCN, may be directed to provide low RC delay and prevent copper diffusion, while a second dielectric material (for the memory domain), such as SiO2 and / or a high-k dielectric material, may be directed to provide high bonding strength. Therefore, the semiconductor devices of this disclosure can have different wafers that are firmly bonded together while avoiding the problems identified above.

[0025] Figure 1 shows a flowchart of Method 100 for forming a semiconductor device (e.g., a package) having at least two bonded (e.g., bonded) wafers, dies, or substrates, based on two hybrid junction layers initially formed on two substrates. Note that Method 100 is merely an example and is not intended to limit the present disclosure. Therefore, understand that additional operations may be provided before, during, and after Method 100 in Figure 1, and that some other operations may only be briefly described herein.

[0026] In various embodiments, each of the substrates to be bonded has at least a first region and a second region, each configured as a real estate for a plurality of logic devices and a plurality of memory cells. Figure 2 shows an exemplary top view (or layout) of such first and second regions arranged laterally on a substrate 200. As shown, the substrate 200 includes a first region 200A and a second region 200B. A plurality of logic devices (e.g., transistors) 210 are formed within the first region 200A, and a plurality of memory arrays 220 and 230 are formed within the second region 200B. In some embodiments, the logic devices 210 and memory arrays 220-230 can be operably coupled to one another via a bus that can transmit and / or receive data based on an interface, such as, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).

[0027] For example, the logic device 210 can function as at least one of the following: an I / O circuit, a logic control circuit, a command register (circuit), an address register (circuit), a sequencer (circuit), a row decoder (circuit), or a sensing amplifier (circuit). Each of the memory arrays 220-230 may contain multiple memory cells, each of which is configured to store data. For example, each of the memory arrays 220-230 may include a dynamic random-access memory (DRAM) array, a static random-access memory (SRAM) array, a resistive random-access memory (RRAM) array, a magnetoresistive random-access memory (MRAM) array, a phase-change random-access memory (PCRAM) array, etc.

[0028] Furthermore, the operation of Method 100 may be associated with cross-sectional views of exemplary semiconductor devices 300 at various manufacturing stages, as shown in Figures 3 to 10, which will be described in more detail below. The semiconductor device 300 includes at least two substrates, each of which may be a mounting configuration of a substrate 200 including a first region and a second region configured to accommodate a logic device and a memory cell, respectively, as shown in Figure 2. It should be understood that the semiconductor devices 300 shown in Figures 3 to 10 may include several other devices, such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of this disclosure.

[0029] Corresponding to operation 102 in Figure 1, Figure 3 is a cross-sectional view of a semiconductor device 300 in which the first substrate 302 is covered with the first dielectric material 306, in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0030] The first substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or similar, which may or may not be doped (e.g., with p-type or n-type dopants). Depending on the embodiment, the first substrate 302 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is typically provided on a substrate that is a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. For example, the semiconductor material of the first substrate 302 may include silicon; compound semiconductors containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors containing GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0031] As described above, the first substrate 302 includes a first region 302A and a second region 302B, respectively, configured to form a logic device (not shown) and a memory cell (not shown). In various embodiments, multiple inter-metal dielectric (IMD) materials are formed on the logic device and the memory cell, i.e., on both the first region 302A and the second region 302B. Multiple interconnection structures may be formed within the IMD material 304, and the IMD material 304 is configured to electrically isolate adjacent interconnection structures. This will be described below. The IMD material 304 may be formed from one or more dielectric materials, such as SiO2. A first dielectric material 306 is formed on the IMD material 304. In the current manufacturing stage, the first dielectric material 306 may be formed on both the first region 302A and the second region 302B. In various embodiments, the first dielectric material 306 may include SiCN, or other suitable materials that can be used to reduce copper diffusion (when forming interconnect structures) and / or to reduce RC delay (between adjacent interconnect structures).

[0032] Corresponding to operation 104 in Figure 1, Figure 4 is a cross-sectional view of a semiconductor device 300 in one of various manufacturing stages according to various embodiments of the present disclosure, in which the first dielectric material 306 is patterned to cover only the first region 302A.

[0033] In various embodiments, the first dielectric material 306 is patterned using lithography. For example, a patternable layer (e.g., a photoresist layer) 410 is formed on a first region 302A of the first dielectric material 306, followed by an etching process to remove the uncovered portion of the first dielectric material 306 (i.e., a second region 302B of the first dielectric material 306). As a result, a portion of the IMD material 304 within the second region 302B can be exposed, as shown in Figure 4.

[0034] Corresponding to operation 106 in Figure 1, Figure 5 is a cross-sectional view of a semiconductor device 300 in one of various manufacturing stages according to various embodiments of the present disclosure, in which a second dielectric material 506 is formed to cover both the first region 302A and the second region 302B.

[0035] When the portion of the IMD material 304 within the second region 302B is exposed, the second dielectric material 506 is formed to completely cover both the first region 302A and the second region 302B. In various embodiments, the second dielectric material 506 may differ from the first dielectric material 306. The second dielectric material 506 may be configured to provide a strong bond strength with another substrate, while the first dielectric material 306 may be configured to reduce copper diffusion and / or reduce RC delay. For example, the second dielectric material 506 may include SiO2 and / or a high-k dielectric material.

[0036] Corresponding to operation 108 in Figure 1, Figure 6 is a cross-sectional view of a semiconductor device 300 having a plurality of first recesses 610 and a plurality of second recesses 620 formed thereon in one of various manufacturing stages according to various embodiments of the present disclosure.

[0037] As shown in the figure, the first recess 610 is formed within the IMD material 304, the first dielectric material 306, and the second dielectric material 506, and the second recess 620 is formed within the IMD material 304 and the second dielectric material 506. In various embodiments, the first recess 610 extends through the second dielectric material 506, the first dielectric material 306, and the IMD material 304 and can reach (e.g., make electrical contact with) a logic device formed in the first region 302A. On the other hand, the second recess 620 extends through the second dielectric material 506 and the IMD material 304, but does not necessarily have to reach (e.g., make electrical contact with) a memory cell formed in the second region 302B.

[0038] Corresponding to operation 110 in Figure 1, Figure 7 is a cross-sectional view of a semiconductor device 300 in one of various manufacturing stages according to various embodiments of the present disclosure, in which a metal material 700 is formed to fill a first recess 610 and a second recess 620.

[0039] Multiple interconnection structures can be formed by filling the first recess 610 and the second recess 620 with a metallic material 710. For example, multiple first interconnection structures 710 can be formed within the first region 302A, and multiple second interconnection structures 720 can be formed within the second region 302B. The first interconnection structures 710 can be connected to logic devices formed within the first region 302A, while the second interconnection structures 720 do not necessarily have to be connected to memory cells formed within the second region 302B. The metallic material 700 may include at least one of Cu, Al, W, Ti, TiN, Ta, and TaN, or a combination thereof.

[0040] Corresponding to operation 112 in Figure 1, Figure 8 is a cross-sectional view of a semiconductor device 300 in which a polishing process has been performed on the workpiece, in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0041] After filling the first and second recesses with the metallic material 700, a chemical mechanical polishing (CMP) process is performed to remove at least the excess metallic material 700 and the portion of the second dielectric material 506 located within the first region 302A until a coplanar surface is formed shared by the first interconnection structure 710, the first dielectric material 306, the second interconnection structure 720, and the second dielectric material 506. As a result, according to various embodiments of the present disclosure, a first bonding layer may be formed within the first region 302A, having an upper surface shared by a mixture of polished surfaces of the first interconnection structure 710 and the first dielectric material 306, and a second bonding layer may be formed within the second region 302B, having an upper surface shared by a mixture of polished surfaces of the second interconnection structure 720 and the second dielectric material 506. A first bonding layer formed in a first region 302A of the first substrate 302 may include at least a first dielectric material 306, and a second bonding layer formed in a second region 302B of the first substrate 302 may include at least a second dielectric material 506.

[0042] Corresponding to operation 114 in Figure 1, Figure 9 is a cross-sectional view of a semiconductor device 300 provided with a second substrate 902 in one of various manufacturing stages according to various embodiments of the present disclosure.

[0043] The second substrate 902 can be prepared in the same manner as the first substrate 302, according to operations 102-112 of method 100 (Figure 1). Thus, the second substrate 902 may also include a first region 902A and a second region 902B. Within the first region 902A, a plurality of first interconnection structures 910 are formed to extend through the IMD material 304 and the first dielectric material 306, and within the second region 902B, a plurality of second interconnection structures 920 are formed to extend through the IMD material 304 and the second dielectric material 506. In other words, the second substrate 902 may also include, according to various embodiments of the present disclosure, a first bonding layer having a top surface shared by a mixture of the first interconnection structure 910 and the polished surface of the first dielectric material 306 within the first region 902A, and a second bonding layer having a top surface shared by a mixture of the second interconnection structure 920 and the polished surface of the second dielectric material 506 within the second region 302B. The first bonding layer formed in the first region 902A of the second substrate 902 may include at least the first dielectric material 306, and the second bonding layer formed in the second region 902B of the second substrate 902 may include at least the second dielectric material 506.

[0044] Corresponding to operation 116 in Figure 1, Figure 10 is a cross-sectional view of a semiconductor device 300 in which a first substrate 302 and a second substrate 902 are joined to each other through a first and second bonding layer, respectively, in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0045] In various embodiments, the first substrate 302 and the second substrate 902 are joined together using a hybrid bonding process by bonding the upper surface of the first bonding layer of the first substrate 302 to the upper surface of the first bonding layer of the second substrate 902, and by bonding the upper surface of the second bonding layer of the first substrate 302 to the upper surface of the second bonding layer of the second substrate 902. Thus, the respective first regions 302A and 902A may be joined to each other through a first bonding layer (essentially composed of the first dielectric material 306), and the respective second regions 302B and 902B may be joined to each other through a second bonding layer (essentially composed of the second dielectric material 506). For example, the first interconnection structure 710 of the first semiconductor substrate 302 is aligned with the first interconnection structure 910 of the second semiconductor substrate 902, and the second interconnection structure 720 of the first semiconductor substrate 302 is aligned with the second interconnection structure 920 of the second semiconductor substrate 902. The alignment of the first and second semiconductor substrates 302 and 902 can be achieved, for example, using optical sensing.

[0046] Following the alignment process, the first and second semiconductor substrates 302 and 902 are hybrid-bonded together by applying pressure and heat. The term “hybrid” refers to forming at least two different types of bonds using a single bonding process, rather than forming only one type of bond, as is done in other types of wafer-to-wafer or die-to-die bonding processes. As shown in the example in Figure 10, a first type of bond may exist between the first interconnection structures 710 and 910, and between the second interconnection structures 720 and 920; a second type of bond may exist between the first dielectric material 306 of the first and second substrates, and a third type of bond may exist between the second dielectric material 506 of the first and second substrates. As a result, the (e.g., central) portion of the joint sidewall of the joined first interconnection structures 710 and 910 may be surrounded by a first bonding layer (formed at least of the first dielectric material 306), and the (e.g., central) portion of the joint sidewall of the joined first interconnection structures 720 and 920 may be surrounded by a second bonding layer (formed at least of the second dielectric material 506).

[0047] Figure 11 shows a flowchart of another method 1100 for forming a semiconductor device (e.g., a package) having at least two bonded (e.g., bonded) wafers, dies, or substrates, based on two hybrid junction layers initially formed on two substrates. Note that method 1100 is merely an example and is not intended to limit the present disclosure. Therefore, understand that additional operations may be provided before, during, and after method 1100 in Figure 11, and that some other operations may only be briefly described herein.

[0048] Similarly, each substrate to be bonded has at least a first region and a second region configured as a site for multiple logic devices and multiple memory cells, as shown in Figure 2. Depending on the embodiment, a logic device can function as at least one of the following: an I / O circuit, a logic control circuit, a command register (circuit), an address register (circuit), a sequencer (circuit), a row decoder (circuit), or a sensing amplifier (circuit). Each memory array may include multiple memory cells, each of which is configured to store data. For example, each memory array may include a dynamic random access memory (DRAM) array, a static random access memory (SRAM) array, a resistive random access memory (RRAM) array, a magnetoresistive random access memory (MRAM) array, a phase-change random access memory (PCRAM) array, and so on.

[0049] Furthermore, the operation of Method 1100 may be associated with cross-sectional views of exemplary semiconductor devices 1200 at various manufacturing stages, as shown in Figures 12 to 19, which will be described in more detail below. The semiconductor device 1200 comprises at least two substrates, each of which may include a first region and a second region configured to accommodate a logic device and a memory cell, respectively, as shown in Figure 2. It should be understood that the semiconductor device 1200 shown in Figures 12 to 19 may include several other devices, such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of this disclosure.

[0050] Corresponding to operation 1102 in Figure 11, Figure 12 is a cross-sectional view of a semiconductor device 1200 in which the first substrate 1202 is covered with the first dielectric material 1206 in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0051] The first substrate 1202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on an insulator (SOI) substrate, or the like, which may or may not be doped (e.g., with p-type or n-type dopants). Depending on the embodiment, the first substrate 1202 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is typically provided on a substrate that is a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. For example, the semiconductor material of the first substrate 1202 may include silicon; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0052] As described above, the first substrate 1202 includes a first region 1202A and a second region 1202B, respectively, configured to form a logic device (not shown) and a memory cell (not shown). In various embodiments, multiple intermetallic dielectric (IMD) materials 1204 are formed on the logic device and the memory cell, i.e., on both the first region 1202A and the second region 1202B. Multiple interconnection structures may be formed within the IMD material 1204, and the IMD material 1204 is configured to electrically isolate adjacent interconnection structures. This will be described below. The IMD material 1204 may be formed of one or more dielectric materials, such as SiO2. A first dielectric material 1206 is formed on the IMD material 1204. In the current manufacturing stage, the first dielectric material 1206 may be formed on both the first region 1202A and the second region 1202B. In various embodiments, the first dielectric material 1206 may include SiCN, or other suitable materials that can be used to reduce copper diffusion (when forming interconnect structures) and / or to reduce RC delay (between adjacent interconnect structures).

[0053] Corresponding to operation 1104 in Figure 11, Figure 13 is a cross-sectional view of a semiconductor device 1200 in one of various manufacturing stages according to various embodiments of the present disclosure, in which the first dielectric material 1206 is patterned to cover only the first region 1202A.

[0054] In various embodiments, the first dielectric material 1206 is patterned using lithography. For example, a patternable layer (e.g., a photoresist layer) 1210 is formed on a first region 1202A of the first dielectric material 1206, followed by an etching process to remove the uncovered portion of the first dielectric material 1206 (i.e., the first dielectric material 1206 within the second region 1202B). As a result, a portion of the IMD material 1204 within the second region 1202B can be exposed, as shown in Figure 13.

[0055] Corresponding to operation 1106 in Figure 11, Figure 14 is a cross-sectional view of a semiconductor device 1200 in one of various manufacturing stages according to various embodiments of the present disclosure, in which a second dielectric material 1406 is formed to cover both the first region 1202A and the second region 1202B.

[0056] When a portion of the IMD material 1204 within the second region 1202B is exposed, the second dielectric material 1406 is formed to completely cover both the first region 1202A and the second region 1202B. In various embodiments, the second dielectric material 1406 may differ from the first dielectric material 1206. The second dielectric material 1406 may be configured to provide a strong bond strength with another substrate, while the first dielectric material 1206 may be configured to reduce copper diffusion and / or reduce RC delay. For example, the second dielectric material 1406 may include SiO2 and / or a high-k dielectric material.

[0057] Corresponding to operation 1108 in Figure 11, Figure 15 is a cross-sectional view of the semiconductor device 1200 with the first substrate 1202 polished, in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0058] In various embodiments, after depositing the second dielectric material 1406, a chemical mechanical polishing (CMP) process is performed to remove at least the portion of the second dielectric material 1406 located within the first region 1202A until a coplanar surface is formed shared by the first dielectric material 1206 and the second dielectric material 1406. Thus, the first region 1202A may be covered only by the first dielectric material 1206, and the second region 1202B may be covered only by the second dielectric material 1406.

[0059] Corresponding to operation 1110 in Figure 11, Figure 16 is a cross-sectional view of a semiconductor device 1200 in one of various manufacturing stages according to various embodiments of the present disclosure, in which a metallic material 1600 is formed to fill a first recess and a second recess formed in a first region 1202A and a second region 1202B, respectively.

[0060] After covering the first region 1202A and the second region 1202B with the first dielectric material 1206 and the second dielectric material 1406, respectively, a plurality of first recesses are formed within the IMD material 1204 and the first dielectric material 1206, and a plurality of second recesses are formed within the IMD material 1204 and the second dielectric material 1406. In various embodiments, the first recesses extend through the first dielectric material 1206 and the IMD material 1204 and can reach (e.g., make electrical contact with) logic devices formed in the first region 1202A. On the other hand, the second recesses extend through the second dielectric material 1406 and the IMD material 1204, but do not necessarily have to reach (e.g., make electrical contact with) memory cells formed in the second region 1202B. Next, the first and second recesses can be filled with a metallic material 1610 that forms a plurality of interconnection structures. For example, a plurality of first interconnection structures 1610 may be formed within a first region 1202A, and a plurality of second interconnection structures 1620 may be formed within a second region 1202B. The first interconnection structures 1610 may be connected to logic devices formed within the first region 1202A, while the second interconnection structures 1620 do not necessarily have to be connected to memory cells formed within the second region 1202B. The metallic material 1600 may include at least one of Cu, Al, W, Ti, TiN, Ta, and TaN, or a combination thereof.

[0061] Corresponding to operation 1112 in Figure 11, Figure 17 is a cross-sectional view of a semiconductor device 1200 in which a polishing process has been performed on the workpiece, in one of the various manufacturing stages according to various embodiments of the present disclosure.

[0062] After filling the first and second recesses with the metallic material 1600, a chemical mechanical polishing (CMP) process is performed to remove at least excess metallic material 1600 until a coplanar surface is formed shared by the first interconnection structure 1610, the first dielectric material 1206, the second interconnection structure 1620, and the second dielectric material 1406. As a result, according to various embodiments of the present disclosure, a first bonding layer may be formed in the first region 1202A having an upper surface shared by a mixture of polished surfaces of the first interconnection structure 1610 and the first dielectric material 1206, and a second bonding layer may be formed in the second region 1202B having an upper surface shared by a mixture of polished surfaces of the second interconnection structure 1620 and the second dielectric material 1506. A first bonding layer formed in a first region 1202A of the first substrate 1202 may include at least a first dielectric material 1206, and a second bonding layer formed in a second region 1202B of the first substrate 1202 may include at least a second dielectric material 1406.

[0063] Corresponding to operation 1114 in Figure 11, Figure 18 is a cross-sectional view of a semiconductor device 1200 provided with a second substrate 1802 in one of various manufacturing stages according to various embodiments of the present disclosure.

[0064] The second substrate 1802 can be prepared in the same manner as the first substrate 1202 according to operations 1102-1112 of method 1100 (Figure 11). Thus, the second substrate 1802 may also include a first region 1802A and a second region 1802B. Within the first region 1802A, a plurality of first interconnection structures 1810 are formed to extend through the IMD material 1204 and the first dielectric material 1206, and within the second region 1202B, a plurality of second interconnection structures 1820 are formed to extend through the IMD material 1204 and the second dielectric material 1406. In other words, the second substrate 1802 may also include, according to various embodiments of the present disclosure, a first bonding layer having a top surface shared by a mixture of the polished surfaces of the first interconnection structure 1810 and the first dielectric material 1206 within the first region 1802A, and a second bonding layer having a top surface shared by a mixture of the polished surfaces of the second interconnection structure 1820 and the second dielectric material 1406 within the second region 1802B. The first bonding layer formed in the first region 1802A of the second substrate 1802 may include at least the first dielectric material 1206, and the second bonding layer formed in the second region 1802B of the second substrate 1802 may include at least the second dielectric material 1406.

[0065] Corresponding to operation 1116 in Figure 11, Figure 19 is a cross-sectional view of a semiconductor device 1200 in one of various manufacturing stages according to various embodiments of the present disclosure, in which a first substrate 1202 and a second substrate 1802 are joined to each other through a first and second bonding layer, respectively.

[0066] In various embodiments, the first substrate 1202 and the second substrate 1802 are joined together using a hybrid bonding process by bonding the upper surface of the first bonding layer of the first substrate 1202 to the upper surface of the first bonding layer of the second substrate 1802, and by bonding the upper surface of the second bonding layer of the first substrate 1202 to the upper surface of the second bonding layer of the second substrate 1802. Thus, the respective first regions 1202A and 1802A may be joined to each other through a first bonding layer (essentially composed of the first dielectric material 1206), and the respective second regions 1202B and 1202B may be joined to each other through a second bonding layer (essentially composed of the second dielectric material 1406). For example, the first interconnection structure 1610 of the first semiconductor substrate 1202 is aligned with the first interconnection structure 1810 of the second semiconductor substrate 1802, and the second interconnection structure 1620 of the first semiconductor substrate 1202 is aligned with the second interconnection structure 1820 of the second semiconductor substrate 1802. The alignment of the first and second semiconductor substrates 1202 and 1802 can be achieved, for example, using optical sensing.

[0067] Following the alignment process, the first and second semiconductor substrates 1202 and 1802 are hybrid-bonded together by applying pressure and heat. The term “hybrid” refers to forming at least two different types of bonds using a single bonding process, rather than forming only one type of bond, as is done in other types of wafer-to-wafer or die-to-die bonding processes. As shown in the example in Figure 19, a first type of bond may exist between the first interconnection structures 1610 and 1810, and between the second interconnection structures 1620 and 1820; a second type of bond may exist between the first dielectric material 1206 of the first and second substrates, and a third type of bond may exist between the second dielectric material 1406 of the first and second substrates. As a result, the (e.g., central) portion of the joint sidewall of the joined first interconnection structures 1610 and 1810 may be surrounded by a first bonding layer (formed of at least the first dielectric material 1206), and the (e.g., central) portion of the joint sidewall of the joined first interconnection structures 1620 and 1820 may be surrounded by a second bonding layer (formed of at least the second dielectric material 1406).

[0068] The above description includes specific details, such as the specific shape of the processing system and the various components and processes used therein. However, it should be understood that the technology described herein may be implemented in other embodiments that deviate from these specific details, and such details are for illustrative purposes only, not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been given for illustrative purposes to ensure a good understanding. However, embodiments may be implemented without such specific details. Components having substantially the same functional configuration are indicated by similar reference numerals, and therefore redundant descriptions may be omitted.

[0069] To aid in understanding the various embodiments, various techniques have been described as multiple distinct operations. The order of description should not be interpreted as meaning that these operations are necessarily order-dependent. In practice, these operations do not need to be performed in the order presented. The operations described may be performed in a different order than in the embodiments described. In additional embodiments, various additional operations may be performed, and / or the operations described may be omitted.

[0070] As used herein, “substrate” or “target substrate” generally refers to the object to be processed by the present invention. A substrate may include any material portion or structure of a device, in particular a semiconductor or other electronic device, and may be a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or covering a base substrate structure, such as a thin film. Therefore, a substrate is not limited to any particular base structure, underlayer or upper layer, whether patterned or not, and includes any such layer or base structure, as well as any combination of layers and / or base structures. This specification may refer to certain types of substrates, but this is for illustrative purposes only.

[0071] Those skilled in the art will understand that many modifications to the operation of the techniques described above can be made while still achieving the same objectives of the present invention. Such modifications are intended to be within the scope of this disclosure. Therefore, the above description of embodiments of the present invention is not intended to be limiting. Rather, all limitations to embodiments of the present invention are set out in the following claims.

Claims

1. It is a semiconductor device, A first substrate including a first region and a second region, A second substrate including a third region and a fourth region, A first bonding layer comprising a first dielectric material that bonds the first region to the third region, A second bonding layer comprising a second dielectric material that bonds the second region to the fourth region, Equipped with, A semiconductor device in which the first dielectric material is different from the second dielectric material.

2. The first substrate described above is A first dielectric layer disposed on the first substrate, A first interconnection structure extending through the first bonding layer into the first dielectric layer and having a first upper surface that does not overlap the first bonding layer, A second interconnection structure extending into the first dielectric layer through the second junction layer and having a second upper surface where the second junction layer does not overlap, A semiconductor device according to claim 1, including the above.

3. The second substrate is A second dielectric layer disposed on the second substrate, A third interconnection structure extending through the first junction layer into the second dielectric layer and having a third upper surface that does not overlap the first junction layer, A fourth interconnection structure extending through the second junction layer into the second dielectric layer and having a fourth upper surface that does not overlap the second junction layer, A semiconductor device according to claim 2, including the above.

4. The semiconductor device according to claim 3, wherein the first upper surface and the third upper surface are in contact with each other, the first interconnection structure is in contact with the third interconnection structure, and the second upper surface and the fourth upper surface are in contact with each other, the second interconnection structure is in contact with the fourth interconnection structure.

5. The semiconductor device according to claim 4, wherein the first bonding layer surrounds a portion of the combined sidewall of the contacting first and third interconnection structures.

6. The semiconductor device according to claim 4, wherein the second bonding layer surrounds a portion of the combined sidewall of the contacting second and fourth interconnection structures.

7. The semiconductor device according to claim 4, wherein each of the first substrates includes a plurality of first logic devices in the first region and a plurality of first memory cells in the second region.

8. The semiconductor device according to claim 7, wherein each of the second substrates includes a plurality of second logic devices in the third region and a plurality of second memory cells in the fourth region.

9. The semiconductor device according to claim 8, wherein the first interconnection structure is electrically coupled to at least one of the plurality of first logic devices, and the third interconnection structure is electrically coupled to at least one of the plurality of second logic devices.

10. The semiconductor device according to claim 8, wherein the second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.

11. The semiconductor device according to claim 1, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains a high k dielectric.

12. The semiconductor device according to claim 1, wherein the first dielectric material comprises silicon carbonitride and the second dielectric material comprises silicon oxide.

13. It is a semiconductor device, Each includes a first substrate containing a first interconnection structure and a second interconnection structure within a first region and a second region, A second substrate comprising a third region and a fourth region, respectively, containing a third interconnection structure and a fourth interconnection structure, wherein the first interconnection structure is in contact with the third interconnection structure and the second interconnection structure is in contact with the fourth interconnection structure, A first bonding layer comprising a first dielectric material that bonds the first region to the third region, A second bonding layer comprising a second dielectric material that bonds the second region to the fourth region, Equipped with, A semiconductor device in which the first dielectric material is different from the second dielectric material.

14. The semiconductor device according to claim 13, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains a high k dielectric.

15. The semiconductor device according to claim 13, wherein the first dielectric material comprises silicon carbonitride and the second dielectric material comprises silicon oxide.

16. The semiconductor device according to claim 13, wherein each of the first substrates includes a plurality of first logic devices in the first region and a plurality of first memory cells in the second region, and each of the second substrates includes a plurality of second logic devices in the third region and a plurality of second memory cells in the fourth region.

17. The semiconductor device according to claim 16, wherein the first interconnection structure is electrically coupled to at least one of the plurality of first logic devices, the third interconnection structure is electrically coupled to at least one of the plurality of second logic devices, the second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.

18. A method for manufacturing semiconductor devices, A first substrate including a first dielectric layer is prepared, A first junction layer containing the first dielectric material and a second junction layer containing the second dielectric material are superimposed on the first region and the second region of the first dielectric layer, respectively. A second substrate including a second dielectric layer is prepared, A third junction layer containing the first dielectric material and a fourth junction layer containing the second dielectric material are superimposed on the third and fourth regions of the second dielectric layer, respectively. In each case, the first substrate is bonded to the second substrate through the first to fourth bonding layers, such that the first region is bonded to the third region and the second region is bonded to the fourth region. Includes, A method wherein the first dielectric material is different from the second dielectric material.

19. The method according to claim 18, wherein the first dielectric material comprises silicon carbonitride and the second dielectric material comprises a high-k dielectric or silicon oxide.

20. A first interconnection structure is formed within the first region, extending through the first junction layer into the first dielectric layer, A second interconnection structure is formed within the second region, extending through the second junction layer into the first dielectric layer, A third interconnection structure is formed within the third region, extending through the third junction layer into the second dielectric layer, A fourth interconnection structure is formed within the fourth region, extending through the fourth junction layer into the second dielectric layer, It further includes, The method according to claim 18, wherein, after the step of joining the first substrate to the second substrate, the first interconnection structure is in contact with the third interconnection structure and the second interconnection structure is in contact with the fourth interconnection structure.

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