Dies, chips, and electronic devices

Abstract

This application discloses a die, a chip, and an electronic device relating to the field of chip technology. The die includes a substrate, a first bus signal board, a first metal plate, and a transistor laminated on the substrate. The first bus signal board and the first metal plate are separated in a first direction, the first direction being the thickness direction of the substrate. In the first direction, the projection area of ​​the first bus signal board onto the substrate is the first projection area, and the projection area of ​​the first metal plate onto the substrate is the second projection area, with the first and second projection areas overlapping at least partially. In the first direction, the projection area of ​​the transistor onto the substrate is the third projection area, with the third projection area and the first projection area separated from each other. The first bus signal board and the first metal plate are separately connected to the pins of the transistor.

Description

Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202310543958.4, titled "Die, Chip, and Electronic Device", filed with the China National Intellectual Property Administration on May 12, 2023, and incorporates it herein in its entirety by reference.

[0002] This application relates to the field of chip technology, and particularly to dies, chips, and electronic devices.

Background Art

[0003] With the development of science and technology, chips are being used more and more widely. Currently, a chip usually includes both a die and passive components to meet the usage requirements in different scenarios. For example, in a power amplifier (PA) chip, in addition to a die configured to implement an amplification function, a capacitor or an inductor may be further arranged to form a matching circuit configured to adjust impedance (such as fundamental impedance (Z_f0) or harmonic impedance, etc.). However, the existing layout solutions for dies and passive components occupy a large area, have a low space utilization rate, and are not conducive to implementing a compact design.

Summary of the Invention

[0004] To solve the above technical problems, this application provides a die, a chip, and an electronic device. The layout of the circuit inside the die is appropriately designed to effectively avoid the passive components from additionally occupying the area of the die, thereby improving the space utilization rate of the die and reducing the manufacturing cost.

[0005] According to a first aspect, the application provides a die comprising a substrate, a first bus signal board, a first metal plate, and a transistor laminated on the substrate. The first bus signal board and the first metal plate are separated in a first direction, the first direction being the thickness direction of the substrate. In the first direction, the projection area of ​​the first bus signal board onto the substrate is the first projection area, and the projection area of ​​the first metal plate onto the substrate is the second projection area, with the first projection area and the second projection area overlapping at least partially. In the first direction, the projection area of ​​the transistor onto the substrate is the third projection area, with the third projection area and the first projection area separated from each other. The first bus signal board and the first metal plate are separately connected to the pins of the transistor.

[0006] According to one implementation of this application, a first bus signal board and a first metal plate within a die can jointly form a capacitor. The layout of the first bus signal board and the first metal plate is appropriately designed so that area reuse is also carried out between the first bus signal board and the first metal plate when circuit design requirements are met, in order to effectively avoid the capacitor occupying additional area on the substrate and to reduce unnecessary components, thereby improving the space utilization rate of the die and reducing the manufacturing cost of the die.

[0007] In one possible implementation of the first embodiment, the second projection region is located within the first projection region in order to further reduce the area occupied by the first metal plate, thereby improving space utilization.

[0008] In one possible implementation of the first embodiment, a dielectric layer is arranged between the first bus signal board and the first metal plate in a first direction.

[0009] According to this implementation of the present application, the first bus signal board and the first metal plate can jointly form a capacitor, and different capacitance values ​​can be designed by adjusting the thickness of the dielectric layer to adapt to different application scenarios and expand the scope of application.

[0010] In one possible implementation according to the first embodiment, the dielectric layer includes silicon nitride or aluminum oxide.

[0011] In one possible implementation of the first embodiment, the first metal plate and the transistor are located on the same surface of the substrate, and the first bus signal board is located on the side of the first metal plate that does not face the substrate.

[0012] Based on this, when it is ensured that the first bus signal board and the first metal plate can jointly form a capacitor, the first metal plate and transistor can also be conveniently manufactured on the substrate, thereby effectively reducing the difficulty of shaping the first metal plate and transistor and the manufacturing cost.

[0013] In one possible implementation of the first embodiment, the transistor is a field-effect transistor.

[0014] In one possible implementation of the first embodiment, the first bus signal board is an input bus signal board, and the input bus signal board is connected to the gate fingers of a transistor. The transistor includes at least one source region, the at least one source region includes a first source region, and a first metal plate is connected to the first source region via a first metal trace.

[0015] In one possible implementation of the first embodiment, the first metal plate and the transistor are separated in a second direction, the second direction being perpendicular to the first direction. The first source region extends in the second direction, and in the second direction, the projection of the first metal trace and the projection of the first source region overlap at least partially.

[0016] To effectively avoid the first metal trace occupying excessive area, area reuse can be implemented between the first metal trace and the first source area, thereby further improving space utilization and reducing manufacturing costs.

[0017] In one possible implementation of the first embodiment, the first metal trace extends in a second direction, in the second direction the projection of the first metal trace lies within the projection of the first source region, in a third direction the projection of the first metal trace and the projection of the first source region overlap at least partially, and the third direction is perpendicular to both the first and second directions.

[0018] To effectively avoid the first metal trace occupying excessive area, area reuse can be implemented between the first metal trace and the first source area, thereby further improving space utilization and reducing manufacturing costs.

[0019] In one possible implementation of the first embodiment, at least one source region further includes a second source region, and a first metal plate is connected to the second source region via a second metal trace. The second source region extends in a second direction, and the second source region and the first source region are separated in a third direction. In the second direction, the projection of the second metal trace and the projection of the second source region overlap at least partially, and in the third direction, the projection of the second metal trace and the projection of the second source region overlap at least partially.

[0020] To effectively avoid the second metal trace occupying excessive area, area reuse can be implemented between the second metal trace and the second source area, thereby further improving space utilization and reducing manufacturing costs.

[0021] In one possible implementation of the first embodiment, each of at least one source region is grounded.

[0022] In one possible implementation of the first embodiment, there are multiple gate fingers of a transistor, the multiple gate fingers extending in a second direction and separated in a third direction, the first, second, and third directions being perpendicular to each other, and the multiple gate fingers are separately connected to a first bus signal board. In the second direction, the projection of the multiple gate fingers lies within the projection of a first metal plate.

[0023] According to this implementation of this application, there are multiple gate fingers to meet the usage requirements in the high-power scenario, thereby further expanding the scope of application. Also, the distance between the capacitor including the first bus signal board and the first metal plate and the multiple gate fingers is not excessively long, and as a result, the effect of the capacitor is better.

[0024] In a possible implementation of the first aspect, the die further has an output bus signal board, and the output bus signal board is connected to the drain fingers of the transistor.

[0025] According to the second aspect, this application provides a chip. The chip includes a base board and a die in any possible implementation of the first aspect and the first aspect. The die is arranged on the base board.

[0026] According to the chip, the necessary circuits can be formed by using the passive components inside the die, effectively reducing unnecessary electronic components, improving the space utilization rate inside the chip, reducing the manufacturing cost, reducing the parasitic inductance inside the chip, and thereby further improving the operating performance of the chip.

[0027] In a possible implementation of the second aspect, the chip is a power amplifier chip.

[0028] According to the third aspect, this application provides an electronic device. The electronic device includes a housing and a chip in any possible implementation of the second aspect and the second aspect. The chip is arranged inside the housing.

Brief Description of the Drawings

[0029] [Figure 1A] It is a three-dimensional view of an electronic device according to an embodiment of this application. [Figure 1B] It is an exploded view of an electronic device according to an embodiment of this application. [Figure 2]This diagram shows the relationship between the phase of the second harmonic impedance and the efficiency of the chip, according to one embodiment of this application. [Figure 3] This is a diagram of the chip structure in some technical solutions. [Figure 4] This is a diagram of the die structure within a chip in some technical solutions. [Figure 5] This is a schematic diagram of the matching circuitry within a chip in some technical solutions. [Figure 6] This is a diagram of the die structure in some other technical solutions. [Figure 7A] This is a top view of a die according to one embodiment of this application. [Figure 7B] This is a cross-sectional view of a die according to one embodiment of this application. [Figure 8A] This is a top view of a die, according to some embodiments of this application, where a first metal trace in the die is equivalent to an inductor. [Figure 8B] This is a cross-sectional view of a die, according to some embodiments of this application, where a first metal trace within the die is equivalent to an inductor. [Figure 9] This is a schematic diagram of a second matching circuit including an inductor and a capacitor in a die, according to one embodiment of this application. [Figure 10A] This shows an example 1 of a first metal trace arrangement method according to some embodiments of this application. [Figure 10B] This shows an example 2 of a first metal trace arrangement method according to some embodiments of this application. [Figure 11] This is a diagram of the structure of a chip including a die according to some embodiments of this application. [Explanation of symbols]

[0030] 1-Electronic device; 10-Chip; 100-Die; 110-Substrate; 120-First bus signal board; 130-First metal plate; 140-Transistor; 141-Gate finger; 142-Source area; 1421-Ground hole; 142'-First source area; 142''-Second source area; 142'''-Third source area; 142''''-Fourth source area; 143-Drain finger Inger; 150 - Dielectric layer; 160 - Metal trace; 161 - First metal trace; 162 - Second metal trace; 163 - Third metal trace; 164 - Fourth metal trace; 170 - Second bus signal board; 10a - Chip; 100a - Die; 110a - Substrate; 120a - First bus signal board; 130a - Second bus signal board; 140a - Transistor; 141a - Gate Finger; 142a - Source area; 1421a - Grounding hole; 143a - Drain finger; 100b - Die; 110b - Substrate; 120b - First bus signal board; 130b - Second bus signal board; 140b - Transistor; 141b - Gate finger; 142b - Source area; 143b - Drain finger; 150b - First plate; 160b - Second plate; 170b - Metal trace; 20 - Display screen; 30 - Housing; 40 - Enclosure space; S1 - First projection area; S2 - Second projection area; S3 - Third projection area; S4 - First part of the first metal trace; C1 - Capacitor; C2 - Capacitor; L1 - Inductor; L2 - Inductor; L3 - Inductor; h0 - Central axis of the first source area; M1 - First matching circuit; M2 - Second matching circuit. [Modes for carrying out the invention]

[0031] To further clarify the purpose, technical solution, and advantages of this application, the implementation of this application will be described in detail below with reference to the attached drawings.

[0032] This application provides a die, a chip containing the die, and electronic equipment. The die provided in embodiments of this application includes a passive component. The layout of the circuitry inside the die is appropriately designed to avoid the passive component occupying additional area of ​​the die, thereby effectively improving the space utilization rate of the die and reducing manufacturing costs.

[0033] It should be understood that the electronic devices provided in this application may be any one of the following, but are not limited to, base station devices, mobile phones, tablet computers, notebook computers, wearable devices, super netbooks, ultra-mobile personal computers (UMPCs), and personal digital assistants (PDAs). The chip may be any one of the following, but are not limited to, power amplifier chips, baseband chips, power management integrated circuits (PMICs), central processing unit / processor (CPU) chips, and system-on-chip (SoC) chips. For the sake of clarity, this application will be described below using the example of a power amplifier chip.

[0034] Figures 1A and 1B are diagrams of an electronic device 1 according to one embodiment of this application. Figure 1A is a three-dimensional view of the electronic device 1, and Figure 1B is an exploded view of the electronic device 1. Please refer to Figures 1A and 1B. The electronic device 1 includes a chip 10, a display screen 20, and a housing 30. The display screen 20 and the housing 30 can together enclose a housing space 40. The chip 10 is located within the housing space 40.

[0035] Chip 10 may include a die (not shown) and passive components (not shown). The die may be configured to implement the amplification function of chip 10. Passive components may be configured to form various circuits. For example, a capacitor or inductor may form a matching circuit for adjusting impedance, thereby improving the performance of chip 10 and reducing energy consumption. For example, Figure 2 is a diagram of the relationship between the phase of the second harmonic impedance and the efficiency of chip 10 according to one embodiment of this application. As shown in Figure 2, by using a matching circuit, the phase of the second harmonic impedance (Z_h2) can be adjusted to 180° (i.e., the second harmonic impedance is close to 0hm (short circuit)). In this case, the efficiency of chip 10 (shown by a solid line in Figure 2) can reach a maximum of approximately 82%, thereby effectively reducing energy consumption. In another example, the phase of the second harmonic impedance can be adjusted to 160° instead by using a matching circuit. In this case, the power of chip 10 (shown by the dashed line in Figure 2) can reach a maximum value of approximately 42.22 dBm.

[0036] The following describes examples of the structure and layout solutions of the die and passive components within the chip, with reference to the attached drawings.

[0037] In some technical solutions, passive components within the chip may be located outside the die. Figure 3 shows the structure of chip 10a in some technical solutions. As shown in Figure 3, chip 10a includes die 100a, capacitor C1, capacitor C2, and baseboard 200a. Die 100a, capacitor C1, and capacitor C2 are each located on baseboard 200a.

[0038] Specifically, Figure 4 shows the structure of die 100a within chip 10a in some technical solutions. Please refer to Figure 4. Die 100a may include a substrate 110a, a first bus signal board 120a, a second bus signal board 130a, and a transistor 140a, all located on the substrate 110a.

[0039] Transistor 140a includes a plurality of gate fingers 141a, a plurality of source regions 142a, and a plurality of drain fingers 143a. The gate fingers 141a are metal fingers for the gate. The source regions 142a are metal strips for the source. The drain fingers 143a are metal fingers for the drain. The plurality of gate fingers 141a, a plurality of source regions 142a, and a plurality of drain fingers 143a extend in the X-axis direction (or referred to as the “second direction”). In the Y-axis direction (or referred to as the “third direction”), the plurality of source regions 142a and a plurality of drain fingers 143a are arranged alternately, with each gate finger 141a located between a group of source regions 142a and drain fingers 143a adjacent to that gate finger 141a. For example, the X-axis direction and the Y-axis direction are perpendicular to each other.

[0040] Multiple gate fingers 141a are separately connected to the first bus signal board 120a. An input terminal signal can be split to the multiple gate fingers 141a via the first bus signal board 120a. Multiple source regions 142a are grounded via a ground hole 1421a. Multiple drain fingers 143a are separately connected to the second bus signal board 130a, and signals on the multiple drain fingers 143a can be coupled to the second bus signal board 130a and output. When an appropriate voltage is applied between the gate fingers 141a and the source regions 142a, a current is generated on the drain fingers 143a. Furthermore, a large current can be driven using only a small voltage, thereby realizing the amplification function of the chip 10a.

[0041] Capacitor C1 is connected to die 100a via bonding wire (BW) 300a, and capacitor C2 is connected to die 100a via bonding wire 400a, forming a matching circuit for chip 10a.

[0042] Figure 5 is a schematic diagram of a matching circuit within chip 10a in some technical solutions. See Figures 3-5. Chip 10a may include a first matching circuit M1 and a second matching circuit M2. The first matching circuit M1 may include a capacitor C1 and an inductor L1 (i.e., bonding wire 300a shown in Figure 3) and be configured to adjust the fundamental impedance. The second matching circuit M2 may include a capacitor C2 and an inductor L2 (i.e., bonding wire 400a shown in Figure 3) and be configured to adjust the second harmonic impedance.

[0043] Specifically, the input terminal IN is connected to the first terminal of inductor L1 via inductor L3. The second terminal of inductor L1 is connected to the gate G of die 100a. The source S of die 100a is grounded. The drain D of die 100a is connected to the output terminal OUT. The first terminal of capacitor C1 is grounded, and the second terminal of capacitor C1 is connected between inductor L1 and inductor L3, forming a first matching circuit M1 together with inductor L1. The first terminal of capacitor C2 is grounded, and the second terminal of capacitor C2 is connected between inductor L1 and gate G via inductor L2, forming a second matching circuit M2 together with inductor L2.

[0044] Based on the structure of chip 10a, it is not difficult to find the following: namely, passive components (e.g., capacitor C1, capacitor C2, inductor L1, or inductor L2) are placed outside die 100a, occupying additional area on baseboard 200a, resulting in low space utilization and increased manufacturing costs.

[0045] In some other technical solutions, the die may use a monolithic microwave integrated circuit (MMIC) design, and passive components may be integrated inside the die.

[0046] Figure 6 shows the structure of die 100b in some other technical solutions. As shown in Figure 6, die 100b includes a substrate 110b and a first bus signal board 120b, a second bus signal board 130b, a transistor 140b, a capacitor C2, and an inductor L2, all located on the substrate 110b.

[0047] The specific structure and connection method of the first bus signal board 120b, the second bus signal board 130b, and transistor 140b are the same as the specific structure and connection method of the first bus signal board 120a, the second bus signal board 130a, and transistor 140a in die 100a. For details, please refer to Figure 4 and its related explanation. Details will not be explained again here.

[0048] Capacitor C2 includes a first plate 150b and a second plate 160b. The first plate 150b is connected to the first bus signal board 120b. The second plate 160b is connected to one source region 142b of transistor 140b via a metal trace 170b. The metal trace 170b can be equivalent to an inductor L2. Thus, capacitor C2 and inductor L2 can form a second matching circuit M2. In other words, the second matching circuit M2 is integrated inside die 100b.

[0049] Compared to Figures 4 and 6, the second matching circuit M2 integrated inside die 100b occupies an additional area of ​​substrate 110b. Compared to die 100a, which does not have the second matching circuit M2 inside, die 100b has a larger overall area and does not contribute to achieving a compact design. In addition, the semiconductor material used in die 100b (e.g., gallium nitride, GaN) is usually expensive. Therefore, the increase in the area of ​​die 100b further results in higher manufacturing costs.

[0050] To solve the aforementioned problems, this application provides a die that includes a passive component. The layout of the circuitry inside the die is appropriately designed so as to effectively reduce wasted space when circuit design requirements are met, thereby further improving the space utilization rate of the die and reducing manufacturing costs. A detailed description is provided below with reference to the attached drawings.

[0051] Figures 7A and 7B show the structure of a die 100 according to one embodiment of this application. Figure 7A is a top view of the die 100, and Figure 7B is a cross-sectional view of the die 100. As shown in Figures 7A and 7B, the die 100 includes a substrate 110, a first bus signal board 120, a first metal plate 130, and a transistor 140. The first bus signal board 120, the first metal plate 130, and the transistor 140 are all stacked on the substrate 110.

[0052] Specifically, the first bus signal board 120 and the first metal plate 130 are separated in the Z-axis direction (or referred to as the "first direction"). For example, the Z-axis direction can be the thickness direction of the substrate 110, and the Z-axis, X-axis, and Y-axis directions are perpendicular to each other. In the Z-axis direction, the projection area of ​​the first bus signal board 120 onto the substrate 110 is the first projection area S1, and the projection area of ​​the first metal plate 130 onto the substrate 110 is the second projection area S2, and the first projection area S1 and the second projection area S2 overlap at least partially.

[0053] Thus, the first bus signal board 120 and the first metal plate 130 can jointly form a capacitor (e.g., capacitor C2) for forming various circuits (e.g., the second matching circuit M2 described above) based on different needs. Different capacitance values ​​can be obtained by adjusting the size of the overlapping region between the first projection region S1 and the second projection region S2 to meet the operating requirements in different application scenarios. For example, the second projection region S2 may be located within the first projection region S1. Thus, different capacitance values ​​can also be designed by adjusting the size of the second projection region S2.

[0054] The first bus signal board 120 and the first metal plate 130 are separately connected to the pins (unmarked) of the transistor 140. In the Z-axis direction, the projection area of ​​the transistor 140 onto the substrate 110 is the third projection area S3, and the third projection area S3 and the first projection area S1 are separated from each other.

[0055] According to die 100, the layout of the first bus signal board 120 and the first metal plate 130 is appropriately designed so that area reuse is also carried out between the first bus signal board 120 and the first metal plate 130 when the circuit design requirements are met, in order to effectively avoid the capacitor C2 occupying additional area on the substrate 110, thereby improving the space utilization rate of die 100 and reducing the manufacturing cost of die 100.

[0056] For example, comparing Figure 6 and Figure 7A, capacitors are still integrated into the die, but capacitor C2 in die 100b occupies additional area on substrate 110b. As a result, die 100b has an excessively large overall area, low space utilization, and high manufacturing costs. On the other hand, in this application, the first metal plate 130 and the first bus signal board 120 share a portion of the area, effectively avoiding the capacitor C2 occupying additional area on substrate 110, and as a result, die 100 has a more compact overall structure, higher space utilization, and lower manufacturing costs.

[0057] In addition, compared to a solution in which two metal plates (i.e., a first plate 150b and a second plate 160b) are added to die 100b to form capacitor C2, die 100 of this application effectively reduces unnecessary components by using the original first bus signal board 120 and the additional first metal plate 130 to jointly form capacitor C2, thereby further improving the space utilization of die 100 and lowering manufacturing costs.

[0058] Please refer to Figure 7B. In some embodiments of this application, the substrate 110 may include substrate layers 111 and semiconductor layers 112 stacked in the Z-axis direction. The semiconductor layer 112 may be one of gallium nitride, gallium arsenide (GaAs), or laterally-diffused metal-oxide semiconductor (LDMOS).

[0059] In some embodiments of this application, a dielectric layer 150 may be positioned between the first bus signal board 120 and the first metal plate 130 in the Z-axis direction. Different capacitance values ​​can be designed by adjusting the thickness of the dielectric layer 150 to adapt to different application scenarios. The thickness of the dielectric layer 150 is the size of the dielectric layer 150 in the Z-axis direction. For example, the dielectric layer 150 may be made of a material such as silicon nitride (e.g., Si3N4 or Si2N3) or aluminum oxide (Al2O3).

[0060] In some embodiments of this application, both the first metal plate 130 and the transistor 140 are located on the same surface of the substrate 110. The first bus signal board 120 is located on the side of the first metal plate 130 that does not face the substrate 110. Thus, the first metal plate 130 and the transistor 140 can be conveniently manufactured on the substrate 110, while ensuring that the first bus signal board 120 and the first metal plate 130 can jointly form a capacitor C2, thereby effectively reducing the difficulty of molding and the manufacturing cost of the first metal plate 130 and the transistor 140.

[0061] Please refer to Figure 7A. In some embodiments of this application, the transistor 140 may be a field-effect transistor. The transistor 140 includes at least one gate finger 141, at least one source region 142, and at least one drain finger 143. The gate finger 141 is a metal finger of the gate of the transistor 140. The source region 142 is a metal strip of the source of the transistor 140. The drain finger 143 is a metal finger of the drain of the transistor 140.

[0062] In some embodiments of this application, a plurality of gate fingers 141, a plurality of source regions 142, and a plurality of drain fingers 143 may be provided to meet the requirements for use in high-power scenarios, thereby further expanding the scope of application of the die 100. For example, the plurality of gate fingers 141, a plurality of source regions 142, and a plurality of drain fingers 143 extend in the X-axis direction. In the Y-axis direction, the plurality of source regions 142 and a plurality of drain fingers 143 are arranged alternately, with each gate finger 141 located between a group of source regions 142 and drain fingers 143 adjacent to that gate finger 141.

[0063] The first bus signal board 120 can be used as an input bus signal board and is connected to a plurality of gate fingers 141 of transistor 140. The input terminal signal can be split to the plurality of gate fingers 141 via the first bus signal board 120. The plurality of gate fingers 141 may also be connected to other elements (e.g., switches or duplexers) or packages via the first bus signal board 120.

[0064] The first metal plate 130 and the transistor 140 are separated in the X-axis direction. In some embodiments of this application, in order to improve the effectiveness of the capacitor C2 and thereby further improve the operating performance of the die 100, the projection of the multiple gate fingers 141 of the transistor 140 is placed within the projection of the first metal plate 130 in the X-axis direction, so as to ensure that the distance between the capacitor C2, including the first bus signal board 120 and the first metal plate 130, and the multiple gate fingers 141 is not excessively long.

[0065] Comparing Figure 6 and Figure 7A, the capacitor C2 in die 100b is located next to the transistor 140b. As a result, the distance between capacitor C2 and the intermediate gate finger 141b is longer, affecting the effect of controlling the second harmonic impedance of the gate finger 141b and resulting in poor performance of die 100b. On the other hand, in this application, the layout of the multiple gate fingers 141 is appropriately arranged to effectively avoid an excessively long distance between the multiple gate fingers 141 and capacitor C2, thereby improving the operating performance of die 100 when high-power usage requirements are met.

[0066] Please refer to Figure 7A. The first metal plate 130 may be connected to one or more of the source regions 142 of the transistor 140 via metal traces 160. For example, the source region 142 includes a first source region 142', a second source region 142'', a third source region 142''', and a fourth source region 142''''. The metal traces 160 include a first metal trace 161, a second metal trace 162, a third metal trace 163, and a fourth metal trace 164. The first source region 142', the second source region 142'', the third source region 142''', and the fourth source region 142'''' are connected to the first metal plate 130 via the first metal traces 161, 2, 3, and 4, respectively.

[0067] In some embodiments of this application, the metal trace 160 can be equivalent to an inductor. Different inductance values ​​can be designed by adjusting the length and width of the metal trace 160 and the number of metal traces 160 to adapt to different application scenarios. The length of the metal trace 160 is the size of the metal trace 160 in the X-axis direction. The width of the metal trace 160 is the size of the metal trace 160 in the Y-axis direction. Inductors with different inductance values ​​can be configured to form various circuits (e.g., a second matching circuit M2) to meet different operating requirements.

[0068] To facilitate the explanation, the specific structure and arrangement of the metal traces 160 when they are equivalent to inductors will be described below, using the first metal trace 161 of the metal traces 160 as an example.

[0069] Figures 8A and 8B illustrate the structure of die 100 when the first metal trace 161 within die 100 is equivalent to an inductor L2, according to certain embodiments of this application. Figure 8A is a top view of die 100, and Figure 8B is a cross-sectional view of die 100. Figure 9 is a schematic diagram of a second matching circuit M2 including an inductor L2 and a capacitor C2 within die 100, according to one embodiment of this application.

[0070] Refer to Figures 8A-9. The first metal trace 161 in die 100 has a specific length and width. Thus, the first metal trace 161 can be equivalent to an inductor L2. The first bus signal board 120 and the first metal plate 130 can together form a capacitor C2. The inductor L2 and capacitor C2 together form a second matching circuit M2. Specifically, the first end of capacitor C2 is connected between the input terminal IN and the gate G of die 100, and the second end of capacitor C2 is connected to the source S of die 100 via inductor L2 and is grounded to form the second matching circuit M2. The drain D of die 100 is connected to the output terminal OUT.

[0071] In some embodiments of this application, area reuse can be achieved between the first metal trace 161 and another component (e.g., transistor 140) to further improve the space utilization of the die 100, reduce manufacturing costs, and expand the scope of application, so as to avoid the first metal trace 161 occupying additional area of ​​the substrate 110 while ensuring that the first metal trace 161 has an appropriate size and quantity.

[0072] Specifically, the projection of the first metal trace 161 and the projection of the first source region 142' overlap at least partially in the X-axis direction. Thus, size reuse is performed between the first metal trace 161 and the first source region 142' in the Y-axis direction, effectively avoiding the first metal trace 161 occupying an excessive area when ensuring that the first metal trace 161 has a specific width, thereby further improving space utilization and reducing manufacturing costs. For example, the first metal trace 161 may extend in the X-axis direction. In addition, the projection of the first metal trace 161 is located within the projection of the first source region 142' in the X-axis direction, further reducing the area of ​​the die 100 and thereby improving space utilization.

[0073] Alternatively, in some other alternative implementations, size reuse may instead be performed in the X-axis direction between the first metal trace 161 and the first source region 142'. Specifically, the projection of the first metal trace 161 and the projection of the first source region 142' overlap at least partially in the Y-axis direction, effectively avoiding the first metal trace 161 occupying an excessive area when ensuring that the first metal trace 161 has a specific length. For example, the projected area of ​​the first portion S4 of the first metal trace 161 lies within the projected area of ​​the first source region 142' in the Y-axis direction. The first portion S4 of the first metal trace 161 may be formed by performing a graphical (e.g., groove) design on the first source region 142'.

[0074] In some embodiments of this application, the first metal trace 161 may be positioned symmetrically with respect to the central axis h0 of the first source region 142'. The central axis h0 of the first source region 142' is a straight line parallel to the X-axis direction and passing through the midpoint of the first source region 142'.

[0075] Alternatively, in some other embodiments, the first metal trace 161 may be positioned elsewhere. For example, Figures 10A and 10B show examples of arrangements of the first metal trace 161 according to some embodiments of this application. As shown in Figure 10A, the first metal trace 161 may instead be positioned alongside the central axis h0 of the first source region 142'. Furthermore, as shown in Figure 10B, two first metal traces 161 may be provided instead. The two first metal traces 161 may be positioned on either side of the central axis h0 of the first source region 142'. This is not limited to this application. Any layout configuration of the first metal trace 161 that enables area reuse between the first source region 142' and the first metal trace 161 falls within the scope of protection of this application.

[0076] In some embodiments of this application, the ratio of the length of the first metal trace 161 to the length of the first source region 142' can be in the range of 0.1 to 0.7, for example, 0.1, 0.2, or 0.3. Thus, the first source region 142' can function normally when it is ensured that the first metal trace 161 can have a specific length and be equivalent to an inductor. The length of the first source region 142' is the size of the first source region 142' in the X-axis direction.

[0077] It should be understood that the embodiments described above have only been explained using examples in which the first metal plate 130 is connected to the first source region 142' via the first metal trace 161. For specific methods of connecting the first metal plate 130 to another source region 142, please refer to the above-described method of connecting the first metal plate 130 to the first source region 142'.

[0078] For example, the first metal plate 130 is connected to the second source region 142 via the second metal trace 162. The projection of the second metal trace 162 in the X-axis direction and the projection of the second source region 142'' overlap at least partially, and the projection of the second metal trace 162 in the Y-axis direction and the projection of the second source region 142'' overlap at least partially, thereby realizing area reuse between the second metal trace 162 and the second source region 142''.

[0079] Accordingly, for specific methods of connecting the first metal plate 130 to the third source region 142''' and the fourth source region 142''', please refer to the methods of connecting the first metal plate 130 to the first source region 142' in Figures 8A, 10A, and 10B. For further details, please refer to the related explanations mentioned above. Details will not be explained again here.

[0080] Please refer to Figure 7A. In some embodiments of this application, each of the source regions 142 of the transistor 140 is further provided with a grounding hole 1421. The grounding holes 1421 can be connected to the source region 142 and the bottom of the die 100 (i.e., the grounding surface) so that the source region 142 is grounded.

[0081] In some embodiments of this application, the die 100 may further include a second bus signal board (used as an output bus signal board) 170. The second bus signal board 170 is connected to a plurality of drain fingers 143 of the transistor 140. Based on this, signals on the plurality of drain fingers 143 can be separately coupled to the second bus signal board 170 and output through the second bus signal board 170. For example, the plurality of drain fingers 143 may also be connected to other elements (e.g., switches or duplexers) or packages via the second bus signal board 170.

[0082] This application further provides a chip 10, which includes at least one die 100. Figure 11 is a diagram of the structure of the chip 10 including the die 100 according to one embodiment of this application. See Figures 8A-9 and 11. The chip 10 includes the die 100, a capacitor C1, and a baseboard 200. The die 100 and the capacitor C1 are placed separately on the baseboard 200. The capacitor C1 is connected to the die 100 via bonding wires 300. The capacitor C1 and the bonding wires 300 may form a first matching circuit M1 configured to adjust the fundamental impedance. A capacitor C2 and an inductor L2 inside the die 100 may form a second matching circuit M2 configured to adjust the second harmonic impedance.

[0083] According to chip 10, the capacitor C2 and inductor L2 inside the die 100 form a second matching circuit M2, which better adjusts the phase of the second harmonic impedance to 180°, thereby further improving the efficiency of chip 10 and reducing energy consumption. Furthermore, the requirement to adjust the impedance of chip 10 can be met by placing only the capacitor C1, die 100, and bonding wire 300 inside chip 10, effectively reducing unnecessary electronic components, improving the space utilization rate inside chip 10, and potentially lowering manufacturing costs. For example, in chip 10a shown in Figure 3, a total of five components—capacitor C1, capacitor C2, die 100a, bonding wire 300a, and bonding wire 400a—are required to meet the impedance adjustment requirement. On the other hand, in this application, only three components are required: capacitor C1, die 100, and bonding wire 300. Compared to chip 10a, two components are eliminated, making the overall structure more compact and, as a result, expanding the range of applications.

[0084] Furthermore, in order to ensure the impedance matching effect, bonding wires 300a and 400a within chip 10a must have a specific length, which results in large parasitic inductance and affects the impedance matching effect. In particular, the effect on the impedance matching effect becomes more pronounced in high-frequency application scenarios. On the other hand, in this application, capacitor C2 and inductor L2 inside die 100 form a second matching circuit M2, leaving only bonding wire 300 connecting capacitor C1 to die 100. This effectively reduces the number of bonding wires, reduces parasitic inductance between bonding wires, and thereby further improves the operating performance of chip 10.

[0085] This embodiment is an example for illustrating the technical solution of this application, and those skilled in the art can make other modifications. For example, in this embodiment, only the example in which the capacitor C2 and inductor L2 in the die 100 form a second matching circuit M2 is used for illustrative purposes. In some other embodiments, the capacitor C2 and inductor L2 inside the die 100 may instead form other circuits, such as a first matching circuit M1.

[0086] In another example, in this embodiment, the first bus signal board 120 and the first metal plate 130 of the die 100 can jointly form a capacitor C2, and the metal trace 160 can be equivalent to an inductor L2. In some other embodiments, more capacitors or inductors can also be formed within the die 100 by using other components to form another circuit. For example, area reuse can also be performed between the second bus signal board 170 of the die 100 and another metal plate to jointly form a capacitor.

[0087] In another example, this embodiment is described using an example where transistor 140 is a field-effect transistor. In some other embodiments, transistor 140 may be another type of transistor instead of a field-effect transistor. For example, transistor 140 may be a diode, a triode, or a thyristor instead.

[0088] Having described the implementation of this application in a specific embodiment, those skilled in the art will readily understand the other advantages and effects of this application from the disclosures herein. Although this application is described with reference to certain embodiments, this does not mean that the features of this application are limited to this implementation only. Rather, the purpose of describing this application with reference to one implementation is to cover other options or modifications that may be derived based on the claims of this application. This application may instead be implemented without using these details. Also, some specific details have been omitted from the description to avoid confusion or obscuring the focus of this application. It should be noted that the embodiments and features in these embodiments of this application may be combined with each other where they do not conflict.

[0089] In this description of the application, it should be noted that directions or positional relationships indicated by terms such as “center,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “outside,” “inside,” “circumferential,” “radial,” and “axial” are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to describe and simplify this application, and are not intended to indicate or imply that the shown devices or elements need to have a particular orientation or be constructed and operated in a particular orientation, and therefore should not be understood as limitations on this application.

[0090] In this description of the application, it should be noted that, unless otherwise expressly stated or limited, terms such as “arrange,” “mount,” “connect,” and “attach” should be understood broadly. For example, such terms may refer to a fixed connection, a detachable connection, or an integrated connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection, an indirect connection via an intermediate medium, or internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of the aforementioned terms in this application based on the specific context.

[0091] Clearly, a person skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. This application is intended to cover changes and modifications to this application insofar as they fall within the scope of protection defined by the following claims and their equivalents in the art.

Claims

1. A die comprising a substrate, a first bus signal board, a first metal plate, and a transistor laminated on the substrate, The first bus signal board and the first metal plate are separated in a first direction, the first direction being the thickness direction of the substrate, and in the first direction, the projection area of ​​the first bus signal board onto the substrate is the first projection area, the projection area of ​​the first metal plate onto the substrate is the second projection area, and the first projection area and the second projection area overlap at least partially. In the first direction, the projection region of the transistor onto the substrate is a third projection region, the third projection region and the first projection region are separated from each other, and the first bus signal board and the first metal plate are separately connected to the pins of the transistor. Thailand.

2. The die according to claim 1, wherein the second projection region is located within the first projection region.

3. The die according to claim 1, wherein a dielectric layer is disposed between the first bus signal board and the first metal plate in the first direction.

4. The die according to claim 3, wherein the dielectric layer has silicon nitride or aluminum oxide.

5. The die according to claim 1, wherein the first metal plate and the transistor are located on the same surface of the substrate, and the first bus signal board is located on the side of the first metal plate that does not face the substrate.

6. The die according to any one of claims 1 to 5, wherein the transistor is a field-effect transistor.

7. The first bus signal board is an input bus signal board, and the input bus signal board is connected to the gate finger of the transistor. The transistor has at least one source region, the at least one source region includes a first source region, and the first metal plate is connected to the first source region via a first metal trace. The die according to claim 6.

8. The first metal plate and the transistor are separated in a second direction, and the second direction is perpendicular to the first direction. The first source region extends in the second direction, and in the second direction, the projection of the first metal trace and the projection of the first source region overlap at least partially. The die according to claim 7.

9. The die according to claim 8, wherein the first metal trace extends in the second direction, the projection of the first metal trace lies within the projection of the first source region in the second direction, the projection of the first metal trace and the projection of the first source region overlap at least partially in the third direction, and the third direction is perpendicular to both the first and second directions.

10. The at least one source region further includes a second source region, the first metal plate being connected to the second source region via a second metal trace, The second source region extends in the second direction, the second source region and the first source region are separated in the third direction, the projection of the second metal trace and the projection of the second source region overlap at least partially in the second direction, and the projection of the second metal trace and the projection of the second source region overlap at least partially in the third direction. The die according to claim 9.

11. The die according to claim 7, wherein each of the at least one source regions is grounded.

12. The die according to claim 7, wherein there are a plurality of gate fingers of the transistor, the plurality of gate fingers extend in a second direction, the plurality of gate fingers are spaced apart in a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the plurality of gate fingers are separately connected to the first bus signal board, and the projection of the plurality of gate fingers in the second direction is located within the projection of the first metal plate.

13. The die according to claim 7, further comprising an output bus signal board, the output bus signal board being connected to the drain finger of the transistor.

14. A chip comprising a baseboard and a die according to any one of claims 1 to 13, wherein the die is disposed on the baseboard.

15. The chip is a power amplifier chip, as described in claim 14.

16. An electronic device comprising a housing and a chip according to claim 14 or 15, wherein the chip is disposed within the housing.

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